Power management system and display device

Abstract

The invention discloses a power management system and a display device. The power management system comprises a judgment module and N power management chips connected with the judgment module, wherein N is greater than or equal to 2; the power supply management chip is used for outputting a first power supply voltage to the display panel; the judgment module is used for acquiring state signals of the power management chips, and controlling all the power management chips connected with the judgment module to stop outputting the first power voltage to the display panel under the condition that at least one power management chip is in a protection state; the state signal is used for representing the working state of the corresponding power management chip. According to the invention, when any one power management chip enters the protection state due to abnormity, the working voltage output by all the power management chips to the display panel is forcibly interrupted, so that the whole system synchronously enters the protection state; the problems of abnormal display and safety caused by the fact that part of the power management chips work and part of the power management chips stop are avoided, and the stability of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a power management system and a display device. Background Technology

[0002] In existing LCD (Liquid Crystal Display) panel driving architectures, as panel sizes increase, multiple power management ICs (PMICs) are typically used to provide the necessary power. When one of these PMICs enters a protection state due to an abnormality such as undervoltage lockout (UVLO) or over-current protection (OCP), that faulty PMIC will stop working, while the other normal PMICs will continue to supply power. This situation, where some PMICs stop working while others continue to work, can lead to display abnormalities in the LCD panel or pose potential safety hazards. Summary of the Invention

[0003] A power management system and display device are provided, which can establish a linkage mechanism between multiple PMICs to solve panel display abnormalities and potential safety hazards.

[0004] To achieve the above objectives, in a first aspect, embodiments of this application provide a power management system, including a judgment module and N power management chips connected to the judgment module, where N ≥ 2; wherein the power management chips are used to output a first power supply voltage to a display panel; the judgment module is used to acquire the status signal of the power management chip, and when at least one power management chip is in a protection state, control all power management chips connected to the judgment module to interrupt the output of the first power supply voltage to the display panel; wherein the status signal is used to characterize the working state of the corresponding power management chip.

[0005] Optionally, the power management chip includes: a status pin for outputting a status signal to the judgment module; and an enable pin for acquiring a control signal output by the judgment module and outputting or interrupting the first power supply voltage to the display panel according to the control signal.

[0006] Optionally, the operating state of the power management chip also includes a normal operating state; wherein, if the power management chip is in the normal operating state, the status pin outputs a first level; if the power management chip is in the protection state, the status pin outputs a second level; wherein, the first level and the second level are different.

[0007] Optionally, the judgment module is further configured to: if the status signal output by the status pin of at least one of the power management chips is the second level, send the control signal to the enable pin of all power management chips connected to the judgment module to control all power management chips to interrupt the output of the first power supply voltage to the display panel.

[0008] Optionally, the judgment module includes N cascaded switch groups. Each of the first to N-1 cascaded switch groups includes a first-type switch unit. The Nth cascaded switch group includes one first-type switch unit and N second-type switch units. The control terminals of the first-type switch units in the first to N-1 cascaded switch groups are connected one-to-one to the status pins of the first to N-1 power management chips. The first terminal of the first-type switch unit is connected to a first preset voltage, and the second terminal is connected to the output terminal. The Nth cascaded switch group includes one first-type switch unit and N second-type switch units connected in series. The control terminal of the first-type switch unit in the Nth cascaded switch group is connected to the status pin of the Nth power management chip. The first terminal is connected to the first preset voltage, and the second terminal is connected to the output terminal. The control terminals of the N second-type switch units in the Nth cascaded switch group are connected one-to-one to the status pins of the first to N power management chips. The first terminal of the N series-connected second-type switch units is connected to the output terminal, and the second terminal is connected to a second preset voltage. The first preset voltage and the second preset voltage are different.

[0009] Optionally, the first type of switching unit includes one type of switching transistor, or at least two type of switching transistors connected in series or in parallel; the second type of switching unit includes one type of switching transistor; wherein the first type of switching transistor and the second type of switching transistor have different turn-on voltages.

[0010] Optionally, the determination module further includes: a control transistor, wherein the control electrode of the control transistor is connected to the output terminal, the first electrode is connected to the enable pins of N power management chips, and the second electrode is connected to a preset low level.

[0011] Optionally, the type of the control transistor is the same as the type of the second type of switching transistor.

[0012] Optionally, the judgment module includes a microcontroller unit, the input terminal of which is electrically connected to the status pin of each of the power management chips, and the output terminal of which is used to output the control signal.

[0013] Optionally, the microcontroller detects the potential of all the status pins by a cyclic reading method or an interrupt triggering method.

[0014] Secondly, embodiments of this application provide a display device, the display device including a display panel, a driving system, and any of the above-mentioned power management systems.

[0015] This application discloses a power management system and a display device. The power management system includes a judgment module and N power management chips connected to the judgment module, where N ≥ 2. The power management chips output a first power supply voltage to the display panel. The judgment module acquires the status signals of the power management chips, and when at least one power management chip is in a protection state, it controls all power management chips connected to the judgment module to interrupt the output of the first power supply voltage to the display panel. The status signals characterize the operating state of the corresponding power management chip. This application can capture the status signals of multiple power management chips through the judgment module, and when any power management chip enters a protection state due to abnormal conditions such as ULVO, OCP, OVP, UVP, SCP, or TSD, it forcibly interrupts the output of all power management chips in the system, thereby interrupting the output of the first power supply voltage to the display panel. All power supplies within the display panel are completely cut off, causing all areas of the display panel to stop driving pixels. This avoids display abnormalities such as screen flickering, image retention, partial black screen, and screen flashing caused by some power management chips working and others stopping, as well as potential safety hazards such as overvoltage breakdown and overcurrent overheating. It meets the safety requirements for LCD panel products and improves the stability of the display panel. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the display panel driving architecture in related technologies; Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of this application; Figure 3 A schematic diagram of a power management system provided in an embodiment of this application; Figure 4 A schematic diagram of a power management system provided in an embodiment of this application; Figure 5 A schematic diagram of another power management system provided in an embodiment of this application; Figure 6 A circuit diagram of a judgment module provided in an embodiment of this application; Figure 7 A circuit diagram of another judgment module provided in an embodiment of this application.

[0018] Explanation of reference numerals in the attached figures: 10. Display device; 100. Power management system; 200. Drive system; 300. Display panel; 110. Judgment module; 120. Power management chip; ST, status pin; EN, enable pin; 1101, first type of switching unit; 1102, second type of switching unit. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0021] Figure 1 This is a schematic diagram of the display panel driving architecture in related technologies. For example... Figure 1As shown in the related technology, the LCD panel driving architecture uses multiple power management chips (PMICs). Taking three PMICs as an example, namely PMIC1, PMIC2, and PMIC3, the external 12V DC power supply voltage is delivered to the power input pin of each PMIC through the power input line. Simultaneously, the external controller also provides an independent 3.3V high-level enable signal, which is sent to the enable pin (EN) of each PMIC. When the enable pin EN receives the 3.3V high-level signal, it triggers all PMICs to synchronously start their working mode. Each PMIC outputs various voltages and control signals required for normal panel display according to the driving requirements of the LCD panel, such as: Gate High (VGH), Gate Low (VGL), and Common (Vcom). At the same time, the timing controller generates and outputs control signals such as the Start Vertical Signal (STV), Clock Signal (CK), and Latch Signal (LC). These control signals, after being level-shifted and power-amplified by the gate driver chip, work in conjunction with the voltage provided by the PMIC to ensure that the LCD panel can normally display images.

[0022] However, in related technologies, each PMIC independently receives the 3.3V enable signal and operates independently, with no signal interaction or status feedback link between chips. When any PMIC is triggered by an abnormality such as undervoltage lockout (UVLO), overcurrent protection (OCP), over-voltage protection (OVP), undervoltage protection (UVP), short circuit protection (SCP), or thermal shutdown (TSD), only the abnormal PMIC will stop outputting voltage and signal. The remaining power management chips 120 that have not experienced any abnormalities will continue to operate normally and continuously output voltage and signal under the continuous drive of the 3.3V enable signal.

[0023] The non-linked design scheme of protecting only one pixel while the rest operate in related technologies will directly cause the power supply system and signal timing of the LCD panel to become disordered: some areas of the panel cannot drive pixels normally due to the lack of corresponding voltage or signal, while other areas continue to work under the action of abnormal voltage or signal, which will eventually manifest as serious display abnormalities such as screen distortion, afterimages, partial black screen, and screen flickering. At the same time, since the abnormal operating conditions do not trigger the system-level comprehensive protection, the continuously output voltage or signal may exceed the rated operating range of the LCD panel and its supporting driving circuit. This will not only accelerate the aging and damage of the core components of the panel, but may also cause safety hazards such as overvoltage breakdown and overcurrent overheating, which does not meet the safety specifications of LCD panel products.

[0024] To address the aforementioned technical problems, embodiments of this application provide a power management system 100 and a display device 10. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0025] like Figure 2 As shown, the display device 10 of this application includes a display panel 300, a driving system 200, and a power management system 100. One end of the driving system 200 is electrically connected to the display panel 300, and the other end is electrically connected to the power management system 100. The display panel 300 may be a liquid crystal display panel 300. It should be noted that this application does not specifically limit the type of display panel 300, and an appropriate type can be selected according to the application scenario requirements.

[0026] The display panel 300 mentioned in this application can be widely used in various electronic devices and scenarios with display functions, including but not limited to: mobile phones, tablets, e-readers, electronic display screens, laptops, media players, wearable devices, smart TVs, home game console displays, car navigation systems, digital cameras, aerospace equipment display panels 300, etc., and this application does not limit it.

[0027] Please see Figure 3 , Figure 3 This is a schematic diagram of a power management system provided in an embodiment of this application. Figure 3As shown, the power management system 100 includes a judgment module 110 and N power management chips 120 connected to the judgment module 110, where N ≥ 2; wherein, the power management chips 120 are used to output a first power supply voltage to the display panel 300; the judgment module 110 is used to acquire the status signal of the power management chips 120, and when at least one power management chip 120 is in a protection state, it controls all power management chips 120 connected to the judgment module 110 to stop outputting the first power supply voltage to the display panel 300; wherein, the status signal is used to characterize the working state of the corresponding power management chip 120.

[0028] It should be understood that Figure 3 The three power management chips 120 shown do not constitute a limitation on the embodiments of this application. In practical applications, the number of power management chips 120 can be two or more. The power management chips 120 are used to provide operating voltages to various parts of the display device 10. For example, the power management chip 120 can be used to output a first power supply voltage to the display panel 300. Specifically, the power management chip 120 is connected to an external power supply and converts the voltage VCC provided by the external power supply into a first power supply voltage output to the display panel 300. It should be understood that this first power supply voltage includes various operating voltages required by the display panel 300, including but not limited to: VGH, VGL, Vcom, analog power supply voltage AVDD, data power supply voltage DVDD, etc.

[0029] Status signals are used to characterize the operating state of the power management chip 120, including but not limited to: normal operating state, protection state, standby / sleep state, power-on sequence (including self-test) state, and power-off state. When any power management chip 120 in the power management system 100 enters the protection state due to abnormal conditions such as ULVO, OCP, OVP, UVP, SCP, or TSD, the judgment module 110 captures the status signal corresponding to the abnormality and forcibly interrupts the output of all power management chips 120 in the system, thereby interrupting the output of the first power supply voltage to the display panel 300. All power supplies within the display panel 300 are completely cut off, causing all areas of the display panel 300 to stop driving pixels. This avoids display abnormalities such as screen flickering, image retention, partial black screen, and screen flashing caused by some power management chips 120 working and others not working, as well as potential safety hazards such as overvoltage breakdown and overcurrent overheating, thus complying with the safety regulations for LCD panel products.

[0030] The technical solution provided in this application embodiment captures the status signals of multiple power management chips 120 by the judgment module 110, and when any power management chip 120 enters the protection state due to an abnormality, it forcibly interrupts the working voltage output by all power management chips 120 to the display panel 300, so that the entire system enters the protection state synchronously, avoiding display abnormalities and safety issues caused by some power management chips 120 working and some power management chips 120 stopping, and improving the stability of the display panel 300.

[0031] In some embodiments, the power management system 100 includes: a status pin ST for outputting a status signal to the judgment module 110; and an enable pin EN for acquiring a control signal output by the judgment module 110 and outputting or interrupting a first power supply voltage to the display panel 300 according to the control signal.

[0032] like Figure 3 As shown, each power management chip 120 is provided with a status pin ST and an enable pin EN. The status pin ST is electrically connected to the judgment module 110 and is used to output the acquired status signal of the corresponding power management chip 120 to the judgment module 110. The judgment module 110 judges and outputs a control signal based on all received status signals. The enable pin EN receives the control signal and outputs or interrupts the output of a first power supply voltage (not shown in the figure) to the display panel 300 according to the control signal. For example, if all status signals indicate that the corresponding power management chip 120 is in a non-protected state, the control signal output by the judgment module 110 controls the continuous output of VDD voltage (e.g., 3.3V) to the enable pin EN, thereby outputting the first power supply voltage to the display panel 300 so that the display panel 300 can work normally; if any status signal indicates that the corresponding power management chip 120 is in a protected state, the control signal output by the judgment module 110 controls the VDD voltage output to the enable pin EN to be pulled down (e.g., from 3.3V to 0V), thereby controlling the interruption of the output of the first power supply voltage to the display panel 300. It should be understood that the control signal controls the VDD voltage of the enable pin EN to be pulled low, which can lower the voltage to a preset threshold, ensuring that the power management chip 120 stops outputting voltage at the threshold voltage. The preset voltage can be 0V, 1.2V, etc., and can be set according to actual needs. This application does not limit it in this regard.

[0033] This application embodiment adds a status pin ST to the power management chip 120 for feedback of the working status of the power management chip 120, so that the judgment module 110 can output a control signal for controlling whether to output a first power supply voltage to the display panel 300 according to the status signal.

[0034] In some embodiments, the operating state of the power management chip 120 also includes a normal operating state; wherein, if the power management chip 120 is in a normal operating state, the status pin ST outputs a first level; if the power management chip 120 is in a protection state, the status pin ST outputs a second level; wherein, the first level and the second level are different.

[0035] The status pin ST outputs a high or low level signal. When a power management chip 120 is operating normally or entering a protection state, the status pin ST outputs different high or low levels. For example, when the power management chip 120 is in normal operating state, the status pin ST outputs a high level "H", while when the power management chip 120 is in protection state, the status pin ST outputs a low level "L". It should be understood that the status pin ST can also output a low level "L" when the power management chip 120 is in normal operating state and a high level "H" when it is in protection state. This application does not limit this, as long as the first level and the second level are different, and the specific settings are made according to actual needs.

[0036] The technical solution provided in this application embodiment allows the status pin ST to characterize different operating states of the power management chip 120 by outputting different level signals.

[0037] In some embodiments, the judgment module 110 is further configured to: if the status signal output by the status pin ST of at least one power management chip 120 is at the second level, send a control signal to the enable pin EN of all power management chips 120 connected to the judgment module 110 to control all power management chips 120 to interrupt the output of the first power supply voltage to the display panel 300.

[0038] The judgment module 110 continuously monitors the status signals output by the status pin ST of all power management chips 120. Once the judgment module 110 detects that the status pin ST of any power management chip 120 outputs a second level (e.g., a low level "L"), it indicates that at least one power management chip 120 has entered a protection state due to an abnormality. At this time, the judgment module 110 will immediately send a control signal to control all power management chips 120 to interrupt the output of the first power supply voltage to the display panel 300, realizing the linkage control of all power management chips 120 and ensuring the safe shutdown of the entire system.

[0039] It should be understood that, for example, if the power management system 100 includes three power management chips 120 (PMIC1, PMIC2, and PMIC3), when one of the power management chips 120 (such as PMIC2) enters a protection state due to an abnormality, an error code Error1 can be set for that power management chip 120. This error code Error1 is used to indicate that the power management chip 120 has entered a protection state due to an abnormality. Of course, different error codes can also be set for each abnormality that leads to entering a protection state. When the judgment module 110 detects that the power management chip 120 (PMIC2) has entered a protection state, and thus controls all power management chips 120 to interrupt the output of the first power supply voltage to the display panel 300, at this time, PMIC1 and PMIC3 are interrupted due to the enable pin EN controlling their interruption, and can be set with an error code different from Error1, Error2. When debugging personnel need to perform rapid fault location, they can accurately locate which specific PMIC has failed through different error codes, thus speeding up the fault location process.

[0040] In practical circuit design, the judgment module 110 can be a microcontroller unit (MCU), a specialized logic circuit, or a switching circuit composed of transistors. For example, if the judgment module 110 uses a logic circuit, this logic circuit can be a combination of multiple-input OR gates and NOT gates. Its output can reflect the level state of all inputs in real time, realizing continuous monitoring of the operating state of each power management chip 120, and outputting the corresponding control signal when a protection state is detected, thereby realizing continuous monitoring and linkage control of the operating state of the power management chip 120. The judgment module 110, implemented using a logic circuit, is suitable for scenarios with high real-time requirements and simplified circuits. Pure hardware implementation requires no programming and offers fast response speed.

[0041] The judgment module 110 can also be implemented using a transistor switching circuit. Figure 4 and Figure 5 This is a schematic diagram of a power management system provided in an embodiment of this application. Figure 6 and Figure 7 A circuit diagram of a judgment module provided in an embodiment of this application is shown below. Figures 4 to 7 As shown, in some embodiments, the determination module 110 includes N cascaded switch groups, the first to N-1 levels of the switch groups each including a first type of switch unit 1101, and the Nth level of the switch group including a first type of switch unit 1101 and N second type of switch units 1102.

[0042] In this case, the control terminal of the first type of switch unit 1101 in the first to N-1 level switch groups is connected to the status pin ST of the first to N-1 power management chips 120. The first terminal of the first type of switch unit 1101 is connected to the first preset voltage VDD1, and the second terminal is connected to the output terminal C.

[0043] The Nth-level switch group includes a first-type switch unit 1101 and N second-type switch units 1102 connected in series. The control terminal of the first-type switch unit 1101 in the Nth switch group is connected to the status pin ST of the Nth power management chip 120, the first terminal is connected to the first preset voltage VDD1, and the second terminal is connected to the output terminal C.

[0044] The control terminals of the N second-type switch units 1102 in the Nth-level switch group are connected one-to-one to the status pin ST of the first to Nth power management chips 120; the N series-connected second-type switch units 1102 can form a whole, the first end of which is connected to the output terminal C, and the second end is connected to the second preset voltage GND1. The first preset voltage and the second preset voltage are different.

[0045] In some embodiments, the first type of switching unit 1101 includes one first type of switching transistor, or at least two first type of switching transistors connected in series or in parallel; the second type of switching unit 1102 includes one second type of switching transistor; wherein the turn-on voltages of the first type of switching transistor and the second type of switching transistor are different.

[0046] like Figure 4 As shown, the power management system 100 includes two power management chips 120 (PMIC1 and PMIC2). The judgment module 110 includes two cascaded switch groups, which are electrically connected to PMIC1 and PMIC2 respectively. The status pin ST of PMIC1 is connected to the control terminal of a first type of switch unit 1101 in the first-stage switch group 110A and the control terminal of a second type of switch unit 1102 in the second-stage switch group 110B. At this time, the first type of switch unit 1101 includes a first type of switch transistor T1, and the second type of switch unit 1102 includes a second type of switch transistor T3. The status pin ST of PMIC2 is connected to the control terminal of a first type of switch unit 1101 in the second-stage switch group 110B and the control terminal of a second type of switch unit 1102 in the second-stage switch group 110B. At this time, the first type of switch unit 1101 includes a first type of switch transistor T2, and the second type of switch unit 1102 includes a second type of switch transistor T4.

[0047] For example, T1 and T2 are P-channel metal-oxide-semiconductor (PMOS) transistors, which are turned on when the voltage level is low and turned off when the voltage level is high; T3 and T4 are N-channel metal-oxide-semiconductor (NMOS) transistors, which are turned on when the voltage level is high and turned off when the voltage level is low. The first preset voltage VDD1 is greater than the second preset voltage GND1, and the first preset voltage VDD1 is at a high level while the second preset voltage GND1 is at a low level. When both PMIC1 and PMIC2 are in normal working condition, point A of their status pin ST outputs a high level "H", T1 and T2 are cut off, T3 and T4 are turned on, and point C of the output terminal is pulled low. When PMIC1 enters protection state due to an abnormality, point A of its status pin ST outputs a low level "L", T1 is turned on, and T3 is cut off. PMIC2 is still in normal working condition, point A of its status pin ST outputs a high level "H", T2 is cut off, T4 is turned on, and point C of the output terminal is pulled high.

[0048] With the above circuit design, the voltage at point C of the output terminal can be pulled up to a high level when any power management chip 120 enters a protection state due to an abnormality.

[0049] The output level at point C controls the conduction and cutoff of the control transistor, thereby controlling the enable pin EN of the power management chip 120. In some embodiments, the determination module 110 further includes a control transistor, the control electrode of which is connected to the output terminal, the first electrode of which is connected to the enable pins EN of N power management chips 120, and the second electrode of which is connected to a preset low level GND2.

[0050] In some embodiments, the type of control transistor is the same as that of the second type of switching transistor.

[0051] Continue to refer to Figure 4 As shown, for example, the control transistor T5 is of the same type as the second type of switching transistors T3 and T4, all of which are NMOS. When the output terminal C outputs a high level, T5 is turned on, pulling the level of the enable pin EN of all power management chips 120 low to the preset low level GND2, forcibly interrupting the power output of all power management chips 120, thus realizing the linkage control of all power management chips 120.

[0052] like Figure 5As shown, the power management system 100 includes three power management chips 120 (PMIC1, PMIC2, and PMIC3), and the judgment module 110 includes three cascaded switch groups, which are electrically connected to PMIC1, PMIC2, and PMIC3 respectively. For example, T1, T2, and T6 are PMOS; T3, T4, and T7 are NMOS. When PMIC1, PMIC2, and PMIC3 are all in normal operating condition, point A of their status pin ST outputs a high level "H", T1, T2, and T6 are cut off, T3, T4, and T7 are turned on, and point C of the output terminal is pulled low. When PMIC1 enters protection mode due to an abnormality, point A of its status pin ST outputs a low level "L", T1 is turned on, and T3 is cut off. When PMIC2 and PMIC3 are still in normal operating condition, point A of their status pin ST outputs a high level "H", T2 and T6 are cut off, T4 and T7 are turned on, and point C of the output terminal is pulled high. The control transistor T5 is an NMOS transistor. When the output terminal C is high, T5 is turned on, which pulls the level of the enable pin EN of all power management chips 120 low to the preset low level GND2, forcibly interrupting the power output of all power management chips 120, thus realizing the linkage control of all power management chips 120.

[0053] like Figure 6 As shown, with Figure 4 The difference lies in that the first type of switching unit 1101 electrically connected to PMIC1 includes two first type of switching transistors T1 and T8 connected in series, while the first type of switching unit 1101 electrically connected to PMIC2 includes two first type of switching transistors T2 and T9 connected in series. ST pin (A) represents point A of the corresponding PMIC's status pin ST. For example, T1, T2, T8, and T9 are PMOS; T3 and T4 are NMOS. When both PMIC1 and PMIC2 are in normal operating state, point A of their status pin ST outputs a high level "H", T1, T2, T8, and T9 are cut off, T3 and T4 are turned on, and the output terminal C is pulled low. When PMIC1 enters protection state due to an abnormality, point A of its status pin ST outputs a low level "L", T1 and T8 are turned on, and T3 is cut off. When PMIC2 is still in normal operating state, point A of its status pin ST outputs a high level "H", T2 and T9 are cut off, T4 is turned on, and the output terminal C is pulled high. The control transistor T5 is an NMOS transistor. When the output terminal C is high, T5 is turned on, which pulls the level of the enable pin EN of all power management chips 120 low to the preset low level GND2, forcibly interrupting the power output of all power management chips 120, thus realizing the linkage control of all power management chips 120.

[0054] like Figure 7As shown, the first-stage switch group 110A includes one first-type switch unit 1101, and the second-stage switch group 110B includes one first-type switch unit 1101 and two second-type switch units 1102. Figure 4 The difference lies in that the first type of switching unit 1101 electrically connected to PMIC1 includes two first type of switching transistors T1 and T10 connected in parallel, while the first type of switching unit 1101 electrically connected to PMIC2 includes two first type of switching transistors T2 and T11 connected in parallel. ST pin (A) represents point A of the corresponding PMIC's status pin ST. For example, T1, T2, T10, and T11 are PMOS; T3 and T4 are NMOS. When both PMIC1 and PMIC2 are in normal operating condition, point A of their status pin ST outputs a high level "H", T1, T2, T10, and T11 are cut off, T3 and T4 are turned on, and the output terminal C is pulled low. When PMIC1 enters protection mode due to an abnormality, point A of its status pin ST outputs a low level "L", T1 and T10 are turned on, and T3 is cut off. PMIC2 is still in normal operating condition, and point A of its status pin ST outputs a high level "H", T2 and T11 are cut off, T4 is turned on, and the output terminal C is pulled high. The control transistor T5 is an NMOS transistor, and its output terminal C outputs a high level. When T5 is turned on, it pulls the level of the enable pin EN of all power management chips 120 low to the preset low level GND2, forcibly interrupting the power output of all power management chips 120, thus realizing the linkage control of all power management chips 120.

[0055] Instructions are required for the above. Figures 4 to 7 The specific circuit design of the judgment module 110 does not constitute a limitation of this application. Furthermore, the first type of switching transistor can be set as NMOS, and the second type of switching transistor and control transistor can be PMOS, as long as the transistor groups can be connected in series and parallel to form OR operation logic; this application does not impose any limitations on this. GND1 and GND2 can be the same or different low levels, and VDD1 and VDD can be the same high-level voltage or different high-level voltages; this application does not impose any limitations on this. The first preset voltage VDD1 can also be less than the second preset voltage GND1, and the first preset voltage VDD1 can be low while the second preset voltage GND1 can be high; this application does not impose any limitations on this.

[0056] The judgment module 110 provided in this application embodiment is implemented using a transistor switching circuit. Specifically, it uses the series and parallel connection of transistor groups to form OR operation logic, which meets the requirements of low cost and high integration panel driving architecture.

[0057] The judgment module 110 can also be implemented using a microcontroller unit (MCU). In some embodiments, the judgment module 110 includes a microcontroller unit, the input terminal of which is electrically connected to the status pin ST of each power management chip 120, and the output terminal of which is used to output control signals.

[0058] The input terminal of the microcontroller is electrically connected to the status pin ST of each power management chip 120 to obtain the status signal output by each status pin ST. The output terminal of the microcontroller is electrically connected to the enable pin EN of all power management chips 120 or the control terminal of the switching device in the system. The output terminal of the microcontroller is used to output a control signal to control the power management chip 120 to interrupt the output of the first power supply voltage to the display panel 300.

[0059] In some embodiments, the microcontroller detects the potential of all status pin ST by a cyclic read method or an interrupt-triggered method.

[0060] For example, the MCU detects the potential of all status pins ST by cyclic reading. The MCU can be pre-configured with a fixed detection cycle. It sequentially scans the status pins ST connected to each input terminal according to the detection cycle to obtain the potential value of each status pin ST. When at least one status pin ST is detected to be at the second level representing the protection state, the MCU immediately outputs a control signal to control all power management chips 120 to interrupt the output of the first power supply voltage to the display panel 300. If the potential of all status pins ST is detected to be at the first level representing the normal operation state, the output terminal outputs a control signal to control each power management chip 120 to output the first power supply voltage to the display panel 300 so that the display panel 300 maintains normal operation.

[0061] For example, the MCU detects the potential of all status pins ST via an interrupt trigger. The MCU can pre-configure interrupt trigger conditions matching the second level for each input terminal. When no abnormality is detected, the MCU is in a low-power standby state. When any power management chip 120 enters a protection state and the potential of its status pin ST output changes to the second level, an interrupt request is triggered in the MCU. The MCU is immediately woken up and executes a preset shutdown program. It outputs a control signal through the output terminal to control all power management chips 120 to interrupt the output of the first power supply voltage to the display panel 300.

[0062] The judgment module 110 implemented by MCU provided in this application embodiment has strong programmability, flexible adaptability, and high integration. It can simplify the system hardware architecture, is compatible with multiple detection methods, fits different application scenarios, and is suitable for scenarios that require flexible transformation and multi-functional expansion.

[0063] This application discloses a power management system 100 and a display device 10. The power management system 100 includes a judgment module 110 and N power management chips 120 connected to the judgment module 110, where N ≥ 2; the power management chips 120 are used to output a first power supply voltage to the display panel 300; the judgment module 110 is used to acquire the status signal of the power management chips 120, and when at least one power management chip 120 is in a protection state, it controls all power management chips 120 connected to the judgment module 110 to interrupt the output of the first power supply voltage to the display panel 300; the status signal is used to characterize the working state of the corresponding power management chip 120. This application can capture the status signals of multiple power management chips 120 through the judgment module 110, and when any power management chip 120 enters the protection state due to abnormal conditions such as ULVO, OCP, OVP, UVP, SCP, TSD, etc., it can forcibly interrupt the output of all power management chips 120 in the system, thereby interrupting the output of the first power supply voltage to the display panel 300. All power supplies in the display panel 300 are completely cut off, so that all areas of the display panel 300 stop driving pixels. This avoids display abnormalities such as screen distortion, image retention, partial black screen, and screen flicker caused by some power management chips 120 working and some power management chips 120 stopping, as well as potential safety hazards such as overvoltage breakdown and overcurrent overheating. It meets the safety requirements of LCD panel products and improves the stability of the display panel 300.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0065] The power management system 100 and display device 10 provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power management system, characterized in that, It includes a judgment module and N power management chips connected to the judgment module, where N ≥ 2; wherein, The power management chip is used to output a first power supply voltage to the display panel; The judgment module is used to obtain the status signal of the power management chip, and when at least one of the power management chips is in a protection state, it controls all the power management chips connected to the judgment module to stop outputting the first power voltage to the display panel. The status signal is used to characterize the operating state of the corresponding power management chip.

2. The power management system according to claim 1, characterized in that, The power management chip includes: A status pin is used to output a status signal to the judgment module. The enable pin is used to acquire the control signal output by the judgment module, and output or interrupt the first power supply voltage to the display panel according to the control signal.

3. The power management system according to claim 2, characterized in that, The power management chip's operating states also include a normal operating state; wherein... If the power management chip is in the normal operating state, the status pin outputs a first level. If the power management chip is in the protection state, the status pin outputs a second level; The first voltage level and the second voltage level are different.

4. The power management system according to claim 3, characterized in that, The judgment module is also used for: If the status signal output by the status pin of at least one of the power management chips is the second level, the control signal is sent to the enable pin of all power management chips connected to the judgment module to control all power management chips to interrupt the output of the first power supply voltage to the display panel.

5. The power management system according to any one of claims 2 to 4, characterized in that, The judgment module includes N cascaded switch groups. Each of the first to N-1 cascaded switch groups includes one first-type switch unit, and the Nth cascaded switch group includes one first-type switch unit and N second-type switch units. The control terminals of the first type of switch units in the switch groups of the first to N-1 levels are connected one-to-one to the status pins of the first to N-1 power management chips. The first terminal of the first type of switch unit is connected to a first preset voltage, and the second terminal is connected to the output terminal. The Nth group of switches includes one first type of switch unit and N second type of switch units connected in series. The control terminal of the first type of switch unit in the Nth group of switches is connected to the status pin of the Nth power management chip, the first terminal is connected to a first preset voltage, and the second terminal is connected to the output terminal. The control terminals of the N second-type switch units in the Nth switch group are connected one-to-one to the status pins of the 1st to Nth power management chips; the first terminal of the N series-connected second-type switch units is connected to the output terminal, and the second terminal is connected to the second preset voltage. The first preset voltage and the second preset voltage are different.

6. The power management system according to claim 5, characterized in that, The first type of switching unit includes one type of switching transistor, or at least two type of switching transistors connected in series or in parallel; The second type of switching unit includes a second type of switching transistor; The first type of switching transistor and the second type of switching transistor have different turn-on voltages.

7. The power management system according to claim 6, characterized in that, The judgment module also includes: A control transistor is provided, wherein the control electrode of the control transistor is connected to the output terminal, the first electrode is connected to the enable pins of N power management chips, and the second electrode is connected to a preset low level.

8. The power management system according to claim 7, characterized in that, The type of the control transistor is the same as that of the second type of switching transistor.

9. The power management system according to any one of claims 2 to 4, characterized in that, The judgment module includes a microcontroller unit, the input terminal of which is electrically connected to the status pin of each of the power management chips, and the output terminal of which is used to output the control signal.

10. The power management system according to claim 9, characterized in that, The microcontroller unit detects the potential of all the status pins by either a cyclic reading method or an interrupt triggering method.

11. A display device, characterized in that, The display device includes a display panel, a driving system, and a power management system as described in any one of claims 1 to 10.

Images