Storage device
By using a differential pair structure for non-volatile polarized memory devices and a cross-coupling design, the threshold voltage drift and noise interference problems of non-volatile polarized memory are solved, resulting in a storage device with high reliability, low power consumption, and high integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-26
- Publication Date
- 2026-04-03
AI Technical Summary
The threshold voltage of non-volatile polarized memory is susceptible to various factors, which can lead to a decrease in the signal-to-noise ratio and affect memory reliability.
Non-volatile polarized memory devices employing differential pair structures achieve data writing and reading through cross-coupling of the gate and substrate, combined with gate driver devices and drain differential detection devices, utilizing the characteristics of differential signals to offset threshold voltage drift and environmental noise interference.
It improves the storage reliability of storage devices, reduces power consumption and chip area, and balances high reliability, low power consumption and high integration.
Smart Images
Figure CN121789730A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a storage device. Background Technology
[0002] Non-volatile polarized memories, such as ferroelectric field-effect transistors (FeFETs), utilize the polarization characteristics of ferroelectric materials to achieve data storage. They offer advantages such as high speed, low power consumption, and high integration density, and are widely used in the memory field. However, in practical applications, the threshold voltage of FeFETs is susceptible to various factors. For example, the fatigue effect of ferroelectric materials reduces polarization switching capability after multiple read / write cycles, leading to threshold voltage drift. Environmental interference such as temperature changes and power supply noise can cause random fluctuations in the threshold voltage. Furthermore, gate voltage stress during the read process can trigger unexpected polarization switching, affecting data integrity. Clearly, all these factors reduce the signal-to-noise ratio of FeFET memory cells, thereby affecting memory reliability.
[0003] Therefore, how to effectively improve the storage reliability of non-volatile polarized memory is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0004] The purpose of this application is to provide a storage device that can effectively improve the storage reliability of non-volatile polarized memory.
[0005] This application discloses a storage device, including: a first non-volatile polarized memory device, a second non-volatile polarized memory device, a gate driver device, and a drain differential detection device;
[0006] The sources of both the first non-volatile polarized memory device and the second non-volatile polarized memory device are grounded, their drains are connected to the drain differential detection device, and their gates are respectively connected to the first output terminal and the second output terminal of the gate driver device.
[0007] The first output terminal is connected to the substrate of the second non-volatile polarized memory device, and / or the second output terminal is connected to the substrate of the first non-volatile polarized memory device;
[0008] The gate driver device is used to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store complementary data to realize data writing of the memory device; it is also used to drive the drain differential detection device to read the differential signal of the first non-volatile polarized memory device and the second non-volatile polarized memory device to realize data reading of the memory device.
[0009] Optionally, the gate driver device is specifically used to output a voltage signal that is opposite to and exceeds the coercive field of the ferroelectric material to the first output terminal and the second output terminal, so as to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store the complementary data, so as to realize the data writing of the memory device.
[0010] Optionally, when the gate driver device outputs a positive high voltage to the first output terminal and does not output a voltage signal to the second output terminal, the first non-volatile polarized memory device stores a logic value of 0, and the second non-volatile polarized memory device stores a logic value of 1; correspondingly, the data written to the memory device is a logic value of 0.
[0011] When the gate driver device outputs a positive high voltage to the second output terminal and does not output a voltage signal to the first output terminal, the first non-volatile polarized memory device stores a logic value of 1, and the second non-volatile polarized memory device stores a logic value of 0; correspondingly, the data written to the memory device is a logic value of 1.
[0012] Optionally, the gate driver device is specifically used to output a read voltage signal to the first output terminal and the second output terminal, and to output a drain bias signal to the drain of the first non-volatile polarized memory device and the second non-volatile polarized memory device, so as to drive the drain differential detection device to read the differential signal of the first non-volatile polarized memory device and the second non-volatile polarized memory device, so as to realize the data reading of the storage device; wherein, the value of the read voltage signal is between the typical threshold voltage of the first non-volatile polarized memory device and the second non-volatile polarized memory device, and is lower than the coercive field voltage of the ferroelectric material.
[0013] Optionally, the differential signal is specifically the difference between the on-current of the first non-volatile polarized memory device and the on-current of the second non-volatile polarized memory device.
[0014] When the difference is greater than 0, the data read by the storage device is a logical value 0; when the difference is less than 0, the data read by the storage device is a logical value 1.
[0015] Optionally, the substrates of the first non-volatile polarized memory device and the second non-volatile polarized memory device are treated with shallow trench isolation.
[0016] Optionally, the first non-volatile polarized memory device and the second non-volatile polarized memory device are specifically two non-volatile polarized memory devices with identical structures.
[0017] Optionally, the first non-volatile polarized memory device and the second non-volatile polarized memory device are specifically two ferroelectric field-effect transistors with identical structures.
[0018] Optionally, the drain differential detection device is specifically a differential amplifier.
[0019] Optionally, the gate driving device is specifically a dedicated high-voltage gate driving circuit.
[0020] This application provides a storage device, including: a first non-volatile polarized memory device, a second non-volatile polarized memory device, a gate driver device, and a drain differential detection device; the sources of the first non-volatile polarized memory device and the second non-volatile polarized memory device are both grounded, the drains of both are connected to the drain differential detection device, and the gates are respectively connected to a first output terminal and a second output terminal of the gate driver device; the first output terminal is connected to the substrate of the second non-volatile polarized memory device, and / or, the second output terminal is connected to the substrate of the first non-volatile polarized memory device; the gate driver device is used to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store complementary data to realize data writing of the storage device; and is also used to drive the drain differential detection device to read the differential signal of the first non-volatile polarized memory device and the second non-volatile polarized memory device to realize data reading of the storage device.
[0021] By applying the technical solution provided in this application, in a storage device, the first non-volatile polarized memory device and the second non-volatile polarized memory device form a differential pair structure, and the two achieve cross-coupling between the gate and the substrate. Combined with a gate driver device and a drain differential detection device, the data read / write function of the storage device is realized. Based on this, the storage device can store the signal difference between the two non-volatile polarized memory devices based on the differential pair structure, ensuring that the drain differential detection device can always read the signal difference between the two non-volatile polarized memory devices during data reading. This effectively expands the storage window of the storage device, thereby improving its storage reliability. Furthermore, this storage device only requires two non-volatile polarized memory devices to achieve differential storage, without relying on material optimization, complex structural design, or periodic circuit calibration. It can compensate for threshold voltage drift and environmental noise interference in real time using only the characteristics of the differential signal. This can reduce power consumption and chip area while ensuring long lifespan and high speed, effectively improving the overall storage performance. Therefore, the storage device provided in this application can meet the application requirements of high reliability, low power consumption, and high integration. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the prior art and the embodiments of this application, the accompanying drawings used in the description of the prior art and the embodiments of this application will be briefly introduced below. Of course, the accompanying drawings described below with respect to the embodiments of this application are only a part of the embodiments in this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and such other drawings also fall within the protection scope of this application.
[0023] Figure 1 This is a schematic diagram of the structure of a first type of storage device provided in an embodiment of this application;
[0024] Figure 2 This is a schematic diagram of the structure of the second type of storage device provided in the embodiments of this application;
[0025] Figure 3 This is a schematic diagram of the structure of the third type of storage device provided in the embodiments of this application;
[0026] Figure 4 This is a schematic diagram of the structure of the fourth type of storage device provided in the embodiments of this application;
[0027] Figure 5 A schematic diagram illustrating the principle of using differential pair FeFETs to improve the storage window of a storage device, provided as an embodiment of this application;
[0028] Figure 6 This is a schematic diagram illustrating the principle of using a differential pair FeFET to enhance anti-interference capability, as provided in an embodiment of this application. Detailed Implementation
[0029] The core of this application is to provide a storage device that can effectively improve the storage reliability of non-volatile polarized memory.
[0030] To provide a clearer and more complete description of the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0031] This application provides a storage device.
[0032] Please refer to Figure 1 , Figure 1This is a schematic diagram of a storage device provided in an embodiment of this application. The storage device may include: a first non-volatile polarized memory device, a second non-volatile polarized memory device, a gate driver device, and a drain differential detection device. Figure 1 (Differential detection module shown).
[0033] The sources of the first non-volatile polarized memory device and the second non-volatile polarized memory device are both grounded, the drains D1 and D2 are both connected to the drain differential detection device, and the gates are respectively connected to the first output terminal G1 and the second output terminal G2 of the gate driver device.
[0034] The first output terminal G1 is connected to the substrate of the second non-volatile polarized memory device, and / or the second output terminal G2 is connected to the substrate of the first non-volatile polarized memory device.
[0035] A gate driver device is used to drive a first non-volatile polarized memory device and a second non-volatile polarized memory device to store complementary data to realize data writing of the memory device; it is also used to drive a drain differential detection device to read the differential signal of the first non-volatile polarized memory device and the second non-volatile polarized memory device to realize data reading of the memory device.
[0036] First, the first and second non-volatile polarized memory devices are arranged in a differential structure. The sources of both devices are grounded, i.e., Vss = 0V. The drains D1 and D2 of both devices are connected to a drain differential detection device to ensure symmetrical differential signal acquisition. The gate of the first device is connected to the first output terminal G1 of the gate driver, which is also connected to the substrate of the second device. The gate of the second device is connected to the second output terminal G2 of the gate driver, which is also connected to the substrate of the first device. This establishes a gate-substrate connection between the first and second devices. Alternatively, the gate of the first non-volatile polarized memory device can be connected to the first output terminal G1 of the gate driver device, and the first output terminal G1 can be connected to the substrate of the second non-volatile polarized memory device. The gate of the second non-volatile polarized memory device can be connected to the second output terminal G2 of the gate driver device. Similarly, a cross-coupling structure between the gate and the substrate can be realized between the first and second non-volatile polarized memory devices. Alternatively, the gate of the first non-volatile polarized memory device can be connected to the first output terminal G1 of the gate driver device, and the gate of the second non-volatile polarized memory device can be connected to the second output terminal G2 of the gate driver device. The second output terminal G2 can be connected to the substrate of the first non-volatile polarized memory device. A cross-coupling structure between the gate and the substrate can also be realized between the first and second non-volatile polarized memory devices.
[0037] Specifically, the first non-volatile polarized memory device and the second non-volatile polarized memory device can be two structurally identical non-volatile polarized memory devices. In one possible implementation, the first and second non-volatile polarized memory devices can be two structurally identical ferroelectric field-effect transistors (FeFETs). More specifically, FeFET1 (the first non-volatile polarized memory device) and FeFET2 (the second non-volatile polarized memory device) can employ identical manufacturing processes and dimensional parameters (such as gate length, gate width, and ferroelectric layer thickness) to effectively ensure that their initial threshold voltage, polarization switching characteristics, and aging rates are completely consistent, thereby effectively guaranteeing subsequent drift synchronization. Furthermore, the substrates of the first and second non-volatile polarized memory devices can be isolated using shallow trench isolation to effectively avoid signal interference between substrates.
[0038] Based on this, please refer to the example of differential pair FeFET1 and FeFET2. Figures 2 to 4 , Figure 2This is a schematic diagram of the structure of the second type of storage device provided in the embodiments of this application. Figure 3 This is a schematic diagram of the structure of the third type of storage device provided in the embodiments of this application. Figure 4 This is a schematic diagram of the structure of a fourth type of storage device provided in the embodiments of this application, which corresponds to the gate connection methods of the three different non-volatile polarized memory devices mentioned above.
[0039] Furthermore, the gate driver device can be used to output a drive signal. During data writing, the gate driver device can output a drive signal to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store complementary data (logic data 0 and logic data 1) to achieve data writing to the memory device; for example, the first non-volatile polarized memory device stores logic data 0 and the second non-volatile polarized memory device stores logic data 1, or the first non-volatile polarized memory device stores logic data 1 and the second non-volatile polarized memory device stores logic data 0, thereby forming an inherent differential characteristic between the first and second non-volatile polarized memory devices. During data reading, the gate driver device can output a drive signal to drive the drain differential detection device to read the differential signal between the first and second non-volatile polarized memory devices to achieve data reading from the memory device. This differential signal is the signal difference between the first and second non-volatile polarized memory devices. In one possible implementation, the drain differential detection device can specifically be a differential amplifier, and the gate driving device can specifically be a dedicated high-voltage gate driving circuit.
[0040] Therefore, the storage device can store the signal difference between two non-volatile polarized memory devices based on a differential pair structure, ensuring that the drain differential detection device can always read the signal difference between the two non-volatile polarized memory devices during data reading, thereby effectively increasing the storage window of the storage device. Figure 5 As shown, Figure 5 This is a schematic diagram illustrating the principle of using differential pair FeFETs to improve the storage window of a storage device, as provided in an embodiment of this application. It can be seen that, compared with a single FeFET, differential pair FeFETs can effectively increase the storage window ∆ of the storage device. In the storage device, the greater the signal difference between the two non-volatile polarized memory devices, the stronger the anti-interference capability and the more stable the data storage, thus effectively improving the storage reliability of the storage device.
[0041] Based on this, the following methods are provided for writing and reading data from storage devices.
[0042] 1. During the data writing process, the core logic is to apply a voltage that is opposite to the first output terminal G1 and the second output terminal G2 and exceeds the coercive field of the ferroelectric material. By using the cross-coupled gate-substrate voltage linkage, the first non-volatile polarized memory device and the second non-volatile polarized memory device form opposite polarization states (corresponding to complementary data "0 / 1" or "1 / 0"), thereby ensuring that the threshold voltage difference is maximized.
[0043] Based on this, the gate driver can specifically be used to output a voltage signal that is opposite to and exceeds the coercive field of the ferroelectric material to the first output terminal and the second output terminal, so as to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store complementary data, thereby realizing data writing to the memory device. More specifically, when the gate driver outputs a positive high voltage to the first output terminal and does not output a voltage signal to the second output terminal, the first non-volatile polarized memory device stores a logic value of 0, and the second non-volatile polarized memory device stores a logic value of 1; correspondingly, the data written to the memory device is a logic value of 0; when the gate driver outputs a positive high voltage to the second output terminal and does not output a voltage signal to the first output terminal, the first non-volatile polarized memory device stores a logic value of 1, and the second non-volatile polarized memory device stores a logic value of 0; correspondingly, the data written to the memory device is a logic value of 1.
[0044] by Figure 2 Taking the storage device shown as an example:
[0045] (1) Write "0" to the storage device (FeFET1=0, FeFET2=1):
[0046] When +Vprog (positive high voltage, exceeding the coercive field of the ferroelectric material) is applied to the first output terminal G1, the source (Vss=0V) and drain of FeFET1 are left floating. The positive gate voltage directly polarizes its own ferroelectric layer, thereby reducing the threshold voltage Vth1, corresponding to "FeFET1=0". Since the first output terminal G1 is extended to the substrate of FeFET2, the substrate of FeFET2 simultaneously receives +Vprog. At the same time, 0V is applied to the second output terminal G2, the source of FeFET2 is grounded, and a reverse electric field is formed between the gate and the substrate (i.e., the gate is 0V and the substrate is +Vprog), which is equivalent to applying a negative bias voltage to the gate of FeFET2, causing the ferroelectric layer of FeFET2 to be reverse polarized, thereby increasing the threshold voltage Vth2, corresponding to "FeFET2=1".
[0047] (2) Write "1" to the storage device (FeFET1=1, FeFET2=0):
[0048] When +Vprog (positive high voltage, exceeding the coercive field of the ferroelectric material) is applied to the second output terminal G2, the source (Vss=0V) and drain of FeFET2 are left floating. The positive gate voltage directly polarizes its own ferroelectric layer, thereby reducing the threshold voltage Vth2, corresponding to "FeFET2=0". Since the second output terminal G2 is extended to the substrate of FeFET1, the substrate of FeFET1 simultaneously receives +Vprog. At the same time, 0V is applied to the first output terminal G1, the source of FeFET1 is grounded, and a reverse electric field is formed between the gate and the substrate (i.e., the gate is 0V and the substrate is +Vprog), which is equivalent to applying a negative bias voltage to the gate of FeFET1, causing the ferroelectric layer of FeFET1 to be reverse polarized, thereby increasing the threshold voltage Vth1, corresponding to "FeFET1=1".
[0049] As can be seen, the above writing method based on the cross-coupling structure applies a voltage that is opposite to and exceeds the coercive field of the ferroelectric material to the first output terminal G1 and the second output terminal G2. The gate-substrate reverse electric field is used to realize the opposite polarization of the two FeFETs, thereby achieving stable storage of complementary data.
[0050] 2. During the data reading process, the core logic is to use the differential detection module to compare the difference in conduction current between the first non-volatile polarization memory device and the second non-volatile polarization memory device in order to identify the stored data, without changing the polarization state of the ferroelectric layer throughout the process.
[0051] Based on this, the gate driver device can specifically be used to output a read voltage signal to the first output terminal and the second output terminal, and to output a drain bias signal to the drain of the first non-volatile polarized memory device and the second non-volatile polarized memory device, so as to drive the drain differential detection device to read the differential signal of the first non-volatile polarized memory device and the second non-volatile polarized memory device, thereby realizing data reading of the storage device; wherein, the value of the read voltage signal is between the typical threshold voltages of the first non-volatile polarized memory device and the second non-volatile polarized memory device, and is lower than the coercive field voltage of the ferroelectric material. More specifically, the differential signal can be the difference between the conduction current of the first non-volatile polarized memory device and the conduction current of the second non-volatile polarized memory device; when the difference is greater than 0, the read data of the storage device is a logic value 0; when the difference is less than 0, the read data of the storage device is a logic value 1.
[0052] Similarly Figure 2Taking the storage device shown as an example, the same intermediate read voltage Vread (Vread is between the typical values of Vth1 and Vth2, and lower than the coercive field voltage of the ferroelectric material) is simultaneously applied to the first output terminal G1 and the second output terminal G2; the sources of FeFET1 and FeFET2 are both grounded, and the drains D1 and D2 are connected to the differential detection module. A fixed drain bias voltage Vdd (low voltage, to avoid affecting polarization) is applied to the drain. At this time, the data read is determined as follows:
[0053] (1) If FeFET1=0 (Vth1 low) and FeFET2=1 (Vth2 high), then Vread is sufficient to turn FeFET1 on (D1 has obvious current) and FeFET2 off (D2 has no obvious current). The differential detection module detects "∆=D1-D2>0", and then outputs the read data "0".
[0054] (2) If FeFET1=1 (Vth1 high) and FeFET2=0 (Vth2 low), then Vread is sufficient to turn FeFET2 on (D2 has obvious current) and FeFET1 off (D1 has no obvious current). The differential detection module detects "∆=D1-D2<0" and outputs the read data "1".
[0055] Therefore, the above non-destructive reading method applies an intermediate reading voltage Vread lower than the coercive field of the ferroelectric material to the first output terminal G1 and the second output terminal G2. By comparing the difference in the conduction current of the drains D1 and D2 of the two FeFETs through the differential detection module, data determination can be achieved without changing the polarization state of the ferroelectric layer.
[0056] Finally, please refer to Figure 6 , Figure 6 This is a schematic diagram illustrating the principle of using differential pair FeFETs to improve anti-interference capability in an embodiment of this application. When threshold voltage drift and noise interference exist in the application environment, the two FeFETs will be subjected to interference signals with the same trend (such as...). Figure 6The signal shown is “threshold voltage drift, environmental noise interference, etc.”, but since the two are symmetrical structures, the interference will act synchronously on the differential pair, making the fluctuation amplitude of the two consistent. At this time, the differential detection module calculates the signal difference between the drain D1 and D2 to cancel the influence of synchronous interference, and finally outputs a stable storage signal. Obviously, compared with the traditional “single FeFET storage” technology, this differential structure has the following advantages: (1) stronger anti-interference capability: “common-mode interference” such as environmental noise and Vth drift caused by device aging will be canceled by the differential pair structure, avoiding the storage signal being overwhelmed by interference; (2) more stable storage window: the storage window (Vth difference) of a single FeFET is easily affected by interference fluctuations, while the differential structure amplifies the effective signal through “dual tube difference”, making the actual detectable range of the storage window more stable; (3) higher read reliability: differential detection judges the storage state through “current / voltage difference”, which is more tolerant to individual device differences and environmental fluctuations than the “absolute current / voltage” reading of a single FeFET.
[0057] In summary, the storage device provided in this application embodiment has a differential pair structure for the first and second non-volatile polarized memory devices, with cross-coupling between their gates and substrates. Combined with a gate driver and a drain differential detection device, the storage device achieves data read / write functionality. Based on this, the storage device can store the signal difference between the two non-volatile polarized memory devices using the differential pair structure, ensuring that the drain differential detection device can always read the signal difference between the two non-volatile polarized memory devices during data reading. This effectively increases the storage window of the storage device, improving its storage reliability. Furthermore, this storage device only requires two non-volatile polarized memory devices to achieve differential storage, without relying on material optimization, complex structural design, or periodic circuit calibration. It utilizes only the differential signal characteristics to cancel threshold voltage drift and environmental noise interference in real time, ensuring long lifespan and high speed while reducing power consumption and chip area, effectively improving overall storage performance. Therefore, the storage device provided in this application can meet the application requirements of high reliability, low power consumption, and high integration.
[0058] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.
[0059] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A storage device, characterized in that, include: A first non-volatile polarized memory device, a second non-volatile polarized memory device, a gate driver device, and a drain differential detection device; The sources of both the first non-volatile polarized memory device and the second non-volatile polarized memory device are grounded, their drains are connected to the drain differential detection device, and their gates are respectively connected to the first output terminal and the second output terminal of the gate driver device. The first output terminal is connected to the substrate of the second non-volatile polarized memory device, and / or the second output terminal is connected to the substrate of the first non-volatile polarized memory device; The gate driver device is used to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store complementary data to realize data writing of the memory device; It is also used to drive the drain differential detection device to read the differential signals of the first non-volatile polarized memory device and the second non-volatile polarized memory device to realize data reading of the storage device.
2. The storage device according to claim 1, characterized in that, The gate driver device is specifically used to output a voltage signal that is opposite to and exceeds the coercive field of the ferroelectric material to the first output terminal and the second output terminal, so as to drive the first non-volatile polarized memory device and the second non-volatile polarized memory device to store the complementary data, thereby realizing the data writing of the storage device.
3. The storage device according to claim 2, characterized in that, When the gate driver device outputs a positive high voltage to the first output terminal and does not output a voltage signal to the second output terminal, the first non-volatile polarized memory device stores a logic value of 0, and the second non-volatile polarized memory device stores a logic value of 1; correspondingly, the data written to the memory device is a logic value of 0. When the gate driver device outputs a positive high voltage to the second output terminal and does not output a voltage signal to the first output terminal, the first non-volatile polarized memory device stores a logic value of 1, and the second non-volatile polarized memory device stores a logic value of 0; correspondingly, the data written to the memory device is a logic value of 1.
4. The storage device according to claim 3, characterized in that, The gate driver device is specifically used to output read voltage signals to the first output terminal and the second output terminal, and to output drain bias signals to the drain terminals of the first non-volatile polarized memory device and the second non-volatile polarized memory device, so as to drive the drain differential detection device to read the differential signals of the first non-volatile polarized memory device and the second non-volatile polarized memory device, so as to realize the data reading of the storage device; wherein, the value of the read voltage signal is between the typical threshold voltages of the first non-volatile polarized memory device and the second non-volatile polarized memory device, and is lower than the coercive field voltage of the ferroelectric material.
5. The storage device according to claim 4, characterized in that, The differential signal is specifically the difference between the on-current of the first non-volatile polarized memory device and the on-current of the second non-volatile polarized memory device. When the difference is greater than 0, the data read from the storage device is a logical value of 0; When the difference is less than 0, the data read by the storage device is a logical value of 1.
6. The storage device according to claim 1, characterized in that, The substrates of the first non-volatile polarized memory device and the second non-volatile polarized memory device are isolated by shallow trench isolation.
7. The storage device according to claim 1, characterized in that, The first non-volatile polarized memory device and the second non-volatile polarized memory device are specifically two non-volatile polarized memory devices with identical structures.
8. The storage device according to claim 7, characterized in that, The first non-volatile polarized memory device and the second non-volatile polarized memory device are specifically two ferroelectric field-effect transistors with identical structures.
9. The storage device according to claim 1, characterized in that, The drain differential detection device is specifically a differential amplifier.
10. The storage device according to claim 1, characterized in that, The gate driving device is specifically a dedicated high-voltage gate driving circuit.