Readout circuit structure

Abstract

The embodiment of the invention provides a readout circuit structure. The readout circuit structure comprises a structural layer, a first interconnection layer and a second interconnection layer, wherein the first interconnection layer and the second interconnection layer are stacked on the top of the structural layer; a transistor forming a first sensing amplification structure is arranged in the structural layer, the structural layer comprises a grid layer, and the first sensing amplification structure is adjacent to the first storage array and the second storage array; the first sensing amplification structure receives a first bit line signal in the first storage array through a first signal line, and the first sensing amplification structure receives a first complementary bit line signal in the second storage array through a first complementary signal line; each of the first signal line and the first complementary signal line comprises a plurality of transmission lines connected in sequence, the adjacent transmission lines are located on different conductive layers, each conductive layer comprises a gate layer, a first interconnection layer and a second interconnection layer, part of the transmission lines in the first signal line are located on the first interconnection layer, and part of the transmission lines in the second signal line are located on the second interconnection layer; each section of transmission line of the first signal line is not located on the second interconnection layer, and part of sections of transmission lines in the first complementary signal line are located on the second interconnection layer.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese Patent Application No. 202110751252.8, filed on July 2, 2021, entitled "Readout Circuit Structure", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of memory layout design, and in particular to a readout circuit structure. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0005] DRAM can be divided into Double Data Rate (DDR) dynamic random access memory, GDDR (Graphics Double Data Rate) dynamic random access memory, and Low Power Double Data Rate (LPDDR) dynamic random access memory. As DRAM applications expand, such as its increasing use in mobile devices, users are demanding higher power consumption from DRAM users.

[0006] However, the performance of current DRAM still needs to be improved. Summary of the Invention

[0007] This application provides a readout circuit structure that, in order to solve the problem of slow memory precharge speed, provides a layout structure and wiring method to reduce the layout area of ​​the readout circuit structure.

[0008] To address the aforementioned technical problems, this application provides a readout circuit structure disposed in the gaps between memory arrays, comprising: a structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; the structural layer contains a first sensing amplification structure, a second sensing amplification structure, and an equalization structure; the first sensing amplification structure is connected to one memory array in an adjacent memory array via a first bit line, and is also connected to another memory array in an adjacent memory array via a first complementary bit line; the second sensing amplification structure is connected to one memory array in an adjacent memory array via a second bit line, and is also connected to another memory array in an adjacent memory array via a second complementary bit line. A storage array; wherein one of a first bit line or a first complementary bit line is disposed in a first interconnect layer, and at least a portion of the other is disposed in a second interconnect layer; one of a second bit line or a second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; an equalization structure is directly connected to the first complementary bit line and the second bit line for pre-charging the first bit line, the first complementary bit line, the first sensing amplification structure, the second bit line, the second complementary bit line, and the second sensing amplification structure; wherein the equalization structure is disposed between the first sensing amplifier structure and the second sensing amplifier structure, and is directly connected to the first complementary bit line and the second bit line in the first interconnect layer.

[0009] Compared with related technologies, the equalization structure directly connects to the first bit line or the first complementary bit line for pre-charging the first bit line and the first complementary bit line. The equalization structure also directly connects to the second bit line or the second complementary bit line for pre-charging the second bit line and the second complementary bit line. By directly connecting the bit lines through the equalization structure, the bit lines are pre-charged directly, avoiding the need for switching transistors to be turned on during the pre-charging process, thus accelerating the charging speed of the bit lines. Furthermore, at least a portion of one of the first bit line or the first complementary bit line is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer. Similarly, at least a portion of one of the second bit line or the second complementary bit line is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer. Through the stacked arrangement of the first and second interconnect layers, the structure required for layout in each layer is reduced, thereby reducing the layout area of ​​the readout circuit structure.

[0010] Furthermore, the first bit line is disposed in the first interconnect layer, and at least a portion of the first complementary bit line is disposed in the second interconnect layer. The first complementary bit line passes through the region where the second sensing amplification structure is located in the second interconnect layer and is coupled to the first sensing amplification structure. At least a portion of the second bit line is disposed in the second interconnect layer, and the second bit line passes through the region where the first sensing amplification structure is located in the first interconnect layer and is coupled to the second sensing amplification structure. The second complementary bit line is disposed in the first interconnect layer. The first complementary bit line passes through the region where the second sensing amplification structure is located and is coupled to the first sensing amplification structure, meaning that the first complementary bit line does not require additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure. Similarly, the second bit line passes through the region where the first sensing amplification structure is located and is coupled to the second sensing amplification structure, meaning that the second bit line does not require additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure.

[0011] Additionally, the equalization structure includes: a first equalization transistor, whose gate is used to receive a first equalization signal, one of its source or drain is connected to a first complementary bit line, and the other is used to receive a first pre-charge voltage, for pre-charging the first bit line, the first complementary bit line, and the first sensing amplification structure to the first pre-charge voltage based on the first equalization signal; and a second equalization transistor, whose gate is used to receive a second equalization signal, one of its source or drain is connected to a second bit line, and the other is used to receive a second pre-charge voltage, for pre-charging the second bit line, the second complementary bit line, and the second sensing amplification structure to the second pre-charge voltage based on the second equalization signal.

[0012] In addition, the first equalization signal and the second equalization signal are the same equalization signal, and the first pre-charge voltage and the second pre-charge voltage are the same pre-charge voltage.

[0013] In addition, the drains of the first equalizer and the second equalizer are connected to receive the same pre-charge voltage.

[0014] In addition, the structural layer also includes a third sensing amplification structure and a fourth sensing amplification structure. The third sensing amplification structure is connected to one of the adjacent memory arrays via a third bit line and to another adjacent memory array via a third complementary bit line. The fourth sensing amplification structure is connected to one of the adjacent memory arrays via a fourth bit line and to another adjacent memory array via a fourth complementary bit line. One of the third bit line or the third complementary bit line is disposed in the first interconnect layer, and the other is at least partially disposed in the second interconnect layer. One of the fourth bit line or the fourth complementary bit line is disposed in the first interconnect layer, and the other is at least partially disposed in the second interconnect layer. An equalization structure is directly connected to the third complementary bit line and the fourth bit line for pre-charging the third bit line, the third complementary bit line, the third sensing amplification structure, the fourth bit line, the fourth complementary bit line, and the fourth sensing amplification structure. The equalization structure is directly connected to the third complementary bit line and the fourth bit line in the first interconnect layer.

[0015] In addition, the equalization structure also includes: a third equalization transistor, disposed on one side of the first equalization transistor in the word line extension direction, sharing the same gate with the first equalization transistor, with one of its source or drain connected to the third complementary bit line, and the other used to receive the first pre-charge voltage, for pre-charging the third bit line, the third complementary bit line, and the third sensing amplification structure to the first pre-charge voltage based on the first equalization signal; and a fourth equalization transistor, disposed on one side of the second equalization transistor in the word line extension direction, sharing the same gate with the second equalization transistor, with one of its source or drain connected to the fourth bit line, and the other used to receive the second pre-charge voltage, for pre-charging the fourth bit line, the fourth complementary bit line, and the fourth sensing amplification structure to the second pre-charge voltage based on the second equalization signal.

[0016] In addition, the structural layer also includes a first data readout module and a second data readout module. The first data readout module includes: a first input / output transistor, a third input / output transistor, a fifth input / output transistor, and a seventh input / output transistor. The source of the first input / output transistor is connected to the first input / output line, and the drain is connected to the first bit line. The source of the third input / output transistor is connected to the third input / output line, and the drain is connected to the second bit line. The source of the fifth input / output transistor is connected to the fifth input / output line, and the drain is connected to the third bit line. The source of the seventh input / output transistor is connected to the seventh input / output line, and the drain is connected to the fourth bit line. The first, second, third, and fourth bit lines are four adjacent bit lines in the same memory array. The gates of the first, third, fifth, and seventh input / output transistors are connected together to receive a column select signal and, based on the column select signal, turn on the first, third, fifth, and seventh input / output transistors. The second data readout module includes a second input / output transistor, a fourth input / output transistor, a sixth input / output transistor, and an eighth input / output transistor. The source of the second input / output transistor is connected to the second input / output line, and the drain is connected to the first complementary bit line. The source of the fourth input / output transistor is connected to the fourth input / output line, and the drain is connected to the second complementary bit line. The source of the sixth input / output transistor is connected to the sixth input / output line, and the drain is connected to the third complementary bit line. The source of the eighth input / output transistor is connected to the eighth input / output line, and the drain is connected to the fourth complementary bit line. The first, second, third, and fourth complementary bit lines are four adjacent bit lines in the same memory array. The gates of the second, fourth, sixth, and eighth input / output transistors are connected together to receive a column select signal and to turn on the second, fourth, sixth, and eighth input / output transistors based on the column select signal.

[0017] Additionally, the first sensing amplification structure includes: a sensing amplification module, connected to the first bit line via a readout bit line and connected to the first complementary bit line via a complementary readout bit line, for sensing the voltage of the memory cells of the memory array and outputting a logic 1 or 0 corresponding to the voltage; an isolation module, connected between the complementary readout bit line and the first complementary bit line, and also connected between the readout bit line and the first bit line, for isolating the signal interaction between the first bit line, the first complementary bit line and the readout bit line, and the complementary readout bit line according to an isolation signal; and an offset cancellation module, connected between the readout bit line and the first complementary bit line, and also connected between the complementary readout bit line and the first bit line, for adjusting the source-drain conduction difference between NMOS transistors or between PMOS transistors in the sensing amplification module according to an offset cancellation signal.

[0018] Additionally, the sensing amplification module includes: a first sensing amplification N-transistor, with its gate connected to the first bit line, its drain connected to the complementary read bit line, and its source connected to the second signal terminal. When the sensing amplification module is in the amplification stage, the second signal terminal is electrically connected to the voltage corresponding to logic 0; a second sensing amplification N-transistor, with its gate connected to the first complementary bit line, its drain connected to the read bit line, and its source connected to the second signal terminal; a first sensing amplification P-transistor, with its gate connected to the read bit line, its drain connected to the complementary read bit line, and its source connected to the first signal terminal. When the sensing amplification module is in the amplification stage, the first signal terminal is electrically connected to the voltage corresponding to logic 1; and a second sensing amplification P-transistor, with its gate connected to the complementary read bit line, its drain connected to the read bit line, and its source connected to the first signal terminal.

[0019] In addition, the gate structures of the first sensing amplification N-transistor, the second sensing amplification N-transistor, the first sensing amplification P-transistor, and the second sensing amplification P-transistor extend in the same direction. The gate structures of the MOS transistor in the isolation module and the MOS transistor in the offset elimination module extend in the same direction, and the gate structures of the first sensing amplification N-transistor and the MOS transistor in the isolation module extend perpendicularly to each other.

[0020] In addition, the first sensing amplifier P-tube, the second sensing amplifier P-tube, the isolation module, and the offset cancellation module are disposed between the first sensing amplifier N-tube and the second sensing amplifier N-tube.

[0021] In addition, the isolation module includes: a first isolation transistor, whose gate is used to receive the isolation signal, whose source is connected to the first bit line, and whose drain is connected to the read bit line; and a second isolation transistor, whose gate is used to receive the isolation signal, whose source is connected to the first complementary bit line, and whose drain is connected to the complementary read bit line.

[0022] In addition, the offset cancellation module includes: a first offset cancellation transistor, whose gate is used to receive the offset cancellation signal, whose source is connected to the first bit line, and whose drain is connected to the complementary read bit line; and a second offset cancellation transistor, whose gate is used to receive the offset cancellation signal, whose source is connected to the first complementary bit line, and whose drain is connected to the read bit line.

[0023] In addition, the source of the first isolation transistor and the source of the first offset cancellation transistor are connected and connected to the first bit line; the source of the second isolation transistor and the source of the second offset cancellation transistor are connected and connected to the first complementary bit line. Attached Figure Description

[0024] Figure 1 and Figure 2 A circuit diagram of the readout circuit structure provided in the embodiments of this application;

[0025] Figure 3 and Figure 4 The layout of the readout circuit structure provided in the embodiments of this application;

[0026] Figure 5 A layout of a balanced structure provided in an embodiment of this application;

[0027] Figure 6 This is a structural layer layout of another balanced structure provided in an embodiment of this application. Detailed Implementation

[0028] As can be seen from the background technology, the performance of existing DRAM technologies still needs to be improved.

[0029] The applicant discovered that existing sense amplifiers with offset compensation functions include the conduction process of switching transistors during the pre-charging process of the alignment line and complementary bit line, resulting in insufficient charging speed of the alignment line and complementary bit line. As the transistor size is further miniaturized, the saturation current of the switching transistor decreases, which exacerbates this situation and is detrimental to improving the read and write performance of the memory.

[0030] To address the aforementioned technical problems, this application provides a readout circuit structure disposed in the gaps between memory arrays, comprising: a structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; the structural layer contains a first sensing amplification structure, a second sensing amplification structure, and an equalization structure; the first sensing amplification structure is connected to one memory array in an adjacent memory array via a first bit line, and is also connected to another memory array in an adjacent memory array via a first complementary bit line; the second sensing amplification structure is connected to one memory array in an adjacent memory array via a second bit line, and is also connected to another memory array in an adjacent memory array via a second complementary bit line. A storage array; wherein one of a first bit line or a first complementary bit line is disposed in a first interconnect layer, and at least a portion of the other is disposed in a second interconnect layer; one of a second bit line or a second complementary bit line is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; an equalization structure is directly connected to the first complementary bit line and the second bit line for pre-charging the first bit line, the first complementary bit line, the first sensing amplification structure, the second bit line, the second complementary bit line, and the second sensing amplification structure; wherein the equalization structure is disposed between the first sensing amplifier structure and the second sensing amplifier structure, and is directly connected to the first complementary bit line and the second bit line in the first interconnect layer.

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the various embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0032] Figure 1 and Figure 2 This is a circuit diagram of the readout circuit structure provided in this embodiment. Figure 3 and Figure 4 The layout of the readout circuit structure provided in this embodiment Figure 5 This embodiment provides a layout of a balanced structure. Figure 6 The following is a detailed description of the readout circuit structure provided in this embodiment, in conjunction with the accompanying drawings, of another balanced structure:

[0033] It should be noted that, due to the large size of the circuit diagram and layout of the readout circuit structure, in order to clearly illustrate the readout circuit structure to be protected in this embodiment, the circuit diagram and layout are separated during the drafting process. Figure 1 and Figure 2 The circuit diagrams of the readout circuit structure provided in this embodiment are combined in the following way: Figure 1 bottom and Figure 2 The top of the merged array; Figure 3 and Figure 4 The layout of the readout circuit structure provided in this embodiment is merged in the following manner: Figure 3 bottom and Figure 4 The top of the merged list.

[0034] refer to Figures 1-4 The readout circuit structure, located in the gap between adjacent memory arrays, includes:

[0035] The storage array has n rows and m columns of storage cells. Each storage cell is used to store 1 bit of data. That is, a storage array can store n×mbit of data. During the data reading process, the data stored in the storage cell can be read out or written into the storage cell by selecting a specific storage cell.

[0036] A structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer, specifically, refer to... Figure 3 and Figure 4The structural layer is the layout on the right side of the diagram, the first interconnect layer is the layout in the middle part of the diagram, and the second interconnect layer is the layout on the left side of the diagram.

[0037] The structural layer is used to form the specific device structure in the readout circuit structure. In this embodiment, the structural layer is provided with a first sensing amplification structure, a second sensing amplification structure, a first equalization structure and a second equalization structure. The first interconnect layer is used to provide internal electrical connections of the sensing amplification structure and connect the bit lines or complementary bit lines of the closer one between adjacent memory arrays. The second interconnect layer is used to connect the bit lines or complementary bit lines of the sensing amplification structure to the bit lines or complementary bit lines of the farther one between adjacent memory arrays.

[0038] refer to Figure 1 and Figure 2 and combined Figure 3 and Figure 4 It can be seen that, in the bit line extension direction, the first sensing amplification structure and the second sensing amplification structure are arranged adjacently for sensing the voltage of the memory cell and outputting logic 1 or 0 corresponding to the voltage; wherein, the first sensing amplification structure is connected to one memory array of the adjacent memory array through the first bit line BL1, the first sensing amplification structure is connected to another memory array of the adjacent memory array through the first complementary bit line BLB1, the second sensing amplification structure is connected to one memory array of the adjacent memory array through the second bit line BL2, and the second sensing amplification structure is connected to another memory array of the adjacent memory array through the second complementary bit line BLB2.

[0039] For the first bit line BL1, the second bit line BL2, the first complementary bit line BLB1, and the second complementary bit line BLB2, one of the first bit line BL1 or the first complementary bit line BLB1 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the second bit line BL2 or the second complementary bit line BLB2 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer.

[0040] Specifically, in this embodiment, the first bit line BL1 is disposed in the first interconnect layer, at least a portion of the first complementary bit line BLB1 is disposed in the second interconnect layer, the first complementary bit line BLB1 passes through the region where the second sensing amplification structure is located in the second interconnect layer and is coupled to the first sensing amplification structure, the second bit line BL2 is disposed at least a portion in the second interconnect layer, the second bit line BL2 passes through the region where the first sensing amplification structure is located in the second interconnect layer and is coupled to the second sensing amplification structure, and the second complementary bit line BLB2 is disposed in the first interconnect layer.

[0041] The first complementary bit line BLB1 passes through the area where the second sensing amplification structure is located and couples with the first sensing amplification structure. That is, the first complementary bit line BLB1 does not need to occupy additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure. The second bit line BL2 passes through the area where the first sensing amplification structure is located and couples with the second sensing amplification structure. That is, the second bit line BL2 does not need to occupy additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure.

[0042] The equalization structure is directly connected to the first complementary bit line BLB1 and the second bit line BL2, and is used to precharge the first bit line BL1, the first complementary bit line BLB1, the first sensing amplification structure, the second bit line BL2, the second complementary bit line BLB2 and the second sensing amplification structure.

[0043] In this embodiment, the equalization structure is disposed between the first sensing amplification structure and the second sensing amplification structure, and is directly connected to the first complementary bit line BLB1 and the second bit line BL2 in the first interconnect layer.

[0044] The equalization structure includes a first equalization tube. <n1>Second equalization tube <n2>.

[0045] First equalizer tube <n1>The gate of the first equalization transistor is used to receive the first equalization signal EQ1. One of its source or drain is connected to the first complementary bit line BLB1, and the other is used to receive the first pre-charge voltage V1. This is used to pre-charge the first bit line BL1, the first complementary bit line BLB1, and the first sensing amplification structure to the first pre-charge voltage V1 based on the first equalization signal EQ1. In this embodiment, the first equalization transistor... <n1>The source is connected to the first complementary bit line BLB1, and the drain is used to receive the first pre-charge voltage V1. Based on the first equalization signal EQ1, the first bit line BL1, the first complementary bit line BLB1 and the first sensing amplification structure are pre-charged to the first pre-charge voltage V1.

[0046] Second equalizer tube <n2>The gate of the second equalization transistor is used to receive the second equalization signal EQ2. One of its source or drain is connected to the second bit line BL2, and the other is used to receive the second pre-charge voltage V2. Based on the second equalization signal EQ2, the second bit line BL2, the second complementary bit line BLB2, and the second sensing amplification structure are pre-charged to the second pre-charge voltage V2. In this embodiment, the second equalization transistor... <n2>The source is connected to the second bit line BL2, and the drain is used to receive the second pre-charge voltage V2. Based on the second equalization signal EQ2, the second bit line BL2, the second complementary bit line BLB2, and the second sensing amplification structure are pre-charged to the second pre-charge voltage V2.

[0047] It should be noted that the specific connection method of the "source" and "drain" in the above description does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" can be used instead of "source", and the connection method of "source" can also be used instead of "drain".

[0048] By directly connecting the bit line / complementary bit line through the equalizer, the bit line and complementary bit line are charged directly, avoiding the need for the switching transistor to be turned on during the pre-charging process, thus speeding up the charging speed of the bit line and complementary bit line.

[0049] It should be noted that the "first pre-charge voltage V1" and "second pre-charge voltage V2" mentioned above are the voltages required for pre-charging of the memory bit lines and complementary bit lines during the pre-charging stage. The specific voltage values ​​are set according to the pre-charge voltage required for normal operation of the memory. This embodiment does not constitute a limitation on the values ​​of "first pre-charge voltage V1" and "second pre-charge voltage V2".

[0050] In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, meaning the same control signal is used to precharge the bit lines and complementary bit lines. The first precharge voltage V1 and the second precharge voltage V2 are the same precharge voltage V. BLP In this embodiment, the pre-charge voltage V BLP =1 / 2V DD , where V DD This refers to the chip's internal power supply voltage; in other embodiments, the pre-charge voltage V... BLP It can be configured according to the specific application scenario.

[0051] Furthermore, in this embodiment, the first equalization tube <n1>The drain and the second equalization tube <n2>The drains are connected to receive the same precharge voltage V. BLP Through the first equalization tube <n1>The drain and the second equalization tube <n2>The drains are connected, which can reduce the first equalization transistor. <n1>Second equalization tube <n2>The spacing is set to reduce the layout area of ​​the readout circuit structure.

[0052] In this embodiment, in order to clearly distinguish between the above-mentioned one memory array and the other memory array, in the following description, the memory array connected by the first sensing amplification structure through the first bit line BL1 is referred to as the "first memory array"; and the memory array connected by the second sensing amplification structure through the second complementary bit line BLB2 is referred to as the "second memory array".

[0053] Furthermore, in the word line extension direction, there is not only one set of sensing amplification structures between adjacent memory arrays. This embodiment uses a 2x2 layout structure as an example for detailed explanation, as follows:

[0054] In this embodiment, the structural layer also includes a third sensing amplification structure, a fourth sensing amplification structure, a third equalization structure, and a fourth equalization structure.

[0055] In the bit line extension direction, the third sensing amplification structure and the fourth sensing amplification structure are arranged adjacent to each other to sense the voltage of the memory cell and output logic 1 or 0 corresponding to the voltage; in the word line extension direction, the third sensing amplification structure and the first sensing amplification structure are arranged adjacent to each other, and the fourth sensing amplification structure and the second sensing amplification structure are arranged adjacent to each other.

[0056] The third sensing amplification structure is connected to the "first memory array" via the third bit line BL3 and to the "second memory array" via the third complementary bit line BLB3. The fourth sensing amplification structure is connected to the "first memory array" via the fourth bit line BL4 and to the "second memory array" via the fourth complementary bit line BLB4.

[0057] For the third bit line BL3, the fourth bit line BL4, the third complementary bit line BLB3, and the fourth complementary bit line BLB4, one of the third bit line BL3 or the third complementary bit line BLB3 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer; one of the fourth bit line BL4 or the fourth complementary bit line BLB4 is disposed in the first interconnect layer, and at least a portion of the other is disposed in the second interconnect layer.

[0058] It should be noted that the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 are four adjacent bit lines in the same memory array; the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4 are four adjacent bit lines in the same memory array.

[0059] Specifically, in this embodiment, the third bit line BL3 is disposed in the first interconnect layer, at least a portion of the third complementary bit line BLB3 is disposed in the second interconnect layer, the third complementary bit line BLB3 passes through the region where the fourth sensing amplification structure is located in the second interconnect layer and is coupled to the third sensing amplification structure, the fourth bit line BL4 is at least a portion disposed in the second interconnect layer, the fourth bit line BL4 passes through the region where the third sensing amplification structure is located in the second interconnect layer and is coupled to the fourth sensing amplification structure, and the fourth complementary bit line BLB4 is disposed in the first interconnect layer.

[0060] The third complementary bit line BLB3 passes through the area where the second sensing amplification structure is located and couples with the first sensing amplification structure. That is, the third complementary bit line BLB3 does not need to occupy additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure. The fourth bit line BL4 passes through the area where the first sensing amplification structure is located and couples with the second sensing amplification structure. That is, the fourth bit line BL4 does not need to occupy additional layout area to complete the routing, thereby reducing the layout area of ​​the readout circuit structure.

[0061] The equalization structure is also directly connected to the third complementary bit line BLB3 and the fourth bit line BL4 for pre-charging the third bit line BL3, the third complementary bit line BLB3, the third sensing amplification structure, the fourth bit line BL4, the fourth complementary bit line BLB4, and the fourth sensing amplification structure.

[0062] In this embodiment, the equalization structure is also directly connected to the third complementary bit line BLB3 and the fourth bit line BL4 in the first interconnect layer.

[0063] Specifically, the equilibrium structure also includes a third equilibrium tube. <n3>and the fourth equalization tube <n4>In the direction of word line extension, the third equalizer tube <n3>Set in the first equalization tube <n1>On one side, with the first equalization tube <n1>Shared gate, fourth equalizer <n4>Set in the second equalization tube <n2>On one side, with the second equalization tube <n2>They share the same gate.

[0064] Third equalizer tube <n3>The gate of the transistor is used to receive the first equalization signal EQ1. One of its source or drain is connected to the third complementary bit line BLB3, and the other is used to receive the first pre-charge voltage V1. This is used to pre-charge the third bit line BL3, the third complementary bit line BLB3, and the third sensing amplification structure to the first pre-charge voltage V1 based on the first equalization signal EQ1. In this embodiment, the third equalization transistor... <n3>The source is connected to the third complementary bit line BLB3, and the drain is used to receive the first pre-charge voltage V1. Based on the first equalization signal EQ1, the third bit line BL3, the third complementary bit line BLB3 and the third sensing amplification structure are pre-charged to the first pre-charge voltage V1.

[0065] Fourth equalization tube <n4>The gate of the transistor is used to receive the second equalization signal EQ2. One of its source or drain is connected to the fourth bit line BL4, and the other is used to receive the second pre-charge voltage V2. This pre-charges the fourth bit line BL4, the fourth complementary bit line BLB4, and the fourth sensing amplification structure to the second pre-charge voltage V2 based on the second equalization signal EQ2. In this embodiment, the fourth equalization transistor... <n4>The source is connected to the fourth bit line BL4, and the drain is used to receive the second pre-charge voltage V2. Based on the second equalization signal EQ2, the fourth bit line BL4, the fourth complementary bit line BLB4 and the fourth sensing amplification structure are pre-charged to the second pre-charge voltage V2.

[0066] It should be noted that the specific connection method of the "source" and "drain" in the above description does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" can be used instead of "source", and the connection method of "source" can also be used instead of "drain".

[0067] By directly connecting the bit line / complementary bit line through the equalizer, the bit line and complementary bit line are charged directly, avoiding the need for the switching transistor to be turned on during the pre-charging process, thus speeding up the charging speed of the bit line and complementary bit line.

[0068] It should be noted that the "first pre-charge voltage V1" and "second pre-charge voltage V2" mentioned above are the voltages required for pre-charging of the memory bit lines and complementary bit lines during the pre-charging stage. The specific voltage values ​​are set according to the pre-charge voltage required for normal operation of the memory. This embodiment does not constitute a limitation on the values ​​of "first pre-charge voltage V1" and "second pre-charge voltage V2".

[0069] In one example, the first equalization signal EQ1 and the second equalization signal EQ2 are the same equalization signal, meaning the same control signal is used to precharge the bit lines and complementary bit lines. The first precharge voltage V1 and the second precharge voltage V2 are the same precharge voltage V. BLP In this embodiment, the pre-charge voltage V BLP =1 / 2V DD , where V DD This refers to the chip's internal power supply voltage; in other embodiments, the pre-charge voltage V... BLP It can be configured according to the specific application scenario.

[0070] Furthermore, in this embodiment, the third equalization tube <n3>The drain and the fourth equalization transistor <n4>The drains are connected to receive the same precharge voltage V. BLP Through the third equalization tube <n3>The drain and the fourth equalization transistor <n4>The drains are connected, which can reduce the third equalization transistor. <n3>and the fourth equalization tube <n4>The spacing is set to reduce the layout area of ​​the readout circuit structure.

[0071] Continue to refer to Figure 1 and Figure 2 The readout circuit structure also includes a first data readout module, which includes a first input / output transistor, a third input / output transistor, a fifth input / output transistor, and a seventh input / output transistor.

[0072] In this embodiment, one of the sources or drains of the first input / output transistor is directly connected to the first input / output line, and the other is connected to the first bit line. The gate of the first input / output transistor is used to receive the column select signal and conducts the first input / output transistor based on the column select signal, so that the first input / output line is electrically connected to the first bit line, thereby outputting the electrical signal carried in the first bit line through the first input / output line. In this embodiment, the source of the first input / output transistor is connected to the first input / output line, and the drain is connected to the first bit line.

[0073] One of the sources or drains of the third input / output transistor is directly connected to the third input / output line, and the other is connected to the second bit line. The gate of the third input / output transistor is used to receive the column select signal and conducts the third input / output transistor based on the column select signal, so that the third input / output line is electrically connected to the second bit line, thereby outputting the electrical signal carried in the second bit line through the third input / output line. In this embodiment, the source of the third input / output transistor is connected to the third input / output line, and the drain is connected to the second bit line.

[0074] One of the sources or drains of the fifth input / output transistor is directly connected to the fifth input / output line, and the other is connected to the third bit line. The gate of the fifth input / output transistor is used to receive the column select signal and conducts the fifth input / output transistor based on the column select signal, so that the fifth input / output line is electrically connected to the third bit line, thereby outputting the electrical signal carried in the third bit line through the fifth input / output line. In this embodiment, the source of the fifth input / output transistor is connected to the fifth input / output line, and the drain is connected to the third bit line.

[0075] One of the sources or drains of the seventh input / output transistor is directly connected to the seventh input / output line, and the other is connected to the fourth bit line. The gate of the seventh input / output transistor is used to receive the column select signal and conducts the seventh input / output transistor based on the column select signal, so that the seventh input / output line is electrically connected to the fourth bit line, thereby outputting the electrical signal carried in the fourth bit line through the seventh input / output line. In this embodiment, the source of the seventh input / output transistor is connected to the seventh input / output line, and the drain is connected to the fourth bit line.

[0076] It should be noted that the specific connection method of the "source" and "drain" in the above description does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" can be used instead of "source", and the connection method of "source" can also be used instead of "drain".

[0077] The second data readout module includes: a second input / output tube, a fourth input / output tube, a sixth input / output tube, and an eighth input / output tube.

[0078] In this embodiment, one of the sources or drains of the second input / output transistor is directly connected to the second input / output line, and the other is connected to the first complementary bit line. The gate of the second input / output transistor is used to receive the column select signal and conducts the second input / output transistor based on the column select signal, so that the second input / output line is electrically connected to the first complementary bit line, thereby outputting the electrical signal carried in the first complementary bit line through the second input / output line. In this embodiment, the source of the second input / output transistor is connected to the second input / output line, and the drain is connected to the first complementary bit line.

[0079] One of the sources or drains of the fourth input / output transistor is directly connected to the fourth input / output line, and the other is connected to the second complementary bit line. The gate of the fourth input / output transistor is used to receive the column select signal and conducts the fourth input / output transistor based on the column select signal, so that the fourth input / output line is electrically connected to the second complementary bit line, thereby outputting the electrical signal carried in the second complementary bit line through the fourth input / output line. In this embodiment, the source of the fourth input / output transistor is connected to the fourth input / output line, and the drain is connected to the second complementary bit line.

[0080] One of the sources or drains of the sixth input / output transistor is directly connected to the sixth input / output line, and the other is connected to the third complementary bit line. The gate of the sixth input / output transistor is used to receive the column select signal and conducts the sixth input / output transistor based on the column select signal, so that the sixth input / output line is electrically connected to the third complementary bit line, thereby outputting the electrical signal carried in the third complementary bit line through the sixth input / output line. In this embodiment, the source of the sixth input / output transistor is connected to the sixth input / output line, and the drain is connected to the third complementary bit line.

[0081] One of the sources or drains of the eighth input / output transistor is directly connected to the eighth input / output line, and the other is connected to the fourth complementary bit line. The gate of the eighth input / output transistor is used to receive the column select signal and conducts the eighth input / output transistor based on the column select signal, so that the eighth input / output line is electrically connected to the fourth complementary bit line, thereby outputting the electrical signal carried in the fourth complementary bit line through the eighth input / output line. In this embodiment, the source of the eighth input / output transistor is connected to the eighth input / output line, and the drain is connected to the fourth complementary bit line.

[0082] It should be noted that the specific connection method of the "source" and "drain" in the above description does not constitute a limitation on this embodiment. In other embodiments, the connection method of "drain" can be used instead of "source", and the connection method of "source" can also be used instead of "drain".

[0083] refer to Figure 1 Regarding the first sensing amplification structure and the third sensing amplification structure, the following detailed explanation will take the first sensing amplification structure as an example. The first sensing amplification structure includes:

[0084] The sensing amplification module is connected to the first bit line BL1 via the readout bit line SABL and to the first complementary bit line BLB1 via the complementary readout bit line SABLB. It is used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage.

[0085] Specifically, the sensing amplification module includes: a first sensing amplification N-transistor. <n1400>The gate is connected to the first bit line BL1, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS. When the sensing amplification module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; the second sensing amplification N-transistor <n1405>The gate is connected to the first complementary bit line BLB1, the drain is connected to the readout bit line SABL, and the source is connected to the second signal terminal NCS; the first sensing amplifier P-tube... <p1401>The gate is connected to the readout bit line SABL, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the first signal terminal PCS. When the sensing amplification module is in the amplification stage, the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1; the second sensing amplification P-tube... <p1400>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, and the source is connected to the first signal terminal PCS.

[0086] An isolation module is connected between the complementary readout bit line SABLB and the first complementary bit line BLB1, and between the readout bit line SABL and the first bit line BL1, for isolating the signal interaction between the first bit line BL1, the first complementary bit line BLB1 and the readout bit line SABL and the complementary readout bit line SABLB according to the isolation signal ISO.

[0087] Specifically, the isolation module includes: a first isolation tube. <n1402>The gate is used to receive the isolation signal ISO, the source is connected to the first bit line BL1, and the drain is connected to the read bit line SABL. The second isolation transistor... <n1403>The gate is used to receive the isolation signal ISO, the source is connected to the first complementary bit line BLB1, and the drain is connected to the complementary readout bit line SABLB.

[0088] An offset cancellation module is connected between the readout bit line SABL and the first complementary bit line BLB1, and between the complementary readout bit line SABLB and the first bit line BL1. It is used to adjust the source-drain conduction difference between NMOS transistors or PMOS transistors in the sensing amplification module according to the offset cancellation signal OC.

[0089] It should be noted that the "source-drain conduction difference" mentioned above refers to the difference in conduction between the first sensing amplifier N-tube and the source-drain conduction difference due to variations in manufacturing processes, temperature, etc. <n1400>Second sensing amplifier N-tube <n1405>and the first sensing amplifier P-tube <p1401>Second sensing amplifier P-tube <p1400>They can have different threshold voltages. In this case, the sensing amplification module may be affected by the first sensing amplification P-tube. <p1401>Second sensing amplifier P-tube <p1400>and the first sensing amplifier N-tube <n1400>Second sensing amplifier N-tube <n1405>The difference between the threshold voltages leads to offset noise.

[0090] Specifically, the offset elimination module includes: a first offset elimination tube. <n1401>The gate is used to receive the offset cancellation signal OC, the source is connected to the first bit line BL1, and the drain is connected to the complementary readout bit line SABLB; the second offset cancellation transistor... <n1404>The gate is used to receive the offset cancellation signal OC, the source is connected to the first complementary bit line BLB1, and the drain is connected to the readout bit line SABL.

[0091] Those skilled in the art will recognize that the structure of the third sensing amplification structure is identical to that of the first sensing amplification structure, and the same applies to the above description after corresponding feature substitutions. Specifically, the corresponding structure includes: the first bit line BL1 corresponding to BL3, the first complementary bit line BLB1 corresponding to BLB3, and the first equalization tube. <n1>Corresponding to <n5>Third equalization tube <n3>Corresponding to <n7>First sensing amplifier N-tube <n1400>Corresponding to <n1410>Second sensing amplifier N-tube <n1405>Corresponding to <n1415>First sensing amplifier P-tube <p1401>Corresponding to <p1411>Second sensing amplifier P-tube <p1400>Corresponding to <p1410>First isolation tube <n1402>Corresponding to <n1412>Second isolation tube <n1403>Corresponding to <n1413>First offset elimination tube <n1401>Corresponding to <n1411>Second offset elimination tube <n1404>Corresponding to <n1414>.

[0092] For the first data readout module, the source of the first input / output transistor is connected to the first input / output line I / O1, the drain is directly connected to the first bit line BL1, and the gate is used to receive the column select signal CY. The source of the third input / output transistor is connected to the third input / output line I / O3, the drain is directly connected to the second bit line BL2, and the gate is used to receive the column select signal CY. The source of the fifth input / output transistor is connected to the fifth input / output line I / O5, the drain is directly connected to the third bit line BL3, and the gate is used to receive the column select signal CY. The source of the seventh input / output transistor is connected to the seventh input / output line I / O7, the drain is directly connected to the fourth bit line BL4, and the gate is used to receive the column select signal CY.

[0093] By using the same column selection signal CY, the first input / output transistor, the third input / output transistor, the fifth input / output transistor, and the seventh input / output transistor are turned on, thereby deriving the level signal transmitted in the first bit line BL1 through the first input / output line I / O1, the level signal transmitted in the second bit line BL2 through the third input / output line I / O3, the level signal transmitted in the third bit line BL3 through the fifth input / output line I / O5, and the level signal transmitted in the fourth bit line BL4 through the seventh input / output line I / O7.

[0094] refer to Figure 2 Regarding the second sensing amplification structure and the fourth sensing amplification structure, the second sensing amplification structure will be described in detail below as an example. The second sensing amplification structure includes:

[0095] The sensing amplification module is connected to the second bit line BL2 via the readout bit line SABL and to the second complementary bit line BLB2 via the complementary readout bit line SABLB. It is used to sense the voltage of the memory cell and output a logic 1 or 0 corresponding to the voltage.

[0096] Specifically, the sensing amplification module includes: a third sensing amplification N-transistor. <n1425>The gate is connected to the second bit line BL2, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the second signal terminal NCS. When the sensing amplification module is in the amplification stage, the second signal terminal NCS is electrically connected to the voltage corresponding to logic 0; the fourth sensing amplification N-transistor <n1420>The gate is connected to the second complementary bit line BLB2, the drain is connected to the readout bit line SABL, and the source is connected to the second signal terminal NCS; the third sensing amplifier P-tube... <p1421>The gate is connected to the readout bit line SABL, the drain is connected to the complementary readout bit line SABLB, and the source is connected to the first signal terminal PCS. When the sensing amplification module is in the amplification stage, the first signal terminal PCS is electrically connected to the voltage corresponding to logic 1; the fourth sensing amplification P-transistor <p1420>The gate is connected to the complementary read bit line SABLB, the drain is connected to the read bit line SABL, and the source is connected to the first signal terminal PCS.

[0097] An isolation module is connected between the complementary readout bit line SABLB and the second complementary bit line BLB2, and between the readout bit line SABL and the second bit line BL2, for isolating the signal interaction between the second bit line BL2, the second complementary bit line BLB2 and the readout bit line SABL and the complementary readout bit line SABLB according to the isolation signal ISO.

[0098] Specifically, the isolation module includes: a first isolation tube. <n1423>The gate is used to receive the isolation signal ISO, the source is connected to the second bit line BL2, and the drain is connected to the read bit line SABL. (Second isolation transistor) <n1422>The gate is used to receive the isolation signal ISO, the source is connected to the second complementary bit line BLB2, and the drain is connected to the complementary readout bit line SABLB.

[0099] An offset cancellation module is connected between the readout bit line SABL and the second complementary bit line BLB2, and between the complementary readout bit line SABLB and the second bit line BL2. It is used to adjust the source-drain conduction difference between NMOS transistors or PMOS transistors in the sensing amplification module according to the offset cancellation signal OC.

[0100] It should be noted that the "source-drain conduction difference" mentioned above refers to the difference in conduction between the third sensing amplifier N-tube and the source-drain conduction difference due to variations in manufacturing processes, temperature, etc. <n1425>and the fourth sensing amplifier N-tube <n1420>and the third sensing amplifier P-tube <p1421>and the fourth sensing amplifier P-tube <p1420>They can have different threshold voltages. In this case, the sensing amplification module may be affected by the third sensing amplification P-tube. <p1421>and the fourth sensing amplifier P-tube <p1420>and the third sensing amplifier N-tube <n1445>and the fourth sensing amplifier N-tube <n1420>The difference between the threshold voltages leads to offset noise.

[0101] Specifically, the offset elimination module includes: a third offset elimination tube. <n1424>The gate is used to receive the offset cancellation signal OC, the source is connected to the second bit line BL2, and the drain is connected to the complementary readout bit line SABLB; the fourth offset cancellation transistor... <n1421>The gate is used to receive the offset cancellation signal OC, the source is connected to the second complementary bit line BLB2, and the drain is connected to the readout bit line SABL.

[0102] Those skilled in the art will recognize that the structure of the fourth sensing amplification structure is identical to that of the second sensing amplification structure, and the same applies to the above description after corresponding structural feature substitutions. Specifically, the corresponding structure includes: the second bit line BL2 corresponding to BL4, the second complementary bit line BLB2 corresponding to BLB4, and the second equalization tube. <n2>Corresponding to <n6>Fourth equalization tube <n4>Corresponding to <n8>Third sensing amplifier N-tube <n1425>Corresponding to <n1435>Fourth sensing amplifier N-tube <n1420>Corresponding to <n1430>Third sensing amplifier P-tube <p1421>Corresponding to <p1431>Fourth sensing amplifier P-tube <p1420>Corresponding to <p1430>Third isolation tube <n1423>Corresponding to <n1433>Fourth isolation tube <n1422>Corresponding to <n1432>Third offset elimination tube <n1424>Corresponding to <n1434>Fourth offset elimination tube <n1421>Corresponding to <n1431>.

[0103] For the second data readout module, the source of the second input / output transistor is connected to the second input / output line I / O2, the drain is directly connected to the first complementary bit line BLB1, and the gate is used to receive the column select signal CY. The source of the fourth input / output transistor is connected to the fourth input / output line I / O4, the drain is directly connected to the second complementary bit line BLB2, and the gate is used to receive the column select signal CY. The source of the sixth input / output transistor is connected to the sixth input / output line I / O6, the drain is directly connected to the third complementary bit line BLB3, and the gate is used to receive the column select signal CY. The source of the eighth input / output transistor is connected to the eighth input / output line I / O8, the drain is directly connected to the fourth complementary bit line BLB4, and the gate is used to receive the column select signal CY.

[0104] By using the same column selection signal CY, the second, fourth, sixth, and eighth input / output transistors are turned on, thereby deriving the level signal transmitted in the first complementary bit line BLB1 through the second input / output line I / O2, the level signal transmitted in the second complementary bit line BLB2 through the fourth input / output line I / O4, the level signal transmitted in the third complementary bit line BLB3 through the sixth input / output line I / O6, and the level signal transmitted in the fourth complementary bit line BLB4 through the eighth input / output line I / O8.

[0105] refer to Figure 3 The left side shows the layout of the second interconnect layer, the middle side shows the layout of the first interconnect layer, and the right side shows the layout of the structural layer. Areas with the same number represent areas that need to be electrically connected in different layer layouts. The slanted frame area is the layout of the active layer, the white frame area is the layout of the gate layer, and the shaded area is the layout of the contact layer.

[0106] The following explanation uses the first sensing amplification structure as an example. The third sensing amplification structure can be compared analogously with the attached diagram; it will not be elaborated further in this embodiment. The structural layer layout, from top to bottom, is as follows:

[0107] First data readout module, first sensing amplifier N-transistor <n1425>An integrated module for first isolation and offset cancellation, and a second sensing amplification P-tube. <p1400>First sensing amplifier P-tube <p1401>The integrated module for second isolation and offset cancellation, and the second sensing amplifier N-tube. <n1405>And a partially balanced structure.

[0108] For the first data readout module, the first input / output transistor <n1001>Gate, third input / output transistor <n1003>Gate, fifth input / output transistor <n1005>Gate and seventh input / output transistor <n1007>The gates of the transistors are connected together to receive the same column select signal CY. Specifically, they are connected to the first interconnect layer via contact area 109, and in the first interconnect layer, they are connected to the second interconnect layer via contact 201 to receive the column select signal CY. That is, the readout circuit structure of this embodiment can read the data stored in four consecutive memory cells through four consecutive bit lines arranged in parallel, based on the same column select signal. It should be noted that in specific applications, the number of input / output transistors controlled by the same column select signal can also be set according to actual needs, i.e., the amount of data to be read through the same column select signal.

[0109] In addition, as shown in the figure, the first input / output transistor <n1001>Third input / output tube <n1003>Fifth input / output transistor <n1005>and the seventh input / output tube <n1007>The staggered arrangement includes contact areas 105, 106, 107, and 108 between the "H"-shaped gates, which are used to connect the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4, respectively. Contact areas 101, 102, 103, and 104 outside the "H"-shaped gates are used to connect to I / O1, I / O3, I / O5, and I / O7 on the first interconnect layer, respectively.

[0110] Furthermore, in the direction of word line extension, the spacing between the first bit line BL1, the second bit line BL2, the third bit line BL3, and the fourth bit line BL4 connected to the first data readout module is equal.

[0111] For the first sensing amplifier N-tube <n1400>The gate is connected to the first interconnect layer through contact regions 110 and 116, and the first bit line BL1 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 118, and the first complementary read bit line SABLB1 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 112, and the first interconnect layer is connected to the second interconnect layer through contact region 204. The second interconnect layer is used to contact the second control signal NCS, which is used to provide a low-level signal during the readout phase.

[0112] For the integrated module of first isolation and offset elimination, including the first offset elimination tube <n1401>and the first isolation tube <n1402>First offset elimination tube <n1401>and the first isolation tube <n1402>A common source electrode is connected to the first interconnect layer via contact region 120. The first bit line BL1 is connected to the first interconnect layer, and the first offset elimination transistor is also connected to it. <n1401>The drain is connected to the first interconnect layer via contact region 118, and the first complementary read bit line SABLB1 and the first isolation tube are connected to the first interconnect layer. <n1402>The drain is connected to the first interconnect layer through contact area 122, and the first read bit line SABL1 is connected to the first interconnect layer.

[0113] For the second sensing amplifier P-tube <p1400>The gate is connected to the first interconnect layer through contact regions 124 and 129, and the first complementary read bit line SABLB1 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 126, and the first read bit line SABLB1 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 127, and the first interconnect layer is connected to the second interconnect layer through contact region 206. The second interconnect layer receives a first control signal PCS, which is used to provide a high-level signal during the readout phase.

[0114] For the first sensing amplifier P-tube <p1401>The gate is connected to the first interconnect layer through contact regions 130 and 135, and the first read bit line SABL1 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 132, and the first complementary read bit line SABLB1 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 131, and the first interconnect layer is connected to the second interconnect layer through contact region 207. The first control signal PCS is received in the second interconnect layer.

[0115] For the integrated module of second isolation and offset elimination, including the second isolation tube <n1403>Second offset elimination tube <n1404>Second isolation tube <n1403>Second offset elimination tube <n1404>A common source is connected to the first interconnect layer via contact region 139, and a first complementary bit line BLB1 is connected to the first interconnect layer. A second isolation transistor is also connected. <n1403>The drain is connected to the first interconnect layer via contact region 137, and the first complementary readout bit line SABLB1 and the second offset cancellation transistor are connected to the first interconnect layer. <n1404>The drain is connected to the first interconnect layer through contact area 141, and the first read bit line SABL1 is connected to the first interconnect layer.

[0116] For the second sensing amplifier N-tube <n1405>The gate is connected to the first interconnect layer through contact regions 143 and 148, and the first complementary bit line BLB1 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 145, and the first read bit line SABL1 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 146, and the first interconnect layer is connected to the second interconnect layer through contact region 209. The second interconnect layer is used to contact the second control signal NCS, which is used to provide a low-level signal during the readout phase.

[0117] refer to Figure 4 The left side shows the layout of the second interconnect layer, the middle side shows the layout of the first interconnect layer, and the right side shows the layout of the structural layer. Areas with the same number represent areas that need to be electrically connected in different layer layouts. The slanted frame area is the layout of the active layer, the white frame area is the layout of the gate layer, and the shaded area is the layout of the contact layer.

[0118] The following explanation uses the second sensing amplification structure as an example. The fourth sensing amplification structure can be compared analogously with the attached diagram; it will not be elaborated further in this embodiment. The structural layer layout, from top to bottom, consists of: a partial equalization structure, and the fourth sensing amplification N-transistor. <n1425>The fourth integrated module for isolation and offset cancellation, and the third sensing amplifier P-tube. <p1421>Fourth sensing amplifier P-tube <p1420>Integrated module for third isolation and offset cancellation, and third sensing amplifier N-tube. <n1420>Second data reading module.

[0119] For the fourth sensing amplifier N-tube <n1425>For the fourth sensing amplifier N-tube <n1425>The gate is connected to the first interconnect layer through contact regions 342 and 348, and the second bit line BL2 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 345, and the second complementary readout bit line SABLB2 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 344, and the first interconnect layer is connected to the second interconnect layer through contact region 408. The second interconnect layer is used to contact the second control signal NCS, which is used to provide a low-level signal during the readout phase.

[0120] For the integrated module of fourth isolation and offset elimination, and for the integrated module of second isolation and offset elimination, including the fourth isolation tube... <n1423>and the fourth offset elimination tube <n1424>Fourth isolation tube <n1423>and the fourth offset elimination tube <n1424>The source electrode is shared and connected to the first interconnect layer via contact region 338. The second bit line BL2 and the fourth isolation transistor are connected to the first interconnect layer. <n1423>The drain is connected to the first interconnect layer via contact region 336, and the second read bit line SABL2 and the fourth offset cancellation transistor are connected to the first interconnect layer. <n1424>The drain is connected to the first interconnect layer via contact region 340, and the second complementary readout bit line SABLB2 is connected to the first interconnect layer.

[0121] For the third sensing amplifier P-tube <p1421>For the third sensing amplifier P-tube <p1421>The gate is connected to the first interconnect layer through contact region 334, and the second complementary read bit line SABLB2 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 331, and the second read bit line SABLB2 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 332, and the first interconnect layer is connected to the second interconnect layer through contact region 407. The first control signal PCS is received in the second interconnect layer.

[0122] For the fourth sensing amplifier P-tube <p1420>For the fourth sensing amplifier P-tube <p1420>The gate is connected to the first interconnect layer through contact region 323, and the second read bit line SABL2 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 326, and the second complementary read bit line SABLB2 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 325, and the first interconnect layer is connected to the second interconnect layer through contact region 405. The first control signal PCS is received on the second interconnect layer. The first control signal PCS is used to provide a high-level signal during the readout phase.

[0123] For the integrated module of third isolation and offset elimination, including the third offset elimination tube <n1421>and the third isolation tube <n1422>Third offset elimination tube <n1421>and the third isolation tube <n1422>A common source is connected to the first interconnect layer via contact region 319. A second complementary bit line BLB2 is connected to the first interconnect layer, along with a third offset cancellation transistor. <n1421>The drain is connected to the first interconnect layer via contact region 317, and the second read bit line SABL2 is connected to the first interconnect layer. The third isolation transistor is also connected to the first interconnect layer. <n1422>The drain is connected to the first interconnect layer via contact region 321, and the second complementary readout bit line SABLB2 is connected to the first interconnect layer.

[0124] For the third sensing amplifier N-tube <n1420>The gate is connected to the first interconnect layer through contact regions 310 and 315, and the second complementary bit line BLB2 is connected to the first interconnect layer. The source is connected to the first interconnect layer through contact region 312, and the second read bit line SABL2 is connected to the first interconnect layer. The drain is connected to the first interconnect layer through contact region 313, and the first interconnect layer is connected to the second interconnect layer through contact region 404. The second interconnect layer is used to contact the second control signal NCS, which is used to provide a low-level signal during the readout phase.

[0125] For the second data readout module, the second input / output transistor <n1002>Gate, fourth input / output transistor <n1004>Gate, sixth input / output transistor <n1006>Gate and eighth input / output transistor <n1008>The gates of the transistors are connected together to receive the same column select signal CY. Specifically, they are connected to the first interconnect layer via contact area 309, and in the first interconnect layer, they are connected to the second interconnect layer via contact area 401 to receive the column select signal CY. That is, the readout circuit structure of this embodiment can read the data stored in four consecutive memory cells through four complementary bit lines arranged in parallel, based on the same column select signal. It should be noted that in specific applications, the number of input / output transistors controlled by the same column select signal can also be set according to actual needs, i.e., the amount of data to be read through the same column select signal.

[0126] In addition, as shown in the figure, the second input / output transistor <n1002>Fourth input / output transistor <n1004>Sixth input / output transistor <n1006>and the eighth input / output tube <n1008>The gates are staggered, with the contact areas between the "H"-shaped gates used to connect the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4, respectively. The contact areas 301, 302, 303, and 304 outside the "H"-shaped gates are used to connect to I / O2, I / O4, I / O6, and I / O8, respectively, on the first interconnect layer.

[0127] Furthermore, in the direction of word line extension, the spacing between the first complementary bit line BLB1, the second complementary bit line BLB2, the third complementary bit line BLB3, and the fourth complementary bit line BLB4 connected to the second data readout module is equal.

[0128] for Figure 3 and Figure 4 Partial equilibrium structure in the middle, the merged structure reference Figure 5 The details are as follows:

[0129] First equalizer tube <n1>The source is connected to the first interconnect layer via contact region 152, and in the first interconnect layer is connected to the second interconnect layer via contact region 212, where it receives the pre-charge voltage V. BLP The drain is connected to the first interconnect layer through contact region 150, and in the first interconnect layer, it is connected to the first complementary bit line BLB1, i.e., the first equalization structure. <n1>Used to precharge the first complementary bit line BLB1. For the first complementary bit line BLB1, refer to... Figure 4 The first complementary bit line BLB1, located in the first interconnect layer, is connected to the second interconnect layer through contact areas 404 and 412. Wiring is performed in the second interconnect layer, thereby reducing the layout area of ​​the readout circuit structure.

[0130] Second equalizer tube <n2>The source is connected to the first interconnect layer via contact region 352, and in the first interconnect layer is connected to the second interconnect layer via contact region 412, where it receives the pre-charge voltage V. BLP The drain is connected to the first interconnect layer through contact region 350, and then connected to the second bit line BL2 in the first interconnect layer, which is the second equalization structure. <n2>Used to precharge the second bit line BL2. For the second bit line BL2, refer to... Figure 3 The second bit line BL2, located in the first interconnect layer, is connected to the second interconnect layer through contact areas 204 and 212. Wiring is performed in the second interconnect layer, thereby reducing the layout area of ​​the readout circuit structure.

[0131] Among them, the first equalization tube <n1>Second equalization tube <n2>They share the same source electrode; that is, contact regions 152 and 352 are the same contact region, and contact regions 212 and 412 located in the first interconnect layer are the same contact region. This is achieved through a first equalization transistor. <n1>Second equalization tube <n2>Shared source, i.e., the first equalization transistor <n1>Second equalization tube <n2>Shared active region, thereby reducing the first equalization tube <n1>Second equalization tube <n2>The spacing reduces the layout area of ​​the readout circuit structure.

[0132] Furthermore, refer to Figure 6 First equalization tube <n1>Gate and second equalization transistor <n2>The gate connection is used to receive the same equalization signal to precharge the first sensing amplification structure and the second sensing amplification structure.

[0133] Compared with related technologies, the equalization structure directly connects to the first bit line or the first complementary bit line for pre-charging; directly connects to the second bit line or the second complementary bit line for pre-charging; directly connects to the third bit line or the third complementary bit line for pre-charging; and directly connects to the fourth bit line or the fourth complementary bit line for pre-charging. By directly connecting the bit lines through the equalization structure, the bit lines are pre-charged directly, avoiding the need for switching transistors to be turned on during the pre-charging process, thus accelerating the charging speed of the bit lines. Furthermore, At least a portion of one of the first bit lines or the first complementary bit lines is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer; at least a portion of one of the second bit lines or the second complementary bit lines is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer; at least a portion of one of the third bit lines or the third complementary bit lines is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer; at least a portion of one of the fourth bit lines or the fourth complementary bit lines is disposed in the second interconnect layer, and the other is disposed in the first interconnect layer. By stacking the first interconnect layer and the second interconnect layer, the required layout structure in each layer is reduced, thereby reducing the layout area of ​​the readout circuit structure.

[0134] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A readout circuit structure, characterized in that, include: A structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; The structural layer is provided with transistors constituting a first sensing amplification structure, the structural layer includes a gate layer, and the first sensing amplification structure is adjacent to a first memory array and a second memory array. The first sensing amplification structure receives the first bit line signal in the first memory array through the first signal line, and the first sensing amplification structure receives the first complementary bit line signal of the second memory array through the first complementary signal line. Both the first signal line and the first complementary signal line include multiple transmission line segments connected in sequence. Adjacent transmission line segments are located in different conductive layers. The conductive layer includes the gate layer, the first interconnect layer, and the second interconnect layer. Some transmission line segments in the first signal line are located in the first interconnect layer, and each transmission line segment of the first signal line is not located in the second interconnect layer. Some transmission line segments in the first complementary signal line are located in the second interconnect layer.

2. The readout circuit structure according to claim 1, characterized in that, Adjacent transmission line segments on different conductive layers are electrically connected through a contact area.

3. The readout circuit structure according to claim 1, characterized in that, The first signal line includes a first transmission line, a second transmission line, and a third transmission line connected in sequence. The first transmission line is closer to the first memory array than the second transmission line. The first complementary signal line includes a fourth transmission line, a fifth transmission line, a sixth transmission line, and a seventh transmission line connected in sequence. The fourth transmission line is closer to the second memory array than the fifth transmission line. The first transmission line, the third transmission line, the fifth transmission line, and the seventh transmission line are located in the first interconnect layer, the second transmission line and the sixth transmission line are located in the gate layer, and the fourth transmission line is located in the second interconnect layer.

4. The readout circuit structure according to claim 3, characterized in that, The structural layer is further provided with transistors constituting a second sensing amplification structure. The second sensing amplification structure receives a second bit line signal from the first memory array through a second signal line. The first sensing amplification structure receives a second complementary bit line signal from the second memory array through a second complementary signal line. The fourth and fifth transmission lines pass through the region where the second sensing amplification structure is located and are then electrically connected to the sixth transmission line, which is located in the region where the first sensing amplification structure is located. The direction in which the first sensing amplification structure points to the second sensing amplification structure is the same as the direction in which the first storage array points to the second storage array.

5. The readout circuit structure according to claim 4, characterized in that, Both the second signal line and the second complementary signal line are composed of multiple transmission line segments connected in sequence. Adjacent transmission line segments are located in different conductive layers. Some transmission line segments in the second complementary signal line are located in the first interconnect layer, and each transmission line segment is not located in the second interconnect layer. Some transmission line segments in the second signal line are located in the second interconnect layer.

6. The readout circuit structure according to claim 5, characterized in that, The second signal line includes an eighth transmission line, a ninth transmission line, a tenth transmission line, and an eleventh transmission line connected in sequence. The eighth transmission line is closer to the first memory array than the ninth transmission line. The eighth transmission line is located in the second interconnect layer. The ninth and eleventh transmission lines are located in the first interconnect layer. The tenth transmission line is located in the gate layer. The eighth and ninth transmission lines pass through the region where the first sensing amplification structure is located and are electrically connected to the tenth transmission line. The tenth transmission line is located in the region where the second sensing amplification structure is located.

7. The readout circuit structure according to claim 6, characterized in that, The second complementary signal line includes a twelfth transmission line, a thirteenth transmission line, and a fourteenth transmission line connected in sequence. The twelfth transmission line is closer to the second memory array than the thirteenth transmission line. The twelfth and fourteenth transmission lines are located in the first interconnect layer, and the thirteenth transmission line is located in the gate layer.

8. The readout circuit structure according to claim 7, characterized in that, The first complementary signal line further includes a fifteenth transmission line segment connected in series between the fourth transmission line segment and the second memory array. The second signal line further includes a sixteenth transmission line segment connected in series between the eighth transmission line segment and the first memory array. The fifteenth and twelfth transmission lines are adjacent conductors of the first interconnect layer, and the sixteenth and first transmission lines are adjacent conductors of the first interconnect layer.

9. The readout circuit structure according to claim 1, characterized in that, The readout circuit structure is located between adjacent memory arrays.

10. The readout circuit structure according to claim 1, characterized in that, The structural layer is also provided with transistors that constitute the first data readout module and the second data readout module; The first data readout module includes a first input / output transistor, the source of which is connected to a first input / output line and the drain of which is electrically connected to the first signal line. The second data readout module includes a second input / output transistor, the source of which is connected to a second input / output line and the drain of which is electrically connected to the first complementary signal line.

11. The readout circuit structure according to claim 4, characterized in that, The structural layer is further provided with transistors constituting a third sensing amplification structure and a fourth sensing amplification structure. The third sensing amplification structure receives a third bit line signal in the first memory array through a third signal line and receives a third complementary bit line signal in the second memory array through a third complementary signal line. The fourth sensing amplification structure receives a fourth bit line signal in the first memory array through a fourth signal line and receives a fourth complementary bit line signal in the second memory array through a fourth complementary signal line. The third signal line, the third complementary signal line, the fourth signal line, and the fourth complementary signal line are all composed of multiple transmission line segments connected in sequence. Adjacent transmission line segments are located in different conductive layers. Some transmission line segments of the third signal line and the fourth complementary signal line are located in the first interconnect layer, and each transmission line segment is not located in the second interconnect layer. Some transmission line segments of the third complementary signal line and the fourth signal line are located in the second interconnect layer. The structural layer is also provided with transistors that constitute the first data readout module and the second data readout module; The first data readout module includes: a first input / output transistor, a third input / output transistor, a fifth input / output transistor, and a seventh input / output transistor; The source of the first input / output transistor is connected to the first input / output line, and the drain is electrically connected to the first signal line. The source of the third input / output transistor is connected to the third input / output line, and the drain is electrically connected to the second signal line. The source of the fifth input / output transistor is connected to the fifth input / output line, and the drain is electrically connected to the third signal line. The source of the seventh input / output transistor is connected to the seventh input / output line, and the drain is electrically connected to the fourth signal line. The gates of the first input / output transistor, the third input / output transistor, the fifth input / output transistor, and the seventh input / output transistor are connected together to receive a column selection signal and to turn on the first input / output transistor, the third input / output transistor, the fifth input / output transistor, and the seventh input / output transistor based on the column selection signal. The second data readout module includes a second input / output transistor, a fourth input / output transistor, a sixth input / output transistor, and an eighth input / output transistor; The source of the second input / output transistor is connected to the second input / output line, and its drain is electrically connected to the first complementary signal line. The source of the fourth input / output transistor is connected to the fourth input / output line, and its drain is electrically connected to the second complementary signal line. The source of the sixth input / output transistor is connected to the sixth input / output line, and its drain is electrically connected to the third complementary signal line. The source of the eighth input / output transistor is connected to the eighth input / output line, and its drain is electrically connected to the fourth complementary signal line. The gates of the second input / output transistor, the fourth input / output transistor, the sixth input / output transistor, and the eighth input / output transistor are connected together to receive the column select signal and to turn on the second input / output transistor, the fourth input / output transistor, the sixth input / output transistor, and the eighth input / output transistor based on the column select signal.

12. The readout circuit structure according to claim 1, characterized in that, The first sensing amplification structure includes a sensing amplification module, the sensing amplification module comprising: The first sensing amplifier N-transistor has its gate connected to the first signal line, its drain connected to the complementary readout bit line, and its source connected to the second signal terminal; the second sensing amplifier N-transistor has its gate connected to the first complementary signal line, its drain connected to the readout bit line, and its source connected to the second signal terminal. When the sensing amplification module is in the amplification stage, the second signal terminal is electrically connected to the voltage corresponding to logic 0, the first signal line is connected to the readout bit line, and the first complementary signal line is connected to the complementary readout bit line.

13. The readout circuit structure according to claim 12, characterized in that, A portion of the transmission line of the first signal line is the gate of the first sensing amplification N-transistor, a portion of the transmission line of the first complementary signal line is the gate of the second sensing amplification N-transistor, and the gate layer is the conductive layer where the gates of the first sensing amplification N-transistor and the second sensing amplification N-transistor are located.

14. The readout circuit structure according to claim 12, characterized in that, The sensing amplification module also includes: The first sensing amplifier P-tube has its gate connected to the readout bit line, its drain connected to the complementary readout bit line, and its source connected to the first signal terminal. When the sensing amplifier module is in the amplification stage, the first signal terminal is electrically connected to the voltage corresponding to logic 1. The second sensing amplifier P-tube has its gate connected to the complementary readout bit line, its drain connected to the readout bit line, and its source connected to the first signal terminal.

15. The readout circuit structure according to claim 12, characterized in that, The first sensing amplification structure further includes: An isolation module is connected between the complementary readout bit line and the first complementary signal line, and between the readout bit line and the first signal line, for isolating the signal interaction between the first signal line and the readout bit line according to the isolation signal, and isolating the signal interaction between the complementary readout bit line and the first complementary signal line; An offset cancellation module is connected between the readout bit line and the first complementary signal line, and between the complementary readout bit line and the first signal line, for adjusting the source-drain conduction difference between different NMOS transistors or different PMOS transistors in the sensing amplification module according to the offset cancellation signal.

16. The readout circuit structure according to claim 15, characterized in that, The first sensing amplification P-tube, the second sensing amplification P-tube, the isolation module, and the offset cancellation module are disposed between the first sensing amplification N-tube and the second sensing amplification N-tube.

17. The readout circuit structure according to claim 15, characterized in that, The gate structures of the first sensing amplification N-transistor, the second sensing amplification N-transistor, the first sensing amplification P-transistor, and the second sensing amplification P-transistor extend in the same direction. The gate structures of the MOS transistor in the isolation module and the MOS transistor in the offset elimination module extend in the same direction, and the gate structures of the first sensing amplification N-transistor and the MOS transistor in the isolation module extend perpendicularly to each other.

18. The readout circuit structure according to claim 15, characterized in that, The isolation module includes: The first isolation transistor has a gate for receiving the isolation signal, a source connected to the first signal line, and a drain connected to the readout bit line. The second isolation transistor has a gate for receiving the isolation signal, a source connected to the first complementary signal line, and a drain connected to the complementary readout bit line. The offset elimination module includes: The first offset cancellation transistor has a gate for receiving the offset cancellation signal, a source connected to the first signal line, and a drain connected to the complementary readout bit line. The second offset cancellation transistor has a gate for receiving the offset cancellation signal, a source connected to the first complementary signal line, and a drain connected to the readout bit line.

19. A readout circuit structure, characterized in that, include: A structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; The structural layer is provided with transistors constituting a first sensing amplification structure. The first sensing amplification structure is adjacent to the first memory array and the second memory array. The first sensing amplification structure includes a sensing amplification module. The sensing amplification module includes a first sensing amplification N-transistor and a second sensing amplification N-transistor. The sources of the first sensing amplification N-transistor and the second sensing amplification N-transistor are both connected to the second signal terminal. The first sensing amplification structure receives the first bit line signal in the first memory array through the first signal line, and the first sensing amplification structure receives the first complementary bit line signal in the second memory array through the first complementary signal line. When the sensing amplification module is in the amplification stage, the first signal line is electrically connected to the gate of the first sensing amplification N-transistor and the drain of the second sensing amplification N-transistor, and the second signal line is electrically connected to the gate of the second sensing amplification N-transistor and the drain of the first sensing amplification N-transistor. One of the first signal line or the first complementary signal line is at least partially disposed in the first interconnect layer, and the other of the first signal line or the first complementary signal line is at least partially disposed in the first interconnect layer and the second interconnect layer.

20. The readout circuit structure according to claim 19, characterized in that, The structural layer includes a gate layer, one of the first signal line or the first complementary signal line is at least partially disposed in the gate layer and the first interconnect layer, and the other of the first signal line or the first complementary signal line is at least partially disposed in the gate layer, the first interconnect layer and the second interconnect layer.

21. The readout circuit structure according to claim 19, characterized in that, The structural layer also includes transistors constituting a second sensing amplification structure. The second sensing amplification structure is connected to the first memory array via a second signal line and a second complementary signal line. The direction from the first sensing amplification structure to the second sensing amplification structure is the same as the direction from the first memory array to the second memory array. One of the first signal line or the first complementary signal line passes through the region where the second sensing amplification structure is located via at least the second interconnect layer and is electrically connected to the first sensing amplification structure.

22. The readout circuit structure according to claim 21, characterized in that, One of the second signal line or the second complementary signal line is at least partially disposed in the first interconnect layer, and the other of the second signal line or the second complementary signal line is at least partially disposed in the first interconnect layer and the second interconnect layer. One of the second signal line or the second complementary signal line passes through the region where the first sensing amplification structure is located based on the second interconnect layer and is electrically connected to the second sensing amplification structure.

23. The readout circuit structure according to claim 22, characterized in that, The first complementary signal line passes through the region where the second sensing amplification structure is located based on the first interconnect layer and the second interconnect layer and is electrically connected to the first sensing amplification structure. The second signal line passes through the region where the first sensing amplification structure is located based on the first interconnect layer and the second interconnect layer and is electrically connected to the second sensing amplification structure.

24. The readout circuit structure according to claim 19, characterized in that, The readout circuit structure is located between adjacent memory arrays.

25. The readout circuit structure according to claim 19, characterized in that, The structural layer is also provided with transistors that constitute the first data readout module and the second data readout module; The first data readout module includes a first input / output transistor, the source of which is connected to a first input / output line and the drain of which is electrically connected to the first signal line. The second data readout module includes a second input / output transistor, the source of which is connected to a second input / output line and the drain of which is electrically connected to the first complementary signal line.

26. The readout circuit structure according to claim 21, characterized in that, The structural layer further comprises transistors constituting a third sensing amplification structure and a fourth sensing amplification structure. The third sensing amplification structure receives a third bit line signal from the first memory array via a third signal line and receives a third complementary bit line signal from the second memory array via a third complementary signal line. The fourth sensing amplification structure receives a fourth bit line signal from the first memory array via a fourth signal line and receives a fourth complementary bit line signal from the second memory array via a fourth complementary signal line. At least one of the third signal line or the third complementary signal line is disposed in the first interconnect layer, and at least one of the third signal line or the other of the third complementary signal line is disposed in both the first interconnect layer and the second interconnect layer. At least one of the fourth signal line or the fourth complementary signal line is disposed in the first interconnect layer, and at least one of the fourth signal line or the other of the fourth complementary signal line is disposed in both the first interconnect layer and the second interconnect layer. The structural layer is also provided with transistors that constitute the first data readout module and the second data readout module; The first data readout module includes: a first input / output transistor, a third input / output transistor, a fifth input / output transistor, and a seventh input / output transistor; The source of the first input / output transistor is connected to the first input / output line, and the drain is electrically connected to the first signal line. The source of the third input / output transistor is connected to the third input / output line, and the drain is electrically connected to the second signal line. The source of the fifth input / output transistor is connected to the fifth input / output line, and the drain is electrically connected to the third signal line. The source of the seventh input / output transistor is connected to the seventh input / output line, and the drain is electrically connected to the fourth signal line. The gates of the first input / output transistor, the third input / output transistor, the fifth input / output transistor, and the seventh input / output transistor are connected together to receive a column selection signal and to turn on the first input / output transistor, the third input / output transistor, the fifth input / output transistor, and the seventh input / output transistor based on the column selection signal. The second data readout module includes a second input / output transistor, a fourth input / output transistor, a sixth input / output transistor, and an eighth input / output transistor; The source of the second input / output transistor is connected to the second input / output line, and its drain is electrically connected to the first complementary signal line. The source of the fourth input / output transistor is connected to the fourth input / output line, and its drain is electrically connected to the second complementary signal line. The source of the sixth input / output transistor is connected to the sixth input / output line, and its drain is electrically connected to the third complementary signal line. The source of the eighth input / output transistor is connected to the eighth input / output line, and its drain is electrically connected to the fourth complementary signal line. The gates of the second input / output transistor, the fourth input / output transistor, the sixth input / output transistor, and the eighth input / output transistor are connected together to receive the column select signal and to turn on the second input / output transistor, the fourth input / output transistor, the sixth input / output transistor, and the eighth input / output transistor based on the column select signal.

27. The readout circuit structure according to claim 19, characterized in that, The drain of the first sensing amplifier N-transistor is connected to the complementary readout bit line, and the drain of the second sensing amplifier N-transistor is connected to the readout bit line. The sensing amplification module further includes: a first sensing amplification P-tube, with its gate connected to the readout bit line, its drain connected to the complementary readout bit line, and its source connected to the first signal terminal; The second sensing amplifier P-tube has its gate connected to the complementary readout bit line, its drain connected to the readout bit line, and its source connected to the first signal terminal. When the sensing amplification module is in the amplification stage, the first signal terminal is electrically connected to the voltage corresponding to logic 1, and the second signal terminal is connected to the voltage corresponding to logic 0.

28. The readout circuit structure according to claim 27, characterized in that, The first sensing amplification structure further includes: An isolation module is connected between the complementary readout bit line and the first complementary signal line, and between the readout bit line and the first signal line, for isolating the signal interaction between the first signal line and the readout bit line according to the isolation signal, and isolating the signal interaction between the complementary readout bit line and the first complementary signal line; An offset cancellation module is connected between the readout bit line and the first complementary signal line, and between the complementary readout bit line and the first signal line, for adjusting the source-drain conduction difference between different NMOS transistors or different PMOS transistors in the sensing amplification module according to the offset cancellation signal.

29. The readout circuit structure according to claim 28, characterized in that, The first sensing amplification P-tube, the second sensing amplification P-tube, the isolation module, and the offset cancellation module are disposed between the first sensing amplification N-tube and the second sensing amplification N-tube.

30. The readout circuit structure according to claim 28, characterized in that, The gate structures of the first sensing amplification N-transistor, the second sensing amplification N-transistor, the first sensing amplification P-transistor, and the second sensing amplification P-transistor extend in the same direction. The gate structures of the MOS transistor in the isolation module and the MOS transistor in the offset elimination module extend in the same direction, and the gate structures of the first sensing amplification N-transistor and the MOS transistor in the isolation module extend perpendicularly to each other.

31. The readout circuit structure according to claim 28, characterized in that, The isolation module includes: The first isolation transistor has a gate for receiving the isolation signal, a source connected to the first signal line, and a drain connected to the readout bit line. The second isolation transistor has a gate for receiving the isolation signal, a source connected to the first complementary signal line, and a drain connected to the complementary readout bit line. The offset elimination module includes: The first offset cancellation transistor has a gate for receiving the offset cancellation signal, a source connected to the first signal line, and a drain connected to the complementary readout bit line. The second offset cancellation transistor has a gate for receiving the offset cancellation signal, a source connected to the first complementary signal line, and a drain connected to the readout bit line.

32. A readout circuit structure, characterized in that, include: A structural layer, a first interconnect layer and a second interconnect layer stacked on top of the structural layer; The structural layer is provided with transistors constituting a first sensing amplification structure, a second sensing amplification structure, and an equalization structure. The first memory array and the second memory array are adjacent memory arrays corresponding to the first sensing amplification structure and the second sensing amplification structure. The arrangement direction of the first sensing amplification structure and the second sensing amplification structure is the bit line extension direction. The arrangement direction of the first memory array and the second memory array is the bit line extension direction. The first sensing amplification structure receives the first bit line signal in the first memory array through the first signal line, and the first sensing amplification structure receives the first complementary bit line signal of the second memory array through the first complementary signal line. The second sensing amplification structure receives the second bit line signal in the first memory array through the second signal line, and the second sensing amplification structure receives the second complementary bit line signal of the second memory array through the second complementary signal line; The equalization structure is disposed between the first sensing amplification structure and the second sensing amplification structure. The equalization structure includes a first equalization transistor and a second equalization transistor. The gate of the first equalization transistor receives a first equalization signal and its first end is connected to the first complementary signal line. The gate of the second equalization transistor receives a second equalization signal and its first end is connected to the second signal line. The second ends of the first equalization transistor and the second equalization transistor share the same source to receive a pre-charge voltage.

33. The readout circuit structure according to claim 32, characterized in that, The first equalization signal and the second equalization signal are the same equalization signal. The gates of the first equalization transistor and the second equalization transistor are physically connected through a connection structure in the gate layer. The gate layer is a part of the structure layer.

34. The readout circuit structure according to claim 33, characterized in that, The gate of the first equalizer, the gate of the second equalizer, and the corresponding connection structure form a rectangle with an opening.

35. The readout circuit structure according to claim 33, characterized in that, The structural layer is provided with transistors constituting the third sensing amplification structure and the fourth sensing amplification structure. The first memory array and the second memory array are adjacent memory arrays corresponding to the first sensing amplification structure to the fourth sensing amplification structure. The arrangement direction of the first sensing amplification structure and the third sensing amplification structure is the word line extension direction. The arrangement direction of the second sensing amplification structure and the fourth sensing amplification structure is the word line extension direction. The third sensing amplification structure receives the third bit line signal in the first memory array through the third signal line, and the third sensing amplification structure receives the third complementary bit line signal of the second memory array through the third complementary signal line; the fourth sensing amplification structure receives the fourth bit line signal in the first memory array through the fourth signal line, and the fourth sensing amplification structure receives the fourth complementary bit line signal of the second memory array through the fourth complementary signal line. The equalization structure is further disposed between the third sensing amplification structure and the fourth sensing amplification structure. The equalization structure includes a third equalization tube and a fourth equalization tube. The first end of the third equalization tube is connected to the third complementary signal line, and the first end of the fourth equalization tube is connected to the second signal line. The gates of the first equalization tube and the fourth equalization tube receive the same equalization signal, and the second ends of the first equalization tube and the fourth equalization tube share the same source to receive the pre-charge voltage.

36. The readout circuit structure according to claim 35, characterized in that, The gates of the first equalizer to the fourth equalizer are connected by a connection structure in the gate layer, and the gates of the first equalizer to the fourth equalizer and the corresponding connection structure form a rectangle.

37. The readout circuit structure according to claim 32, characterized in that, In each pair of complementary signal lines, only one signal line receives the pre-charge voltage through the equalization tube during the pre-charge phase.

38. The readout circuit structure according to claim 37, characterized in that, In each pair of complementary signal lines, only one signal line receives the pre-charge voltage through an equalization tube of the equalization structure to pre-charge the two complementary signal lines and the corresponding sensing amplification structure.

39. The readout circuit structure according to claim 38, characterized in that, The signal line used to receive the pre-charge voltage is directly connected to the corresponding equalization transistor in the first interconnect layer.

40. The readout circuit structure according to claim 32, characterized in that, In the bit line extension direction, the first memory array, the first sensing amplification structure, the second sensing amplification structure, and the second memory array are arranged in sequence.

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