Clock stabilization circuit, memory system and operation method of memory system

Abstract

The invention relates to a clock stabilization circuit, a memory system and an operation method of the memory system. The clock stabilization circuit includes: a shift register configured to output one or more shift signals by shifting data and an inversion flag based on a clock signal; a comparison circuit configured to output one or more comparison signals by comparing the one or more shift signals with the one or more keys, respectively; a stabilization flag register configured to enable a stabilization flag based on a first delayed clock signal and the one or more comparison signals, the first delayed clock signal being generated by delaying the clock signal; and a shielding circuit configured to output the internal clock signal by shielding a second delayed clock signal based on the stabilization flag, the second delayed clock signal being generated by delaying the first delayed clock signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0134089, filed on October 2, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to a semiconductor circuit for processing clock signals. Background Technology

[0004] Memory devices are essential components in computers or electronic devices used for storing data, and they can operate based on clock signals. Data is sent to the memory device synchronously with the clock signal. The memory device can process data based on the timing of the clock signal.

[0005] Clock signal transmission can be unstable due to various external factors and the characteristics of the circuit itself. For example, power supply or temperature changes can cause variations in the clock signal. Furthermore, the clock signal may be unstable during the initial transmission interval before it stabilizes. An unstable clock signal can cause memory devices to process data incorrectly, potentially leading to data loss or system errors. Therefore, to maximize system performance and maintain data integrity, data must be processed based on a stable clock signal. Summary of the Invention

[0006] In embodiments of this disclosure, a clock stabilization circuit may include: a shift register configured to output one or more shift signals by shifting data and an inversion flag based on a clock signal; a comparison circuit configured to output one or more comparison signals by comparing the one or more shift signals with one or more keys respectively; a stabilization flag register configured to enable a stabilization flag based on a first delayed clock signal and one or more comparison signals, the first delayed clock signal being generated by delaying the clock signal; and a shielding circuit configured to output an internal clock signal by shielding a second delayed clock signal based on the stabilization flag, the second delayed clock signal being generated by delaying the first delayed clock signal.

[0007] In embodiments of this disclosure, a memory system may include: a first means configured to output data and an inversion flag synchronized with a clock signal; and a second means configured to identify one or more initial patterns in a combination of data and the inversion flag, and generate an internal clock signal based on a second clock cycle following a first clock cycle in the clock signal synchronized with one or more initial patterns.

[0008] In embodiments of this disclosure, a method of operating a memory system may include: outputting data and an inversion flag synchronized with a clock signal via a first means; identifying one or more initial patterns in a combination of data and the inversion flag via a second means; and generating an internal clock signal via the second means based on a second clock cycle following a first clock cycle synchronized with one or more initial patterns in the clock signal. Attached Figure Description

[0009] Figure 1 This is a diagram illustrating clock signals transmitted between devices in a system according to an embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating a system according to an embodiment of the present disclosure.

[0011] Figure 3 This is a diagram illustrating the DBI function of a system according to an embodiment of the present disclosure.

[0012] Figure 4 This is a diagram illustrating an initial configuration according to an embodiment of the present disclosure.

[0013] Figure 5 This is a block diagram illustrating a clock stabilization circuit according to an embodiment of the present disclosure.

[0014] Figure 6 It is used to describe embodiments according to this disclosure, including Figure 5 The timing diagram of the system operation of the clock stabilization circuit.

[0015] Figure 7 This is a flowchart illustrating a method of operating a system according to an embodiment of the present disclosure.

[0016] Figure 8 This is a block diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0017] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0018] Figure 1 This is a diagram illustrating a clock signal CLK transmitted between devices in a system (e.g., a memory device and a controller in a memory system) according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The clock signal CLK can be sent sequentially through intervals P1 to P4. Figure 1In the illustrated embodiment, the clock signal CLK can remain high without switching during interval P1. In another embodiment, the clock signal CLK can remain at a predetermined voltage level that is not high during interval P1. Interval P1 can be the interval during which the clock signal CLK is in a disabled state. That is, the clock signal CLK will not continue to switch, but can remain disabled when there is no data transmission or the system is in a low-power mode.

[0020] The clock signal CLK can transition from high to low within interval P2 and can be transmitted at a low level. In another embodiment, the clock signal CLK can be at a predetermined voltage level that is not low within interval P2. Interval P2 can be the interval in which the clock signal CLK is transmitted as a preamble.

[0021] The clock signal CLK can switch within interval P3. Because the clock signal CLK begins to switch within interval P3, the power within the memory device may experience a sudden drop. This sudden drop in power may cause instability in the clock signal CLK. Interval P3 can be the interval during which the clock signal CLK is transmitted in an unstable or transient state.

[0022] After the power supply stabilizes, the clock signal CLK can be sent in a stable state within interval P4.

[0023] For example, when the system begins to send burst data, the clock signal CLK, which was inactive during interval P1, may be sent, such as... Figure 1 As shown. Because the clock signal CLK within interval P3 may be unstable, the transmitting device of the system may not transmit data within interval P3. Instead, the transmitting device can transmit data within interval P4 based on the stable clock signal CLK. The receiving device of the system can count the clock cycles of the clock signal CLK to ignore the clock signal CLK in interval P3 and can identify the start point of interval P4. It can be predetermined how many clock cycles of the clock signal CLK will be ignored between the transmitting and receiving devices. However, as the unit interval (UI) of the signal gradually decreases, the counting of the clock signal CLK may be inaccurate.

[0024] Therefore, the counting of the clock signal CLK may be inaccurate. Thus, a scheme to eliminate or reduce interval P3 by improving power drop and recovery characteristics could be considered. However, since analog characteristics are scheme-dependent, it may be difficult to maintain consistent performance during system operation.

[0025] Figure 2 This is a block diagram illustrating a system 100 according to an embodiment of the present disclosure.

[0026] System 100 may include a first device 110 and a second device 120. Each component of each of the first device 110 and the second device 120 may consist of hardware, software, firmware, or a combination thereof.

[0027] The first device 110 may include a first control circuit 111 and a transmitting circuit 114.

[0028] The first control circuit 111 can control the transmitting circuit 114 by sending the control signal TCT.

[0029] The transmitting circuit 114 can transmit a clock signal CLK, and data DQ and an inversion flag IF synchronized with the clock signal CLK, to the second device 120. The data DQ and inversion flag IF may include one or more initial modes. One or more initial modes can... Figure 1 Transmitted within interval P3. The clock cycle of the clock signal CLK, which has been synchronized with one or more initial patterns, may be in an unstable state. One or more initial patterns can be used to identify the start of a stable clock cycle in the clock signal CLK.

[0030] Each of one or more initialization patterns may consist of data DQ and an inversion flag IF. At least one of the one or more initialization patterns may include data DQ with a majority of "1"s and an inversion flag IF that is enabled, such as "1".

[0031] According to an embodiment, the transmitting circuit 114 can transmit a predetermined number of clock cycles as a clock signal CLK to the second device 120 during a pre-run interval before transmitting one or more initial modes.

[0032] According to an embodiment, the first control circuit 111 can control the second device 120 to store one or more keys in the clock stabilization circuit 122 before sending data DQ, including one or more initial modes, and an inversion flag IF to the second device 120. The one or more keys may each be identical to one or more initial modes. For example, the first control circuit 111 can control the second device 120 to store one or more keys in the clock stabilization circuit 122 during system 100 startup. The first control circuit 111 can also control the second device 120 to change the stored one or more keys.

[0033] The second device 120 may include a second control circuit 121, a clock stabilization circuit 122, and a processing circuit 123.

[0034] The second control circuit 121 can control the clock stabilization circuit 122 through the clock stabilization control signal CCT and the processing circuit 123 through the processing control signal PCT.

[0035] Clock stabilization circuit 122 can receive data DQ and inversion flag IF synchronized with clock signal CLK. Clock stabilization circuit 122 can identify one or more initial patterns in the combination of data DQ and inversion flag IF. Clock stabilization circuit 122 can generate internal clock signal ICLK based on a second clock cycle following a first clock cycle in clock signal CLK synchronized with one or more initial patterns. Internal clock signal ICLK can be generated based on a second clock cycle in clock signal CLK that is in a stable state, excluding the first clock cycle which is in an unstable state.

[0036] The clock stabilization circuit 122 can store one or more keys that are identical to one or more initial patterns. The clock stabilization circuit 122 can identify one or more initial patterns by comparing the data DQ and the inversion flag IF with one or more keys.

[0037] According to one embodiment, during manufacturing operations, one or more keys can be hardwired to clock stabilization circuit 122. According to another embodiment, one or more keys stored in clock stabilization circuit 122 can be changed under the control of first device 110.

[0038] Processing circuit 123 can process data DQ and inversion flag IF based on the internal clock signal ICLK. Specifically, processing circuit 123 can generate internal data and an internal inversion flag based on data DQ and inversion flag IF. Furthermore, processing circuit 123 can capture internal data and an internal inversion flag based on the internal clock signal ICLK. Additionally, processing circuit 123 can selectively invert the captured internal data based on the captured internal inversion flag. Specifically, processing circuit 123 can invert the captured internal data when the captured internal inversion flag is enabled, and can not invert the captured internal data when the captured internal inversion flag is disabled.

[0039] According to an embodiment, system 100 may be a memory system. The first device 110 and the second device 120 may be a controller and a memory device included in the memory system, or vice versa.

[0040] Figure 3 This is a diagram illustrating the data bus inversion (DBI) function of system 100 according to an embodiment of the present disclosure.

[0041] Reference Figure 3To reduce power consumption, data DQ can be transmitted from the first device 110 to the second device 120 according to the DBI method. According to the DBI method, when the original data RDQ includes a majority of "1"s, the first device 110 can generate data DQ by inverting each bit in the original data RDQ, and can transmit the data DQ along with an enabled inversion flag IF to the second device 120. The enabled inversion flag IF indicates that the data DQ transmitted with the inversion flag IF has been inverted from the original data RDQ. The disabled inversion flag IF indicates that the data DQ transmitted with the inversion flag IF is the original data RDQ. Therefore, when the data DQ transmitted with the enabled inversion flag IF is inverted again, the original data RDQ can be recovered. For example, the inversion flag IF can be enabled as "1" and disabled as "0".

[0042] For example, the original data RDQ can be "0xFF, 0x03, and 0xEF". The data DQ sent by the first device 110 to the second device 120 can be "0x00, 0x03, and 0x10". Specifically, the original data RDQ "0xFF" can be inverted to data DQ "0x00" because the original data RDQ "0xFF" includes a majority of "1". Data DQ "0x00" can be sent together with the inversion flag IF "1". Data DQ "0x00" can be inverted again based on the inversion flag IF "1". Therefore, the original data RDQ "0xFF" can be recovered. The original data RDQ "0x03" can be sent as data DQ "0x03" together with the inversion flag IF "0". Data DQ "0x03" can be processed without any changes, that is, no recovery processing is performed based on the inversion flag IF "0". The original data RDQ "0xEF" can be inverted to the data DQ "0x10" because the original data RDQ "0xEF" contains a majority of "1". The data DQ "0x10" can be sent along with the inversion flag IF "1". The data DQ "0x10" can be inverted again based on the inversion flag IF "1". Therefore, the original data RDQ "0xEF" can be recovered.

[0043] Depending on the situation, the original data RDQ "0xFF, 0x03, and 0xEF" can all be sent from the first device 110 to the second device 120 along with the inversion flags IF "0, 0, and 0" without inversion. The second device 120 can process the data DQ "0xFF, 0x03, and 0xEF" without making any changes, that is, without performing recovery processing based on the inversion flags IF "0, 0, and 0".

[0044] Figure 4 These are diagrams illustrating initial configurations 41 to 43 according to embodiments of the present disclosure.

[0045] Reference Figure 4 Initial modes 41 to 43 may include modes not yet defined in the state supporting DBI functionality, namely modes consisting of data DQ including a majority of "1"s and an inversion flag IF "1". Specifically, initial modes 41 to 43 may include data DQ "0xFF, 0x03, and 0xEF" and corresponding inversion flags IF "1, 0, and 1". In this case, the data DQ "0xFF" including a majority of "1"s and the inversion flag IF "1" in initial mode 41 may be a mode not yet defined in the state supporting DBI functionality. Furthermore, the data DQ "0xEF" including a majority of "1"s and the inversion flag IF "1" in initial mode 43 may also be a mode not yet defined in the state supporting DBI functionality.

[0046] Modes 41 and 43 can be used as initial modes because these modes are not yet defined in the state of supporting DBI functionality and can be distinguished from normal data. The data DQ "0xFF, 0x03, and 0xEF" sent as initial mode can be used as normal data DQ because the data DQ "0xFF, 0x03, and 0xEF" is sent along with the inverted flags IF "0, 0, and 0" that conform to the flags defined in the DBI functionality.

[0047] Figure 5 This is a block diagram illustrating a clock stabilization circuit 122 according to an embodiment of the present disclosure. Figure 5 In one embodiment, four initial modes, such as the first to fourth initial modes, can be sent via data DQ and the inversion flag IF.

[0048] Reference Figure 5 The clock stabilization circuit 122 may include a key storage circuit 210, a shift register 220, a comparator circuit 230, a delay circuit 240, a stabilization flag register 250, and a shielding circuit 260. Although not shown, the components included in the clock stabilization circuit 122 can operate based on the clock stabilization control signal CCT sent by the second control circuit 121, such as... Figure 2 As shown.

[0049] The key storage circuit 210 can store and output the first to fourth keys KEY1 to KEY4. The first to fourth keys KEY1 to KEY4 can each be the same as the first to fourth initial modes. When each of the first to fourth initial modes consists of 8 bits of data DQ and 1 bit of inversion flag IF, each of the first to fourth keys KEY1 to KEY4 can consist of 9 bits. According to an embodiment, the key storage circuit 210 can change the stored first to fourth keys KEY1 to KEY4 under the control of the first device 110.

[0050] The shift register 220 can output the first to fourth shift signals C1 to C4 by shifting the data DQ and the inversion flag IF based on the clock signal CLK. Each of the first to fourth shift signals C1 to C4 can be composed of 8 bits of data DQ and 1 bit of inversion flag IF.

[0051] Shift register 220 may include first to fourth registers REG1 to REG4. First register REG1 can receive and store data DQ and an inversion flag IF based on a clock signal CLK. First register REG1 can output the stored data DQ and inversion flag IF as a first shift signal C1 based on a clock signal CLK. Second register REG2 can receive and store the data DQ and inversion flag IF output from first register REG1 as the first shift signal C1 based on a clock signal CLK. Second register REG2 can output the stored data DQ and inversion flag IF as a second shift signal C2 based on a clock signal CLK. Third register REG3 can receive and store the data DQ and inversion flag IF output from second register REG2 as the second shift signal C2 based on a clock signal CLK. Third register REG3 can output the stored data DQ and inversion flag IF as a third shift signal C3 based on a clock signal CLK. Fourth register REG4 can receive and store the data DQ and inversion flag IF output from third register REG3 as the third shift signal C3 based on a clock signal CLK. The fourth register REG4 can output the stored data DQ and the inversion flag IF based on the clock signal CLK as the fourth shift signal C4.

[0052] The comparison circuit 230 can output the first to fourth comparison signals M1 to M4 by comparing the first to fourth shift signals C1 to C4 with the first to fourth keys KEY1 to KEY4 respectively.

[0053] The comparison circuit 230 may include first to fourth comparators COM1 to COM4. The first to fourth comparators COM1 to COM4 may receive first to fourth keys KEY1 to KEY4 output from the key storage circuit 210, may receive first to fourth shift signals C1 to C4 output from the first to fourth registers REG1 to REG4, and may output first to fourth comparison signals M1 to M4. Each of the first to fourth comparators COM1 to COM4 may compare the corresponding shift signal with the corresponding key, and may output the corresponding comparison signal based on determining that the corresponding shift signal and the corresponding key are the same. For example, the first comparator COM1 may output a first comparison signal M1 in a disabled state based on determining that the first shift signal C1 and the first key KEY1 are different, and may output a first comparison signal M1 in an enabled state based on determining that the first shift signal C1 and the first key KEY1 are the same. Each of the first to fourth comparison signals M1 to M4 may, for example, be enabled as "1" and disabled as "0".

[0054] The delay circuit 240 can output a first delayed clock signal CLK1 and a second delayed clock signal CLK2 based on the clock signal CLK. Specifically, the delay circuit 240 can output the first delayed clock signal CLK1 through the delayed clock signal CLK, and can output the second delayed clock signal CLK2 by delaying the first delayed clock signal CLK1.

[0055] The stability flag register 250 can receive and store the first to fourth comparison signals M1 to M4 based on the first delayed clock signal CLK1. The stability flag register 250 can output the stability flag SOT based on the stored first to fourth comparison signals M1 to M4, according to the first delayed clock signal CLK1. Specifically, the stability flag register 250 can output the stability flag SOT in the enabled state based on the first to fourth comparison signals M1 to M4 in the enabled state. The stability flag register 250 can maintain the stability flag SOT in the enabled state.

[0056] The shielding circuit 260 can output the internal clock signal ICLK by shielding the second delayed clock signal CLK2 based on the stability flag SOT. Specifically, when the stability flag SOT is disabled, the shielding circuit 260 can block (shield) the second delayed clock signal CLK2 and can output the internal clock signal ICLK at a predetermined voltage level (e.g., low level). When the stability flag SOT is enabled, the shielding circuit 260 can output the second delayed clock signal CLK2 as the internal clock signal ICLK.

[0057] According to an embodiment, the number of initial patterns sent by the first device 110 may not be four. The number of registers included in the shift register 220 and the number of comparators included in the comparator circuit 230 may each be the same as the number of initial patterns.

[0058] Figure 6 It is used to describe embodiments according to this disclosure, including Figure 5 Timing diagram of the operation of system 100 with clock stabilization circuit 122.

[0059] Reference Figure 6 , Figure 2 The transmitting circuit 114 of the first device 110 can transmit the clock signal CLK, data DQ, and inversion flag IF to the second device 120. The clock signal CLK may include a predetermined number of clock cycles within a pre-run interval before the first to fourth initial modes P1 to P4 are transmitted. According to an embodiment, the pre-run interval may be omitted.

[0060] The first to fourth initial modes P1 to P4 may respectively include data DQ K0, K1, K2, and K3. Each of data DQ K0, K1, K2, and K3 may include a majority of "1". Each of the first to fourth initial modes P1 to P4 may include an inverted flag IF "1". As described above, according to the embodiment, only some, and not all, of the first to fourth initial modes P1 to P4 may be modes that have not yet been defined in the state of supporting DBI functionality.

[0061] The second device 120 can determine the start point of a stable clock cycle in the clock signal CLK by identifying the first to fourth initial modes P1 to P4 included in the data DQ and the inversion flag IF. The start point of a stable clock cycle in the clock signal CLK can be the first rising edge (indicated by the arrow) after a clock cycle synchronized with the first to fourth initial modes P1 to P4. The second device 120 can receive data DQ using the internal clock signal ICLK based on the stable clock cycle.

[0062] Specifically, the first initial mode P1 can be sequentially sent from the first register REG1 to the fourth register REG4, and can be sequentially output as the first shift signal C1 to the fourth shift signal C4. The second to fourth initial modes P2 to P4 can be processed similarly to the first initial mode P1. If the first to fourth initial modes P1 to P4 are simultaneously output as the first to fourth shift signals C1 to C4 respectively, then the first to fourth comparators COM1 to COM4 can determine that the first to fourth initial modes P1 to P4 are the same as the first to fourth keys KEY1 to KEY4 respectively, and can respectively enable the first to fourth comparison signals M1 to M4. Each of the first to fourth registers REG1 to REG4 can stop the shift operation based on each of the first to fourth comparison signals M1 to M4 that is enabled.

[0063] The stability flag register 250 can receive the first to fourth comparison signals M1 to M4 based on the first delayed clock signal CLK1, and can maintain the stability flag SOT in the enabled state based on the first to fourth comparison signals M1 to M4 that are in the enabled state.

[0064] When the stability flag SOT is disabled, the shielding circuit 260 can shield the second delayed clock signal CLK2 and output the internal clock signal ICLK at a low level. When the stability flag SOT is enabled, the shielding circuit 260 can output the second delayed clock signal CLK2 as the internal clock signal ICLK. Therefore, the clock cycle starting from the first rising edge (indicated by the arrow) after the clock cycle synchronized with the first to fourth initial modes P1 to P4 in the clock signal CLK can be generated as the internal clock signal ICLK.

[0065] Processing circuit 123 can generate internal data IDQ and internal inversion flag IIF by delaying data DQ and inversion flag IIF respectively. Furthermore, processing circuit 123 can capture and process internal data IDQ and internal inversion flag IIF based on internal clock signal ICLK. Additionally, processing circuit 123 can selectively invert the captured internal data based on the captured internal inversion flag. Specifically, processing circuit 123 can invert the captured internal data when the captured internal inversion flag is enabled, and can not invert the captured internal data when the captured internal inversion flag is disabled.

[0066] The clock stabilization circuit 122 can effectively eliminate unstable clock cycles from the clock signal CLK by identifying the first to fourth initial modes P1 to P4, and can generate an internal clock signal ICLK based on the stable clock cycles. Since the processing circuit 123 processes the data DQ based on the stable internal clock signal ICLK, the system performance 100 can be improved.

[0067] Figure 7 This is a flowchart illustrating the operation method of system 100 according to an embodiment of the present disclosure.

[0068] Reference Figure 7 In operation S110, the first device 110 may output data DQ and an inversion flag IF synchronized with the clock signal CLK. According to an embodiment, the operation of outputting data DQ and an inversion flag IF synchronized with the clock signal CLK may include sending a predetermined number of clock cycles as the clock signal CLK to the second device 120 during a pre-run interval before the first device 110 sends one or more initial modes.

[0069] In operation S120, the second device 120 can identify one or more initial patterns in the combination of data DQ and inversion flag IF output by the first device 110. At least one of the one or more initial patterns may include data DQ having a majority of "1"s and an inversion flag IF that is enabled. According to an embodiment, the operation of identifying one or more initial patterns may include: the second device 120 reading one or more keys that are the same as the one or more initial patterns from the key storage circuit 210; the second device 120 comparing data DQ and inversion flag IF with one or more keys; and the second device 120 enabling the stability flag SOT based on determining that all of data DQ and inversion flag IF are the same as one or more keys.

[0070] In operation S130, the second device 120 may generate an internal clock signal ICLK based on a second clock cycle following a first clock cycle in the clock signal CLK that is synchronized with one or more initial modes. According to an embodiment, the operation of generating the internal clock signal ICLK may include the second device 120 outputting the internal clock signal ICLK by means of a clock cycle in the delayed clock signal corresponding to the first clock cycle based on the stability flag SOT mask.

[0071] According to an embodiment, the operation method of system 100 may further include, prior to the operation S110 of output data DQ and inversion flag IF, the operation of the first device 110 controlling the second device 120 to store one or more keys in the key storage circuit 210.

[0072] According to an embodiment, the operation method of system 100 may further include: the second device 120 generating internal data and an internal inversion flag based on data DQ and an inversion flag IF; the second device 120 capturing internal data and an internal inversion flag based on an internal clock signal ICLK; and the second device 120 selectively inverting the captured internal data based on the captured internal inversion flag.

[0073] Figure 8 This is a block diagram illustrating a memory system 300 according to an embodiment of the present disclosure.

[0074] Reference Figure 8 The memory system 300 can store data received from an external device in response to a write request from the external device. Furthermore, the memory system 300 can send the stored data to the external device in response to a read request from the external device.

[0075] The memory system 300 may include a memory device 320 and a controller 310.

[0076] Under the control of the controller 310, the memory device 320 can store data in the memory device by performing a write operation, and output the data stored in the memory device to the controller 310 by performing a read operation.

[0077] The memory device 320 may include a second control circuit 321, a second clock stabilizing circuit 322, a second processing circuit 323, and a second transmitting circuit 324. The second control circuit 321, the second clock stabilizing circuit 322, and the second processing circuit 323 may be respectively similar to... Figure 2 The second control circuit 121, the clock stabilization circuit 122, and the processing circuit 123 are constructed and operated.

[0078] The second transmitting circuit 324 can be similar to Figure 2 The transmitting circuit 114 is constructed and operated. Specifically, it is similar to... Figure 2 Under the control of the second control circuit 321, the second transmission circuit 324 of the memory device 320 can transmit data synchronized with the clock signal and the inversion flag to the controller 310.

[0079] The controller 310 can store data in the memory device 320 by controlling the memory device 320 to perform write operations. Specifically, the controller 310 can send data and an inversion flag synchronized with a clock signal to the memory device 320. The memory device 320 can process the data and the inversion flag by generating an internal clock signal based on the clock signal received from the controller 310.

[0080] The controller 310 can read data from the memory device 320 by controlling the memory device 320 to perform a read operation. The memory device 320 can send data and an inversion flag synchronized with a clock signal to the controller 310 by performing the read operation. The controller 310 can process the data and the inversion flag by generating an internal clock signal based on the clock signal received from the memory device 320.

[0081] The controller 310 may include a first control circuit 311, a first clock stabilization circuit 312, a first processing circuit 313, and a first transmitting circuit 314. The first transmitting circuit 314 may be similar to... Figure 2 The transmitting circuit 114 is constructed and operated.

[0082] The first clock stabilizing circuit 312 can be similar to... Figure 2 The clock stabilization circuit 122 is constructed and operated. Specifically, it is similar to... Figure 2 The operation of the clock stabilization circuit 122 of the controller 310: the first clock stabilization circuit 312 can receive data and inversion flags synchronized with the clock signal output by the memory device 320, can identify one or more initial patterns in the combination of data and inversion flags, and can generate an internal clock signal based on a second clock cycle after a first clock cycle synchronized with one or more initial patterns in the clock signal.

[0083] The first processing circuit 313 can generate internal data and internal inversion flag based on the data and inversion flag output by the memory device 320, capture internal data and internal inversion flag based on the internal clock signal output by the first clock stabilization circuit 312, and selectively invert the captured internal data based on the captured internal inversion flag.

[0084] The first control circuit 311 can control the first clock stabilization circuit 312, the first processing circuit 313, and the first transmitting circuit 314.

[0085] The memory system 300 may include PCMCIA cards, smart media cards, memory sticks, various multimedia cards (e.g., MMC, eMMC, RS-MMC, and micro MMC), secure digital (SD) cards (e.g., SD, mini SD, and micro SD), universal flash memory (UFS), or solid-state drives (SSD).

[0086] Memory device 320 may include non-volatile memory devices and volatile memory devices. Non-volatile memory devices may include various types of memory, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin-transfer torque random access memory (STT-RAM). Volatile memory devices may include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0087] According to embodiments of this disclosure, a clock stabilization circuit can generate an internal clock signal by effectively determining the starting point of a clock signal in a stable state.

[0088] According to embodiments of this disclosure, the system and its operating method can improve data processing performance by generating a stable internal clock signal.

[0089] The above description is merely a description of the technical spirit of this disclosure. Those skilled in the art can change and modify the embodiments of this disclosure in various ways without departing from its essential characteristics. Therefore, the disclosed embodiments should not be construed as limiting the technical scope of this disclosure, but rather as describing its scope. The technical scope of this disclosure is not limited by the embodiments. The scope of protection of the embodiments should be interpreted based on the appended claims, and all technical details within the equivalent scope of the embodiments should be interpreted as included within the scope of the rights of this disclosure. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A clock stabilizing circuit, comprising: A shift register outputs one or more shift signals by shifting data and a toggle flag based on a clock signal; The comparison circuit outputs one or more comparison signals by comparing the one or more shift signals with one or more keys respectively; A stability flag register enables a stability flag based on a first delayed clock signal and the one or more comparison signals, wherein the first delayed clock signal is generated by delaying the clock signal; as well as The shielding circuit outputs an internal clock signal by shielding a second delayed clock signal based on the stability flag. The second delayed clock signal is generated by delaying the first delayed clock signal.

2. The clock stabilizing circuit according to claim 1, wherein, The comparison circuit includes one or more comparators, and Each of the one or more comparators enables a corresponding comparison signal among the one or more comparison signals based on determining that a corresponding shift signal among the one or more shift signals is the same as a corresponding key among the one or more keys.

3. The clock stabilization circuit according to claim 1, further comprising a key storage circuit, the key storage circuit storing the one or more keys, and changing the stored one or more keys under the control of an external device.

4. The clock stabilizing circuit according to claim 1, wherein, The one or more keys are identical to one or more initial patterns included in the combination of the data and the inverted flag, and At least one of the initial modes in the combination includes a data entry with a majority of "1"s and a first inversion flag that is enabled.

5. The clock stabilizing circuit according to claim 1, wherein, When the stability flag is disabled, the shielding circuit shields the second delayed clock signal, and when the stability flag is enabled, the shielding circuit outputs the second delayed clock signal as the internal clock signal.

6. A memory system, comprising: The first device outputs data synchronized with the clock signal and an inversion flag; as well as The second device identifies one or more initial patterns in the combination of the data and the inversion flag, and generates an internal clock signal based on a second clock cycle following a first clock cycle in the clock signal that is synchronized with the one or more initial patterns.

7. The memory system according to claim 6, wherein, At least one of the initial modes in the combination includes a data entry with a majority of "1"s and a first inversion flag that is enabled.

8. The memory system according to claim 6, wherein, The second device reads one or more keys that are the same as the one or more initial patterns from the key storage circuit, compares the data and the inversion flag with the one or more keys, and identifies the one or more initial patterns by enabling a stability flag based on determining that all of the data and the inversion flag are the same as the one or more keys.

9. The memory system according to claim 8, wherein, The second device generates the internal clock signal by masking the clock period corresponding to the first clock period in the delayed clock signal based on the stability flag, wherein the delayed clock signal is generated by delaying the clock signal.

10. The memory system according to claim 8, wherein, Before sending the data and the inversion flag to the second device, the first device controls the second device to store the one or more keys in the key storage circuit.

11. The memory system according to claim 6, wherein, The first device sends a predetermined number of clock cycles as the clock signal to the second device during a pre-run interval before sending the one or more initial modes.

12. The memory system according to claim 6, wherein, The second device generates internal data and an internal inversion flag based on the data and the inversion flag, captures the internal data and the internal inversion flag based on the internal clock signal, and selectively inverts the captured internal data based on the captured internal inversion flag.

13. A method of operating a memory system, the method comprising: The first device outputs data synchronized with the clock signal and a reversal flag. as well as The second device identifies one or more initial patterns in the combination of the data and the inversion flag; as well as The second device generates an internal clock signal based on a second clock cycle following a first clock cycle that is synchronized with one or more initial modes in the clock signal.

14. The operating method according to claim 13, wherein, At least one of the initial modes in the combination includes a data entry with a majority of "1"s and a first inversion flag that is enabled.

15. The operating method according to claim 13, wherein, Identifying the one or more initial patterns includes: The second device reads one or more keys that are the same as the one or more initial patterns from the key storage circuit; The second device compares the data and the inversion flag with the one or more keys; and The second device enables the stability flag based on determining that all of the data and the inversion flag are the same as the one or more keys.

16. The operating method according to claim 15, wherein, Generating the internal clock signal includes: generating the internal clock signal by means of the second device by means of a clock period corresponding to the first clock period in the delayed clock signal based on the stability flag, wherein the delayed clock signal is generated by delaying the clock signal.

17. The operating method according to claim 15, further comprising: Before outputting the data and the inversion flag, the first device controls the second device to store the one or more keys in the key storage circuit.

18. The operating method according to claim 13, wherein, Outputting the data and the inversion flag includes: sending a predetermined number of clock cycles as the clock signal to the second device within a pre-run interval prior to sending the one or more initial modes via the first device.

19. The operating method according to claim 13, further comprising: The second device generates internal data and an internal inversion flag based on the data and the inversion flag. The second device captures the internal data and the internal inversion flag based on the internal clock signal; as well as The second device selectively inverts the captured internal data based on the captured internal inversion flag.

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