Three-dimensional integrated circuit

Abstract

A three-dimensional integrated circuit includes a first level, a second level vertically stacked over the first level, and a memory circuit. The memory circuit includes an array of bit cells disposed in a first level. The memory circuit also includes a column peripheral circuit having at least one elongated first portion disposed in a second level. The memory circuit also includes a row decoder that is elongated and disposed in the second level and extends in a direction parallel to the column peripheral circuit first portion.

Description

Technical Field

[0001] This invention relates to a three-dimensional (3D) integrated circuit. Background Technology

[0002] Traditionally, integrated memory circuits and integrated logic circuits are fabricated on separate semiconductor substrates. The memory chips and logic chips are then attached to a circuit board and interconnected using suitable interconnect structures. With advancements in semiconductor manufacturing technology, a trend has emerged to fabricate memory circuits and logic circuits on the same substrate. This structure is called a system-on-chip (SoC). Compared to traditional discrete chips, SoCs offer advantages such as compact size, improved power efficiency, and enhanced performance.

[0003] There are several ways to form memory circuits and logic circuits on the same substrate. For example, the two-dimensional (2D) partitioning method arranges memory circuits and logic circuits side by side in the same layer of the device. The advantage of this method is that it is relatively simple to implement, but the disadvantage is that the interconnects between memory circuits and logic circuits are relatively long, which will reduce device performance.

[0004] 3D integration involves placing memory circuitry and logic circuitry in different layers (or levels) of a device. For example, in their article "Thermal Stress-Aware CMOS-SRAM Partitioning in Sequential 3-D Technology" published in IEEE Transactions on Electron Devices, Vol. 67, No. 11, pp. 4631-4635 (doi:10.1109 / TED.2020.3023923), SMSalahuddin et al. proposed using sequential integration technology to fabricate logic circuitry above the bit cell array of memory circuitry. This structure is called "CMOS Under Array" (AuC).

[0005] Traditional two-dimensional random access memory (RAM) circuits consist of a bit cell array, a row decoder, and column peripheral circuitry. The row decoder and column peripheral circuitry are arranged along the sides of the bit cell array and are typically orthogonal to each other, thus forming an "L"-shaped structure. In some cases, two bit cell arrays can be formed adjacent to each other and share some components of the row decoder. In these cases, the peripheral circuitry forms an inverted "T"-shaped structure. This latter shape, due to the symmetry on both sides of the row decoder, can be called a butterfly arrangement.

[0006] As described in the article by SMSalahuddin et al., during three-dimensional sequential integration, the memory bit cell array (as well as word lines and bit lines) can be formed in the RAM layer of the device. CMOS logic circuitry can be formed in the CMOS layer above the RAM layer. This approach allows for separate optimization of RAM transistors and CMOS transistors. However, since peripheral circuitry is also based on CMOS technology, it can also be formed in the CMOS logic layer.

[0007] While placing peripheral circuitry in the CMOS layer offers advantages in transistor optimization, it imposes limitations on logic circuit design, as the logic circuitry must be arranged around the peripheral circuitry.

[0008] In view of the above, it is necessary to improve the design of the memory peripheral circuit in three-dimensional integrated circuits. Summary of the Invention

[0009] The purpose of this disclosure is to provide a three-dimensional integrated circuit that provides greater design freedom for the arrangement of logic circuits and reduces wiring congestion caused by peripheral circuits of memory.

[0010] According to a first aspect, a three-dimensional integrated circuit is provided, the circuit including a first layer, a second layer vertically stacked above the first layer, and memory circuitry. The memory circuitry includes: a bit cell array disposed in the first layer and including a plurality of bit cells arranged in multiple rows and columns. The memory circuitry also includes: a plurality of word lines disposed in the first layer, each word line connecting to a row of bit cells in the plurality of rows. Additionally, the memory circuitry includes: a plurality of bit lines disposed in the first layer, each bit line connecting to a column of bit cells in the plurality of columns. Column peripheral circuitry is coupled to each of the plurality of bit lines and configured to read / write data from the bit cell array during a read / write operation, the column peripheral circuitry having at least one elongated first portion disposed in the second layer. The memory circuitry also includes: a row decoder coupled to each of the plurality of word lines and configured to select a row of bit cell rows during the read / write operation, the row decoder being elongated and disposed in the second layer and extending in a direction parallel to the first portion of the column peripheral circuitry.

[0011] By arranging the first portions of the row decoder and column peripheral circuitry in parallel within the second level, additional space is created for placing logic circuitry in the second level. When the row decoder and column peripheral circuitry are arranged orthogonally, the space in the second level is limited in both the row and column directions. With parallel arrangement, space is limited in only one direction. This means that larger standard logic modules can be used above the memory circuitry in the second level. This approach allows standard logic modules to be placed close to each other and improves wiring resources. This reduces or avoids obstacles that may arise from wiring having to "cross" the inverted "T" shaped peripheral structure. By aligning the first portions of the row decoder and column peripheral circuitry in parallel, wiring congestion in the logic level above the bit cell array is minimized. The row decoder and column peripheral circuitry can be referred to as memory peripheral circuitry. The bit cell array can be a two-dimensional array.

[0012] Row decoders and column peripheral circuits are typically elongated. This is because they comprise a series of sub-circuits configured to couple to each word line or bit line. To ensure efficient space utilization, these sub-circuits can be arranged along the sides of the bit cell array, resulting in an overall elongated shape for the row decoder and column peripheral circuits. In this example, the length of the first portion of the column peripheral circuit and the row decoder in the elongated direction is greater than or equal to the length of the bit cell array in the row or column direction. The wiring congestion mitigation achieved by placing the peripheral circuits in parallel is more significant than that achieved by equivalent circuits that might be shorter.

[0013] The peripheral circuitry can be located in multiple different positions within the second layer. It can be situated in a region within the second layer adjacent to the side of the bit cell array. For example, the first portion of the column peripheral circuitry and the row decoder can each be positioned in the second layer, above the region adjacent to the first side of the bit cell array in the first layer. In this arrangement, the bit cell array defines a bit cell region within the horizontal plane of the first layer, while the row decoder and column peripheral circuitry are located above the region outside the bit cell region within the first layer. This arrangement offers the advantage of reducing the required metal trace length between the peripheral circuitry and the corresponding circuit elements or vias located in the first layer.

[0014] Peripheral circuitry can be arranged parallel to word lines or orthogonal to bit lines. In one example, the first part of the column peripheral circuitry and the row decoder are arranged parallel to multiple rows. With this arrangement, the row decoder cannot be directly connected to any end of a word line. Therefore, the memory circuitry also includes multiple word line interconnects, each of which can be coupled between a corresponding word line and the row decoder. Arranging the peripheral circuitry in this way requires only an additional metallization layer to couple the row decoder to the word line.

[0015] As an alternative, the peripheral circuitry can also be arranged in parallel with multiple columns. In this case, bit line interconnects can be used, with each bit line interconnect coupled between a corresponding bit line and the column peripheral circuitry.

[0016] In one example, each of the multiple word line interconnects is arranged parallel to multiple bit lines and aligned with one column of multiple bit cell columns. This alignment of word line interconnects allows the use of a conventional line decoder. Because the line decoder is coupled to the word line interconnects in the same way as it is directly coupled to the word lines, its layout can be similar to a conventional line decoder. This reduces design costs. In one example, the line decoder may include multiple word line transistor circuits, each coupled to and aligned with a corresponding word line interconnect.

[0017] A memory bit cell array typically contains one or more worst-case bit cells. These worst-case bit cells are the most error-prone, usually because they are located furthest from the peripheral circuitry. To shorten the metal trace length between the row decoder and the worst-case bit cells, word line interconnects near the center of the row decoder are coupled to the word lines furthest from the row decoder. The worst-case bit cells are typically located in the corners of the bit cell array furthest from the row decoder. In this example, word line interconnects near the edge of the bit cell array are coupled to the word lines closest to the row decoder, while word line interconnects near the center of the bit cell array are coupled to the word lines furthest from the row decoder.

[0018] The first level may include multiple metallization layers. This allows word line interconnects to be arranged above word lines and other components of the bit cell array. For example, word lines may be formed above bit cell transistors. In this example, multiple word lines are formed in a first metallization layer of the first level, while multiple word line interconnects are formed in a second metallization layer perpendicularly above the first metallization layer in the first level. The three-dimensional integrated circuit also includes multiple word line vias, each configured to couple a word line to a word line interconnect and extending perpendicularly from the first metallization layer to the second metallization layer.

[0019] The column peripheral circuitry can be arranged in one, two, or more parts. For example, a first part located in the second level can be the sole part, containing all components of the column peripheral circuitry. Alternatively, the column peripheral circuitry can be split into a first level and a second level. This approach allows circuit elements that do not need to be coupled to logic circuitry to be arranged in the first level. In this example, the column peripheral circuitry includes a second part located in a region within the first level adjacent to the first side of the bit cell array. This region may be located vertically below the first part. The first part of the column peripheral circuitry may include multiple sense amplifiers and multiple write drivers, each located in the second level and aligned with each corresponding bit cell column. The second part of the column peripheral circuitry may further include a column multiplexer. The two parts of the column peripheral circuitry can be connected via multiple vias spanning the first and second levels.

[0020] Bit lines and word lines can be arranged in various configurations. In one example, each of multiple bit lines is aligned with a corresponding column of bit cells, and each of multiple word lines is aligned with a corresponding row of bit cells. Multiple bit lines and multiple word lines can be orthogonal to each other. Bit lines can include pairs of bit lines, each pair coupled to the same column of bit cells. One of the paired bit lines is called a bit line. The other of the paired bit lines is called a bit line bar. The polarity of the bit line bar is opposite to that of the bit line.

[0021] The three-dimensional integrated circuit includes one or more logic circuits disposed in a second level. These logic circuits may be located vertically above the bit cell array. Traditionally, the layout of the logic circuits is limited due to the orthogonal arrangement of row decoders and column peripheral circuits. However, by arranging the row decoders and column peripheral circuits in parallel, the coverage of the logic circuits over the bit cell array in either the column or row direction is no longer limited. Multiple memory circuits can be arranged as an array containing multiple rows and columns of memory circuits, each memory circuit including a bit cell array. The logic circuits in the second level can be arranged to span multiple memory circuits in either the row or column direction. This allows for the implementation of logic circuits with larger standard design modules, while simultaneously reducing wiring congestion in the logic circuits.

[0022] Each level of a 3D integrated circuit includes a device layer, which can be implemented using different process technologies. For example, the first level may be optimized for RAM bit cells, while the second level may be optimized for CMOS-based logic circuits. In one example, the first level includes a first device layer and a first back-to-line (BEOL) layer stacked on top of the first device layer. The second level may include a second device layer and a second BEOL layer stacked on top of the second device layer. The bit cell array may be formed in the first device layer, and the line decoder may be formed in the second device layer.

[0023] Each layer of a 3D integrated circuit can be manufactured using any suitable 3D integration technology. For example, the first and second layers can be formed through sequential integration or bonding. The bonding method can be hybrid bonding or other suitable bonding techniques.

[0024] The memory circuitry can be configured in a butterfly arrangement. This arrangement includes two bit cell arrays arranged adjacent to each other in the first level. These two bit cell arrays can share elements of the row decoder or column peripheral circuitry. In this example, the three-dimensional integrated circuit may include multiple memory circuits as described above, arranged in pairs, with each pair of memory circuits arranged in a butterfly configuration.

[0025] The memory circuitry can be random access memory (RAM). Alternatively, the circuitry can also be implemented using any memory employing a bit cell array and row and column peripheral circuitry. Memory arrays with "L", inverted "T", or butterfly peripheral configurations benefit from the parallel alignment of row and column peripheral circuitry. For example, the memory can be static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM). It should be clarified that for ROM memory, there is no write operation. Therefore, for writable memory circuitry, the "read / write operation" mentioned in the claims should be understood as "both read and write operations". For ROM memory circuitry, the "read / write operation" mentioned in the claims should be understood as only "read operation".

[0026] According to a second aspect, an integrated memory and logic device is provided, comprising a plurality of three-dimensional integrated circuits as described in any of the above-described technical solutions, wherein these three-dimensional integrated circuits are arranged in a multi-row and multi-column manner. The row decoders and column peripheral circuits of the plurality of three-dimensional integrated circuits are arranged in parallel in multiple rows.

[0027] According to a third aspect, a three-dimensional integrated circuit is provided, the circuit comprising: a first layer; a second layer vertically stacked above the first layer; and a memory circuit comprising: a bit cell array comprising a plurality of bit cells arranged in multiple rows and columns and disposed in the first layer; a plurality of word lines extending along each row and coupled to each bit cell in the corresponding row; and a row decoder disposed in the second layer and arranged parallel to the word lines.

[0028] According to a fourth aspect, a three-dimensional integrated circuit is provided, the circuit comprising: a first layer; a second layer vertically stacked above the first layer; and a memory circuit comprising: a bit cell array disposed within the first layer; at least two elongated peripheral circuits arranged parallel to each other and disposed in the second layer; and logic circuitry disposed in the second layer.

[0029] It should be noted that relative spatial terms such as “vertical,” “above,” “below,” and “stacked” should be understood as indicating a position or orientation related to the normal direction of the substrate or the bottom-up direction of the device layer stack. Accordingly, terms such as “lateral” and “horizontal” should be understood as a position or orientation parallel to the substrate (i.e., parallel to the upper surface of the substrate’s main extension plane).

[0030] Other features and advantages of the present invention will be further illustrated by the following description of preferred embodiments of the invention (given by way of example only) in conjunction with the accompanying drawings. Attached Figure Description

[0031] The above and other objects, features, and advantages can be better understood by referring to the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0032] Figure 1 A top view of a conventional two-dimensional RAM circuit is shown;

[0033] Figure 2 A top view of a conventional two-dimensional RAM circuit employing a butterfly structure is shown;

[0034] Figure 3A A side view of a three-dimensional integrated circuit is shown;

[0035] Figure 3B It shows Figure 3A A three-dimensional diagram of an integrated circuit;

[0036] Figure 4 It shows Figure 3A A top-down view of a 3D integrated circuit simulation;

[0037] Figure 5 A top view of a three-dimensional integrated circuit according to an embodiment of the present disclosure is shown;

[0038] Figure 6 It shows Figure 5 A side view of a three-dimensional integrated circuit;

[0039] Figure 7 It shows Figure 5 A side view of a three-dimensional integrated circuit; and

[0040] Figures 8A to 8D Various top views of a three-dimensional integrated circuit containing four groups of three-dimensional memory circuits are shown. Detailed Implementation

[0041] Figure 1A schematic top view of a conventional two-dimensional RAM circuit 100 is shown. The RAM circuit 100 includes a bit cell array 102 containing a plurality of bit cells 104. The bit cells 104 are arranged in a multi-row, multi-column configuration. In this example, the number of rows is the same as the number of columns. Although conventionally the number of rows and columns is usually the same, they can differ in some cases. The RAM circuit 100 also includes a plurality of word lines 106. Each word line 106 is coupled to all the bit cells 104 in a given row. Figure 1 In the RAM circuit 100, word lines 106 are arranged parallel to the rows, which is the traditional orientation of word lines. The RAM circuit 100 also includes multiple bit lines 108A and anti-phase lines 108B. Each bit line 108A and each anti-phase line 108B is coupled to all bit cells 104 in a column. Bit lines 108A and anti-phase lines 108B are arranged in pairs, with each pair coupled to a column of bit cells 104. The polarity of the anti-phase line 108B is opposite to that of the bit lines 108A. Bit lines 108A and anti-phase lines 108B are arranged parallel to the columns.

[0042] RAM circuitry 100 also includes a row decoder 110 arranged along one side of and adjacent to the bit cell array 102, and parallel to the columns. Each word line 104 is connected to the row decoder 110. The row decoder 110 is configured to select a row for memory read / write operations. In this respect, the row decoder 110 represents a series of sub-circuits, each coupled to a word line 104. The overall size of the row decoder 110 makes it elongated. This shape represents the overall footprint of the circuits constituting the row decoder.

[0043] RAM circuitry 100 also includes column peripheral circuitry 112, which is arranged along one side of the bit cell array 102 and parallel to the rows. Each bit line 108A and each anti-phase line 108B is connected to column peripheral circuitry 112. Column peripheral circuitry 112 may include multiple sub-circuits performing different functions, such as multiplexers, sense amplifiers, and write drivers. Each pair of bit lines 108A and anti-phase lines 108B is coupled to one or more circuits configured to manipulate the corresponding column bit cell 104. The overall size of column peripheral circuitry 112 makes it elongated. This shape represents the overall footprint of the circuits constituting the column peripheral circuitry.

[0044] The row decoder 110 and column peripheral circuitry 112 are elongated and arranged along the sides of the bit cell array 102, partly to ensure the RAM circuitry is as compact as possible. Since the row decoder 110 and column peripheral circuitry 112 are at the same level as the bit cell array 102, they must be arranged outside the peripheral region of the bit cell array. By arranging them adjacent to each other along the sides of the bit cell array 102, the number of bit cell arrays that can be arranged on a given substrate can be increased.

[0045] The orthogonal arrangement of the row decoder 110 and the column peripheral circuit 112 can be called an "L" shaped structure.

[0046] Figure 1 A top view of the two-dimensional RAM circuit 100 is shown. Figure 1 As shown, the column direction is labeled as the "z" direction, and the row direction is labeled as the "x" direction. This represents the horizontal plane; the rows and columns of the bit cell array are formed within the zx horizontal plane.

[0047] Figure 2 This is a schematic top view of a pair of conventional two-dimensional RAM circuits arranged in a butterfly configuration. Two-dimensional RAM circuits 100A and 100B are manufactured adjacent to each other and aligned along the row direction (i.e., the "x" direction). A row decoder 110A is formed between two two-dimensional RAM circuits 100A and 100B, and the two circuits share this row decoder 110A. A column peripheral circuit 112A is formed along one side of the two two-dimensional RAM circuits 100A and 100B, providing the data read and write functions performed by the column peripheral circuit 112A for both circuits.

[0048] Due to the symmetry surrounding the shared line decoder 110A, this configuration is called a butterfly arrangement. This arrangement can also be referred to as an inverted "T" structure.

[0049] Butterfly arrangements can be used to reduce word line load, shorten latency, improve performance, and make efficient use of chip space.

[0050] Figure 3A This is a side view of a three-dimensional integrated circuit 200, which includes a memory circuit 202 and a logic circuit 204. The three-dimensional integrated circuit 200 includes a substrate 206, on which the memory circuit and the logic circuit are fabricated. In terms of composition, the memory circuit 202 may be similar to a two-dimensional RAM circuit 100.

[0051] The three-dimensional integrated circuit 200 is arranged in two layers. A first layer 208A is formed on and above a substrate 206. A second layer 208B is formed on and above the first layer 208A. Each layer represents a specific process technology and is configured to support memory bit cells or logic transistors. Each layer itself includes multiple layers, such as transistor layers and back-to-line (BEOL) layers, which may contain multiple metallization layers.

[0052] The bit cell array 210 of the memory circuit 202 is formed in a first level 208A. The logic circuit 204 is formed in a second level 208B. The first level 208A also includes a first level BEOL layer 212, which is disposed above the bit cell array 210. The second level 208B includes a second level BEOL layer 214, which is disposed above the logic circuit 204.

[0053] The row decoder 216 of memory circuit 202 is formed in the second level 208B. In this example, the row decoder 216 is formed between the two parts of logic circuit 204. One or more vias 218 couple the bit cell array 210 to the row decoder 216. The column peripheral circuitry of memory circuit 204 is not in... Figure 3A As shown below, Figure 3B Please provide an explanation.

[0054] Figure 3B for Figure 3A A perspective view of the three-dimensional integrated circuit 200 is shown. For clarity, some components are omitted. Specifically, BEOL layers 212 and 214 and logic circuit 204 are not shown. The bit cell array 210 of the memory circuit 202 is shown in the first layer 208A. Figure 3B The column peripheral circuitry of memory circuitry 202 is also shown. A first portion 220A of this column peripheral circuitry is disposed in a second layer 208B of the three-dimensional integrated circuit 200. A second portion 220B is disposed in the first layer 208A.

[0055] The first part 220A of the column peripheral circuitry may include a sense amplifier and a write driver. The second part 220B may include column select / multiplexer circuitry.

[0056] As can be seen, the layout design of logic circuit 204 is restricted because the row decoder 216 and the first part 220A of the column peripheral circuit are located in the second level 208B. Logic circuit 204 cannot be freely designed to occupy all the areas provided in the second level 208B. The parts of logic circuit 204 located on both sides of the row decoder 216 must be connected by wiring around the row decoder 216.

[0057] Figure 4 It shows Figure 3A A simulated top view of the three-dimensional integrated circuit 200. This view shows the "top" of the second layer 208B, but omits the BEOL layer 214. Therefore, Figure 4The top of logic circuit 204, row decoder 216, and column peripheral circuit first section 220A is shown. The butterfly or inverted "T" shaped structures represent the row decoder 216 and column peripheral circuit first section 220A of memory circuit 202. The area between each inverted "T" shaped structure represents logic circuit 204. In this example, four sets of butterfly arrangements are shown. In real-world applications, the total number of circuits may be much greater. During use, congestion occurs at the edges of the inverted "T" shaped structures because signals in logic circuit 204 must navigate around the row decoder and column peripheral circuits. This congestion is most severe at the corners of the inverted "T" shaped structures. This congestion is indicated by "x" markings 222, which represent wiring violations. These are either simulation results or calculation results used to determine feasible wiring schemes.

[0058] Figure 5 This is a schematic top view of a three-dimensional integrated circuit 500 according to an embodiment of the present disclosure. The three-dimensional integrated circuit 500 includes memory circuitry, such as a three-dimensional RAM circuit 501. As described above, as defined in the claims, the memory circuitry can be any type of memory (RAM, magnetoresistive RAM (MRAM), dynamic RAM (DRAM), resistive RAM (RRAM), read-only memory (ROM), programmable read-only memory (PROM), etc.), as long as it employs a bit cell array and row decoder and column peripheral circuitry. Although the drawings will be described below in conjunction with a RAM scenario, those skilled in the art will understand that other types of memory are also included within the scope of protection of the specification and claims. For clarity, Figure 5 Only components of the exemplary three-dimensional RAM memory circuit 501 are shown. In practical applications, these components are integrated with logic circuitry, which will be described below.

[0059] The 3D RAM circuit 501 includes a bit cell array 502 containing a plurality of bit cells 504. The bit cells 504 are arranged in a multi-row, multi-column configuration. In this example, the number of rows is the same as the number of columns, but this can differ in some cases. The 3DRAM circuit 501 also includes a plurality of word lines 506. Each word line 506 is coupled to all the bit cells 504 in a given row. Figure 5 In this circuit, word line 506 is parallel to the row of bit cells 504. The 3D RAM circuit 501 also includes multiple bit lines 508A and anti-phase lines 508B. Each bit line 508A and each anti-phase line 508B is coupled to all bit cells 504 in a column. Bit lines 508A and anti-phase lines 508B are arranged in pairs, with each pair coupled to a column of bit cells 504. The polarity of the anti-phase line 508B is opposite to that of the bit line 508A. Both bit lines 508A and anti-phase lines 508B are arranged parallel to the column of bit cells 504.

[0060] The 3D RAM circuit 501 also includes a row decoder 510. The row decoder 510 is arranged along one side of the bit cell array 502 and adjacent to it. The row decoder 510 is parallel to the rows and word lines 506 of the bit cells 504, and orthogonal to the columns of the bit cells 504, as well as bit lines 508A and anti-phase lines 508B. Because the row decoder 510 is arranged parallel to the rows of the bit cells 504, word lines 504 cannot be directly connected to the row decoder 510. Therefore, the 3DRAM circuit 501 also includes multiple word line interconnects 511. The word line interconnects 511 are arranged parallel to the columns of the bit cells 504. Each word line interconnect 511 is aligned with a column of bit cells 504 and coupled to an available word line 506 using a via 511V. Each word line interconnect 511 is coupled to a different corresponding word line 506.

[0061] Word line interconnects 511 located near the edge of the bit cell array 502 are connected to the word line 506 closest to the line decoder 510. Word line interconnects located near the center of the bit cell array 502 are connected to the word line 506 furthest from the line decoder 510. This arrangement has the advantage of reducing the length of metal traces required to reach the "worst-case bit cell". Figure 5 In the middle, the worst-case bit cell 504W is located in the top left and top right corners. By placing the word line interconnect 511 in the middle of this row, the total length of the metal trace required to reach the worst-case bit cell 504W can be minimized.

[0062] The line decoder 510 is configured to select a line for a memory read / write operation. In this respect, the line decoder 510 represents a series of circuits, each coupled to a word line 504 and a word line interconnect 511. The overall size of the line decoder 510 makes it elongated. This shape represents the overall footprint of the circuits constituting the line decoder 510.

[0063] The 3D RAM circuitry 501 also includes column peripheral circuitry 512, which is spaced apart from the bit cell array and located along the same side of the bit cell array 502 as the row decoder 510. Each bit line 508A and each anti-phase line 508B is connected to the column peripheral circuitry 512. The column peripheral circuitry 512 may include multiple sub-circuits performing different functions, such as multiplexers, sense amplifiers, and write drivers. Each pair of bit lines 508A and anti-phase lines 508B is coupled to one or more circuits configured to manipulate the corresponding column bit cell 504. The overall size of the column peripheral circuitry 512 makes it elongated. This shape represents the overall footprint of the circuits constituting the column peripheral circuitry.

[0064] Since the row decoder 510 and the column peripheral circuitry 512 are located on the same side of the bit cell array 502, they are arranged parallel to each other. This is consistent with... Figure 1This differs from the conventional two-dimensional RAM circuit 100, where the two components are orthogonally arranged. It should be clarified that for... Figure 5 In this regard, the positions of the row decoder 510 and the column peripheral circuit 512 can be interchanged or even staggered, and these embodiments are all within the protection scope of this disclosure.

[0065] Some components of the 3D RAM circuit 501 are located in different layers of the three-dimensional integrated circuit 500. These layers are not in... Figure 5 As shown in the text, but will be combined below. Figure 6 Please provide a detailed explanation.

[0066] Figure 6 This is a side view or cross-sectional view of a 3D integrated circuit 500. The side view is taken along the yz plane, where the z-direction is aligned with the column direction.

[0067] The 3D integrated circuit 500 includes a substrate 514, on which an exemplary three-dimensional RAM circuit 501 is fabricated. The three-dimensional integrated circuit 500 is arranged in two layers. A first layer 516A is formed on and above the substrate 514. A second layer 516B is formed on and above the first layer 516B. Each layer represents a specific process technology and is configured to, for example, support memory bit cells or logic transistors. Each layer itself includes multiple layers, such as transistor layers and back-to-work (BEOL) layers, which may contain multiple metallization layers. These layers are typically part of a layered planar technology implementation of integrated electronic circuits.

[0068] An exemplary 3D RAM circuit 501 has a bit cell array 502 formed in a first level 516A. A logic circuit 518 is formed in a second level 516B. The first level 516A also includes a first-level BEOL layer 520 disposed above the bit cell array 502. The second level 516B includes a second-level BEOL layer 522 disposed above the logic circuit 518. The logic circuit 518 may include logic transistors, digital macrocells, and wiring interconnects. The logic circuit 518 may be constructed using CMOS-based process technology.

[0069] A row decoder 510 is also formed in the second level 516B. The row decoder 510 includes active units (transistors) for performing row decoder functions. The column peripheral circuitry 512 includes a first portion 512A, which is disposed in the second level 516B of the three-dimensional integrated circuit 500. A second portion 512B of the column peripheral circuitry 512 is disposed in the first level 516A. The first portion 512A of the column peripheral circuitry may include a sense amplifier and a write driver. The second portion 512B may include column select / multiplexer circuitry.

[0070] The row decoder 510 and column peripheral circuitry 512 are coupled to unit 504 via various metal layers and vias formed in the first-level BEOL layer 520. These metal layers and vias are not in Figure 6 As shown below, Figure 7 Explanation

[0071] Figure 7 for Figure 5 and Figure 6 The image shown is a 3D view of the 500 integrated circuit. For clarity, Figure 7 The logic circuit 518, metal traces, vias, and various insulating layers between layers are not shown. Figure 7 The arrangement of metal traces and vias for the connection bit unit 504, row decoder 510, and column peripheral circuitry, first part 512A and second part 512B, is shown in further detail.

[0072] exist Figure 7 In the middle, bit line 508A and anti-phase line 508B are formed in the intermediate metallization layer of the same layer as bit cell 504. Word line 506 is formed in the first metal layer M1 of the first-level BEOL layer 520. Word line interconnect 511 is formed in the second metal layer M2 of the first-level BEOL layer 520. Via 511V is formed at the intersection of word line interconnect 511 in the second metal layer M2 and word line 506 in the first metal layer M1, typically as follows: Figure 7 As shown, the end of the word line interconnect 511 formed in the second metal layer M2 is between the word line 506 in the first metal layer M1. The word line interconnect 511 is coupled to the row decoder 510 through via 524. The first portion 512A and the second portion 512B of the column peripheral circuit 512 are coupled to each other and to the bit line through via 526.

[0073] Figure 8A A top view of a 3D integrated circuit 500 is shown. This figure illustrates a set of four 3D memory circuits, hereinafter referred to as 3D RAM circuits, including 3D RAM circuit 501. This view shows the "top" of the second level 516B, but the second level BEOL layer 522 is omitted. Therefore, Figure 8A The top of logic circuit 518, row decoder 510, and column peripheral circuitry first section 512A is shown. Bit cell array 502 is located below the top surface of second level 516B and is therefore shown with dashed lines.

[0074] Because the row decoder 510 and the first part of the column peripheral circuit 512A are configured in parallel. Figure 4The inverted "T" structure shown is no longer present in the second level 516B. Therefore, logic circuit 518 can be designed to extend freely in the row direction. This allows for the use of larger standard logic circuit cells (or macrocells). Since logic circuit 518 does not need to be routed around the row decoder 510 arranged along the column direction, circuit congestion is significantly reduced. Figure 8A In this design, logic circuit 518 spans two bit cell arrays 502 in the "x" direction. For devices containing more bit cells in the "x" direction, logic circuit 518 may span all existing bit cell arrays 502 in the "x" direction. The length of logic circuit 518 in the "x" direction does not need to be an integer multiple of the number of bit cell arrays 502. Instead, logic circuit 518 may partially cover one or more bit cell arrays 502. Furthermore, logic circuit 518 does not need to completely span two bit cell arrays 502. Instead, logic circuit 518 may only extend to the area previously occupied by the row decoder arranged along the "z" direction, so its length in the "x" direction is only slightly greater than a single bit cell array 502. This will be described below. Figure 8B , Figure 8C and Figure 8D The same principle applies.

[0075] Figure 8B This diagram illustrates another arrangement of the three-dimensional integrated circuit 500, where the row decoder 510 and the first section 512A of the column peripheral circuitry are positioned on opposite sides of the bit cell array 502. This arrangement allows for greater freedom in logic circuit design compared to... Figure 8A The advantages of the same arrangement shown.

[0076] Figure 8C Another arrangement of the three-dimensional integrated circuit 500 is shown, in which the row decoder 510 and the first portion 512A of the column peripheral circuitry are aligned with the column (rather than the row) and arranged along one side of the bit cell array 502. In this arrangement, the row decoder can be directly coupled to the word line 506, thus eliminating the need for word line interconnects. However, the bit line 508A and the anti-phase line 508B require bit line interconnects arranged along the row direction. Since the number of bit lines is twice the number of word lines, this layout is less efficient. However, in terms of logic circuit design freedom, it is comparable to the example above (albeit in the column direction). This can be advantageous for certain circuit designs.

[0077] Figure 8DAnother arrangement of the three-dimensional integrated circuit 500 is shown, in which the row decoder 510 and the first portion 512A of the column peripheral circuit are positioned near the center of the bit cell array 502. In this example, they are arranged along the row direction. However, a similar arrangement along the column direction is also possible. Since the row decoder and the first portion 512A of the column peripheral circuit are located in the second level 516B, they are not limited to the edges of the bit cell array 502. Therefore, they can be placed to overlap with the bit cell array 502. By placing the row decoder 510 and the first portion 512A of the column peripheral circuit close to each other, the space and design freedom provided for the logic circuit 518 are... Figure 8A The arrangement shown is similar.

[0078] exist Figure 7 and Figure 8A In the example shown, the first portion 512A and the second portion 512B of the column peripheral circuit have the same or similar dimensions and are aligned in the vertical direction. In this respect, the first portion 512A is located vertically above the second portion 512B. This arrangement facilitates the formation of a simple through-hole connection between the first portion 512A and the second portion 512B. However, since both the second portion 512B and the bit cell array 502 are located in the first level 516A, the second portion 512B should be arranged outside the bit cell array 502, while the position of the first portion 512A can be different. For example, as Figure 8D As shown, the first portion 512A may be located vertically above the bit cell array 502. In this example, a suitable metal trace (not shown) needs to be formed between the first portion 512A and the second portion 512B of the column peripheral circuitry.

[0079] In the above example, the row decoder 510 is shown as a single cell formed in the second level 516B, and the column peripheral circuitry is shown as divided into two parts, formed in the first level 516A and the second level 516B respectively. The column peripheral circuitry 512 can also be designed as a single cell, entirely located in the second level 516B, similar to the arrangement of the row decoder 510. Alternatively, the row decoder 510 can also be divided into two parts, one located in the first level 516A and the other in the second level 516B. For both types of circuitry, any part located in the first level 516A should be located outside the bit cell array 502. Any part located in the second level 516B can be parallel-aligned and arranged adjacently to maximize the design freedom of the logic circuitry.

[0080] In an embodiment where all components of the column peripheral circuitry 512 are located in the second level, the row decoder 510 and the column peripheral circuitry 512 can be arranged in the second level in an area aligned with and above the bit cell array 502. In this example, suitable wiring can be provided via the first-level BEOL layer 520 to couple the word line interconnect 511, bit line 508A, and anti-phase line 508B to the peripheral circuitry. Similar to the previous embodiments, in this example, the row decoder 510 and the column peripheral circuitry 512 can be aligned in parallel to maximize the space provided for the logic circuitry 518 in the second level.

[0081] The row decoder 510 and column peripheral circuitry 512 are typically elongated, meaning their elongation in the elongated direction is greater than their width or depth. Since both circuits need to be coupled to all bit cells 504, the elongation of the row decoder 510 and column peripheral circuitry 512 typically reaches at least the width of the bit cell array 502. In this respect, their elongation in the elongated direction can be the same or similar. Figure 5 In the example shown, the extension in the elongated direction is the same as the extension in the row direction. Figure 5 In the example shown, the row decoder 510 and the first part of the column peripheral circuitry 512A are arranged adjacent to each other. In this respect, since the row decoder 510 and the first part of the column peripheral circuitry 512A are a collection of circuit components, the row decoder 510 and the first part 512A can be directly adjacent or slightly separated, but no other components or circuits will be formed between them. They can be placed as close as possible without affecting the circuit function.

[0082] The positions of the row decoder 510 and the first part 512A of the column peripheral circuitry in the second level 516B are not limited by the bit cell array 502. However, in Figure 8A , Figure 8B and Figure 8C In the examples shown, the row decoder 510 and the first portion 512A of the column peripheral circuitry are positioned on one side of the bit cell array 502 to form the shortest path with corresponding elements in the first level 516A. In these examples, the row decoder 510 and the first portion 512A of the column peripheral circuitry are located in a region of the second level 516B, which is perpendicularly located above a region in the first level 516A that is adjacent to and extends along the side of the bit cell array 502.

[0083] In the above example, the vertical direction is defined as the y-direction. Layers are stacked in the vertical direction. The horizontal plane is defined as the xz plane. The bit cell array 502 and the logic circuit 518 extend within the horizontal plane. When the specification or claims refer to a component or layer being "above" another component or layer, it refers only to the relative orientation shown in the figures. In actual use, the orientation of the devices may be different (e.g., inverted). In this respect, the relative positions of the components are described within the context of the conventional arrangement shown in the figures. For example, in terms of layers, each layer has a main surface and a certain thickness. The second layer 516B is stacked on the main surface of the first layer 516A.

[0084] In the example above, "two-dimensional (2D)" is used to describe circuits that do not extend into multiple layers. In this respect, while two-dimensional circuits do have depth (technically a third dimension), their circuit components are typically arranged in the same plane.

[0085] The first layer 516A and the second layer 516B can be manufactured using sequential integration technology, that is, the second layer is manufactured sequentially above the first layer. Alternatively, the first layer 516A and the second layer 516B can be manufactured separately and then coupled together using bonding techniques such as hybrid bonding.

[0086] The above embodiments should be understood as exemplary examples of the present invention. Other embodiments of the present invention are conceivable. It should be understood that any feature described with respect to any embodiment may be used alone, or in combination with other described features, or in combination with one or more features of any other embodiment, or in any combination of any other embodiment. Furthermore, equivalents and modifications not described above may be employed without departing from the scope of protection of the present invention as defined by the appended claims.

Claims

1. A three-dimensional integrated circuit, comprising: First level; The second layer is stacked vertically on top of the first layer; as well as Memory circuitry, including: A bit cell array, wherein the bit cell array is disposed in the first level and includes multiple bit cells arranged in multiple rows and multiple columns; Multiple character lines are provided in the first level, and each character line connects to a row unit in the multiple rows; Multiple bit lines are disposed in the first level, and each bit line connects to a column of bit cells in the multiple columns; A column peripheral circuit, coupled to each of the plurality of bit lines and configured to read / write data from the bit cell array during a read / write operation, the column peripheral circuit having at least one elongated first portion disposed in the second level; and A row decoder, coupled to each of the plurality of word lines and configured to select one row of bit cell rows during the read / write operation, the row decoder being elongated and disposed in the second level and extending in a direction parallel to the first portion of the column peripheral circuitry.

2. The three-dimensional integrated circuit as described in claim 1, characterized in that, The length of the first portion of the column peripheral circuit and the length of the row decoder in the elongated direction are greater than or equal to the range of the bit cell array in the row or column direction.

3. The three-dimensional integrated circuit as described in claim 1 or 2, characterized in that, The first portion of the column peripheral circuitry and the row decoder are each positioned in the second level, above the region of the bit cell array adjacent to the first side of the bit cell array in the first level.

4. The three-dimensional integrated circuit as described in any one of claims 1 to 3, characterized in that, The first portion of the column peripheral circuit and the row decoder are arranged in parallel with the multiple rows; and the memory circuit further includes a plurality of word line interconnects, each word line interconnect being coupled between a corresponding word line among the plurality of word lines and the row decoder.

5. The three-dimensional integrated circuit as described in claim 4, characterized in that: Each of the plurality of word line interconnects is arranged parallel to the plurality of bit lines and aligned with one column of the plurality of bit cell columns; and The line decoder includes multiple word line transistor circuits, each of which is coupled to and aligned with a corresponding word line interconnect.

6. The three-dimensional integrated circuit as described in claim 5, characterized in that, Word line interconnects near the edge of the bit cell array are coupled to the word line closest to the line decoder, while word line interconnects near the center of the bit cell array are coupled to the word line farthest from the line decoder.

7. The three-dimensional integrated circuit as described in any of the preceding claims, characterized in that, The plurality of word lines are formed in a first metallization layer of the first level, and the plurality of word line interconnects are formed in a second metallization layer perpendicularly above the first metallization layer in the first level; the three-dimensional integrated circuit further includes a plurality of word line vias, each word line via being configured to couple a word line to a word line interconnect and extending perpendicularly from the first metallization layer to the second metallization layer.

8. The three-dimensional integrated circuit as described in any of the preceding claims, characterized in that, The column peripheral circuitry includes a second portion disposed in a region adjacent to the first side of the bit cell array in the first layer, wherein the first portion of the column peripheral circuitry includes a plurality of sense amplifiers and a plurality of write drivers, each disposed in the second layer and aligned with a corresponding bit cell column, and the second portion of the column peripheral circuitry further includes a column multiplexer.

9. The three-dimensional integrated circuit as described in any of the preceding claims, characterized in that, Each of the plurality of bit lines is aligned with a corresponding column of bit cells, while each of the plurality of word lines is aligned with a corresponding row of bit cells, and the plurality of bit lines and the plurality of word lines are orthogonal to each other.

10. The three-dimensional integrated circuit as described in any one of the preceding claims, characterized in that, It further includes one or more core logic circuits disposed in the second level.

11. The three-dimensional integrated circuit as claimed in any of the preceding claims, characterized in that: The first level includes a first device layer and a first back-end process BEOL layer stacked on top of the first device layer; The second layer includes a second device layer and a second BEOL layer stacked on top of the second device layer; and The bit cell array is formed in the first device layer, while the line decoder is formed in the second device layer.

12. The three-dimensional integrated circuit as described in any of the preceding claims, characterized in that, The first level and the second level can be sequentially integrated or bonded.

13. The three-dimensional integrated circuit as described in any of the preceding claims, characterized in that, It further includes a plurality of the aforementioned memory circuits, which are arranged in pairs, with each pair of memory circuits arranged in a butterfly configuration.

14. The three-dimensional integrated circuit as claimed in any of the preceding claims, characterized in that, The memory circuit is a random access memory (RAM) circuit.

15. An integrated memory and logic device, comprising: The plurality of three-dimensional integrated circuits as described in any one of claims 1 to 14 are arranged in multiple rows and multiple columns; in The row decoders and column peripheral circuits of the multiple three-dimensional integrated circuits are arranged in parallel rows.

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