Operation method of memory and memory

Abstract

The embodiment of the invention provides an operation method of a memory and the memory. The memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array; the memory cell array comprises a plurality of first address lines, a plurality of second address lines and a plurality of memory cells; the operation method of the memory comprises the following steps: during a first write operation, applying a first voltage to a selected first address line, applying a second voltage to a selected second address line, and applying a reference voltage to a non-selected second address line; wherein the reference voltage is smaller than the first voltage and larger than the second voltage; sensing a memory state of the selected memory cell based on the first voltage and the second voltage; according to the storage state of the storage unit, maintaining the reference voltage or increasing the reference voltage to a third voltage so that the storage unit is written into a first target state; wherein the third voltage is smaller than the first voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for operating a memory and a memory. Background Technology

[0002] Phase-change random access memory (PCRAM) bridges the performance gap between dynamic random access memory (DRAM) and flash memory, offering advantages such as high-speed read / write speeds, high erasing / write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation, leading to its widespread use. However, PCRAM power consumption has always been a bottleneck for PCRAM chips, necessitating optimization of PCRAM operations to reduce or avoid power waste. Summary of the Invention

[0003] This application provides a memory operation method and a memory that can reduce or avoid memory power consumption waste.

[0004] In a first aspect, embodiments of this application provide a method for operating a memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array including multiple first address lines, multiple second address lines, and multiple memory cells; the method for operating the memory includes: during a first write operation, applying a first voltage to selected first address lines, applying a second voltage to selected second address lines, and applying a reference voltage to unselected second address lines; wherein the reference voltage is less than the first voltage and greater than the second voltage; sensing the storage state of selected memory cells based on the first voltage and the second voltage; and maintaining the reference voltage or increasing the reference voltage to a third voltage according to the storage state of the memory cells to write the memory cells to a first target state; wherein the third voltage is less than the first voltage.

[0005] In some embodiments, the memory operation method includes: in response to a storage state being a first state matching a first target state, maintaining the voltage values ​​of a first voltage, a second voltage, and a reference voltage for a first duration to maintain the storage state of a selected memory cell as the first target state.

[0006] In some embodiments, the memory operation method includes: in response to a storage state being a second state that does not match a first target state, maintaining the voltage values ​​of a first voltage, a second voltage, and a reference voltage for a second duration; increasing the first voltage and maintaining the reference voltage, and maintaining the increased first voltage, second voltage, and reference voltage for a third duration; wherein the increased first voltage is less than or equal to a first preset value; decreasing the increased first voltage and maintaining the reference voltage, and maintaining the decreased first voltage, second voltage, and reference voltage values ​​for a fourth duration, so that the storage state of a selected memory cell is changed from the second state to the first target state; wherein the decreased first voltage is greater than the reference voltage.

[0007] In some embodiments, the fourth duration is greater than the sum of the third and second durations.

[0008] In some embodiments, the memory operation method includes: in response to a storage state being a second state that does not match a first target state, maintaining the voltage values ​​of a first voltage, a second voltage, and a reference voltage for a fifth duration; increasing the first voltage and increasing the reference voltage to a third voltage, and maintaining the increased voltage values ​​of the first voltage, the second voltage, and the third voltage for a sixth duration; wherein the increased first voltage is greater than a first preset value; decreasing the increased first voltage and decreasing the third voltage to a reference voltage, and maintaining the decreased voltage values ​​of the first voltage, the second voltage, and the reference voltage for a seventh duration, so that the storage state of a selected memory cell is changed from the second state to the first target state; wherein the decreased first voltage is greater than the reference voltage.

[0009] In some embodiments, the sixth duration is greater than or equal to the fifth duration; the seventh duration is greater than the sum of the sixth and fifth durations.

[0010] In some embodiments, the peripheral circuitry includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are coupled to the memory cell via a first address line and a second address line, respectively; the memory cell array includes a first region and a second region; the second region is located outside the first region; the electrical distance between the memory cells in the first region is less than the electrical distance between the memory cells in the second region; wherein the electrical distance is the sum of a first length of the first address line between the memory cell and the first driving circuit and a second length of the second address line between the memory cell and the second driving circuit; the memory operation method further includes: determining whether the selected memory cell belongs to the first region before performing a first write operation; and maintaining a reference voltage if the selected memory cell belongs to the first region during the first write operation.

[0011] In some embodiments, the method of operating the memory includes: in response to the memory state being a second state, increasing a first voltage while decreasing a second voltage.

[0012] In some embodiments, the memory operation method includes: during a second write operation, applying a fourth voltage to a selected first address line and applying a fifth voltage to a selected second address line, so that the storage state of the selected memory cell is a second target state; wherein the resistance value of the memory cell in the second target state is greater than the resistance value in the first target state.

[0013] In a second aspect, embodiments of this application provide a memory comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array comprising a plurality of first address lines, a plurality of second address lines, and a plurality of memory cells; the peripheral circuitry being configured to perform any of the operating methods provided in the first aspect.

[0014] In various embodiments of this application, the process of the first write operation (which can be understood as a set operation) can be optimized. During at least a portion of the set operation, the voltage applied to the unselected second address line can be maintained at the reference voltage. That is, during at least a portion of the set operation, it is not necessary to apply a third voltage greater than the reference voltage to the unselected second address line, thus avoiding power waste caused by applying unnecessarily high voltages to the unselected second address line during the set operation. This reduces or avoids memory power waste and optimizes memory power consumption. Attached Figure Description

[0015] Figure 1 A block diagram of a memory system provided in an embodiment of this application; Figure 2 A block diagram of an exemplary memory including a storage array and peripheral circuitry provided for embodiments of this application; Figure 3 Block diagrams of exemplary storage arrays and exemplary peripheral circuits provided for embodiments of this application; Figure 4 One of the three-dimensional schematic diagrams of a memory provided in an embodiment of this application; Figure 5 A second three-dimensional schematic diagram of a memory provided in an embodiment of this application; Figure 6 A schematic diagram of pulses during each operation process of the storage unit provided in the embodiments of this application; Figure 7 This is one of the pulse diagrams for the set operation provided in the embodiments of this application; Figure 8 This is the second pulse diagram of the set operation provided in the embodiments of this application; Figure 9 This is the third pulse diagram illustrating the set operation provided in the embodiments of this application; Figure 10Fourth of four schematic diagrams of the pulse for setting operation provided in the embodiments of this application; Figure 11 Fifth of the pulse diagrams for the set operation provided in the embodiments of this application; Figure 12 A schematic diagram of the planar layout of a storage cell array including a first region and a second region, provided for an embodiment of this application; Figure 13 for Figure 12 A simplified diagram; Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application. Detailed Implementation

[0016] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0018] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0020] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0022] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0023] This application provides a system comprising: a host and a memory system coupled to the host (see reference). Figure 1 The system can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The host can be the processor of the electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), where the SoC can be, for example, an application processor (AP). The host can be configured to send data to or receive data from the memory system.

[0024] Figure 1 A block diagram of a memory system provided in an embodiment of this application.

[0025] refer to Figure 1 This application provides a memory system 100 including: a memory 300; and a memory controller 200 coupled to the memory 300 and configured to control the memory 300.

[0026] In some embodiments, the memory controller 200 may control the overall operation of the memory system 100, such as write operations, read operations, and refresh operations. In some embodiments, the memory controller 200 is configured to store data in the memory 300, or to read data stored in the memory 300.

[0027] In some embodiments, the memory controller 200 is also configured to handle error checking and correction (ECC) of data read from or written to the memory 300. In some embodiments, the memory controller 200 may also be configured to manage various functions relating to data stored or to be stored in the memory, including but not limited to logical-to-physical address translation, bad block management, garbage collection, wear leveling, etc.

[0028] In some embodiments, memory 300 may include one of phase-change random access memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), and nanotube random access memory (NRAM).

[0029] In some embodiments, the memory controller 200 is also configured to store various information required for the operation of the memory system 100 (e.g., metadata information and mapping tables) into volatile memory. Figure 1 (Not shown), and memory 300 can be accessed based on information stored in volatile memory. In some embodiments, the volatile storage device may include dynamic random access memory, static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), or double-data-rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM).

[0030] Figure 2 A block diagram of an exemplary memory including a storage array and peripheral circuitry, provided for embodiments of this application.

[0031] refer to Figure 2 The memory 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. In some embodiments, the peripheral circuitry 302 is configured to control the overall operation of the memory 300, such as write operations, read operations, and refresh operations. In some embodiments, the peripheral circuitry 302 is configured to store data in the memory array 301, or to read data stored in the memory array 301.

[0032] Figure 3 Block diagrams of exemplary memory arrays and exemplary peripheral circuits provided for embodiments of this application.

[0033] refer to Figure 3The memory 300 may include a memory array 301 and peripheral circuitry coupled to the memory array 301. In some embodiments, the memory array 301 may include word lines WL, bit lines BL, and memory cells 301a formed between the word lines WL and BL; the memory cells 301a are located at the intersection between the word lines WL and BL and are coupled to the word lines WL and BL. In some embodiments, the peripheral circuitry may be configured to apply word line voltages to selected word lines WL and bit line voltages to selected bit lines BL, operating the memory cells 301a of the memory array 301. In some embodiments, the peripheral circuitry may include: control logic 312, an address register 314, a voltage generator 310, a row decoder / word line driver 308, a page buffer / sensor amplifier circuit 304, a column decoder / bit line driver 306, and a data register / data I / O 316.

[0034] Page buffer / sensor amplifier circuit 304 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store programming data (write data) to be programmed into a page of memory array 301. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal representing a data bit stored in the memory cell from the selected bit line and amplify a small voltage swing to a recognizable logic level during a read operation. In some embodiments, page buffer / sensor amplifier 304 may include a comparator (e.g., a voltage comparator) for comparing a voltage signal (e.g., a read voltage) with a reference voltage signal. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more memory cells and bit lines. Column decoder / bit line driver 306 can be further configured to drive the selected bit line. The column decoder / bit line driver 306 may be further configured to drive the bit lines using a bit line voltage generated from the voltage generator 310. The column decoder / bit line driver 306 may be a binary data storage device for storing bits. In some embodiments, the column decoder / bit line driver 306 may include a read data latch to store read data.

[0035] The data register / data I / O 316 may be coupled to the page buffer / sensor amplifier 304, and / or coupled to the column decoder / bit line driver 306, and is configured to route data input from the data bus 318 to the desired memory cell of the memory array 301, and to route data output from the desired memory cell to the data bus 318.

[0036] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select one or more memory cells and word lines of the memory array 301. The row decoder / word line driver 308 can be further configured to drive the selected word lines. The row decoder / word line driver 308 can be further configured to drive the word lines using word line voltages generated from voltage generator 310.

[0037] The voltage generator 310 can be configured to be controlled according to control signals from the control logic 312 and to generate word line voltages, bit line voltages and reference voltages to be supplied to the memory array 301.

[0038] Control logic 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each of the peripheral circuits. Control logic 312 is configured to receive a clock signal ( Figure 3 (Not shown), command signal CMD, address signal ( Figure 3 (Not shown) and data signal DQ, wherein command signal CMD is received via command bus 320; and data signal DQ is received via data bus 318. In some embodiments, control logic 312 may be implemented by a microprocessor, microcontroller (also known as a micro controller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described.

[0039] In some embodiments, memory 300 may be phase-change random access memory (PDRAM), and memory cells 301a of memory array 301 may be phase-change memory cells. In some embodiments, the PDRAM has a transistorless crosspoint architecture, which positions the phase-change memory cells between intersecting (e.g., perpendicular) word lines and bit lines. The word lines and bit lines may be made of a conductive material with equal linewidth (Line / Space, L / S) formed after a patterning process. The phase-change memory cell may include stacked gating elements and phase-change memory elements.

[0040] In this document, the first direction, the second direction, and the third direction intersect each other (e.g., are orthogonal). The first direction can be understood as the extension direction of the first address line, the second direction as the extension direction of the second address line, and the third direction as the stacking direction of each layer / component of the phase-change memory cell. For example, the first direction is represented by the X direction in the attached figure; the second direction is represented by the Y direction in the attached figure; and the third direction is represented by the Z direction in the attached figure. Any two of the X, Y, and Z directions are orthogonal to each other.

[0041] Figure 4 This is one of the three-dimensional schematic diagrams of a memory provided in an embodiment of this application.

[0042] refer to Figure 4 In some embodiments, the memory includes word line WL, phase change memory unit 301-0, and bit line BL stacked sequentially from bottom to top; the phase change memory unit 301-0 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top.

[0043] In some embodiments, the word line WL and bit line BL are made of conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, conductive nitrides, or any combination thereof. The word line WL and bit line BL may have the same conductive material or different conductive materials. Exemplarily, the word line WL and bit line BL are made of tungsten.

[0044] In some embodiments, the first electrode 3011, the second electrode 3013, and the third electrode 3015 are electrode layers in a phase-change memory cell, used for conducting electrical signals. It should be noted that... Figure 4 The electrode layers, designated by different reference numerals in the accompanying drawings, are merely for distinguishing differences in the location of the electrode layers and are not necessarily used to describe a specific order or sequence. In some embodiments, the materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may be the same or different. The materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may include amorphous carbon, such as α-phase carbon.

[0045] In some embodiments, the material of the gating element 3012 may include: an octane threshold switching (OTS) material, such as Zn. a Te b 、Ge a Te b 、Nb a O b Or Si a As bTe c etc., where a, b, and c represent stoichiometric coefficients.

[0046] In some embodiments, the phase change memory element 3014 is made of a chalcogenide-based phase change material. Exemplarily, the phase change memory element 3014 is made of a binary phase change material, such as GaSb, InSb, InSe, Sb₂Te₃, Sb₇Te₃, GeTe, etc. Exemplarily, the phase change memory element 3014 is made of a ternary phase change material, such as Ge₂Sb₂Te₅, Ge₁Sb₄Te₇, InSbTe, GaSeTe, etc. Exemplarily, the phase change memory element 3014 is made of a quaternary phase change material, such as AgInSbTe, GeTeSbS, GeTeInGa, etc.

[0047] Figure 5 This is a second three-dimensional schematic diagram of a memory provided in an embodiment of this application. Figure 5 The memory shown can be understood as a three-dimensional memory, which can consist of multiple... Figure 4 The memory modules shown are stacked together.

[0048] In some embodiments, the memory includes an upper memory structure 301-U and a lower memory structure 301-D stacked sequentially from top to bottom. The lower memory structure 301-D includes a word line WL, a phase-change memory cell 301-1, and a bit line BL stacked sequentially from bottom to top. The phase-change memory cell 301-1 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The upper memory structure 301-U is located above the lower memory structure 301-D and includes a bit line BL, a phase-change memory cell 301-2, and a word line WL stacked sequentially from bottom to top. The phase-change memory cell 301-2 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The materials for the word line WL, bit line BL, first electrode 3011, gating element 3012, second electrode 3013, phase change memory element 3014, and third electrode 3015 can be referenced. Figure 4 The relevant embodiments will be understood from here, and will not be repeated. It is understood that the bit line BL of the upper memory structure 301-U and the bit line BL of the lower memory structure 301-D can be understood as a common bit line.

[0049] Figure 4 and Figure 5The word line WL and bit line BL in the illustrated memory can also be understood by interchanged positions. In practical applications, by activating the selected word line and the selected bit line, the phase-change memory cell connected to both the selected word line and the selected bit line can be selected.

[0050] Figure 6 This is a pulse diagram illustrating the various operational processes of the phase-change memory unit provided in the embodiments of this application. It should be noted that... Figure 6 The voltage pulses shown are only used to illustrate the principle of the transition between the crystalline and amorphous states of the phase change material in the phase change memory cell. The actual pulses in each operation process of the phase change memory cell can be based on... Figure 6 The principle of the voltage pulse shown is adapted accordingly. For example, Figure 6 The voltage pulse for the SET operation shown is a voltage plateau, but in practice it can also be multiple voltage plateaus in a stepped pattern. For example, Figure 6 The voltage pulses of the RESET operation shown above the melting temperature TM exhibit a curve of rising and then falling, and may actually include a voltage plateau.

[0051] refer to Figure 6In some embodiments, the memory utilizes the crystalline and amorphous properties of the phase change material in the phase change memory cell to store data. Different electrical pulses are used to induce a rapid and reversible phase transition between the amorphous and crystalline states of the phase change material. During the transition between the crystalline and amorphous states of the phase change material in the phase change memory cell, different pulses (e.g., light pulses, electrical pulses) can be used to control the heating of the phase change material. In one optional implementation, a long and medium-intensity programming pulse (also known as a Set Pulse) is applied to raise the temperature of the phase change material in the phase change memory cell above the crystallization temperature TX but below the melting temperature TM, and this temperature is maintained for a period of time to promote nucleus growth. This allows the phase change material in the phase change memory cell to transition from an amorphous state (corresponding to a high-resistivity state) to a crystalline state (corresponding to a low-resistivity state). The process of changing the phase change material in the phase change memory cell from a high configuration (logic state "0") to a low-resistivity state (logic state "1") is called a set operation, or a write operation. After applying a short and high-intensity reset pulse (also known as a Reset Pulse) to raise the temperature of the phase change material in the phase change memory cell above the melting temperature TM, it is then rapidly cooled. The reset (or erase) operation is a process that enables the phase change material of a phase change memory cell to transition from a crystalline to an amorphous state. This process, where the phase change material changes from a low-resistance state (logic state "1") to a high-resistance state (logic state "0"), is called the reset operation or the erase operation. The reset and set operations are reversible. A phase change memory cell can use the crystalline state of the phase change material to represent binary data "1" and the amorphous state to represent binary data "0". In some embodiments, a short, low-intensity read pulse (also called a read pulse) is applied to keep the temperature of the phase change material far below its crystallization temperature TX, preventing a phase change. The current in the circuit is measured to determine the resistance of the phase change material. Based on the resistance value, the read data is determined to be either "0" or "1". This process is called the read operation (RD). For example, the set operation of the memory requires time t3 to complete, the reset operation requires time t2 to complete, and the read operation requires time t1 to complete, wherein time t2 is greater than time t1, and time t3 is greater than time t2.

[0052] Figure 7 This is one of the pulse diagrams for the set operation provided in the embodiments of this application.

[0053] refer to Figure 7 Compared to the reset operation (see reference) Figure 6The set operation of a memory requires a long pulse (e.g., an electrical pulse) to complete. For example, to perform a set operation on a selected phase-change memory cell, a first voltage V1 (greater than the reference voltage VSS, and can have different step voltages, such as 2V, 3V, or 4V) needs to be applied to the selected word line selWL, and a second voltage V2 (less than the reference voltage VSS, such as -3V; and can also have different step voltages) needs to be applied to the selected bit line selBL. Figure 7 (Not shown); a third voltage V3 (greater than the reference voltage VSS, e.g., 0.8V, 1.0V, 1.2V, or 1.4V) also needs to be applied to the unselected bit line unsel BL to reduce the problem of array leakage in phase-change memory cells. Because the set operation requires little current and the voltage applied to the selected word line is low during at least part of the set operation, it is not necessary to apply a high third voltage V3 (e.g., 1.2V) to the unselected bit line throughout the entire set operation. Therefore, the set operation process needs to be optimized to reduce or avoid memory power consumption waste and optimize memory power consumption.

[0054] Figure 8 This is the second pulse diagram of the set operation provided in the embodiments of this application. Figure 9 The third schematic diagram of the pulse for the set operation provided in the embodiments of this application. Figure 10 The fourth pulse diagram of the set operation provided in the embodiments of this application. Figure 11 This is the fifth schematic diagram of the pulse for the set operation provided in the embodiments of this application. It should be noted that, for ease of reference... Figure 8 , Figure 9 , Figure 10 and Figure 11 Comparing them with each other, Figure 8 , Figure 9 , Figure 10 and Figure 11 Each stage is identified as P1-1, P1-2, P1-3, P2, P3, P4, and P5, and time points t1, t2, t3, t4, t5, t6, t7, and t8 are also identified, along with durations T1, T2, T3, T4, T5, T6, and T7. However, this does not necessarily mean... Figure 8 , Figure 9 , Figure 10 and Figure 11 The first write operation in the illustrated embodiments all requires passing through stages P1-1 to P5. For example, refer to... Figure 8 The first write operation goes through stages P1-1 to P1-3; see reference. Figure 9 , Figure 10 or Figure 11The first write operation goes through stages P1-1 to P5. For example, Figure 9 and Figure 10 The first write operation can also omit stage P1-2 or stage P1-3. Figure 8 It is also shown that the sensing current Curr in stage P1-1 is current Ih, and the sensing current Curr in stage P1-2 is current Is. Figure 9 , Figure 10 and Figure 11 It is also shown that the sensing current Curr in stage P1-1 is current Ih, the sensing current Curr in stages P1-2 and P1-3 is current I1, and the sensing current Curr in stages P2, P3, P4, and P5 are currents I2, I3, I4, and I5, respectively. It should be noted that the reference... Figure 8 , Figure 9 , Figure 10 and Figure 11 The durations T1, T2, T3, T4, T5, T6, and T7 shown can all be adaptively increased or decreased.

[0055] refer to Figure 8 , Figure 9 , Figure 10 or Figure 11 According to a first aspect of this application, a method for operating a memory is provided. The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple first address lines, multiple second address lines, and multiple memory cells. The method for operating the memory includes: during a first write operation, applying a first voltage V1-1 to selected first address lines, applying a second voltage V2-1 to selected second address lines, and applying a reference voltage V3-1 to unselected second address lines; wherein the reference voltage V3-1 is less than the first voltage V1-1 and greater than the second voltage V2-1; sensing the storage state of selected memory cells based on the first voltage V1-1 and the second voltage V2-1; and maintaining the reference voltage V3-1 or increasing the reference voltage to a third voltage V3-2 (reference voltage V3-1) according to the storage state of the memory cells. Figure 10 or Figure 11 In various embodiments of this application, the process of the first write operation (which can be understood as a set operation) can be optimized. During at least a portion of the set operation, the voltage applied to the unselected second address line can be maintained at the reference voltage. That is, during at least a portion of the set operation, it is not necessary to apply a third voltage greater than the reference voltage to the unselected second address line, thus avoiding power waste caused by applying unnecessarily high voltages to the unselected second address line during the set operation. This reduces or avoids memory power waste and optimizes memory power consumption.

[0056] Here and below, the memory array and peripheral circuitry can be referenced from the above. Figure 2 and Figure 3 To understand the relevant descriptions, refer to the storage units of the storage unit array. Figure 4 and Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0057] Herein and below, the first address line can be understood as one of the word line WL and the bit line BL, and the second address line can be understood as the other of the word line WL and the bit line BL. In the following description, the example of the first address line being the word line WL and the second address line being the bit line BL is used, and this example is not intended to limit the embodiments of this application.

[0058] Here and below, the first write operation can be understood as a set operation, and the second write operation can be understood as a reset operation. To describe the embodiments of this application, the first write operation can be understood in multiple stages. (See reference...) Figures 9 to 11 In some embodiments, the first write operation may include a first stage and a second stage; the first stage of the first write operation can be understood as a heating stage, which allows the temperature of the phase change material in the phase change memory cell to rise to the crystallization temperature TX (see reference) relatively quickly. Figure 6 Above and controlled at the melting temperature TM (reference) Figure 6 Under this condition, the first stage involves sensing the current Curr through the phase change material. Figures 9 to 11 Except for the current spikes shown, it remains basically unchanged; the second stage of the first write operation can be understood as the nucleus growth stage and the cooling stage. The nucleus growth stage can promote the nucleus growth of the phase change material in the phase change memory cell, so that the phase change material of the phase change memory cell presents a crystalline state (low configuration, indicated by logic state "1"). The cooling stage occurs after the phase change material presents a crystalline state. The second stage is achieved through the sensing current Curr of the phase change material (Curr). Figures 9 to 11 The sensing current Curr shown is in chronological order as current I2, current I3, current I4, and current I5, which increases and then decreases.

[0059] Here and below, sensing can be understood as connecting the selected second address line (or the selected first address line) to the sensing amplifier (see reference). Figure 3 The sensing amplifier 304 shown is connected to sense the storage state of the selected phase change memory cell coupled to the selected first address line and the selected second address line.

[0060] Figure 8 This is the second pulse diagram of the set operation provided in the embodiments of this application.

[0061] refer to Figure 8In some embodiments, the memory operation method includes: in response to a storage state being a first state matching a first target state, maintaining the voltage values ​​of a first voltage V1-1, a second voltage V2-1, and a reference voltage V3-1 for a first duration ( Figure 8 The durations T1, T2, and T3 shown are summed to maintain the storage state of the selected phase-change memory cell in the first target state. In this embodiment, the storage state of the phase-change memory cell can be identified by sensing as the first state (which can be understood as the state after the first target state degradation), and a first write operation matching the first state can be performed, thereby reducing or avoiding memory power consumption waste. Compared to the case where the storage state of the selected phase-change memory cell changes from the second target state to the first target state, in this embodiment, the storage state of the selected phase-change memory cell changes from the first state matching the first target state to the first target state. The voltage applied to the selected first address line can be maintained at the first voltage, and the voltage applied to the unselected second address line can be maintained at the reference voltage (or the unselected second address line can be set to a floating state or a ground state), thereby reducing or avoiding memory power consumption waste.

[0062] It should be noted that when the first write operation to a phase-change memory cell is completed, the storage state of the phase-change memory cell is the first target state. After the storage state of the phase-change memory cell is maintained for a period of time, or after the phase-change memory cell has been read a certain number of times, the storage state of the phase-change memory cell is the first state. The first state can be understood as the state after the first target state has degraded. In some cases, although the first target state and the first state can still be distinguished / identified from the second target state by read operations, reading a phase-change memory cell in the first state will cause a higher raw bit error rate (RBER) or error rate compared to reading a phase-change memory cell in the first target state. This phenomenon is called slow read disturbance (SRD) in phase-change random access memory. In some embodiments, the longer the storage state of the phase-change memory cell is maintained, or the more times the phase-change memory cell is read, the more severe the slow read disturbance becomes.

[0063] In some embodiments, the voltage value of the first voltage V1-1 ranges from 2V to 5V. For example, the voltage value of the first voltage V1-1 is 2.5V, 3V, 3.5V, 4V, or 4.5V.

[0064] In some embodiments, the voltage value of the second voltage V2-1 ranges from -2V to -5V. For example, the voltage value of the second voltage V2-1 is -2.5V, -3V, -3.5V, -4V, or -4.5V.

[0065] In some embodiments, the reference voltage V3-1 has a voltage range of -0.5V to 0.5V. Exemplarily, the reference voltage V3-1 may have a value of -0.4V, -0.3V, -0.2V, -0.1V, 0V, 0.1V, 0.2V, 0.3V, or 0.4V. In some embodiments, the second address line is either in a floating state or a grounded state. In some embodiments, the reference voltage V3-1 may be a reference voltage VSS. The reference voltage VSS may have a value of 0V or a value near 0V. Exemplarily, the reference voltage VSS may have a value of -0.5V, -0.4V, -0.3V, -0.2V, -0.1V, 0V, 0.1V, 0.2V, 0.3V, 0.4V, or 0.5V.

[0066] In some embodiments, the first duration is less than or equal to 100 ns. Exemplarily, the first duration is less than or equal to 40 ns, 50 ns, 60 ns, 70 ns, 80 ns, or 90 ns. Exemplarily, the first duration is 10 ns, 15 ns, 20 ns, 25 ns, 30 ns, or 35 ns. Here and below, the first target storage state can be understood as the phase change material of the phase change memory cell being in a crystalline state, i.e., in a low-resistivity state (logic state "1"); the second target storage state can be understood as the phase change material of the phase change memory cell being in a non-crystalline state, i.e., in a high-configuration state (logic state "0").

[0067] Figure 9 The third schematic diagram of the pulse for the set operation provided in the embodiments of this application.

[0068] refer to Figure 9 In some embodiments, the memory operation method includes: in response to a second state in which the storage state does not match a first target state, maintaining the voltage values ​​of the first voltage V1-1, the second voltage V2-1, and the reference voltage V3-1 for a second duration ( Figure 9 The duration T1 is shown); the first voltage V1-1 is increased while the reference voltage is maintained, and the increased first voltage is maintained ( Figure 9 The voltage values ​​of the voltage V1-2, the second voltage V2-1, and the reference voltage V3-1 shown are maintained for a third duration ( Figure 9 The sum of durations T2 and T3 shown); wherein, the increased first voltage is less than or equal to the first preset value; the increased first voltage is reduced while maintaining the reference voltage V3-1, and the reduced first voltage is maintained ( Figure 9The voltage values ​​shown (V1-4), the second voltage V2-1, and the reference voltage V3-1) are maintained for a fourth duration. Figure 9 The sum of durations T4, T5, T6, and T7 (shown) is used to change the storage state of the selected memory cell from the second state to the first target state; wherein, the reduced first voltage is greater than the reference voltage. In this embodiment, the second state of multiple memory cells may include a first partial state and a second partial state different from the first partial state. Compared to the storage state of the memory cell being in the second partial state, the storage state of the memory cell in this embodiment is in the first partial state. During the first write operation, the voltage applied to the selected first address line is set to be smaller (i.e., the increased first voltage is less than or equal to the first preset value), and the voltage applied to the non-selected second address line can be maintained at the reference voltage (or the non-selected second address line can be set to a floating state or a grounded state), reducing or avoiding memory power consumption waste. Compared to Figure 10 The embodiment shown, Figure 9 In the embodiment shown, the voltage applied to the selected first address line can be set to be smaller (i.e., the increased first voltage is less than or equal to the first preset value).

[0069] In some embodiments, the memory operation method includes: after maintaining voltage V1-2, second voltage V2-1 and reference voltage V3-1 for a duration T2, sensing the storage state of a selected memory cell; and based on the sensed storage state being a second state, continuing to maintain voltage V1-2, second voltage V2-1 and reference voltage V3-1 for a duration T3.

[0070] In some embodiments, the first preset value may be an empirical value; or it may be a default value configured at the time of manufacture of the memory, which is obtained through extensive simulation experiments before the memory leaves the factory. For example, the first preset value may be 4V, 4.5V, or 5.5V.

[0071] In some embodiments, the voltage value of voltage V1-2 ranges from 3V to 6V. Exemplarily, the voltage value of voltage V1-2 is 3.5V, 4V, 4.5V, 5V, or 5.5V. Exemplarily, the voltage value of the first voltage V1-1 ranges from 3V to 3.5V, the voltage value of voltage V1-2 ranges from 4V to 4.5V, and the first preset value can be 4.5V.

[0072] In some embodiments, the second or third duration is less than or equal to 50 ns. Exemplarily, the second or third duration is less than or equal to 20 ns, 30 ns, or 40 ns. Exemplarily, the second or third duration is 5 ns, 10 ns, or 15 ns.

[0073] In some embodiments, the third duration is longer than the second duration. This allows the phase change material of the memory cell to reach its crystallization temperature TX (reference temperature) more rapidly by maintaining a higher voltage for a longer duration. Figure 6 For example, the second duration is 5ns, 10ns, or 15ns, and the third duration is 20ns, 25ns, or 30ns.

[0074] refer to Figure 9 In some embodiments, the fourth duration is greater than the sum of the third and second durations. In the embodiments of this application, the fourth duration being greater than the sum of the third and second durations can ensure sufficient time for the nucleus growth of the phase change material in the storage cell and sufficient time for cooling, thereby achieving sufficient conversion of the crystalline state and its cooling.

[0075] In some embodiments, the second stage of the first write operation may include: the stage in which the phase change material of the memory cell completes nucleus growth ( Figure 9 The stage shown is P3), and the cooling stage after the phase change material of the memory cell completes its nucleation growth (as shown). Figure 9 Stage P4 is shown.

[0076] In some embodiments, the fourth duration is less than or equal to 500 ns. Exemplarily, the fourth duration is less than or equal to 20 ns, 50 ns, 100 ns, 200 ns, 300 ns, or 400 ns. Exemplarily, the fourth duration is 50 ns, 100 ns, 150 ns, 200 ns, 250 ns, 300 ns, 350 ns, 400 ns, or 450 ns.

[0077] Figure 10 The fourth pulse diagram of the set operation provided in the embodiments of this application.

[0078] refer to Figure 10 In some embodiments, the memory operation method includes: in response to a second state in which the memory state does not match a first target state, maintaining the voltage values ​​of the first voltage V1-1, the second voltage V2-1, and the reference voltage V3-1 for a fifth duration. Figure 10 The duration T1 is shown); the first voltage V1-1 and the reference voltage V3-1 are increased to the third voltage V3-2, and the increased first voltage is maintained ( Figure 10 The voltage values ​​shown (V1-2), the second voltage V2-1, and the third voltage V3-2) persist for a sixth time period. Figure 10 The sum of durations T2 and T3 shown); wherein, the increased first voltage is greater than the first preset value; the decreased increased first voltage V1-1 and decreased third voltage V3-2 are reference voltage V3-1, and the decreased first voltage is maintained ( Figure 10The voltage values ​​shown (V1-4), the second voltage V2-1, and the reference voltage V3-1) remained for the seventh time period. Figure 10 The durations T4, T5, T6, and T7 shown are the sum of these durations, causing the selected memory cell's storage state to change from the second state to the first target state. In this embodiment, the second state of multiple memory cells may include a first partial state and a second partial state different from the first partial state. Compared to the memory cell being in the second partial state, the memory cell in this embodiment is in the first partial state. During the first write operation, the voltage applied to the selected first address line is set to be larger (i.e., the increased first voltage is greater than the first preset value), and at least in some stages, the voltage applied to the non-selected second address line can be maintained at the reference voltage (or the non-selected second address line can be set to a floating state or a ground state), reducing or avoiding memory power consumption waste. In this embodiment, the fifth duration can be referenced. Figure 9 The third duration shown is for reference; the sixth duration can be understood by referring to... Figure 9 The fourth duration shown is for reference; the seventh duration can be understood by referring to... Figure 9 The fourth duration shown will be understood in more detail here. Compared to... Figure 9 The embodiment shown, Figure 10 In the embodiment shown, the voltage applied to the selected first address line is set to be larger (i.e., the increased first voltage is greater than the first preset value).

[0079] refer to Figure 10 In some embodiments, the sixth duration is greater than or equal to the fifth duration; the seventh duration is greater than the sum of the sixth and fifth durations. In the embodiments of this application, the sixth duration is greater than or equal to the fifth duration, and a higher voltage is maintained for a higher duration, allowing the temperature of the phase change material in the memory cell to rise to the crystallization temperature TX (reference) more quickly. Figure 6 The seventh duration is greater than the sum of the sixth and fifth durations, which can guarantee sufficient time for the nuclei to grow in the phase change material of the storage unit, thus achieving a full conversion of the crystalline state.

[0080] Figure 11 The fifth example is a pulse diagram illustrating the set operation provided in the embodiments of this application. Figure 11 The implementation scheme shown can be understood as Figure 10 An alternative to the illustrated implementation scheme.

[0081] refer to Figure 11 In some embodiments, the memory operation method includes: in response to a storage state being a second state, maintaining the voltage values ​​of a first voltage V1-1, a second voltage V2-1, and a reference voltage V3-1 for an eighth duration. Figure 11The duration T1 is shown); the first voltage V1-1 is increased and the reference voltage V3-1 is maintained, and the first voltage after the first increase is maintained ( Figure 11 The voltage values ​​of the voltage V1-2, the second voltage V2-1, and the reference voltage V3-1 shown remain for a ninth time period. Figure 11 The duration T2 is shown; where the first voltage after the first increase ( Figure 11 The voltage V1-2 shown is less than or equal to the first preset value; the first voltage V1-1 is increased a second time and the reference voltage V3-1 is increased to the third voltage V3-2, maintaining the first voltage after the second increase ( Figure 11 The voltage values ​​shown (V1-3), the second voltage V2-1, and the third voltage V3-2) are maintained for ten hours. Figure 11 The duration T3 is shown; where the first voltage after the second increase ( Figure 11 The voltage V1-3 shown is greater than the first preset value; the first voltage V1-1 after the second increase and the third voltage V3-2 after the third increase are used as the reference voltage V3-1, and the first voltage after the decrease is maintained. Figure 11 The voltage values ​​shown (V1-4), the second voltage V2-1, and the reference voltage V3-1) are maintained for an eleventh time. Figure 11 The duration T4, T5, T6, and T7 shown are the sum of these durations, so that the storage state of the selected storage cell is changed from the second state to the first target state. In this embodiment, the eighth duration can be referred to... Figure 10 The fifth duration shown is for reference; the sum of the ninth and tenth durations can be used as a reference. Figure 10 The sixth duration shown is for reference; the eleventh duration can be understood by referring to the previous one. Figure 10 The seventh duration shown is for reference only and will not be elaborated upon here.

[0082] In some embodiments, the voltage value of voltage V1-2 ranges from 3V to 5V; the voltage value of voltage V1-3 ranges from 4V to 6V; the first preset value can be 4V, 4.5V, or 5.5V. For example, the voltage value of voltage V1-2 is 3.5V, 4V, or 4.5V, the voltage value of voltage V1-3 is 5V, 5.5V, or 6V, and the first preset value can be 4.5V.

[0083] In some embodiments, the range of the eighth, ninth, or tenth duration is less than or equal to 50 ns. Exemplarily, the range of the eighth, ninth, or tenth duration is less than or equal to 20 ns, 30 ns, or 40 ns. Exemplarily, the eighth, ninth, or tenth duration is 5 ns, 10 ns, or 15 ns.

[0084] In some embodiments, the tenth duration is longer than the ninth duration. This allows the phase change material of the memory cell to reach its crystallization temperature TX (reference temperature) more rapidly by maintaining a higher voltage for a longer duration. Figure 6 For example, the ninth duration is 5ns, 10ns, or 15ns, and the tenth duration is 20ns, 25ns, or 30ns.

[0085] In some embodiments, the eleventh duration is greater than the sum of the eighth, ninth, and tenth durations, which can ensure sufficient time for the nucleus growth of the phase change material in the storage cell and sufficient time for cooling, thereby achieving sufficient conversion of the crystalline state and its cooling.

[0086] Figure 12 This is a schematic diagram of a planar layout of a storage cell array including a first region and a second region, provided for embodiments of this application. It should be noted that... Figure 12 A portion of the memory cells Cx are shown. The position of memory cell Cx is used to indicate its relative positional relationship with word lines and bit lines. The size of memory cell Cx is not used to indicate its relative size relationship with word lines and bit lines. Figure 13 for Figure 12 A simplified diagram. Compared to Figure 12 , Figure 13 This illustrates one feature storage unit in each of the first and second regions.

[0087] Here and below, functionally speaking, compared to the second region, the first region can be understood as the region where errors are more concentrated. Therefore, it is necessary to set specific error checking and correction thresholds for both the first and second regions. In terms of relative location, compared to the memory cells in the second region, the memory cells in the first region are closer to the characteristic circuitry of the peripheral circuitry (e.g., word line drivers and bit line drivers). In some embodiments, the second region may surround the first region.

[0088] In some embodiments, the memory cell array includes multiple memory blocks; each memory block includes multiple first address lines, multiple second address lines, and multiple memory cells; the memory cells are located at the intersection of the first and second address lines; each memory block includes a first region and a second region; the second region is located outside the first region. In some embodiments, a memory block may be a repeating structure having the same number of memory cells. A memory block may have M word lines, N bit lines, and M x N memory cells coupled to the M word lines and N bit lines, where M and N are positive integers. Hereinafter, an example of 32 word lines, 64 bit lines, and 32 x 64 = 2048 memory cells coupled to the 32 word lines and 64 bit lines is used for illustration; this example is not intended to limit the embodiments of this application.

[0089] In some embodiments, because the conductive path length of current through the first address line, the memory cell, and the second address line differs in different regions of the memory block, i.e., the voltage drop caused by the conductive path differs in different regions, the electrical performance requirements of memory cells in different regions differ. Therefore, it is necessary to set matching operations for different regions based on these different electrical performance requirements. For example, when performing a first write operation on memory cells in different regions, the voltage applied to non-selected bit lines can be set differently. Another example is setting matching error checking and correction thresholds (a first threshold and a second threshold) to provide different means of detecting slow read interference for memory cells in different regions, effectively preventing the problem of high original bit error rate or error rate due to regional differences.

[0090] refer to Figure 12 and Figure 13 In some embodiments, the peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are coupled to the memory cell via a first address line and a second address line, respectively; the memory cell array includes a first region and a second region; the second region is located outside the first region; the electrical distance between the memory cells in the first region is less than the electrical distance between the memory cells in the second region; the electrical distance is the sum of the first length of the first address line between the memory cell and the first driving circuit and the second length of the second address line between the memory cell and the second driving circuit; the memory operation method further includes: before performing a first write operation, determining whether the selected memory cell belongs to the first region; during the execution of the first write operation, if the selected memory cell belongs to the first region, maintaining the reference voltage V3-1. In the embodiments of this application, when performing a first write operation on a memory cell in the first region, the voltage applied to the non-selected bit line can be maintained at the reference voltage, which can minimize the power consumption caused by unnecessary voltage increases during the first write operation.

[0091] In this embodiment, the smaller the electrical distance between the storage cells, the smaller the resistance and the smaller the voltage drop. Compared to driving the storage cells in the second region, driving the storage cells in the first region based on the first and second driving circuits results in a smaller electrical distance between the storage cells, leading to lower resistance and a smaller voltage drop.

[0092] refer to Figure 13For example, the memory cell C14-35 of the first region P-101 is located at the intersection between word line WL14 and bit line BL35 and is coupled to word line WL14 and bit line BL35. The electrical distance ED1 of the memory cell C14-35 can be the sum of size D1 and size D2. The memory cell C9-45 of the second region P-102 is located at the intersection between word line WL9 and bit line BL45 and is coupled to word line WL9 and bit line BL45. The electrical distance ED2 of the memory cell C9-45 can be the sum of size D3 and size D4. Wherein, the electrical distance ED1 is less than the electrical distance ED2.

[0093] Here and below, the first driving circuit can be understood as a word line driver (see reference). Figure 3 The word line driver 308 and bit line driver (see reference) are shown. Figure 3 One of the position line drivers 306 shown, the second driving circuit can be understood as a word line driver (see reference). Figure 3 The word line driver 308 and bit line driver (see reference) are shown. Figure 3 The other of the position line drivers (306) shown. Hereinafter, the first driving circuit is described as a word line driver and the second driving circuit as a bit line driver, but this example is not intended to limit the embodiments of this application.

[0094] refer to Figure 9 , Figure 10 or Figure 11 In some embodiments, the memory operation method further includes: in response to a second storage state, increasing the first voltage V1-1 while decreasing the second voltage V2-1. In this embodiment, a higher voltage difference can be provided across the selected memory cell, which facilitates rapid heating of the phase change material of the selected memory cell, or promotes the nucleus growth of the phase change material of the selected memory cell. For example, compared to the first voltage V1-1 and the second voltage V2-1, the voltages V1-2 and V2-2 provided across the selected memory cell have a greater voltage difference than the voltage difference between the first voltage V1-1 and the second voltage V2-1, thus providing a higher voltage difference across the selected memory cell.

[0095] In some embodiments, the voltage value of the second voltage V2-1 ranges from -2V to -4V, and the voltage value of the voltage V2-2 ranges from -3V to -5V. For example, the voltage value of the second voltage V2-1 is -2.5V or -3V. For example, the voltage value of the voltage V2-2 is -4V or -4.5V.

[0096] In some embodiments, the memory operation method further includes: during a second write operation, applying a fourth voltage to a selected first address line and applying a fifth voltage to a selected second address line, so that the storage state of the selected memory cell is a second target state; wherein the resistance value of the memory cell in the second target state is greater than the resistance value of the memory cell in the first target state. In this embodiment, the fourth voltage can be understood as being able to raise the temperature of the phase change material of the memory cell to the melting temperature TM (refer to...). Figure 6 The voltage above; the fifth voltage can be understood as the second voltage V2-1 or voltage V2-2. In the embodiments of this application, the second write operation can be understood as a reset operation. The second write operation may include multiple stages, and the first stage of the second write operation can be understood as a rapid heating (or heating) stage, which can make the temperature of the phase change material of the memory cell rise to the melting temperature TM (refer to) relatively quickly. Figure 6 Above. The second stage of the second write operation can be understood as a rapid cooling stage, which prevents the nucleus growth of the phase change material in the memory cell from occurring or fully progressing, resulting in the phase change material of the memory cell being in an amorphous state (high configuration, represented by logic state "0"). In this case, the phase change material of the memory cell is either in an amorphous state (high configuration, represented by logic state "0") or in a crystalline state (low configuration, represented by logic state "1").

[0097] According to a second aspect of the present application, a memory is provided, comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of memory cells; the peripheral circuitry is configured to perform any of the operating methods provided in the first aspect.

[0098] In some embodiments, the peripheral circuitry is configured to: apply a first voltage to a selected first address line, apply a second voltage to a selected second address line, and apply a reference voltage to a non-selected second address line during the first write operation; wherein the reference voltage is less than the first voltage and greater than the second voltage; sense the storage state of a selected memory cell based on the first voltage and the second voltage; and maintain the reference voltage or increase the reference voltage to a third voltage according to the storage state of the memory cell.

[0099] In some embodiments, the peripheral circuitry is configured to: maintain the voltage values ​​of the first voltage, the second voltage, and the reference voltage for a first duration in response to the storage state being a first state that matches the first target state, so that the storage state of the selected storage cell is maintained as the first target state.

[0100] In some embodiments, the peripheral circuitry is configured to: in response to a second state in which the storage state does not match a first target state, maintain the voltage values ​​of a first voltage, a second voltage, and a reference voltage for a second duration; increase the first voltage and maintain the reference voltage, and maintain the increased first voltage, second voltage, and reference voltage for a third duration; wherein the increased first voltage is less than or equal to a first preset value; decrease the increased first voltage and maintain the reference voltage, and maintain the decreased first voltage, second voltage, and reference voltage values ​​for a fourth duration, so that the storage state of the selected storage cell is changed from the second state to the first target state; wherein the decreased first voltage is greater than the reference voltage.

[0101] In some embodiments, the fourth duration is greater than the sum of the third and second durations.

[0102] In some embodiments, the peripheral circuitry is configured to: in response to a second state where the storage state does not match the first target state, maintain the voltage values ​​of the first voltage, the second voltage, and the reference voltage for a fifth duration; increase the first voltage and the reference voltage to a third voltage, and maintain the increased voltage values ​​of the first voltage, the second voltage, and the third voltage for a sixth duration; wherein the increased first voltage is greater than a first preset value; decrease the increased first voltage and the decreased third voltage to a reference voltage, and maintain the decreased voltage values ​​of the first voltage, the second voltage, and the reference voltage for a seventh duration, so that the storage state of the selected storage cell is changed from the second state to the first target state; wherein the decreased first voltage is greater than the reference voltage.

[0103] In some embodiments, the sixth duration is greater than or equal to the fifth duration; the seventh duration is greater than the sum of the sixth and fifth durations.

[0104] In some embodiments, the peripheral circuitry includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are coupled to memory cells via a first address line and a second address line, respectively; the memory cell array includes a first region and a second region; the second region is located outside the first region; the electrical distance between memory cells in the first region is less than the electrical distance between memory cells in the second region; wherein the electrical distance is the sum of a first length of the first address line between the memory cell and the first driving circuit and a second length of the second address line between the memory cell and the second driving circuit; the peripheral circuitry is further configured to: determine whether a selected memory cell belongs to the first region before performing a first write operation; and maintain a reference voltage if the selected memory cell belongs to the first region during the first write operation.

[0105] In some embodiments, the peripheral circuitry is further configured to increase the first voltage while decreasing the second voltage in response to the storage state being the second state.

[0106] In some embodiments, the peripheral circuitry is further configured to: apply a fourth voltage to a selected first address line and a fifth voltage to a selected second address line during the second write operation, so that the storage state of the selected memory cell is a second target state; wherein the resistance value of the memory cell in the second target state is greater than the resistance value in the first target state. The memory used in the memory operation methods provided in the embodiments of the second aspect of this application is the same as or similar to the memory in the embodiments of the first aspect described above. For technical features not disclosed in detail in the second aspect of this application, please refer to the memory in the embodiments of the first aspect described above for understanding; further details will not be provided here.

[0107] According to a third aspect of the present application, a memory system is provided, the memory system comprising: a memory, including any of the memory provided in the second aspect, or a memory applied according to any of the operating methods provided in the first aspect; and a memory controller, coupled to the memory and configured to control the memory.

[0108] In this embodiment, the memory and memory controller of the memory system can be referred to the above. Figure 1 The relevant descriptions can be used for understanding, and will not be repeated here. The memory array and peripheral circuitry can be referred to the above. Figure 2 and Figure 3 To understand the relevant descriptions, refer to the storage units of the storage unit array. Figure 4 and Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0109] Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application.

[0110] like Figure 14 As shown, according to a fourth aspect of the present application, a readable storage medium 400 is provided, which stores a computer program 410. When the computer program 410 is executed, it can implement any of the memory operation methods provided in the second aspect.

[0111] For example, the memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of memory cells; the memory operation method includes: during a first write operation, applying a first voltage to selected first address lines, applying a second voltage to selected second address lines, and applying a reference voltage to unselected second address lines; wherein the reference voltage is less than the first voltage and greater than the second voltage; sensing the storage state of selected memory cells based on the first voltage and the second voltage; and maintaining the reference voltage or increasing the reference voltage to a third voltage according to the storage state of the memory cells to write the memory cells to a first target state; wherein the third voltage is less than the first voltage.

[0112] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0113] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A method for operating a memory, characterized in that, The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array; The memory cell array includes multiple first address lines, multiple second address lines, and multiple memory cells; The operation method includes: During the first write operation, a first voltage is applied to the selected first address line, a second voltage is applied to the selected second address line, and a reference voltage is applied to the unselected second address line; wherein the reference voltage is less than the first voltage and greater than the second voltage; Based on the first voltage and the second voltage, the storage state of the selected storage cell is sensed; Based on the storage state of the storage cell, the reference voltage is maintained or the reference voltage is increased to a third voltage so that the storage cell is written to a first target state; wherein the third voltage is less than the first voltage.

2. The operating method according to claim 1, characterized in that, The operation method includes: In response to the storage state being a first state that matches the first target state, the voltage values ​​of the first voltage, the second voltage, and the reference voltage are maintained for a first duration so that the storage state of the selected storage cell is maintained as the first target state.

3. The operating method according to claim 1, characterized in that, The operation method includes: In response to the storage state being a second state that does not match the first target state, the voltage values ​​of the first voltage, the second voltage, and the reference voltage are maintained for a second duration; The first voltage is increased while the reference voltage is maintained, and the increased first voltage, the second voltage, and the reference voltage are maintained for a third duration; wherein the increased first voltage is less than or equal to a first preset value; The increased first voltage is reduced while the reference voltage is maintained, such that the reduced first voltage, the second voltage, and the reference voltage values ​​remain for a fourth duration, so that the storage state of the selected storage cell is changed from the second state to the first target state; wherein the reduced first voltage is greater than the reference voltage.

4. The operating method according to claim 3, characterized in that, The fourth duration is greater than the sum of the third duration and the second duration.

5. The operating method according to claim 1, characterized in that, The operation method includes: In response to the storage state being a second state that does not match the first target state, the voltage values ​​of the first voltage, the second voltage, and the reference voltage are maintained for a fifth duration; The first voltage and the reference voltage are increased to the third voltage, and the increased voltage values ​​of the first voltage, the second voltage, and the third voltage are maintained for a sixth duration; wherein the increased first voltage is greater than a first preset value; The increased first voltage and the decreased third voltage are used as the reference voltage. The voltage values ​​of the decreased first voltage, the second voltage, and the reference voltage are maintained for a seventh duration to change the storage state of the selected storage cell from the second state to the first target state; wherein the decreased first voltage is greater than the reference voltage.

6. The operating method according to claim 5, characterized in that, The sixth duration is greater than or equal to the fifth duration; the seventh duration is greater than the sum of the sixth duration and the fifth duration.

7. The operating method according to claim 1, characterized in that, The peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are respectively coupled to the memory cell via the first address line and the second address line; the memory cell array includes a first region and a second region; the second region is located outside the first region; the electrical distance between the memory cells in the first region is less than the electrical distance between the memory cells in the second region; wherein, the electrical distance is the sum of the first length of the first address line between the memory cell and the first driving circuit and the second length of the second address line between the memory cell and the second driving circuit; the operation method further includes: Before performing the first write operation, determine whether the selected storage cell belongs to the first region; During the execution of the first write operation, if the selected memory cell belongs to the first region, the reference voltage is maintained.

8. The operating method according to claim 1, characterized in that, The operation method further includes: In response to the storage state being the second state, the first voltage is increased while the second voltage is decreased.

9. The operating method according to claim 1, characterized in that, The operation method further includes: During the second write operation, a fourth voltage is applied to the selected first address line and a fifth voltage is applied to the selected second address line to make the storage state of the selected memory cell a second target state; wherein the resistance value of the memory cell in the second target state is greater than the resistance value in the first target state.

10. A memory, characterized in that... include: A memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple first address lines, multiple second address lines, and multiple memory cells; the peripheral circuitry is configured to perform the operation method as described in any one of claims 1 to 9.

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