Bus voltage control method and system based on Vienna topology, and converter equipment

Abstract

The invention provides a Vienna topology-based bus voltage control method and system, and a converter device, and relates to the technical field of circuit control technologies. The method comprises the following steps: acquiring an actual total bus voltage value and an actual input current value output by the Vienna topology; performing closed-loop control on the bus voltage of the Vienna topology according to the actual total bus voltage value and the actual input current value; when the bus voltage output by the Vienna topology meets a preset grading overvoltage condition, triggering a corresponding voltage regulation action so as to reduce the bus voltage of the Vienna topology to be within a preset standard range; the preset grading overvoltage condition comprises a plurality of voltage thresholds and detection time corresponding to each voltage threshold, and the regulation response degree of the voltage regulation action is increased along with the rise of the bus voltage. According to the invention, the bus voltage of the Vienna topology is stably controlled, and the operation stability and safety of equipment are improved.

Description

Technical Field

[0001] This application relates to the field of circuit control technology, and in particular to a bus voltage control method, system and converter based on Vienna topology. Background Technology

[0002] A power converter is a device that performs functions such as rectification and inversion. For example, an uninterruptible power supply (UPS) is a key type of power converter. Its core function is to draw power from the grid (such as mains power), process it through rectification, power factor correction (PFC), and inversion, and then output stable AC / DC power. When the mains power is interrupted, backup batteries can continue to provide power to downstream loads, ensuring continuous operation. To improve the power supply efficiency of the equipment and the utilization rate of the power system, a power factor correction (PFC) circuit is usually designed to improve its power factor.

[0003] The Vienna topology is a circuit topology commonly used in power factor correction (PFC). It employs a boost circuit structure, combining an energy storage inductor, a controllable semiconductor switch, a diode, and a capacitor. The output bus voltage is boosted through the high-frequency switching action of the switch. Its operating state varies with the current direction and the switching action of the switch. When the current is input in the positive direction, the AC input voltage is boosted to the positive bus through the switching action, while there is no energy input to the negative bus. Conversely, when the current is input in the negative direction, the AC input voltage is boosted to the negative bus through the switching action, while there is no energy input to the positive bus.

[0004] However, due to the unidirectional energy flow characteristic of the VIENNA topology, the circuit alternates between positive and negative bus voltage boosting based on the direction of the AC input voltage. That is, at any given time, either the positive bus or the negative bus is controlled. When the equipment is under light load or no load, the lack of load consuming bus energy or a sudden decrease in the energy required by the load can cause an abnormal rise in the output bus voltage. For example, when the AC input voltage is positive, the positive bus is controlled, but the negative bus is uncontrolled. If the energy consumed by the downstream load decreases, the negative bus voltage will rise because the negative bus is uncontrolled. The negative bus voltage can only be controlled and reduced when the AC input voltage is negative. The negative bus voltage can last for up to half an AC cycle. Although the positive bus voltage is controlled, it will also rise due to the lag in control if no intervention is provided. Similarly, when the AC input voltage is negative, the negative bus voltage is controlled, but the positive bus voltage will rise abnormally due to prolonged lack of control. If the bus voltage remains too high for an extended period, it will increase the stress on the circuit power devices, reducing the stability and safety of the equipment operation. Summary of the Invention

[0005] This application provides a bus voltage control method, system, and converter based on the Vienna topology to solve the problem in the prior art where, due to the unidirectional energy flow characteristics of the Vienna topology, the output bus voltage rises abnormally when the equipment is under light load or no load, resulting in reduced equipment operation stability and safety.

[0006] In a first aspect, embodiments of this application provide a bus voltage control method based on Vienna topology, including: Obtain the actual total bus voltage and actual input current value output by the Vienna topology; Based on the actual total bus voltage value and the actual input current value, the bus voltage of the Vienna topology is controlled in a closed loop. When the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions, the corresponding voltage regulation action is triggered to reduce the bus voltage of the Vienna topology to a preset standard range. The preset graded overvoltage conditions include multiple voltage thresholds and a detection time corresponding to each voltage threshold. The degree of regulation response of the voltage regulation action increases as the bus voltage increases.

[0007] In one possible implementation, triggering a corresponding voltage regulation action when the bus voltage output by the Vienna topology meets a preset graded overvoltage condition includes: When the bus voltage is greater than or equal to the first voltage threshold and lasts for a first detection time, a first adjustment action is triggered; the first adjustment action is to perform an integrator deintegration operation on the proportional-integral (PI) regulator in the voltage loop. When the bus voltage is greater than or equal to the second voltage threshold and lasts for a second detection time, a second adjustment action is triggered; the second adjustment action is to block the drive signal of the switching transistor in the Vienna topology; the second voltage threshold is greater than the first voltage threshold; When the bus voltage is greater than or equal to the third voltage threshold, a third adjustment action is triggered; the third adjustment action is to control the converter equipment to stop working in order to cut off the inverter output of the converter equipment; the third voltage threshold is greater than the second voltage threshold.

[0008] In one possible implementation, triggering the third regulation action when the bus voltage is greater than or equal to the third voltage threshold includes: The third adjustment action is triggered when the bus voltage is greater than or equal to the third voltage threshold and lasts for a third detection time, or when the bus voltage is greater than or equal to the fourth voltage threshold and lasts for a fourth detection time; the fourth voltage threshold is greater than the third voltage threshold, and the fourth detection time is less than the third detection time.

[0009] In one possible implementation, the step of triggering a corresponding voltage regulation action when the bus voltage output by the Vienna topology meets a preset graded overvoltage condition further includes: Obtain the bus voltage signal output by the hardware voltage sampling circuit; When the bus voltage signal is a high-level signal and continues for the fifth detection time, the third adjustment action is triggered; The hardware voltage sampling circuit acquires the bus voltage in real time and compares the bus voltage with a fifth voltage threshold. When the bus voltage is greater than or equal to the fifth voltage threshold, the output bus voltage signal is a high-level signal; otherwise, the output bus voltage signal is a low-level signal. The fifth voltage threshold is greater than the fourth voltage threshold.

[0010] In one possible implementation, the closed-loop control of the bus voltage of the Vienna topology based on the actual total bus voltage value and the actual input current value includes: Based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint, the total bus voltage is subjected to closed-loop voltage control to obtain a current reference. Based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology, the input current is subjected to closed-loop control to obtain the first voltage compensation control quantity so that the input current tracks the sine wave. The difference between the positive bus voltage and the negative bus voltage of the Vienna topology is subjected to closed-loop control to obtain a second voltage compensation control quantity, so that the difference is within a preset error range; The drive signal for the switching transistor in the Vienna topology is generated based on the first voltage compensation control value and the second voltage compensation control value.

[0011] In one possible implementation, the step of performing closed-loop voltage control on the total bus voltage based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint to obtain a current reference includes: Calculate the voltage error between the actual total bus voltage value and the given total bus voltage value; The voltage error is input to a first PI regulator so that the first PI regulator adjusts the voltage error and outputs a current reference.

[0012] In one possible implementation, the step of performing closed-loop control on the input current based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology to obtain a first voltage compensation control quantity includes: Multiply the current reference by the sine function of the phase angle of the AC input voltage to obtain the sinusoidal current setpoint; Calculate the current error between the given sinusoidal current value and the actual input current value; The current error is input to the second PI regulator so that the second PI regulator adjusts the current error and outputs a first voltage compensation control quantity.

[0013] In one possible implementation, the closed-loop control of the difference between the positive and negative bus voltages of the Vienna topology to obtain a second voltage compensation control quantity includes: Obtain the actual difference between the positive bus voltage and the negative bus voltage; The deviation between the actual difference and the target difference is calculated and input to the third PI regulator so that the third PI regulator adjusts the deviation and outputs a second voltage compensation control quantity; wherein the target difference is 0.

[0014] Secondly, embodiments of this application provide a bus voltage control system based on Vienna topology, including: Vienna topology, acquisition module and control module; The output terminal of the acquisition module is connected to the input terminal of the control module, and is used to acquire the actual total bus voltage value and actual input current value output by the Vienna topology, and send them to the control module. The output of the control module is connected to the switching transistor in the Vienna topology, and is used to execute the bus voltage control method based on the Vienna topology described in the first aspect above.

[0015] Thirdly, embodiments of this application provide a converter device, including the bus voltage control system based on Vienna topology described in the second aspect above.

[0016] In this embodiment, the bus voltage of the Vienna topology is first controlled in a closed loop based on the actual total bus voltage and actual input current of the obtained Vienna topology output, so as to provide a suitable voltage for the downstream load. When the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions, the corresponding voltage regulation action is triggered to reduce the bus voltage of the Vienna topology to the preset standard range. Since the preset graded overvoltage conditions include multiple voltage thresholds and the detection time corresponding to each voltage threshold, and the regulation response of the voltage regulation action increases with the increase of the bus voltage, that is, the higher the bus voltage, the higher the corresponding overvoltage level, the higher the regulation intensity of the voltage regulation action, and the higher the corresponding voltage regulation response (i.e., the higher the voltage drop), graded overvoltage regulation is realized. The degree of increase of the bus voltage can be judged according to multiple voltage thresholds, the duration of continuous overvoltage can be controlled by the detection time, and the corresponding voltage regulation action can be triggered according to the degree of voltage increase and the continuous detection time, dynamically adjusting the intervention intensity. While ensuring the safe operation of power conversion equipment (such as UPS equipment), the bus voltage is maintained within the standard range, maximizing the continuity and stability of system operation, and solving the problem of unstable voltage under light load / no-load caused by the unidirectional flow of energy in the Vienna topology.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a single-phase Vienna topology provided in an embodiment of this application; Figure 2This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in an embodiment of this application; Figure 3a This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in another embodiment of this application; Figure 3b This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in another embodiment of this application; Figure 4a This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in another embodiment of this application; Figure 4b This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in another embodiment of this application; Figure 5 This is a closed-loop control block diagram of the Vienna topology provided in one embodiment of this application; Figure 6 This is a schematic diagram of a bus voltage control system based on Vienna topology provided in another embodiment of this application; Figure 7 This is a schematic diagram of the structure of a converter device provided in one embodiment of this application. Detailed Implementation

[0020] The present application will be described more clearly below with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the function of the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0021] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] In the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0025] Furthermore, the term "multiple" mentioned in the embodiments of this application should be interpreted as two or more.

[0026] In related technologies, the Vienna topology is a commonly used circuit topology for power factor correction (PFC). It employs a boost converter structure, combining an energy storage inductor, a controllable semiconductor switch (such as an IGBT or MOSFET), diodes, and capacitors. The high-frequency switching action of the switch achieves boost control of the output bus voltage. By controlling the switching frequency and conduction time of the switch, the bus voltage is stabilized at a preset value. Its operating state changes with the current direction (or voltage direction) and the on / off action of the switch; for example, as... Figure 1 The single-phase Vienna topology shown includes input inductor L1, diodes D1 and D2, switching transistors Q1 and Q2, and bus capacitors C1 and C2. (Refer to...) Figure 1 As indicated by the red arrow 'a', when the current is input in the positive direction (IN_L port input) and the switching transistor Q1 is turned on, the input inductor L1 stores energy in the forward direction; (Refer to...) Figure 1 In step b, when the current is input in the positive direction (IN_L port input) and the switch Q1 is off, the inductor L1 releases energy, enabling the AC input voltage to be boosted to the positive bus (BUS+), while there is no energy input to the negative bus (BUS-). (Reference) Figure 1 In the context of 'c', when the current is input in the negative direction (IN_N port input) and the switch Q2 is turned on, the inductor L1 stores energy in the reverse direction; (Reference) Figure 1 When the current is input in the negative direction (IN_N port input) and the switch Q2 is turned off, the inductor L1 releases energy in the reverse direction, and the energy is transferred to the negative bus (BUS-), so that the AC input voltage is boosted to the negative bus and there is no energy input to the positive bus (BUS+).

[0027] However, due to the unidirectional energy flow characteristic of the VIENNA topology, the AC input voltage alternates between positive and negative bus boosts. That is, the alternation of positive and negative bus voltages is stably controlled and cannot be controlled simultaneously. Under normal circumstances, when supplying power to a load, the load draws energy from the bus. When the load decreases, there is no load consuming bus energy, or the load suddenly decreases, causing the bus voltage to rise. Specifically, if the positive bus is currently operating (i.e., the AC input current is in the positive half-cycle), and the load suddenly decreases to a light load or no-load state, the positive bus voltage rises. Because it is currently in the AC positive half-cycle, the loop is controlling the positive bus voltage, while the negative bus is not controlled; therefore, the negative bus voltage will also be abnormally pulled up. Similarly, if the negative bus is operating (i.e., the AC input current is in the negative half-cycle), when the load decreases to a light load or no-load state, the positive bus voltage will also be abnormally pulled up. In practical scenarios, for AC mains power with an input frequency of 50Hz, one AC input cycle is 20ms. Therefore, the positive half-cycle working time and the negative half-cycle working time are both 10ms. This means that when the positive bus is working, the negative bus is uncontrolled for as long as 10ms. However, for the VIENNA topology, the control cycle is at the microsecond level (e.g., 100us), which means that the negative bus is uncontrolled for 100 control cycles. Similarly, when the negative bus is working, the positive bus is uncontrolled for 100 control cycles. Therefore, when the UPS is under light load or no load, regardless of whether the positive or negative bus is currently working, the other bus will experience an abnormal voltage increase due to prolonged lack of control. If the bus voltage remains excessively high for an extended period, it will increase the stress on the circuit power devices, seriously affecting the operational stability and safety of power conversion equipment (such as UPS systems).

[0028] The traditional approach involves setting a voltage threshold. When the bus voltage exceeds this threshold, the converter equipment is shut down to prevent further voltage increases. However, this method struggles to determine the optimal voltage threshold. If the threshold is set too low, even a brief overvoltage event can cause the equipment to shut down, leading to frequent shutdowns and unstable operation, significantly impacting user experience. Conversely, if the threshold is set too high, it may miss detections, failing to completely eliminate the risks associated with bus overvoltage.

[0029] Based on the above analysis of the existing technology, this application proposes the following technical concept: For the bus voltage of the Vienna topology, in addition to employing dual closed-loop control of voltage and current loops, a graded control method is also adopted. Specifically, graded overvoltage conditions are set, and these basic overvoltage conditions include multiple voltage thresholds and a corresponding detection time for each voltage threshold. The rise in bus voltage is divided into multiple levels through these multiple voltage thresholds. The detection time corresponding to each voltage threshold is the duration exceeding that voltage threshold. When the bus voltage output by the Vienna topology meets a certain overvoltage condition, a corresponding voltage regulation action is triggered. Furthermore, the degree of regulation response of the voltage regulation action increases with the rise in bus voltage. The higher the voltage, the stronger the corresponding voltage regulation action and the higher the corresponding voltage regulation response (i.e., the greater the voltage drop). This achieves graded overvoltage regulation, which can determine the degree of bus voltage rise based on multiple voltage thresholds, control the duration of continuous overvoltage through detection time, and trigger corresponding voltage regulation actions based on the degree of voltage rise and the duration of detection time. The intervention intensity is dynamically adjusted to ensure the safe operation of power conversion equipment (such as UPS systems) while maintaining the bus voltage within the standard range, maximizing the continuity and stability of system operation. This solves the problem of voltage instability under light load / no-load conditions caused by unidirectional energy flow in Vienna topologies, and improves the user experience.

[0030] The bus voltage control method based on Vienna topology provided in this application is described below with reference to the accompanying drawings. The implementer of the method may be, but is not limited to, a processor or controller, such as a digital signal processor (DSP).

[0031] Figure 2 This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in an embodiment of this application.

[0032] like Figure 2 As shown, the method in this application embodiment may include the following steps: Step S201: Obtain the actual total bus voltage and actual input current value output by the Vienna topology.

[0033] In this step, the actual total bus voltage (denoted as U) bus_sum U is the sum of the positive bus voltage and the negative bus voltage. bus_sum =U bus+ +| U bus- The actual input current is the input inductance in the Vienna topology (reference). Figure 1 The AC input current (denoted as i) of L1 in the input (in the input) L ).

[0034] In this step, the actual total bus voltage value and the actual input current value can be obtained by real-time acquisition through corresponding sensors (such as voltage sensors and current sensors), or can be obtained by voltage sampling circuits or current sampling circuits.

[0035] Step S202: Perform closed-loop control on the bus voltage of the Vienna topology according to the actual total bus voltage value and the actual input current value.

[0036] In this step, due to the single-phase flow characteristic of the Vienna topology, the positive and negative buses work alternately rather than simultaneously. Therefore, it is impossible to control the positive and negative buses separately. Thus, it is necessary to perform closed-loop control on the total bus voltage of the Vienna topology according to the actual total bus voltage value and the given value of the total bus voltage to stabilize the total bus voltage (i.e., the closed-loop control of the bus voltage loop); and use the output of the bus voltage loop as the given value of the current loop, and combine the actual input current value to perform closed-loop control on the AC input current of the Vienna topology to make the input current track the given sinusoidal waveform and achieve power factor correction; through the double closed-loop control of the voltage loop and the current loop, the stable output of the bus voltage is achieved to supply power to the subsequent load.

[0037] Step S203: When the bus voltage output by the Vienna topology meets the preset hierarchical overvoltage condition, trigger the corresponding voltage regulation action to reduce the bus voltage of the Vienna topology to within the preset standard range; the preset hierarchical overvoltage condition includes multiple voltage thresholds and the detection time corresponding to each voltage threshold, and the regulation response degree of the voltage regulation action increases with the increase of the bus voltage.

[0038] In this step, the values of the multiple voltage thresholds can be set according to the actual operation conditions of the equipment. The values of multiple different voltage thresholds increase in sequence (for example, the preset hierarchical overvoltage condition can include four voltage thresholds, namely V1, V2, V3, V4, and V5, and V1 < V2 < V3 < V4 < V5), dividing the increase degree of the bus voltage into multiple levels (to facilitate the distinction of slight overvoltage, medium overvoltage, severe overvoltage, and extreme overvoltage, etc.). The detection time corresponding to each voltage threshold is the duration of exceeding this voltage threshold. Each voltage threshold corresponds to a voltage regulation action, and the regulation response degree of the voltage regulation action increases with the increase of the bus voltage, that is: the higher the bus voltage, the higher the regulation intensity of the corresponding voltage regulation action, and the higher the corresponding voltage regulation response degree (that is, the faster the voltage drops). When the bus voltage reaches one of the voltage thresholds and lasts for the corresponding detection time, trigger the corresponding voltage regulation action to reduce the bus voltage.

[0039] In the embodiments of the present application, by obtaining the actual total bus voltage and actual input current output by the Vienna topology, the bus voltage of the Vienna topology is closed-loop controlled to provide a suitable voltage for the subsequent load. When the bus voltage output by the Vienna topology meets the preset hierarchical overvoltage condition, the corresponding voltage regulation action is triggered to reduce the bus voltage of the Vienna topology to within the preset standard range; since the preset hierarchical overvoltage condition includes multiple voltage thresholds and the detection time corresponding to each voltage threshold, and the regulation response degree of the voltage regulation action increases with the increase of the bus voltage, that is, the higher the bus voltage, the higher the regulation intensity of the corresponding voltage regulation action, and the higher the corresponding voltage regulation response degree (that is, the higher the voltage drop degree), thus realizing hierarchical overvoltage regulation, the increase degree of the bus voltage can be judged according to multiple voltage thresholds, the continuous overvoltage duration can be controlled by the detection time, and the corresponding voltage regulation actions can be triggered hierarchically according to the voltage increase degree and the continuous detection time, dynamically adjusting the intervention intensity, while ensuring the safe operation of the converter device (such as a UPS device), ensuring that the bus voltage is maintained within the standard range, and maximizing the continuity and stability of the system operation, solving the problem of unstable light load / no load voltage caused by the unidirectional energy flow of the Vienna topology.

[0040] Figure 3a and Figure 3b is a schematic flowchart of a bus voltage control method based on the Vienna topology provided by another embodiment of the present application; the embodiments of the present application focus on a detailed description of the hierarchical control scheme of the bus voltage of the Vienna topology.

[0041] In a possible implementation manner, the preset hierarchical overvoltage condition may but is not limited to include 5 voltage thresholds, namely the first voltage threshold V1, the second voltage threshold V2, the third voltage threshold V3, the fourth voltage threshold V4, and the fifth voltage threshold V5, and V1 < V2 < V3 < V4 < V5; the corresponding detection times are the first detection time T1, the second detection time T2, the third detection time T3, the fourth detection time T4, and the fifth detection time T5 respectively.

[0042] It should be noted that the bus voltage monitored by the hierarchical control scheme of the bus voltage in this embodiment may be the total bus voltage or the half bus voltage (such as the positive bus voltage). Therefore, the setting of multiple voltage thresholds can be adjusted according to the actual situation. For example, when the device is working normally, the normal working range of the half bus voltage is about ३६०~३८०V, then the first voltage threshold can be taken within the range of ३८०~४००V (such as ३९०V or ४००V); the second voltage threshold is larger than the first voltage threshold and can be taken within the range of ४१०~४२०; the third and fourth voltage thresholds increase in turn, and the fifth voltage threshold can be set according to the limit withstand voltage value of the power device in the circuit. For example, it can be taken within the range of ४७०~४८०V.

[0043] It should be noted that the values ​​of the above five detection times are determined based on the actual situation.

[0044] like Figure 3a As shown, the bus voltage control method based on Vienna topology provided in this embodiment includes the following steps: Step S201: Obtain the actual total bus voltage and actual input current value output by the Vienna topology.

[0045] Step S202: Perform closed-loop control on the bus voltage of the Vienna topology based on the actual total bus voltage value and the actual input current value.

[0046] Step S2031: When the bus voltage (U) is greater than or equal to the first voltage threshold (V1) and continues for the first detection time (T1), (bus voltage U) V1 and duration T T1), triggering the first adjustment action; the first adjustment action is to perform an integrator deintegration operation on the PI regulator in the voltage loop.

[0047] In this step, the processor acquires the bus voltage at fixed time intervals (interrupt cycles). When the bus voltage reaches the first voltage threshold V1 and remains there for the first detection time T1, it indicates a slight overvoltage. This triggers the deintegration operation of the voltage loop PI regulator (e.g., clearing the integral term to zero or proportionally reducing it), limiting the control quantity output by the voltage loop. Since the control quantity output by the voltage loop serves as a reference for the current loop setpoint, this effectively reduces the setpoint of the current loop input, thereby reducing the control quantity output by the current loop and consequently lowering the bus voltage. This deintegration operation does not interrupt the drive signals of the switching transistors in the Vienna topology; it only slows down the rise rate of the bus voltage by adjusting the integral, having no impact on the equipment operation. It is a preventative, stable control measure and the earliest intervention level. When the bus voltage begins to rise but has not reached the second voltage threshold (V2), deintegration prevents the voltage loop PI regulator from continuously increasing its output control quantity due to integral saturation, thus suppressing the upward trend of the bus voltage at its source and ensuring stable operation of the PFC loop when the voltage is close to the setpoint.

[0048] It should be noted that the first detection time T1 can be, but is not limited to, one interrupt cycle. Since the processor automatically triggers the voltage monitoring action at fixed time intervals (i.e., interrupt cycles), each time an interrupt occurs, the processor will collect data such as bus voltage and input current, and then execute a series of subsequent control algorithms (such as closed-loop control) and update the drive signal of the switching transistor. Therefore, for a slight overvoltage scenario where the bus voltage is greater than the first voltage threshold, the first detection time T1 can be set to one interrupt cycle (for example, an interrupt cycle of 100us) to improve the response speed of the deintegration operation and quickly and timely suppress the upward trend of the bus voltage.

[0049] Step S2032, when the bus voltage is greater than or equal to the second voltage threshold and continues for a second detection time (bus voltage U) V2 and duration T T2), triggering a second adjustment action; the second adjustment action is to block the drive signal of the switching transistor in the Vienna topology; the second voltage threshold is greater than the first voltage threshold.

[0050] In this step, when the bus voltage reaches the second voltage threshold V2 and remains there for the second detection time, it indicates that the first-level deintegration operation is no longer able to suppress the rising trend of the bus voltage, and the intervention intensity needs to be further increased. Therefore, the drive blocking operation is triggered, that is, the drive signal of the switching transistor in the Vienna topology is blocked (e.g., Figure 1 In this mode, the drive signals of switching transistors Q1 and Q2 are blocked, stopping the high-frequency switching action of the transistors, but the inverter side continues to operate normally (at this time, the inverter side still has inverter output), and the equipment can still operate normally. This is a regulatory intervention, not a direct shutdown. After the drive is blocked, the PFC stops injecting energy into the bus, and the bus voltage can slowly release energy through the load on the inverter side (light load or inverter losses), thereby reducing the voltage. The second voltage threshold in this mode is lower than the third voltage threshold. Before the bus voltage reaches the dangerous value, the voltage drops by suspending energy input, while maintaining the inverter output to ensure basic power supply. The degree of regulation and the voltage drop rate of this second-level drive blocking are more obvious than the degree of integral decomposition in the first level, but neither affects the normal power supply to the load.

[0051] It should be noted that the second detection time T2 can also be set to one interrupt cycle. It should be noted that when the sealing drive operation is triggered, the first-level deintegration operation can still be performed simultaneously to reduce the bus voltage. If the bus voltage falls below the second voltage threshold, the sealing drive is released. When it falls below the first voltage threshold, the deintegration operation is released and normal operation is restored.

[0052] In one possible implementation, a third regulation action is triggered when the bus voltage (U) is greater than or equal to a third voltage threshold (V3); the third regulation action is to control the converter to stop working in order to cut off the inverter output of the converter; the third voltage threshold is greater than the second voltage threshold.

[0053] In this embodiment, when the bus voltage is greater than or equal to the third voltage threshold, it indicates that the bus voltage is severely overvoltage. Neither deintegration nor sealing drive can reduce the bus voltage. Further, more effective measures need to be taken, namely, controlling the converter equipment to stop working, executing equipment protection actions to cut off the inverter output, and preventing the bus voltage from continuing to rise and affecting equipment safety.

[0054] In one possible implementation, for severe overvoltage scenarios where the bus voltage is greater than or equal to the third voltage threshold, two detection modes can be defined based on the actual situation. Specifically, when the bus voltage is greater than or equal to the third voltage threshold, triggering the third adjustment action includes: Step S2033: When the bus voltage is greater than or equal to the third voltage threshold and continues for a third detection time (bus voltage U) V3 and duration T T3), or, when the bus voltage is greater than or equal to the fourth voltage threshold and lasts for a fourth detection time (bus voltage U) V4 and duration T T4), triggering the third adjustment action; the fourth voltage threshold is greater than the third voltage threshold, and the fourth detection time is less than the third detection time.

[0055] In this embodiment, for scenarios where the voltage is greater than or equal to the third voltage threshold, two methods are used: slow detection and fast detection. The third voltage threshold corresponding to slow detection is lower than the fourth voltage threshold corresponding to fast detection, but the continuous third detection time corresponding to slow detection is longer than the continuous fourth detection time corresponding to fast detection (T3>T4, for example, T3 is 1s and T4 is 5ms). Specifically, slow detection is a software-level overvoltage scenario where the bus voltage rises slowly and continuously (such as long-term no-load energy accumulation). When the bus voltage exceeds the third voltage threshold, the system monitors the bus voltage with each interruption. If the bus voltage sampled in all interruptions exceeds the third voltage threshold within the third consecutive detection time T3 (e.g., 1 second), it is determined to be a continuous overvoltage and triggers the third voltage regulation action. This type of slow continuous overvoltage usually occurs under light load / no-load conditions, where energy is continuously injected into the bus but the load consumption is low, resulting in a slow rise in bus voltage. If the third detection time T3 is set too short, it may falsely trigger protection actions due to short-term voltage fluctuations. By setting a longer third detection time (e.g., 1 second), occasional voltage fluctuation conditions can be filtered out, ensuring accurate response only to continuous overvoltage scenarios that truly require intervention. For instantaneous overvoltage scenarios (such as short-term voltage spikes caused by load changes), when the bus voltage exceeds the fourth voltage threshold, the system records the bus voltage during each interruption. If the bus voltage sampled during all interruptions within the fourth detection time T4 (e.g., 5ms) exceeds the fourth voltage threshold, it is determined to be an instantaneous overvoltage, and the third voltage regulation action is triggered. This type of instantaneous overvoltage is usually caused by load changes (such as sudden load disconnection), power grid impact, etc., which causes the bus voltage to rise rapidly, with a short duration but a large amplitude. If there is no rapid response, it may instantly exceed the withstand voltage limit of the circuit devices. Therefore, the value of the fourth detection time T4 should avoid misjudgment caused by short-term noise interference, and take protective measures quickly in response to the actual overvoltage situation. It is a compromise value that takes into account both "avoiding misjudgment" and "rapid protection".

[0056] In one possible implementation, such as Figure 3b As shown, the hierarchical control scheme can also be a progressive decision relationship. Specifically, the steps are as follows: Step S2031: When the bus voltage (U) is greater than or equal to the first voltage threshold (V1) and continues for the first detection time (T1), (bus voltage U) V1 and duration T (T1) triggers the first adjustment action; the first adjustment action is to perform an integrator deintegration operation on the PI regulator in the voltage loop. Otherwise, the bus voltage is controlled normally in closed loop according to the logic of steps S201 and S202.

[0057] Step S2032, when the bus voltage is greater than or equal to the second voltage threshold and continues for a second detection time (bus voltage U) V2 and duration T If T2), trigger the second adjustment action; otherwise, return to step S2031 to determine whether the conditions for triggering the first adjustment action are met.

[0058] Step S2033: When the bus voltage is greater than or equal to the third voltage threshold and continues for a third detection time (bus voltage U) V3 and duration T T3), or, when the bus voltage is greater than or equal to the fourth voltage threshold and lasts for a fourth detection time (bus voltage U) V4 and duration T (T4) triggers the third adjustment action; otherwise, return to step S2032 to determine whether the conditions for triggering the second adjustment action are met.

[0059] In this embodiment, when the bus voltage reaches V1 and the duration reaches T1, the first adjustment action (deintegration) is triggered first. Deintegration slows down the rate of increase of the bus voltage, and the deintegration adjustment can slow down the time to rise to V2. If the bus voltage continues to rise to V2, the second adjustment action (block drive) is further triggered. Block drive increases the degree of bus voltage adjustment and suppresses the continuous rapid rise of the bus voltage. When the bus voltage drops below V2, block drive is stopped, and the process returns to the previous step. If the bus voltage continues to rise to V3 and the duration reaches T3, or rises to V4 and the duration reaches T4, the third adjustment action (shutdown) is triggered. When the bus voltage falls back, the process returns to the previous step. It should be noted that the above-mentioned deintegration, block drive, and stop inverter output processes are all software-level protection measures. That is, the bus voltage is obtained in real time through software AD sampling, and after digital filtering, it is compared with the first, second, third, and fourth thresholds to trigger the corresponding voltage adjustment actions. However, for extreme overvoltage scenarios where the bus voltage is greater than or equal to the fifth voltage threshold, the software AD sampling, filtering, and threshold comparison processes all have certain delays, making it impossible to respond at the fastest speed. Therefore, this application also provides a hardware overvoltage protection measure when controlling the bus voltage of the Vienna topology.

[0060] This embodiment serves as a front-line defense for hardware protection. Both the third and fourth voltage thresholds are lower than the hardware protection threshold (i.e., the fifth voltage threshold). By flexibly setting time parameters in software, and by setting the third voltage threshold, the third detection time, and the fourth voltage threshold and the fourth detection time to divide into slow detection and fast detection methods, it can cover more bus voltage overvoltage conditions, avoid accidental equipment shutdown due to brief overvoltage (such as brief voltage spikes), and intervene in advance for continuous overvoltage.

[0061] In one possible implementation, such as Figure 3a and Figure 3b As shown, when the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions, triggering the corresponding voltage regulation action further includes: acquiring the bus voltage signal output by the hardware voltage sampling circuit; when the bus voltage signal is a high-level signal and lasts for a fifth detection time (T5), triggering the third regulation action (corresponding to step S2034); wherein, the hardware voltage sampling circuit acquires the bus voltage in real time and compares the bus voltage with a fifth voltage threshold; when the bus voltage is greater than or equal to the fifth voltage threshold, the output bus voltage signal is a high-level signal; otherwise, the output bus voltage signal is a low-level signal; the fifth voltage threshold is greater than the fourth voltage threshold.

[0062] In this embodiment, the bus voltage is monitored in real time by a hardware voltage sampling circuit (such as a voltage comparator). When the bus voltage exceeds the fifth voltage threshold, the hardware voltage sampling circuit directly outputs a high level. When the hardware voltage sampling circuit detects that the signal remains high for the fifth detection time T5, an interrupt signal is directly triggered to control the equipment to stop and cut off the inverter output. This eliminates the need for software calculation delays and provides the fastest response speed. This hardware protection serves as the final safety line. When the bus voltage reaches the device's withstand voltage limit, the device is forcibly shut down by hardware to prevent permanent damage due to overvoltage breakdown.

[0063] In this embodiment, intervention measures are progressively escalated from minor adjustment to emergency protection based on the severity and duration of the bus voltage rise. By clearly defining the threshold progression relationship and specific operations of the first to third adjustment actions (integral decompression → drive shutdown → shutdown), the graded adjustment is made more operable: the first adjustment action (integral decompression) can suppress the saturation of the voltage loop PI regulator when the voltage rises slightly, preventing the voltage from continuing to rise at the source; the second adjustment action (drive shutdown) can suspend energy input when the voltage rises further, reducing the voltage through load consumption while maintaining the inverter output; the third adjustment action (shutdown) can cut off the output when the voltage approaches a dangerous value, avoiding device damage. The three-level action works together to achieve precise control of first adjusting, then limiting, and finally protecting, improving the reliability of the system. Furthermore, the third adjustment action is subdivided into "third voltage threshold + long detection time" and "fourth voltage threshold + short detection time," respectively targeting scenarios of slowly accumulating overvoltage (such as long-term accumulation of no-load energy) and instantaneous sudden overvoltage (such as sudden load changes): the long detection time (slow detection, such as 1 second) can avoid false triggering of protection due to short-term fluctuations, ensuring a stable response to continuous overvoltage; the short detection time (fast detection, such as 5 ms) can quickly intercept sudden high voltage, preventing the voltage from instantly exceeding the safety limit. The combination of the two detection logics improves the accuracy and timeliness of overvoltage protection. In addition, through the hardware overvoltage protection measure of "fifth voltage threshold + hardware detection," as the last line of defense for software protection, the hardware detection response speed is faster than software, and it can force shutdown when the voltage instantly reaches the device's limit withstand voltage (such as 475V), avoiding device damage caused by software protection failure; together with software protection, it forms a "software + hardware" dual guarantee, further improving system safety. This hierarchical control strategy, which first adjusts, then limits, and finally protects, effectively slows down the rate of voltage rise at each stage of adjustment / limitation before protection, ensuring sufficient detection and protection time. This achieves stable control of the bus voltage under no-load / light-load conditions, ensuring circuit safety, minimizing downtime, and improving equipment reliability and stability.

[0064] Figure 4a and Figure 4b This is a schematic flowchart of a bus voltage control method based on Vienna topology provided in another embodiment of this application; Figure 5 This is a closed-loop control block diagram of the Vienna topology; the embodiments of this application focus on describing in detail the closed-loop control of the bus voltage of the Vienna topology.

[0065] like Figure 4a and Figure 4b As shown, the bus voltage control method based on Vienna topology provided in this embodiment includes the following steps: Step S201: Obtain the actual total bus voltage and actual input current value output by the Vienna topology.

[0066] In one possible implementation, such as Figure 4a As shown, based on the actual total bus voltage value and the actual input current value, closed-loop control of the bus voltage in the Vienna topology is performed, including: Step S2021: Based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint, perform voltage closed-loop control on the total bus voltage to obtain a current reference.

[0067] It should be noted that, since the positive and negative buses of the Vienna topology work alternately rather than simultaneously, it is impossible to control the positive and negative buses individually; only the voltage of the main bus can be closed-loop controlled.

[0068] In one possible implementation, refer to Figure 5 The step of performing closed-loop voltage control on the total bus voltage based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint to obtain a current reference reference includes: calculating the actual total bus voltage value (U... bus_sum ) and the total bus voltage setpoint (U bus_ref The voltage error between the two points is calculated; the voltage error is input to the first PI regulator so that the first PI regulator adjusts the voltage error and outputs a current reference.

[0069] refer to Figure 5 This step involves closed-loop control of the bus voltage loop. The input to the bus voltage loop is the total bus voltage setpoint U. bus_ref The feedback input is the actual total bus voltage value U. bus_sum After filtering by a low-pass filter (LPF1), U is obtained. bus_sum_lpf1 Total bus voltage setpoint U bus_ref Subtract the actual total bus voltage U after filtering bus_sum_lpf1 The obtained voltage error is input to the first PI regulator, which performs proportional-integral regulation to bring the actual total bus voltage closer to the given value of the total bus voltage, thereby stabilizing the total bus voltage, providing a reference for the input current loop, and ensuring that the bus voltage meets the system requirements.

[0070] Step S2022: Based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology, closed-loop control is performed on the input current to obtain the first voltage compensation control quantity, so that the input current tracks the sine wave.

[0071] In one possible implementation, the step of performing closed-loop control of the input current based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology to obtain a first voltage compensation control quantity includes: multiplying the current reference by a sine function (sinθ) of the phase angle of the AC input voltage to obtain a sinusoidal current setpoint; calculating the sinusoidal current setpoint and the actual input current value (i... L The current error between the two is calculated; the current error is input to the second PI regulator so that the second PI regulator adjusts the current error and outputs a first voltage compensation control quantity.

[0072] refer to Figure 5 This step involves closed-loop control of the input current loop. Using the output of the bus voltage loop as the current reference, a sinusoidal current setpoint in phase with the AC input voltage of the Vienna topology is generated. This setpoint is the output of the first PI regulator of the bus voltage loop × sinθ, and is used as the input setpoint for the input current loop. Here, θ is the phase angle of the AC grid input voltage, ensuring the input current is in phase with the grid voltage to achieve a high power factor. The feedback input of the current loop is the actual input current value i. L (Actual measured input inductor current); Sinusoidal current setpoint (bus voltage loop PI output × sinθ) minus actual input current value i L The current error is obtained, and after proportional-integral regulation by the second PI regulator, the first voltage compensation control quantity is obtained. The first voltage compensation control quantity is related to the compensation AC input grid voltage (U). grid ) Do the difference (U) grid - First voltage compensation control quantity), to compensate for AC input grid voltage (U grid The effect of the input current on the input current is to ensure that the input current strictly follows the sinusoidal given value, thereby achieving sinusoidal input current (power factor correction). At the same time, the input power is adjusted according to the requirements of the bus voltage loop to maintain the stability of the bus voltage.

[0073] Step S2023: Perform closed-loop control on the difference between the positive bus voltage and the negative bus voltage of the Vienna topology to obtain a second voltage compensation control quantity so that the difference is within a preset error range.

[0074] It should be noted that the bus voltage loop can only control the sum of the positive and negative bus voltages, but cannot control the balance between the positive and negative bus voltages. Therefore, an additional midpoint balancing loop is needed to perform closed-loop control on the voltage difference between the positive and negative bus voltages.

[0075] In one possible implementation, the closed-loop control of the difference between the positive bus voltage and the negative bus voltage of the Vienna topology to obtain a second voltage compensation control quantity includes: obtaining the actual difference between the positive bus voltage and the negative bus voltage; calculating the deviation between the actual difference and the target difference, and inputting it to a third PI regulator so that the third PI regulator adjusts the deviation and outputs the second voltage compensation control quantity; wherein the target difference is 0.

[0076] refer to Figure 5 This step involves closed-loop control of the midpoint balancing loop. The given input to the midpoint balancing loop is the target difference of 0 (the desired voltage difference between the positive and negative buses is 0, i.e., midpoint balance). The feedback input is the actual difference between the positive and negative bus voltages (U). bus_diff The given target difference 0 minus the actual difference U bus_diff The midpoint deviation is obtained and, after proportional-integral regulation by the third IP regulator, outputs a second voltage compensation control quantity. This second voltage compensation control quantity compensates the output control path of the current loop, adjusting the conduction strategy of the switching transistors to ensure a reasonable distribution of energy between the positive and negative buses, ultimately eliminating the voltage difference. This ensures voltage balance between the positive and negative buses (avoiding excessively high / low voltage on one side), improving system stability and extending the lifespan of power devices.

[0077] Step S2024: Generate the drive signal for the switching transistor in the Vienna topology based on the first voltage compensation control quantity and the second voltage compensation control quantity.

[0078] In this step, refer to Figure 5 The voltage compensation control quantity, obtained by superimposing the outputs of the grid voltage and current loop and the midpoint balance loop, is subtracted to obtain the final voltage control signal, which is then input to the modulation module. The voltage control quantity is first multiplied by a normalization coefficient (2 / U). bus_sum The amplitude is adjusted, and then a drive pulse signal with a specific duty cycle is generated by the modulation algorithm of the modulator to control the on and off time of the switching transistor. In this step, the continuous control signal is converted into a pulse width modulation (PWM) signal by the modulation module to drive the switching transistor in the Vienna topology to turn on and off, the power electronic conversion (controlling the inductor energy storage / release process) is completed, and finally the power factor correction and bus voltage control are completed.

[0079] In this embodiment, the bus voltage loop stabilizes the total bus voltage, the input current loop sinusoids the input current and tracks the voltage demand, the midpoint balance loop ensures the balance between the positive and negative buses, and the modulation module converts the control signal into a switching transistor drive pulse. The four components work together to achieve efficient and stable operation of the VIENNA topology, providing a stable and reliable voltage for the downstream load.

[0080] Step S2031: When the bus voltage (U) is greater than or equal to the first voltage threshold (V1) and continues for the first detection time (T1), (bus voltage U) V1 and duration T T1), triggering the first adjustment action; the first adjustment action is to perform an integrator deintegration operation on the PI regulator in the voltage loop.

[0081] Step S2032, when the bus voltage is greater than or equal to the second voltage threshold and continues for the second detection time (bus voltage U) V2 and duration T T2), triggering the second adjustment action; the second adjustment action is to block the drive signal of the switching transistor in the Vienna topology; the second voltage threshold is greater than the first voltage threshold.

[0082] Step S2033: When the bus voltage is greater than or equal to the third voltage threshold and continues for a third detection time (bus voltage U) V3 and duration T T3), or, when the bus voltage is greater than or equal to the fourth voltage threshold and lasts for the fourth detection time (bus voltage U) V4 and duration T T4), triggering the third adjustment action; the fourth voltage threshold is greater than the third voltage threshold, and the fourth detection time is less than the third detection time.

[0083] Step S2034: The bus voltage signal output by the hardware voltage sampling circuit is a high-level signal and remains high for the fifth detection time (T). When T5), the third adjustment action is triggered.

[0084] In this embodiment, the Vienna topology output voltage is first ensured to be stable and reliable through closed-loop control of voltage loop, current loop and midpoint balance loop; then the bus voltage is monitored in real time, and when the bus voltage is over-voltage, the corresponding voltage regulation action is triggered according to the corresponding over-voltage level to realize graded over-voltage regulation and protection, which greatly improves the stability and reliability of equipment operation.

[0085] It should be noted that steps not described in detail in the above embodiments can be referred to in the descriptions in other embodiments, and multiple embodiments can be referenced from each other.

[0086] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0087] Figure 6This is a schematic diagram of the structure of a bus voltage control system based on Vienna topology provided in another embodiment of this application.

[0088] like Figure 6 As shown, the system includes: a Vienna topology, a data acquisition module, and a control module; the output of the data acquisition module is connected to the input of the control module, and is used to acquire the actual total bus voltage value and the actual input current value output by the Vienna topology, and send them to the control module; the output of the control module is connected to the switching transistor in the Vienna topology, and is used to execute the bus voltage control method based on the Vienna topology described in the above method embodiment.

[0089] It should be noted that the detailed implementation of this system embodiment can be found in the description of the relevant method embodiments above, and will not be repeated here.

[0090] It should be noted that the bus voltage control method provided in the above embodiments can be applied to single-phase Vienna topology as well as three-phase Vienna topology. This embodiment takes single-phase Vienna topology as an example to describe the bus voltage control system.

[0091] This application also provides a converter device, including the aforementioned bus voltage control system based on Vienna topology.

[0092] Figure 7 This is a schematic diagram of the structure of a converter device provided in one embodiment of this application. Figure 7 As shown, the device 700 of this embodiment includes a processor 710 and a memory 720, wherein the memory 720 stores a computer program 721 that can run on the processor 710. When the processor 710 executes the computer program 721, it implements the steps in any of the above method embodiments. Alternatively, when the processor 710 executes the computer program 721, it implements the functions of each module / unit in the above device embodiments.

[0093] For example, computer program 721 may be divided into one or more modules / units, one or more of which are stored in memory 720 and executed by processor 710 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 721 in device 700.

[0094] Those skilled in the art will understand that Figure 7 This is merely an example of a device and does not constitute a limitation on the device. It may include more or fewer components than shown, or combinations of certain components, or different components, such as input / output devices, network access devices, buses, etc.

[0095] The processor 710 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0096] The memory 720 can be an internal storage unit of the device, such as a hard disk or RAM, or an external storage device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. The memory 720 can also include both internal and external storage units. The memory 720 is used to store computer programs and other programs and data required by the device. The memory 720 can also be used to temporarily store data that has been output or will be output.

[0097] For the sake of simplicity and clarity, only the above-described functional modules / units are used as examples. In practical applications, the functions described above can be assigned to different functional modules / units as needed. These modules / units can be implemented in hardware, software, or a combination of both.

[0098] An embodiment of this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described in the above-described method embodiments.

[0099] This invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.

[0100] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0101] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0102] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A bus voltage control method based on Vienna topology, characterized in that, include: Obtain the actual total bus voltage and actual input current value output by the Vienna topology; Based on the actual total bus voltage value and the actual input current value, the bus voltage of the Vienna topology is controlled in a closed loop. When the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions, the corresponding voltage regulation action is triggered to reduce the bus voltage of the Vienna topology to a preset standard range. The preset graded overvoltage conditions include multiple voltage thresholds and a detection time corresponding to each voltage threshold. The degree of regulation response of the voltage regulation action increases as the bus voltage increases.

2. The bus voltage control method based on Vienna topology according to claim 1, characterized in that, When the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions, the corresponding voltage regulation action is triggered, including: When the bus voltage is greater than or equal to the first voltage threshold and lasts for a first detection time, a first adjustment action is triggered; the first adjustment action is to perform an integrator deintegration operation on the PI regulator in the voltage loop. When the bus voltage is greater than or equal to the second voltage threshold and lasts for a second detection time, a second adjustment action is triggered; the second adjustment action is to block the drive signal of the switching transistor in the Vienna topology; the second voltage threshold is greater than the first voltage threshold; When the bus voltage is greater than or equal to the third voltage threshold, a third adjustment action is triggered; the third adjustment action is to control the converter equipment to stop working in order to cut off the inverter output of the converter equipment; the third voltage threshold is greater than the second voltage threshold.

3. The bus voltage control method based on Vienna topology according to claim 2, characterized in that, The third adjustment action is triggered when the bus voltage is greater than or equal to the third voltage threshold, including: The third adjustment action is triggered when the bus voltage is greater than or equal to the third voltage threshold and lasts for a third detection time, or when the bus voltage is greater than or equal to the fourth voltage threshold and lasts for a fourth detection time; the fourth voltage threshold is greater than the third voltage threshold, and the fourth detection time is less than the third detection time.

4. The bus voltage control method based on Vienna topology according to claim 3, characterized in that, The step of triggering a corresponding voltage regulation action when the bus voltage output by the Vienna topology meets the preset graded overvoltage conditions also includes: Obtain the bus voltage signal output by the hardware voltage sampling circuit; When the bus voltage signal is a high-level signal and continues for the fifth detection time, the third adjustment action is triggered; The hardware voltage sampling circuit acquires the bus voltage in real time and compares the bus voltage with a fifth voltage threshold. When the bus voltage is greater than or equal to the fifth voltage threshold, the output bus voltage signal is a high-level signal; otherwise, the output bus voltage signal is a low-level signal. The fifth voltage threshold is greater than the fourth voltage threshold.

5. The bus voltage control method based on Vienna topology according to claim 1, characterized in that, The step of performing closed-loop control of the bus voltage of the Vienna topology based on the actual total bus voltage value and the actual input current value includes: Based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint, the total bus voltage is subjected to closed-loop voltage control to obtain a current reference. Based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology, the input current is subjected to closed-loop control to obtain the first voltage compensation control quantity so that the input current tracks the sine wave. The difference between the positive bus voltage and the negative bus voltage of the Vienna topology is subjected to closed-loop control to obtain a second voltage compensation control quantity, so that the difference is within a preset error range; The drive signal for the switching transistor in the Vienna topology is generated based on the first voltage compensation control value and the second voltage compensation control value.

6. The bus voltage control method based on Vienna topology according to claim 5, characterized in that, The step of performing closed-loop voltage control on the total bus voltage based on the voltage error between the actual total bus voltage value and the preset total bus voltage setpoint to obtain a current reference includes: Calculate the voltage error between the actual total bus voltage value and the given total bus voltage value; The voltage error is input to a first PI regulator so that the first PI regulator adjusts the voltage error and outputs a current reference.

7. The bus voltage control method based on Vienna topology according to claim 5, characterized in that, The step of performing closed-loop control on the input current based on the current reference, the actual input current value, and the phase information of the AC input voltage of the Vienna topology to obtain the first voltage compensation control quantity includes: Multiply the current reference by the sine function of the phase angle of the AC input voltage to obtain the sinusoidal current setpoint; Calculate the current error between the given sinusoidal current value and the actual input current value; The current error is input to the second PI regulator so that the second PI regulator adjusts the current error and outputs a first voltage compensation control quantity.

8. The bus voltage control method based on Vienna topology according to claim 5, characterized in that, The difference between the positive bus voltage and the negative bus voltage of the Vienna topology is subjected to closed-loop control to obtain a second voltage compensation control quantity, including: Obtain the actual difference between the positive bus voltage and the negative bus voltage; The deviation between the actual difference and the target difference is calculated and input to the third PI regulator so that the third PI regulator adjusts the deviation and outputs a second voltage compensation control quantity; wherein the target difference is 0.

9. A bus voltage control system based on Vienna topology, characterized in that, include: Vienna topology, acquisition module, and control module; The output terminal of the acquisition module is connected to the input terminal of the control module, and is used to acquire the actual total bus voltage value and actual input current value output by the Vienna topology, and send them to the control module. The output of the control module is connected to the switching transistor in the Vienna topology, and is used to execute the bus voltage control method based on the Vienna topology as described in any one of claims 1 to 8.

10. A converter device, characterized in that, This includes the bus voltage control system based on Vienna topology as described in claim 9.

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