Processing technology optimization method for semiconductor lining

Abstract

The invention discloses a processing technology optimization method for a semiconductor lining, and relates to the technical field of semiconductors, and the method comprises the steps: obtaining the multi-source data of a semiconductor lining processing technology, and carrying out the preprocessing, and obtaining the multi-source feature data; analyzing the multi-source feature data by using an anomaly analysis algorithm, and identifying key factors influencing the quality of the semiconductor lining; and based on the key factors, establishing a dynamic scheduling model, and adjusting the treatment process parameters of the semiconductor lining in real time by using the dynamic scheduling model to optimize the treatment process control strategy. According to the invention, the uniformity of the film layer can be improved, the fluctuation of the film thickness can be reduced, the stability of the process can be enhanced, the coverage rate and the electrical performance of the lining material can be optimized, and by accurately adjusting the process control strategy, not only is the production yield improved, but also the long-term reliability and consistency of the product can be improved, so that the defect rate in the production process can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a method for optimizing the processing of semiconductor liners. Background Technology

[0002] Semiconductor device manufacturing processes refer to the complex workflow of constructing electronic functional structures on silicon wafers or other semiconductor materials. The processing of semiconductor liners involves several key steps, including photolithography pattern definition, etching to form trench structures, liner material deposition, diffusion barrier treatment, ion implantation to modulate electrical properties, and subsequent annealing to stabilize material properties. As a crucial component of the connection or shielding structure, the deposition process of the liner requires extremely high parameter control, such as film thickness uniformity, coverage, material stress, and interface bonding. Each step requires precise process control strategies to ensure device reliability, functional consistency, and manufacturing yield. Optimizing these processes is crucial for improving integration density and reducing defect rates.

[0003] However, existing technologies typically rely on traditional static process control methods, lacking in-depth mining and analysis of multi-source data. This makes it difficult to accurately identify and address key factors affecting quality. Furthermore, the failure to achieve real-time dynamic adjustment during processing makes it difficult to cope with complex process fluctuations, resulting in poor film uniformity and large film thickness fluctuations, which in turn affect the consistency and reliability of product performance.

[0004] There are currently no effective solutions to the problems in the relevant technologies. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a process optimization method for semiconductor liners. This method solves the problems mentioned in the background, which typically rely on traditional static process control methods. These methods lack in-depth mining and analysis of multi-source data, making it difficult to accurately identify and address key factors affecting quality. Furthermore, the lack of real-time dynamic adjustment during processing makes it difficult to cope with complex process fluctuations, resulting in poor film uniformity, large film thickness fluctuations, and consequently affecting the consistency and reliability of product performance.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A method for optimizing the processing of semiconductor liners, comprising: Multi-source data of semiconductor liner processing technology are acquired and preprocessed to obtain multi-source feature data; Anomaly analysis algorithms are used to analyze multi-source feature data. By using a node expansion algorithm, alternative states of sibling nodes and their parent nodes are constructed starting from leaf nodes to expand the diagnostic candidate solution space. Based on a probability evaluation algorithm, the probability change of each alternative state path is evaluated to determine the potential abnormal fluctuation characteristics in the candidate paths and identify the key factors affecting the quality of semiconductor liners. Based on key factors, a dynamic scheduling model is established, and the processing parameters of the semiconductor liner are adjusted in real time using the dynamic scheduling model to optimize the processing control strategy.

[0007] Furthermore, multi-source data on the semiconductor liner processing technology are acquired and preprocessed to obtain multi-source feature data, including: The duplicate data, missing values ​​and outliers of the acquired multi-source data are denoised, filtered and smoothed to obtain complete multi-source data. Standardize the complete multi-source data and convert it into a unified scale to extract key process change curves that reflect changes in process status; Based on the process variation curve and the preset parameter model, the required phase function and feature point information are calculated; The core envelope signal is extracted using wavelet packet decomposition, and key features in the process are deconstructed by combining short-time Fourier transform. The frequency domain analysis of the demodulated signal spectrum is performed to extract the peak values ​​in the spectrum and output multi-source feature data.

[0008] Furthermore, before expanding the diagnostic candidate solution space by constructing alternative states of sibling nodes and their parent nodes starting from leaf nodes using a node expansion algorithm, the following steps are also included: Construct a multi-source feature data search tree, initialize an expandable node set, and use the root node to represent the overall state as the starting search entry point; The root node state cost is evaluated based on the anomaly analysis model, and the optimal feature path is recursively generated to the leaf node to form a candidate diagnostic scheme. After expanding the diagnostic candidate solution space by constructing alternative states of sibling nodes and their parent nodes starting from leaf nodes using the node expansion algorithm, the following steps are also included: Determine whether the constraints are met. If they are met, output the feature combination that satisfies the constraints. Otherwise, generate a conflict set and mark the abnormal feature state. The process of repeated search and conflict analysis is used to finally screen and output all feature combinations that meet the constraints as key factors affecting the quality of semiconductor liners.

[0009] Furthermore, based on the anomaly analysis model, the state cost of the root node is evaluated, and the optimal feature path is recursively generated to the leaf nodes, forming candidate diagnostic schemes, including: Evaluate the cost of abnormal root node states and quantify its deviation from the overall feature space as a starting reference for path generation; Based on the minimum cost criterion, a recursive search is performed in the feature space to prioritize the construction of candidate path nodes with the lowest cost. Expand along the recursive path and filter leaf nodes that meet the constraints, and record their corresponding feature state sequences; The leaf node paths are summarized to form candidate diagnostic solutions.

[0010] Furthermore, before assessing the probability variation of each alternative state path based on a probability evaluation algorithm and determining the potential abnormal fluctuation characteristics among candidate paths, the following steps are also included: Starting from the current leaf node, generate the optimal feature path and obtain the probabilistic feature state corresponding to the leaf node; For a selected leaf node, construct the alternative states of its sibling nodes and parent nodes, and generate the optimal feature path starting from the selected leaf node to obtain the feature probability path corresponding to the selected leaf node. After assessing the probability changes of each alternative state path based on a probabilistic evaluation algorithm and determining the potential abnormal fluctuation characteristics among the candidate paths, the following steps are also included: Calculate the anomaly score of the candidate state path to measure the degree of deviation between the candidate state path and the normal state; Construct a conflict set based on the anomaly score, remove states that do not meet the constraints, and update the scalable node set. Repeatedly perform alternative path generation and anomaly screening to continuously expand the candidate solution space until a set of diagnostic candidate solutions that meets the constraints is formed.

[0011] Furthermore, for the selected leaf node, alternative states for its sibling nodes and parent nodes are constructed, and the optimal feature path is generated starting from the selected leaf node. The feature probability path corresponding to the selected leaf node includes: Identify the structural location of the selected leaf node and use it as the starting point for the current feature path expansion; Based on the node topology, construct the alternative states of the corresponding sibling nodes and parent nodes; The feature cost of each alternative node state is evaluated, and the set of nodes that can participate in path generation is selected. Starting from the selected leaf node, the optimal feature path is recursively generated by combining the state cost, and the state sequence in the complete path is extracted to construct the feature probability path corresponding to the selected leaf node.

[0012] Furthermore, based on the probability evaluation algorithm, the degree of probability change of each alternative state path is assessed, and the potential abnormal fluctuation characteristics of the candidate paths are determined, including: Construct a complex network, set the initial state of all nodes to the uncovered state, and initialize the number of overlaps to the non-overlapping state; Calculate the exclusion quality to centrality ratio for each node, select the central node of the box based on the ratio, divide the region, and assign the nodes that meet the conditions to the box; Mark the covered nodes as processed, and among the remaining uncovered nodes, select the node with the smallest quality-to-centrality ratio and exclude it as the center node of the next box; Continue executing the operations of selecting the central node and dividing the boxes until all nodes in the network have been divided, ensuring the integrity of coverage and allocation; Based on the partitioned box node information, the probability changes of each alternative path are evaluated, and potential abnormal fluctuation characteristics in the candidate paths are identified.

[0013] Furthermore, the formula for calculating the anomaly score of the candidate state path is as follows: ; In the formula, S ( P () indicates the anomaly score of the candidate state path; P Indicates the selected state path; P 0 indicates a normal path; ψ a (·) indicates the first (·) a A state feature extraction function; oh a Indicates the first a The weights of each state feature; n This represents the total number of state features.

[0014] Furthermore, based on key factors, a dynamic scheduling model is established, and this model is used to adjust the processing parameters of the semiconductor liner in real time, optimizing the processing control strategy, including: Obtain historical processing data samples and assess the sensitivity of key factors by combining them with the error cost function; Based on key factors, a sample subset and a validation set are constructed, and multiple basic decision tree models are trained. The performance of each basic decision tree model is evaluated using the validation set. The scheduling weights of the basic decision tree models are determined based on the classification accuracy. The outputs of each basic decision tree model are then fused to construct a dynamic scheduling model. The constructed dynamic scheduling model is optimized using model optimization algorithms, and the processing parameters of the semiconductor liner are adjusted in real time through the optimized dynamic scheduling model to optimize the processing control strategy.

[0015] Furthermore, the constructed dynamic scheduling model is optimized using model optimization algorithms, and the processing parameters of the semiconductor liner are adjusted in real time through the optimized dynamic scheduling model. The optimized processing control strategy includes: Set the parameters of the model optimization algorithm, set the maximum number of iterations, and define the optimization boundary of the process parameters; The performance of the current parameter combination is evaluated using semiconductor process control error as the fitness function. Based on the current iteration progress, update the exploration probability and adjustment intensity of the process parameters; The target process parameters are selected by using a roulette wheel selection mechanism and then fine-tuned to improve the stability and convergence accuracy of process control. If the maximum number of iterations is reached, the target process parameters are output, and the target process parameters are input into the dynamic scheduling model to obtain the optimized dynamic scheduling model. The processing process parameters of the semiconductor liner are adjusted in real time to optimize the processing process control strategy. Otherwise, the optimization continues.

[0016] The beneficial effects of this invention are as follows: 1. This invention accurately identifies key factors affecting the quality of the liner through anomaly analysis algorithms. Based on these key factors, a dynamic scheduling model is established to optimize the processing parameters in real time, thereby improving the uniformity of the membrane layer, reducing membrane thickness fluctuations, enhancing process stability, and optimizing the coverage and electrical performance of the liner material. By precisely adjusting the process control strategy, not only is the production yield improved, but the long-term reliability and consistency of the product are also enhanced, thereby reducing the defect rate in the production process.

[0017] 2. By constructing a feature path search mechanism based on anomaly analysis and probability assessment, this invention can efficiently identify key state variations affecting process quality, dynamically expand the optimal process control path, and improve the accuracy and coverage of anomaly detection. This enables real-time optimization and precise control of semiconductor liner processing technology, thereby improving yield and consistency.

[0018] 3. This invention constructs a dynamic scheduling model based on key factors and uses model optimization algorithms for real-time adjustment, which can effectively improve the parameter optimization efficiency and real-time performance of the semiconductor liner processing process. By adjusting process parameters in real time and optimizing the control strategy, the quality and consistency of liner processing can be effectively improved, the defect rate can be reduced, and thus the production yield and product performance stability can be improved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of a process optimization method for semiconductor liners according to an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0022] In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] According to an embodiment of the present invention, a method for optimizing the processing of semiconductor liners is provided.

[0024] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figure 1 As shown, the process optimization method for semiconductor liners according to an embodiment of the present invention includes: S1. Obtain multi-source data of semiconductor liner processing technology and perform preprocessing to obtain multi-source feature data; Specifically, multi-source data on semiconductor liner processing can be obtained through equipment-level data acquisition (process equipment sensors, liner deposition, annealing, plasma treatment, etc.), process monitoring systems (APC / SPC), measurement and testing systems (such as CD-SEM, XRD, AFM), MES systems, and log recording.

[0025] Specifically, the multi-source data includes temperature setpoint, RF power, gas flow rate, real-time temperature / power curve, reaction chamber pressure change, film thickness, component ratio, roughness, interfacial adhesion, defect density, number of poorly covered areas, uniformity index, etc.

[0026] Specifically, multi-source characteristic data include temperature curve characteristics (such as heating rate, peak temperature, isothermal time, etc.), pressure change characteristics (such as pressure fluctuation range in the steady-state section), gas flow ratio, gas switching time point, RF power intensity, fluctuation frequency, surface roughness (Ra / Rq), deposition coverage, sidewall coating uniformity, mean and standard deviation of film thickness, maximum and minimum difference, etc.

[0027] S2. Analyze multi-source feature data using anomaly analysis algorithms to identify key factors affecting the quality of semiconductor liners; Specifically, key factors include the stability of process parameters (such as temperature, gas flow rate, RF power, etc.), film characteristics (film thickness uniformity, film stress, film density, etc.), equipment operating status (equipment aging, precision, etc.), environmental factors (humidity, atmosphere, etc.), and material quality (purity, batch differences, etc.).

[0028] S3. Based on key factors, establish a dynamic scheduling model and use the dynamic scheduling model to adjust the processing parameters of the semiconductor liner in real time to optimize the processing control strategy.

[0029] In this optional embodiment, multi-source data of the semiconductor liner processing technology is acquired and preprocessed to obtain multi-source feature data, including: The duplicate data, missing values ​​and outliers of the acquired multi-source data are denoised, filtered and smoothed to obtain complete multi-source data. Standardize the complete multi-source data and convert it into a unified scale to extract key process change curves that reflect changes in process status; Based on the process variation curve and the preset parameter model, the required phase function and feature point information are calculated; The core envelope signal is extracted using wavelet packet decomposition, and key features in the process are deconstructed by combining short-time Fourier transform. The frequency domain analysis of the demodulated signal spectrum is performed to extract the peak values ​​in the spectrum and output multi-source feature data.

[0030] Specifically, firstly, multi-source data on the semiconductor liner processing technology is acquired, including equipment parameters, process curves, and test results. This data is then denoised, imputed for missing values, and smoothed to form a complete dataset. Next, the complete data is standardized, key process variation curves are extracted, and phase functions and feature points are calculated using a parametric model. Then, wavelet packet decomposition and short-time Fourier transform are used to extract the core envelope signal, followed by frequency domain analysis to extract spectral peaks. Finally, multi-source feature data is generated. This improves the accuracy of process feature extraction, enables precise characterization of the process state, and enhances the stability of the liner quality.

[0031] In this optional embodiment, anomaly analysis algorithms are used to analyze multi-source feature data to identify key factors affecting the quality of semiconductor liners, including: Construct a multi-source feature data search tree, initialize an expandable node set, and use the root node to represent the overall state as the starting search entry point; The root node state cost is evaluated based on the anomaly analysis model, and the optimal feature path is recursively generated to the leaf node to form a candidate diagnostic scheme. By using a node expansion algorithm, alternative states of sibling nodes and their parent nodes are constructed starting from leaf nodes, thus expanding the diagnostic candidate solution space. Determine whether the constraints are met. If they are met, output the feature combination that satisfies the constraints. Otherwise, generate a conflict set and mark the abnormal feature state. The process of repeated search and conflict analysis is used to finally screen and output all feature combinations that meet the constraints as key factors affecting the quality of semiconductor liners.

[0032] Specifically, firstly, a multi-source feature data search tree is constructed, and an expandable node set is initialized, with the root node representing the overall state as the initial search entry point. Then, based on an anomaly analysis model, the state cost of the root node is evaluated, and the optimal feature path is recursively generated to the leaf nodes, forming preliminary candidate diagnostic solutions. Next, through a node expansion algorithm, alternative states of sibling nodes and their parent nodes are constructed starting from the leaf nodes, expanding the diagnostic candidate solution space. Subsequently, it is determined whether the feature combination satisfies the constraints; if so, it is output; otherwise, a conflict set is generated and abnormal feature states are marked. Finally, the search and conflict analysis are repeated, and all feature combinations that satisfy the constraints are selected and output as key factors affecting the lining quality. Thus, through recursive search and conflict analysis, key factors affecting the lining quality can be accurately identified, process control strategies optimized, and production yield and quality consistency improved.

[0033] Specifically, the anomaly analysis algorithm is the A-Star Conflict Algorithm, an anomaly diagnosis algorithm that combines A-Star search with conflict set analysis. In this invention, it constructs a multi-source feature search tree, recursively generates the optimal path from the root node, and constructs a conflict set when an anomaly is encountered. The algorithm iteratively expands the feature states, filters combinations that satisfy the film quality constraints, thereby identifying key anomalies such as "low steady-state temperature" and "large temperature fluctuations," which are then used for subsequent process scheduling optimization.

[0034] In this optional embodiment, the root node state cost is evaluated based on the anomaly analysis model, and the optimal feature path is recursively generated to the leaf nodes to form a candidate diagnostic scheme, including: Evaluate the cost of abnormal root node states and quantify its deviation from the overall feature space as a starting reference for path generation; Based on the minimum cost criterion, a recursive search is performed in the feature space to prioritize the construction of candidate path nodes with the lowest cost. Expand along the recursive path and filter leaf nodes that meet the constraints, and record their corresponding feature state sequences; The leaf node paths are summarized to form candidate diagnostic solutions.

[0035] Specifically, firstly, a multi-source feature data search tree is constructed, with the overall process status as the root node and serving as the starting point for the recursive search. Then, based on an anomaly analysis model, the anomaly cost of the root node is evaluated, its deviation in the feature space is quantified, and the feature path with the lowest cost is recursively generated to the leaf nodes according to the minimum cost criterion. Next, nodes meeting the constraints are selected at each step, and their feature state sequences are extracted. Finally, all leaf node paths are summarized to construct candidate diagnostic schemes for identifying anomaly influencing factors. This achieves automatic identification and attribution of key anomaly paths, enhancing the diagnostic accuracy and response efficiency of the lining process.

[0036] In this optional embodiment, the diagnostic candidate solution space is expanded by constructing alternative states of sibling nodes and their parent nodes starting from leaf nodes using a node expansion algorithm, including: Starting from the current leaf node, generate the optimal feature path and obtain the probabilistic feature state corresponding to the leaf node; For a selected leaf node, construct the alternative states of its sibling nodes and parent nodes, and generate the optimal feature path starting from the selected leaf node to obtain the feature probability path corresponding to the selected leaf node. The probability evaluation algorithm is used to assess the degree of probability change of each alternative state path and to determine the potential abnormal fluctuation characteristics in the candidate paths. Calculate the anomaly score of the candidate state path to measure the degree of deviation between the candidate state path and the normal state; Construct a conflict set based on the anomaly score, remove states that do not meet the constraints, and update the scalable node set. Repeatedly perform alternative path generation and anomaly screening to continuously expand the candidate solution space until a set of diagnostic candidate solutions that meets the constraints is formed.

[0037] Specifically, firstly, starting from the currently identified abnormal leaf node, the corresponding optimal feature path is generated, and its probabilistic feature state is obtained. Then, alternative states for the sibling and parent nodes of this node are constructed, generating corresponding feature probability paths. Next, the variation amplitude of each path is analyzed based on a probability evaluation algorithm, potential abnormal fluctuation features are extracted, and an anomaly score is calculated for each candidate path. A conflict set is constructed based on the score results, states that do not meet the constraints are eliminated, and the expandable node set is updated. Finally, the process of generating and filtering alternative paths is repeated to continuously expand the diagnostic solution space until a set of diagnostic solutions that meets the conditions is output. This improves the depth and accuracy of anomaly identification, effectively expands diagnostic solutions, and enhances the robustness of process control.

[0038] Specifically, the node expansion algorithm is a quantum walk algorithm, a search method based on quantum probabilistic evolution. In this invention, it is used to construct alternative feature state paths between sibling and parent nodes starting from leaf nodes, and to evaluate path probability changes and anomaly scores. By continuously generating and filtering alternative paths, the diagnostic candidate space is expanded, and finally, feature combinations that satisfy the membrane quality constraints are output.

[0039] In this optional embodiment, for a selected leaf node, alternative states of its sibling nodes and parent nodes are constructed, and an optimal feature path is generated starting from the selected leaf node. The feature probability path corresponding to the selected leaf node is obtained by: Identify the structural location of the selected leaf node and use it as the starting point for the current feature path expansion; Based on the node topology, construct the alternative states of the corresponding sibling nodes and parent nodes; The feature cost of each alternative node state is evaluated, and the set of nodes that can participate in path generation is selected. Starting from the selected leaf node, the optimal feature path is recursively generated by combining the state cost, and the state sequence in the complete path is extracted to construct the feature probability path corresponding to the selected leaf node.

[0040] Specifically, first, the structural position of the selected leaf node in the feature path is identified as the starting point for path expansion. Then, based on the node topology, alternative states of its sibling and parent nodes are constructed, and feature costs are evaluated for each alternative state to select the effective set of nodes that can participate in path generation. Next, starting from the selected leaf node, the optimal feature path is recursively generated by combining state costs, and the feature state sequence in the complete path is extracted to construct the corresponding feature probability path. This enhances the coverage and accuracy of diagnostic paths and improves the ability to identify abnormal state evolution paths.

[0041] In this optional embodiment, the probability change of each alternative state path is evaluated based on a probability assessment algorithm to determine the potential abnormal fluctuation characteristics in the candidate paths, including: Construct a complex network, set the initial state of all nodes to the uncovered state, and initialize the number of overlaps to the non-overlapping state; Calculate the exclusion quality to centrality ratio for each node, select the central node of the box based on the ratio, divide the region, and assign the nodes that meet the conditions to the box; Mark the covered nodes as processed, and among the remaining uncovered nodes, select the node with the smallest quality-to-centrality ratio and exclude it as the center node of the next box; Continue executing the operations of selecting the central node and dividing the boxes until all nodes in the network have been divided, ensuring the integrity of coverage and allocation; Based on the partitioned box node information, the probability changes of each alternative path are evaluated, and potential abnormal fluctuation characteristics in the candidate paths are identified.

[0042] Specifically, first, a complex feature node network is constructed, initializing all nodes to an uncovered state and setting the overlap count to non-overlap. Then, the exclusion quality to centrality ratio of each node is calculated, and the node with the smallest ratio is selected as the center, dividing the area into boxes and assigning nodes that meet the criteria. Next, the selection of center nodes and region division are iteratively performed until all nodes are completely covered. Finally, based on the node information in each box, the probability changes of alternative paths are analyzed to identify potential abnormal fluctuation characteristics. This allows for accurate identification of the source of abnormal process changes, improving the depth of path evaluation and diagnostic sensitivity.

[0043] Specifically, the probabilistic evaluation algorithm is the overlapping box covering algorithm, a probabilistic evaluation method based on complex network partitioning. In this invention, feature nodes are initialized to an uncovered state. By calculating the exclusion quality-centrality ratio, center nodes are selected sequentially to generate "overlapping boxes," gradually dividing the network region. The algorithm evaluates the probability differences of box coverage in each path, thereby identifying potential abnormal fluctuation features for candidate state screening and abnormal path identification.

[0044] In this optional embodiment, the formula for calculating the anomaly score of the candidate state path is: ; In the formula, S ( P () represents the anomaly score of the candidate state path, which is used to measure the degree of deviation from the normal state path; P This indicates the selected state path, where it is necessary to assess whether there are any abnormal fluctuations in the path. P 0 indicates a normal path, and it is currently necessary to assess whether there are any abnormal fluctuations in the path. ψ a (·) indicates the first (·) a Each state feature extraction function extracts corresponding feature values ​​(such as average number of hops, rate of change, complexity, etc.) from the path. oh a Indicates the first a The weight of each state feature reflects the importance of that feature in anomaly detection; n This represents the total number of state features.

[0045] In this optional embodiment, a dynamic scheduling model is established based on key factors, and the processing parameters of the semiconductor liner are adjusted in real time using the dynamic scheduling model to optimize the processing control strategy, including: Obtain historical processing data samples and assess the sensitivity of key factors by combining them with the error cost function; Based on key factors, a sample subset and a validation set are constructed, and multiple basic decision tree models are trained. The performance of each basic decision tree model is evaluated using the validation set. The scheduling weights of the basic decision tree models are determined based on the classification accuracy. The outputs of each basic decision tree model are then fused to construct a dynamic scheduling model. The constructed dynamic scheduling model is optimized using model optimization algorithms, and the processing parameters of the semiconductor liner are adjusted in real time through the optimized dynamic scheduling model to optimize the processing control strategy.

[0046] Specifically, firstly, historical semiconductor liner processing data is collected, and the sensitivity of key factors is analyzed using an error cost function to screen for feature variables that significantly impact the process. Then, training and validation sets are created based on these key factors, multiple basic decision tree models are constructed, and the performance of each model is evaluated using the validation set. Scheduling weights are assigned based on classification accuracy. Next, the models are weighted and fused to establish an initial dynamic scheduling model, and a model optimization algorithm is introduced for global optimization. Finally, the optimized model is used to adjust processing parameters in real time and optimize the control strategy. This improves the accuracy and responsiveness of the scheduling model, enables dynamic adaptive adjustment of process parameters, and enhances process robustness.

[0047] In this optional embodiment, the constructed dynamic scheduling model is optimized using a model optimization algorithm, and the processing parameters of the semiconductor liner are adjusted in real time using the optimized dynamic scheduling model. The optimized processing control strategy includes: Set the parameters of the model optimization algorithm, set the maximum number of iterations, and define the optimization boundary of the process parameters; The performance of the current parameter combination is evaluated using semiconductor process control error as the fitness function. Based on the current iteration progress, update the exploration probability and adjustment intensity of the process parameters; The target process parameters are selected by using a roulette wheel selection mechanism and then fine-tuned to improve the stability and convergence accuracy of process control. If the maximum number of iterations is reached, the target process parameters are output, and the target process parameters are input into the dynamic scheduling model to obtain the optimized dynamic scheduling model. The processing process parameters of the semiconductor liner are adjusted in real time to optimize the processing process control strategy. Otherwise, the optimization continues.

[0048] Specifically, first, the parameters of the model optimization algorithm are set, including the maximum number of iterations and the optimization boundary of the process parameters are defined. Then, the performance of the current parameter combination is evaluated using the process control error as the fitness function. Next, the exploration probability and adjustment intensity of the process parameters are dynamically adjusted according to the iteration progress. A roulette wheel selection mechanism is used to select the target process parameters, which are then fine-tuned. If the preset number of iterations is reached, the target process parameters are output and input into the dynamic scheduling model for real-time adjustment; otherwise, the iterative optimization process continues. Thus, through iterative optimization, the adjustment accuracy and convergence speed of the process parameters are improved, enhancing the real-time performance and adaptability of the dynamic scheduling model.

[0049] Specifically, the model optimization algorithm is the multiverse algorithm, a cosmology-inspired optimization algorithm used to find the optimal solution for multiple objective functions. In this invention, the algorithm dynamically adjusts the exploration probability and intensity of process parameters by setting parameters and iteration counts, using process control error as the fitness function, and employing a roulette wheel selection mechanism to select and fine-tune parameters, ultimately outputting optimized process parameters. This optimizes the dynamic scheduling model and adjusts the semiconductor liner processing process in real time, improving the stability and accuracy of process control.

[0050] To facilitate understanding of the above technical solutions of the present invention, the following provides a detailed description of the process optimization of semiconductor liners in actual practice.

[0051] I. Real-time data acquisition and feature extraction: In the semiconductor liner plasma-enhanced deposition (PECVD) process, the system collects real-time temperature and power curve data. Table 1 below shows the temperature data acquisition results and feature extraction for a certain batch A: Table 1. Temperature process parameters and characteristic data of a certain batch A II. Anomaly Analysis and Key Factor Identification: Based on the multi-source temperature characteristics of batch A, the system invoked the anomaly analysis model (feature path search tree + cost function optimization), obtaining an anomaly cost score S=0.81 (threshold 0.65). The analysis and judgment are as follows: Temperature anomaly mode definition: steady state temperature <228°C, fluctuation range >±1.5°C.

[0052] Corresponding results: poor film thickness uniformity, measured ±9.1%; defect rate as high as 8.4%; finished product yield of only 91.2%.

[0053] The aforementioned abnormal temperature patterns were identified by the model as the core factors that mainly affect the quality and yield of the film layer, and were used as the basis for parameter correction of the subsequent dynamic scheduling model.

[0054] III. Dynamic Scheduling and Optimization Control Based on Abnormal Patterns: Based on the identified temperature anomaly patterns, the system activates a dynamic scheduling model (composed of 50 ensemble decision trees) to automatically recommend and adjust process parameters in real time for the next batch B. Table 2 below shows the process data for batch B and the adjustments made after scheduling: Table 2. Temperature data after adjustment for batch B The optimized performance is shown in Table 3 below, compared with batch A: Table 3. Performance Comparison Before and After Optimization By identifying and dynamically managing abnormal temperature patterns, fluctuations and defects are significantly reduced, film uniformity is greatly improved, and yield is significantly increased.

[0055] In summary, by utilizing the above-mentioned technical solutions of this invention, the present invention, through constructing a feature path search mechanism based on anomaly analysis and probability assessment, can efficiently identify key state variations affecting process quality, dynamically expand the optimal process control path, and improve the accuracy and coverage of anomaly detection. This enables real-time optimization and precise control of the semiconductor liner processing process, thereby improving yield and consistency. Furthermore, by constructing a dynamic scheduling model based on key factors and utilizing model optimization algorithms for real-time adjustment, this invention can effectively improve the parameter optimization efficiency and real-time performance of the semiconductor liner processing process. By adjusting process parameters in real-time and optimizing the control strategy, the quality and consistency of liner processing can be effectively improved, the defect rate reduced, and thus production yield and product performance stability increased.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing the processing of semiconductor liners, characterized in that, include: Multi-source data of semiconductor liner processing technology are acquired and preprocessed to obtain multi-source feature data; Anomaly analysis algorithms are used to analyze multi-source feature data. By using a node expansion algorithm, alternative states of sibling nodes and their parent nodes are constructed starting from leaf nodes to expand the diagnostic candidate solution space. The probability evaluation algorithm is used to assess the degree of probability change of each alternative state path, determine the potential abnormal fluctuation characteristics in the candidate path, and identify the key factors affecting the quality of the semiconductor liner. Based on key factors, a dynamic scheduling model is established, and the processing parameters of the semiconductor liner are adjusted in real time using the dynamic scheduling model to optimize the processing control strategy.

2. The method for optimizing the processing of semiconductor liners according to claim 1, characterized in that, The process of acquiring multi-source data on semiconductor liner processing technology and preprocessing it to obtain multi-source feature data includes: The duplicate data, missing values ​​and outliers of the acquired multi-source data are denoised, filtered and smoothed to obtain complete multi-source data. Standardize the complete multi-source data and convert it into a unified scale to extract key process change curves that reflect changes in process status; Based on the process variation curve and the preset parameter model, the required phase function and feature point information are calculated; The core envelope signal is extracted using wavelet packet decomposition, and key features in the process are deconstructed by combining short-time Fourier transform. The frequency domain analysis of the demodulated signal spectrum is performed to extract the peak values ​​in the spectrum and output multi-source feature data.

3. The method for optimizing the processing of semiconductor liners according to claim 1, characterized in that, Before expanding the diagnostic candidate solution space by constructing alternative states of sibling nodes and their parent nodes starting from leaf nodes using the node expansion algorithm, the following steps are also included: Construct a multi-source feature data search tree, initialize an expandable node set, and use the root node to represent the overall state as the starting search entry point; The root node state cost is evaluated based on the anomaly analysis model, and the optimal feature path is recursively generated to the leaf node to form a candidate diagnostic scheme. The step of expanding the diagnostic candidate solution space by constructing alternative states of sibling nodes and their parent nodes starting from leaf nodes using a node expansion algorithm also includes: Determine whether the constraints are met. If they are met, output the feature combination that satisfies the constraints. Otherwise, generate a conflict set and mark the abnormal feature state. The process of repeated search and conflict analysis is used to finally screen and output all feature combinations that meet the constraints as key factors affecting the quality of semiconductor liners.

4. The method for optimizing the processing of semiconductor liners according to claim 3, characterized in that, The process of evaluating the root node state cost based on the anomaly analysis model and recursively generating the optimal feature path to the leaf nodes to form candidate diagnostic schemes includes: Evaluate the cost of abnormal root node states and quantify its deviation from the overall feature space as a starting reference for path generation; Based on the minimum cost criterion, a recursive search is performed in the feature space to prioritize the construction of candidate path nodes with the lowest cost. Expand along the recursive path and filter leaf nodes that meet the constraints, and record their corresponding feature state sequences; The leaf node paths are summarized to form candidate diagnostic solutions.

5. The method for optimizing the processing of semiconductor liners according to claim 1, characterized in that, Before assessing the probability change of each alternative state path based on the probability evaluation algorithm and determining the potential abnormal fluctuation characteristics in the candidate paths, the following steps are also included: Starting from the current leaf node, generate the optimal feature path and obtain the probabilistic feature state corresponding to the leaf node; For a selected leaf node, construct the alternative states of its sibling nodes and parent nodes, and generate the optimal feature path starting from the selected leaf node to obtain the feature probability path corresponding to the selected leaf node. After evaluating the probability change of each alternative state path based on the probability assessment algorithm and determining the potential abnormal fluctuation characteristics in the candidate paths, the process further includes: Calculate the anomaly score of the candidate state path to measure the degree of deviation between the candidate state path and the normal state; Construct a conflict set based on the anomaly score, remove states that do not meet the constraints, and update the scalable node set. Repeatedly perform alternative path generation and anomaly screening to continuously expand the candidate solution space until a set of diagnostic candidate solutions that meets the constraints is formed.

6. The method for optimizing the processing of a semiconductor liner according to claim 5, characterized in that, The process of constructing alternative states for the selected leaf node's sibling and parent nodes, generating the optimal feature path starting from the selected leaf node, and obtaining the feature probability path corresponding to the selected leaf node includes: Identify the structural location of the selected leaf node and use it as the starting point for the current feature path expansion; Based on the node topology, construct the alternative states of the corresponding sibling nodes and parent nodes; The feature cost of each alternative node state is evaluated, and the set of nodes that can participate in path generation is selected. Starting from the selected leaf node, the optimal feature path is recursively generated by combining the state cost, and the state sequence in the complete path is extracted to construct the feature probability path corresponding to the selected leaf node.

7. The method for optimizing the processing of a semiconductor liner according to claim 5, characterized in that, The probability evaluation algorithm assesses the degree of probability change of each alternative state path and determines the potential abnormal fluctuation characteristics in the candidate paths, including: Construct a complex network, set the initial state of all nodes to the uncovered state, and initialize the number of overlaps to the non-overlapping state; Calculate the exclusion quality to centrality ratio for each node, select the central node of the box based on the ratio, divide the region, and assign the nodes that meet the conditions to the box; Mark the covered nodes as processed, and among the remaining uncovered nodes, select the node with the smallest quality-to-centrality ratio and exclude it as the center node of the next box; Continue executing the operations of selecting the central node and dividing the boxes until all nodes in the network have been divided, ensuring the integrity of coverage and allocation; Based on the partitioned box node information, the probability changes of each alternative path are evaluated, and potential abnormal fluctuation characteristics in the candidate paths are identified.

8. The method for optimizing the processing of a semiconductor liner according to claim 5, characterized in that, The formula for calculating the anomaly score of the candidate state path is: ； In the formula, S ( P () indicates the anomaly score of the candidate state path; P Indicates the selected state path; P 0 indicates a normal path; ψ a (·) indicates the first (·) a A state feature extraction function; ω a Indicates the first a The weights of each state feature; n This represents the total number of state features.

9. The method for optimizing the processing of semiconductor liners according to claim 1, characterized in that, The process of establishing a dynamic scheduling model based on key factors and using this model to adjust the processing parameters of the semiconductor liner in real time to optimize the processing control strategy includes: Obtain historical processing data samples and assess the sensitivity of key factors by combining them with the error cost function; Based on key factors, a sample subset and a validation set are constructed, and multiple basic decision tree models are trained. The performance of each basic decision tree model is evaluated using the validation set. The scheduling weights of the basic decision tree models are determined based on the classification accuracy. The outputs of each basic decision tree model are then fused to construct a dynamic scheduling model. The constructed dynamic scheduling model is optimized using model optimization algorithms, and the processing parameters of the semiconductor liner are adjusted in real time through the optimized dynamic scheduling model to optimize the processing control strategy.

10. The method for optimizing the processing of a semiconductor liner according to claim 9, characterized in that, The process involves optimizing the constructed dynamic scheduling model using a model optimization algorithm, and then adjusting the processing parameters of the semiconductor liner in real time using the optimized dynamic scheduling model. The optimized processing control strategy includes: Set the parameters of the model optimization algorithm, set the maximum number of iterations, and define the optimization boundary of the process parameters; The performance of the current parameter combination is evaluated using semiconductor process control error as the fitness function. Based on the current iteration progress, update the exploration probability and adjustment intensity of the process parameters; The target process parameters are selected by using a roulette wheel selection mechanism and then fine-tuned to improve the stability and convergence accuracy of process control. If the maximum number of iterations is reached, the target process parameters are output, and the target process parameters are input into the dynamic scheduling model to obtain the optimized dynamic scheduling model. The processing process parameters of the semiconductor liner are adjusted in real time to optimize the processing process control strategy. Otherwise, the optimization continues.

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