Miniaturized low-power-consumption processor board
By integrating the Phytium D2000/8 processor and bridge chip X100, a miniaturized low-power processor board has been developed, solving the problems of large size and high power consumption in traditional computers. This results in a high-performance, low-power processor board suitable for complex application scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-04-07
AI Technical Summary
Traditional computer equipment is large in size and consumes a lot of power, making it difficult to meet the requirements of domestic production, high performance, and high reliability, especially in fields such as military electronics, aerospace, and industrial control.
It adopts the Phytium D2000/8 processor, Phytium bridge chip X100, CPLD, BMC and onboard DDR4 chips. Through precision circuit design and integration technology, it achieves miniaturization and low power consumption, and provides rich computing, storage and I/O expansion functions.
It achieves a miniaturized, low-power processor board that integrates Phytium CPU, memory, network, serial port and other chips, and has display, control, storage and data transmission functions to meet the performance requirements of complex application scenarios.
Smart Images
Figure CN121807115A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of signal processing system technology, specifically relating to a miniaturized, low-power processor board. Background Technology
[0002] With the increasingly severe security challenges and supply chain risks in the global information technology field, the development of domestically produced computers aims to break through foreign technological monopolies and achieve independent control over core technologies. Driven by the national cybersecurity strategy and the demand for domestic substitution of critical information infrastructure, the goal is to build a fully domestically produced system from underlying chips to upper-layer applications by adopting independently developed processors (such as Phytium and Loongson), operating systems, and supporting software and hardware ecosystems. This will free China from dependence on foreign technologies and promote the leapfrog development of the domestic integrated circuit and basic software industries.
[0003] Phytium processors are China's most independently developed CPUs. The D2000 / 8 industrial version processor integrates eight Phytium-developed FTC663 processing cores, adopts the ARM-V8 64-bit architecture, and is a high-performance general-purpose processor for desktop applications. This processor features high performance and low power consumption, and is widely used in high-performance computers and high-end embedded applications.
[0004] Currently, my country's critical information infrastructure sector has an urgent need for independently controllable, high-performance, and highly reliable computing platforms. To address the issues of large size and high power consumption in traditional equipment used in industries such as military electronics, aerospace, and industrial control, and while meeting domestic production requirements, the domestically produced Phytium D2000 / 8 high-performance eight-core processor is adopted. Following internationally accepted miniaturization standards such as 3U VPX, and through precise circuit design and integration technology, rich computing, storage, and I / O expansion functions are highly integrated into a compact board space, enabling stable and reliable operation of the fully domestically produced product in harsh environments. Summary of the Invention
[0005] (a) Technical problems to be solved The technical problem to be solved by this invention is how to provide a miniaturized, low-power processor board to address the issues of large size and high power consumption in traditional computers.
[0006] (II) Technical Solution To solve the above-mentioned technical problems, the present invention proposes a miniaturized low-power processor board, characterized in that the processor board includes: Phytium D2000 / 8 processor, Phytium bridge chip X100, CPLD, BMC and onboard DDR4 chip; The Phytium D2000 / 8 integrates two PCIe 3.0 x16 interfaces. One PCIe x16 interface connects to the VPX connector for flexible expansion as needed. The other PCIe x8 interface connects to the Phytium X100 bridge chip to expand other interfaces, enabling display output and data storage. The Phytium D2000 / 8 connects to NOR Flash via a QSPI interface to store BIOS firmware and to EEPROM via an I2C interface to store system logs. The processor board has external DDR4 memory chips used as data buffers, with two of them being ECC chips. The UART0 and UART1 interfaces on the Phytium D2000 / 8 are converted to RS232 interfaces via an RS232 converter chip. The UART1 interface is a dedicated debugging interface for the CPU, while the UART0 interface is used for data communication and is directly led to the VPX connector. The Phytium X100 bridge chip expands the HDMI display interface through a video conversion chip, with both HDMI display interfaces being brought out to the rear panel. The Phytium D2000 / 8 integrates two RGMII gigabit Ethernet ports, which are converted through a PHY chip; the network card chip is expanded through the bridge chip X100PCIe X2 interface, and two gigabit Ethernet ports are extended, both of which are led to the VPX connector. The Phytium X100 bridge chip provides 4 USB ports. The Phytium X100 bridge chip integrates 8 USB host controllers and supports 8 independent USB 3.1 Gen1 ports. Two of the extended USB ports are led to the front panel for debugging, and the remaining two are led to the VPX connector for connecting USB peripherals. The Phytium D2000 / 8 directly leads one PCIe x8 interface to the VPX connector. This PCIe interface is led to P1 of the VPX connector to expand peripherals that support PCIe interfaces. CPLD is used for level conversion, controlling the power-on sequence of the entire motherboard, and resetting peripherals at all levels; The BMC is used for temperature and voltage monitoring of the processor board. The I2C bus is connected to the VPX connector through a buffer chip, and communicates with other boards through this bus. An external NOR Flash is attached to the BMC chip to store relevant management information.
[0007] (III) Beneficial Effects This invention proposes a miniaturized, low-power processor board that integrates a Phytium CPU, memory, network, serial port, and other chips. The motherboard has a number of reserved interfaces, which can realize functions such as display, control, storage, and external data transmission, and can meet the performance requirements of complex application scenarios. Attached Figure Description
[0008] Figure 1This is a structural diagram of the miniaturized, low-power processor board of the present invention. Detailed Implementation
[0009] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0010] To address the aforementioned issues, this invention provides a miniaturized, low-power processor board based on Phytium. This processor board offers high-bandwidth, high-precision data transmission and reception capabilities, possessing high-performance computing power to meet the high-speed data processing needs of various application scenarios. The board integrates a Phytium D2000 / 8 processor chip, domestically produced DDR4 memory chips, a network card chip, and a serial port chip, among other features. It boasts a rich array of interfaces to meet diverse customer requirements. Furthermore, the processor board includes temperature monitoring, voltage monitoring, and power-on / off control functions. The Phytium D2000 / 8 and bridge-chip architecture computer processor board developed using this invention supports external accelerator cards, storage devices, and various peripherals, adapting to diverse application scenarios.
[0011] To achieve the above functions, the technical solution is as follows: A miniaturized, low-power processor board based on Phytium, with the Phytium D2000 / 8 as its core, is capable of display, control, storage, and external data interface functions. The processor board includes: a Phytium D2000 / 8 processor, a Phytium X100 bridge chip, a CPLD, a BMC, and onboard DDR4 memory chips. The processor board features two 10 / 100 / 1000M adaptive network interfaces, two HDMI interfaces, four USB 2.0 interfaces, three SATA 3.0 interfaces, an RS232 interface, four GPIO ports, two IPMB interfaces, and one PCIe 3.0 x8 interface. The processor board supports temperature and voltage monitoring and uses the CPLD chip for power-on / off management.
[0012] Furthermore, the Phytium D2000 / 8 processor board integrates two PCIe 3.0 x16 interfaces. One PCIe x16 interface connects to the VPX connector, allowing users to flexibly expand as needed. The other PCIe x8 interface connects to the Phytium bridge chip X100 to expand other interfaces, enabling display output and data storage. The Phytium D2000 / 8 connects to NOR Flash via a QSPI interface to store BIOS firmware and to EEPROM via an I2C interface to store system logs. The processor board is externally connected to 18 1GB DDR4 memory chips for data buffering, two of which are ECC chips. The UART0 and UART1 interfaces on the Phytium D2000 / 8 are converted to RS232 interfaces via an RS232 conversion chip. The UART1 interface is a dedicated debugging interface for the CPU, while the UART0 interface is used for data communication and is directly led to the VPX connector.
[0013] Furthermore, the HDMI display interfaces on the processor board are all extended from the Phytium X100 bridge chip through a video conversion chip, with both HDMI display interfaces being led out to the rear panel, and the video memory being 2GB.
[0014] Furthermore, the processor board has two Gigabit Ethernet ports, of which the Phytium D2000 / 8 integrates two RGMII Gigabit Ethernet ports, but these need to be converted out by a PHY chip; the processor board expands the network card chip through the bridge chip X100 PCIe X2 interface, and the two Gigabit Ethernet ports are both led out to the VPX connector.
[0015] Furthermore, the USB interface of the processor board is mainly used to connect peripheral devices that support USB interfaces. The four USB interfaces of the processor board are provided by Phytium X100 bridge chip. The Phytium X100 bridge chip integrates eight USB host controllers and supports eight independent USB 3.1 Gen1 interfaces. Two of the extended USB interfaces are led to the front panel for debugging, and the remaining two are led to the VPX connector for connecting peripherals with USB interfaces.
[0016] Furthermore, the processor board's one PCIe x8 interface is directly led from Phytium D2000 / 8 to the VPX connector. This PCIe interface is led to P1 of the VPX connector to expand peripherals that support PCIE interfaces.
[0017] Furthermore, the processor board also includes a CPLD, which is used for level conversion, controlling the power-on sequence of the entire motherboard, and resetting peripherals at all levels.
[0018] Furthermore, the processor board BMC chip is used for temperature and voltage monitoring of the processor board. The I2C bus is connected to the VPX connector through a buffer chip, and can communicate with other boards through this bus. An external NOR Flash chip is attached to the BMC chip to store relevant management information.
[0019] Furthermore, a temperature sensor is used to monitor the temperature of the processor board, enabling real-time monitoring.
[0020] Example 1: This invention provides a Phytium miniaturized low-power processor board, such as... Figure 1 As shown, the main processor board uses a Phytium CPU processor and provides a Gigabit Ethernet interface, USB interface, UART interface, HDMI display interface, PCIe interface, mSATA interface, RS232 interface, 4 GPIO channels, and IPMB interface for customers to flexibly select according to their needs. The processor board provides status indicator lights, a reset button, and a power button, and also supports temperature and voltage monitoring. It implements power-on and power-off management functions through a CPLD, which can meet the needs of high-bandwidth, high-precision data transmission and reception, and high-speed information processing scenarios.
[0021] The Phytium D2000 / 8 consists of a control unit, a logic unit, and a storage unit, primarily used for processing and calculating externally received data. The Phytium D2000 / 8 integrates eight FTC663 cores with a clock speed of 2.0 GHz. The Phytium D2000 / 8 executes related instructions by reading firmware loaded from NOR Flash. Specifically: The Phytium D2000 / 8 uses QSPI as its sole interface for booting and loading. After booting, the Phytium D2000 / 8 first verifies the external firmware through the on-chip root of trust. After successful verification, it loads the firmware using the NOR Flash selected by QSPI_CS0 to execute relevant instructions. The NOR Flash model used is FM25Q128A-SOB-UG. The Phytium D2000 / 8 supports an external high-capacity storage DDR controller and DDR PHY. Its main function is to manage the entire chip's storage space. The high-capacity storage DDR controller has 36 DDR4 chips mounted on it, each with a capacity of 1GB and a maximum data transfer rate of 2666Mb / s. The DDR4 chips are Changxin Memory CXDQ3A8AM-IJ-A, placed on two channels, with 18 DDR4 chips on each channel, used as data cache.
[0022] The Phytium D2000 / 8 integrates two RGMII gigabit network interfaces, supporting 10 / 100 / 1000Mbps auto-sensing. These interfaces are brought out as general-purpose network interfaces via the YT8521SH-CA PHY chip, connecting to an RJ45 connector on the front panel. An AT3232EESE+ RS232 chip converts UART signals to RS232 signals for output. The two UART interfaces and one PCIe x8 interface on the Phytium D2000 / 8 connect to VPX connectors P1 and P2, serving as communication interfaces with other boards. The Phytium D2000 / 8 connects to the X100 bridge chip via a PCIe x8 interface to expand the CPU's I / O interfaces.
[0023] The I / O expansion bridge uses the Phytium X100 bridge chip, which is a matching bridge chip for Phytium processors. The X100 bridge chip integrates a low-power GPU with a clock speed of 800MHz, a peak single-precision floating-point computing power of 400GFLOPS, a maximum pixel fill rate of 6.4GPixel / s, and a maximum texture fill rate of 12.8GTexture / s. The X100 bridge chip connects to four external DDR memory chips, specifically the Changxin CXDQ3BFAM-WG DDR4 model. This chip has a 16-bit bus width, a single-chip capacity of 1GB, and supports a maximum data transfer rate of 2666Mb / s. The X100 bridge chip also connects to an external FLASH chip to store the boot firmware. The FLASH memory chip used is the FM25Q128A-SOB-UG, with a capacity of 128MB. The X100 bridge chip directly outputs five USB ports, one to the front panel and four to the VPX connector P2, for expanding USB interface devices. The X100 bridge chip connects to two external video conversion chips, converting the two DP signals from the X100 bridge chip to HDMI signals, and outputting the HDMI display signal to VPX connector P2. The X100 bridge chip also connects to one mSATA interface for connecting an expanded SSD to store user data; the two SATA interfaces of the X100 connect to the VPX connector. The X100 bridge chip's PCIe x2 interface connects to a WX1860 network card chip, outputting two Gigabit Ethernet ports to VPX connector P1, enabling network communication between the motherboard and other expansion cards.
[0024] The HDMI interface is mainly used for system display output. The HDMI signal is provided by the X100 bridge chip DP interface to HDMI interface chip, which is the LT8712X chip from Longxun Semiconductor.
[0025] The MCU chip used in the BMC is a GD32F103VBT6, which is used for monitoring the temperature and voltage of the board. The IPMB bus is connected to the VPX connector P0 through the buffer chip AT4300A, and the information of this board is reported to the host system through this bus.
[0026] The main function of the CPLD is to perform level conversion and control the CPU power-on timing. The CPLD chip selected is the EF2L45BG256I7 from Shanghai Anlu Information Technology Co., Ltd., which has 207 user I / O interfaces.
[0027] The front panel power indicator light is a green dual-row straight connector, using the YZ-CDR03-2G from China Zhenhua Group Yongguang Electronics Co., Ltd., used to indicate the motherboard power supply status.
[0028] The front panel reset button is the KAQ-66L9 from Beijing Yuanjiu Xingda Co., Ltd., which provides restart and system reset functions for the board.
[0029] The voltage monitoring module includes a voltage monitoring chip connected to the MCU. The voltage monitoring chip is the LINEAR LTC2991, which supports monitoring up to 8 voltage channels.
[0030] The temperature management utilizes a temperature sensor to monitor the temperature of the board. The temperature sensor is a JSD18B20S from the 58th Research Institute of China Electronics Technology Group Corporation, which is connected to the MCU to achieve real-time monitoring of the board temperature.
[0031] The beneficial effects of this invention: This invention provides a Phytium miniaturized low-power processor board, which integrates Phytium CPU, memory, network, serial port and other chips. The motherboard has a lot of reserved interfaces, which can realize display, control, storage and external data transmission functions, and can meet the performance requirements of complex application scenarios.
[0032] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A miniaturized, low-power processor board, characterized in that, The processor board includes: Phytium D2000 / 8 processor, Phytium bridge chip X100, CPLD, BMC and onboard DDR4 chips; The Phytium D2000 / 8 integrates two PCIe 3.0 x16 interfaces. One PCIe x16 interface connects to the VPX connector for flexible expansion as needed. The other PCIe x8 interface connects to the Phytium X100 bridge chip to expand other interfaces, enabling display output and data storage. The Phytium D2000 / 8 connects to NOR Flash via a QSPI interface to store BIOS firmware and to EEPROM via an I2C interface to store system logs. The processor board has external DDR4 memory chips used as data buffers, with two of them being ECC chips. The UART0 and UART1 interfaces on the Phytium D2000 / 8 are converted to RS232 interfaces via an RS232 converter chip. The UART1 interface is a dedicated debugging interface for the CPU, while the UART0 interface is used for data communication and is directly led to the VPX connector. The Phytium X100 bridge chip expands the HDMI display interface through a video conversion chip, with both HDMI display interfaces being brought out to the rear panel. The Phytium D2000 / 8 integrates two RGMII gigabit Ethernet ports, which are converted through a PHY chip; the network card chip is expanded through the bridge chip X100 PCIeX2 interface, and two gigabit Ethernet ports are extended, both of which are led to the VPX connector. The Phytium X100 bridge chip provides 4 USB ports. The Phytium X100 bridge chip integrates 8 USB host controllers and supports 8 independent USB 3.1 Gen1 ports. Two of the extended USB ports are led to the front panel for debugging, and the remaining two are led to the VPX connector for connecting USB peripherals. The Phytium D2000 / 8 directly leads one PCIe x8 interface to the VPX connector. This PCIe interface is led to P1 of the VPX connector to expand peripherals that support PCIe interfaces. CPLD is used for level conversion, controlling the power-on sequence of the entire motherboard, and resetting peripherals at all levels; The BMC is used for temperature and voltage monitoring of the processor board. The I2C bus is connected to the VPX connector through a buffer chip, and communicates with other boards through this bus. An external NOR Flash is attached to the BMC chip to store relevant management information.
2. The miniaturized, low-power processor board as described in claim 1, characterized in that, The processor board has two 10 / 100 / 1000M adaptive network interfaces, two HDMI interfaces, four USB 2.0 interfaces, three SATA 3.0 interfaces, an RS232 interface, four GPIOs, two IPMB interfaces, and one PCIe 3.0 x8 interface. The processor board supports temperature and voltage monitoring and implements power-on / off management functions through a CPLD chip.
3. The miniaturized, low-power processor board as described in claim 1, characterized in that, The processor board provides status indicator lights, a reset button, and a power button. It also supports temperature and voltage monitoring and uses a CPLD to manage power-on and power-off functions.
4. The miniaturized, low-power processor board as described in claim 1, characterized in that, The Phytium D2000 / 8 consists of a control unit, a logic unit, and a storage unit, used to process and operate on externally received data. The Phytium D2000 / 8 integrates eight FTC663 cores with a main frequency of 2.0GHz. The Phytium D2000 / 8 executes relevant instruction operations by reading firmware loaded from NOR Flash.
5. The miniaturized, low-power processor board as described in claim 4, characterized in that, The Phytium D2000 / 8 uses QSPI as its sole interface for booting and loading. After booting, the Phytium D2000 / 8 first verifies the external firmware through the on-chip root of trust. Once verification is successful, it loads the firmware from the NOR Flash selected by QSPI_CS0 to execute relevant instructions. The NOR Flash model used is FM25Q128A-SOB-UG. The Phytium D2000 / 8 supports an off-chip high-capacity DDR controller and DDR PHY, which manage the entire chip's storage space. The high-capacity DDR controller has 36 DDR4 chips mounted on it, each with a capacity of 1GB and a maximum data transfer rate of 2666Mb / s. The DDR4 chips are model CXDQ3A8AM-IJ-A, and are placed on two channels, with 18 DDR4 chips on each channel, used as data cache.
6. The miniaturized, low-power processor board as described in claim 4, characterized in that, The Phytium D2000 / 8 integrates two RGMII gigabit network interfaces, supporting 10 / 100 / 1000Mbps auto-negotiation. These interfaces are brought out as general-purpose network interfaces via the PHY chip YT8521SH-CA, connecting to an RJ45 connector on the front panel. The RS232 chip uses the AT3232EESE+ to convert UART signals into RS232 signals for external output. The Phytium D2000 / 8 has two UART interfaces and one PCIe x8 interface connected to VPX connectors P1 and P2, serving as communication interfaces between this board and other boards. The Phytium D2000 / 8 connects to the X100 bridge chip via one PCIe x8 interface to expand the CPU's I / O interfaces.
7. The miniaturized, low-power processor board as described in claim 1, characterized in that, The X100 bridge chip connects to four external DDR4 memory chips (model CXDQ3BFAM-WG). It also connects to an external FLASH chip (FM25Q128A-SOB-UG) to store the boot firmware. The X100 bridge chip directly outputs five USB ports, one to the front panel and four to VPX connector P2 for expanding USB connectivity. Two external video converter chips convert the X100 bridge chip's two DP signals to HDMI signals, outputting the HDMI display signal to VPX connector P2. The X100 bridge chip connects to one mSATA interface for connecting an SSD to store user data, and its two SATA interfaces connect to the VPX connector. Finally, the X100 bridge chip's PCIe x2 interface connects to a WX1860 network card chip, outputting two Gigabit Ethernet ports to VPX connector P1 for network communication between the motherboard and other expansion cards.
8. The miniaturized, low-power processor board as described in claim 1, characterized in that, The HDMI interface is used for system display output. The HDMI signal is provided by the X100 bridge chip DP interface to HDMI interface chip, which is model LT8712X chip.
9. The miniaturized, low-power processor board as described in claim 1, characterized in that, The BMC uses a GD32F103VBT6 MCU chip for monitoring the board's temperature and voltage. The IPMB bus is connected to the VPX connector P0 via a buffer chip AT4300A, through which information from this board is reported to the host system. The voltage monitoring chip is an LTC2991, which supports monitoring up to 8 voltage channels. Temperature management utilizes a JSD18B20S temperature sensor connected to the MCU to monitor the board's temperature in real time.
10. The miniaturized, low-power processor board as described in claim 1, characterized in that, The CPLD is used for level conversion and controlling the CPU power-on timing. The CPLD chip selected is EF2L45BG256I7, which has 207 user I / O interfaces.