Memory data line training method, memory controller, processor and equipment

Abstract

The invention relates to a memory data line training method, a memory controller, a processor and electronic equipment, and belongs to the field of electronic circuits. The method comprises the steps that a two-dimensional eye pattern corresponding to a target data line of the memory is acquired, the two-dimensional eye pattern comprises a plurality of test points located in a two-dimensional space formed by a voltage dimension and a time delay dimension, and each test point corresponds to a combination of a voltage value and a transmission time delay value; determining the center of mass of the two-dimensional eye diagram; and based on the coordinates of the centroid in the voltage dimension and the time delay dimension, determining a reference voltage configuration value and a transmission time delay configuration value corresponding to the target data line. By introducing the centroid algorithm in mathematics, automatic selection of the optimal equilibrium point of the eye pattern is realized, the centroid reflects the equilibrium center of the effective area of the eye pattern in geometric and physical distribution, and the centroid is taken as the sampling center point, so that natural equilibrium between the time domain and the voltage domain can be realized; therefore, the influence of external interference on the eye pattern shape is reduced to the minimum.

Description

Technical Field

[0001] This application belongs to the field of electronic circuits, and specifically relates to a training method for memory data lines, a memory controller, a processor, and an electronic device. Background Technology

[0002] With the iteration of Double Data Rate (DDR) memory technology, data transfer rates have significantly improved, for example, from 800MT / s (millions of transfers per second) in DDR2 to 8800MT / s and even higher in DDR5. The bandwidth and capacity of memory systems have also continuously increased. As a core storage peripheral for the processor, each channel of the DDR subsystem typically supports multiple memory ranks. Signal crosstalk exists between different ranks. Combined with factors such as motherboard routing differences, Dual In-line Memory Module (DIMM) compatibility, and power supply noise, signal integrity (SI) issues are becoming increasingly prominent. Especially under high load and high frequency scenarios, the eye diagram of the data queue (DQ) is easily interfered with, exhibiting irregular, non-standard, and complex shapes. This places higher demands on the accurate selection of eye diagram points during read / write training.

[0003] During memory initialization, the timing and voltage reference for data sampling need to be optimized through training. Two-dimensional training requires determining the optimal point for each data line in a two-dimensional space comprised of the voltage domain (reference voltage VREFDQ) and the time domain (sampling delay) to ensure sufficient timing margin and voltage noise tolerance in the sampling window. Traditional point selection algorithms primarily rely on embedding pre-defined regular shapes (such as inscribed circles or rhombuses) within the acquired eye diagram and selecting points within these shapes. For example, one common method is to embed a parameterizable rhombus mask in the eye diagram, adjusting the rhombus shape to balance the biases in the time and voltage domains. However, when the eye diagram is severely irregular, this method still struggles to select the optimal balance, posing a risk of decreased memory system stability due to point selection deviations. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a training method for memory data lines, a memory controller, a processor, and an electronic device to improve the reliability and robustness of memory systems in complex environments.

[0005] The embodiments of this application are implemented as follows: In a first aspect, embodiments of this application provide a training method for a memory data line, comprising: acquiring a two-dimensional eye diagram corresponding to a target data line of the memory, wherein the two-dimensional eye diagram includes multiple test points located in a two-dimensional space composed of a voltage dimension and a delay dimension, each test point corresponding to a combination of a voltage value and a transmission delay value; determining the centroid of the two-dimensional eye diagram; and determining a reference voltage configuration value and a transmission delay configuration value corresponding to the target data line based on the coordinates of the centroid in the voltage dimension and the delay dimension.

[0006] In the above implementation scheme, this application introduces the centroid algorithm from mathematics to automatically select the optimal equilibrium point of the eye diagram. Since the centroid reflects the balance center of the effective region of the eye diagram in terms of geometry and physical distribution, using it as the sampling center point can achieve a natural balance between the time domain and the voltage domain, thereby minimizing the impact of external interference on the shape of the eye diagram. In addition, the processing flow of this application is simple and clear, without relying on empirical configurations such as preset graphics in traditional methods, which significantly reduces the complexity and uncertainty of the specific implementation. At the same time, the center point selected based on the centroid algorithm has good scene adaptability and robustness, and can cope with various regular and irregular eye diagrams, ensuring that the memory system maintains sufficient timing and voltage margins under changes in voltage, temperature and signal integrity, thereby improving the overall working stability and reliability of the memory system.

[0007] In one possible implementation of the first aspect embodiment, determining the centroid of the two-dimensional eye diagram includes: determining the geometric centroid of the two-dimensional eye diagram based on the spatial distribution of all test points in the two-dimensional eye diagram; and using the geometric centroid as the centroid of the two-dimensional eye diagram.

[0008] In the above implementation scheme, since the geometric centroid is essentially the "balance center" of all points in the eye diagram, it is automatically calculated from the global distribution of the eye diagram to find the most balanced center point in the time domain (X-axis) and voltage domain (Y-axis). This ensures that the sampling points have the maximum time margin and voltage noise tolerance at the same time, thereby improving the robustness of the signal from the root.

[0009] In one possible implementation of the first aspect embodiment, determining the geometric centroid of the two-dimensional eye diagram includes: determining the total area of ​​the two-dimensional eye diagram; determining the first product of the time delay coordinate value of each test point in the two-dimensional eye diagram and the unit area represented by the test point, and summing the first products of all test points to obtain a first summation value; determining the second product of the voltage coordinate value of each test point in the two-dimensional eye diagram and the unit area represented by the test point, and summing the second products of all test points to obtain a second summation value; determining the quotient of the first summation value and the total area to obtain the time delay coordinate of the geometric centroid; and determining the quotient of the second summation value and the total area to obtain the voltage coordinate of the geometric centroid.

[0010] In the above implementation scheme, by introducing a mathematical centroid calculation formula, this embodiment can adaptively determine the optimal equilibrium center of the eye diagram. Specifically, referring to the centroid calculation formula for planar graphics and adapting it to a two-dimensional eye diagram scenario composed of discrete test points, the total area A of the two-dimensional eye diagram can be calculated using the formula ∑(R.Δx.Δy). If the first summation value is represented by B, then B=∑(RxΔx.Δy), and the second summation value is represented by C, then C=∑(RyΔx.Δy). Finally, the centroid abscissa X=B / A=∑(RxΔx.Δy) / A; the centroid ordinate Y=C / A=∑(RyΔx.Δy) / A, where R is the weight of each test point, Δx... Δy represents the unit area represented by the test point, where Δx and Δy are the scan step sizes in the time delay direction and voltage direction, respectively. If the step size is uniform and normalized, it can be considered as Δx.Δy=1; x and y are the time delay coordinates and voltage coordinates of the test point in two-dimensional space, respectively. In a preferred embodiment, if the scan step size is set to be uniform and the weight R of each test point is the same, the above calculation is simplified to calculating the arithmetic mean of the coordinates of all points passed through, achieving simplicity and efficiency. It can be understood that the above formula framework is also applicable to scenarios with other scan step sizes or weight settings.

[0011] In one possible implementation of the first aspect embodiment, when the unit areas represented by the test points in the two-dimensional eye diagram are equal, the time delay coordinate of the centroid is the average of the time delay coordinate values ​​of all test points in the two-dimensional eye diagram; the voltage coordinate of the centroid is the average of the voltage coordinate values ​​of all test points in the two-dimensional eye diagram.

[0012] In the above implementation scheme, when the unit area represented by the test points in the two-dimensional eye diagram is equal, the calculation process of the time delay coordinate of the centroid can be simplified to obtaining the average value of the time delay coordinate of all test points in the two-dimensional eye diagram, and the calculation process of the voltage coordinate of the centroid can be simplified to obtaining the average value of the voltage coordinate of all test points in the two-dimensional eye diagram. In this way, a balance point that takes into account both time margin and voltage noise tolerance can be obtained quickly.

[0013] In one possible implementation of the first aspect embodiment, obtaining the two-dimensional eye diagram corresponding to the target data line of the memory includes: performing a two-dimensional scan test on the target data line within a preset voltage range and a preset delay range; recording the test results of test points that combine each voltage value within the preset voltage range with each transmission delay value within the preset delay range, the test results including test pass or test failure; and obtaining the two-dimensional eye diagram corresponding to the target data line based on the region formed by all the test points that passed the test.

[0014] In the above implementation scheme, a two-dimensional scan test is performed on the target data line within a preset voltage range and a preset time delay range. The test results of the test points are combined with each voltage value within the preset voltage range and each transmission delay value within the preset time delay range. Finally, a two-dimensional eye diagram corresponding to the target data line is obtained based on the area formed by all the test points that have passed the test. Since the test covers the entire preset parameter space and the scan grid is dense and complete, it ensures that the two-dimensional eye diagram can accurately and completely reflect all possible stable operating areas of the data line in the time domain and voltage domain.

[0015] In one possible implementation of the first aspect embodiment, the target data line is a data line of the memory's storage rank; the method further includes: sequentially performing the above-described steps of obtaining a two-dimensional eye diagram, determining the centroid, and determining the configuration value on each data line of the memory's rank.

[0016] In the above implementation scheme, when the memory contains multiple independent Ranks, the data lines of each Rank of the memory need to be trained independently. The training process of the data lines of each Rank is consistent, all involving the steps of obtaining the two-dimensional eye diagram, determining the centroid, and determining the configuration value. This allows for precise optimization based on the unique physical location and signal integrity characteristics of each Rank.

[0017] In one possible implementation of the first aspect embodiment, the method further includes: configuring the delay parameter of the transmission link where the target data line is located in the physical layer interface of the memory controller according to the transmission delay configuration value; configuring the reference voltage of the physical layer interface corresponding to the target data line in the memory controller according to the reference voltage configuration value, or configuring the reference voltage of the memory chip corresponding to the target data line in the memory.

[0018] In the above implementation scheme, after determining the reference voltage configuration value and transmission delay configuration value corresponding to the target data line, the delay parameter of the transmission link where the target data line is located in the physical layer interface of the memory controller is configured according to the transmission delay configuration value, and the reference voltage of the physical layer interface corresponding to the target data line in the memory controller is configured according to the reference voltage configuration value, or the reference voltage of the memory chip corresponding to the target data line in the memory is configured. In this way, the theoretical optimal value calculated by the algorithm can be accurately and completely mapped and applied to the actual physical hardware, thereby forming a complete technical closed loop from "algorithm analysis" to "hardware parameter configuration", ultimately ensuring the long-term stability and high reliability of the overall operation of the storage system.

[0019] In one possible implementation of the first aspect embodiment, the memory is a double data rate synchronous dynamic random access memory.

[0020] In the above implementation scheme, taking the current mainstream DDR memory as the application object, the center point selected by the centroid algorithm proposed in this application can ensure that the memory system can maintain sufficient timing margin and voltage noise tolerance under various actual working conditions such as voltage fluctuations, temperature changes and dynamic degradation of signal integrity. This significantly improves the memory system's tolerance to external environment and its own aging, and ultimately ensures the long-term stability and high reliability of the overall operation of the memory system.

[0021] Secondly, embodiments of this application also provide a memory controller, including: a control and processing module, configured to acquire a two-dimensional eye diagram corresponding to a target data line of the memory, wherein the two-dimensional eye diagram includes multiple test points located in a two-dimensional space composed of a voltage dimension and a delay dimension, each test point corresponding to a combination of a voltage value and a transmission delay value; determine the centroid of the two-dimensional eye diagram; and determine a reference voltage configuration value and a transmission delay configuration value corresponding to the target data line based on the coordinates of the centroid in the voltage dimension and the delay dimension.

[0022] In one possible implementation of the second aspect embodiment, the memory controller further includes: a delay adjustment module and a voltage adjustment module; wherein, the delay adjustment module is located on the transmission link where the target data line is located, and is used to adjust the delay of the target data line; the voltage adjustment module is used to adjust the reference voltage of the physical layer interface corresponding to the target data line in the memory controller; the control and processing module is specifically used to: control the delay adjustment module to adjust the delay of the target data line, and control the voltage adjustment module to adjust the reference voltage of the physical layer interface corresponding to the target data line; perform a two-dimensional scan test on the target data line within a preset voltage range and a preset delay range; record the test results of test points combining each voltage value within the preset voltage range and each transmission delay value within the preset delay range, the test results including test pass or test failure; and obtain a two-dimensional eye diagram corresponding to the target data line based on the region formed by all the test points that passed the test.

[0023] Thirdly, embodiments of this application also provide a processor, including: a processor core and a memory controller provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments; the processor core is configured to send training instructions to the memory controller; the memory controller is configured to execute a training method for memory data lines in response to the training instructions.

[0024] Fourthly, embodiments of this application also provide an electronic device, including: a memory and a processor as provided in the third aspect of the embodiments above, wherein the memory is connected to a memory controller in the processor.

[0025] Fifthly, embodiments of this application also provide an electronic device, including: a processor, a memory, and a memory controller as provided in any possible implementation of the second aspect embodiments and / or in combination with the second aspect embodiments, wherein the memory controller is connected to the processor and the memory respectively; the processor is configured to send training instructions to the memory controller; and the memory controller is configured to execute a training method for the memory data line in response to the training instructions.

[0026] The technical effects of any of the implementation methods in the second to fifth aspects can be referred to the technical effects of the same or similar implementation methods in the first aspect, and will not be repeated here.

[0027] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.

[0029] Figure 1 This illustration shows a connection diagram of a CPU and a memory module on a motherboard according to an embodiment of this application.

[0030] Figure 2 This illustration shows a schematic diagram of the connection between a PHY and a DDR memory according to an embodiment of this application.

[0031] Figure 3 A flowchart illustrating a training method for a memory data line provided in an embodiment of this application is shown.

[0032] Figure 4 This illustration shows a schematic diagram of a relatively regular DQ read direction eye diagram provided in an embodiment of this application.

[0033] Figure 5 A schematic diagram of a first irregular eye diagram provided in an embodiment of this application is shown.

[0034] Figure 6 A schematic diagram of a second irregular eye diagram provided in an embodiment of this application is shown.

[0035] Figure 7A schematic diagram of a third irregular eye diagram provided in an embodiment of this application is shown.

[0036] Figure 8 The diagram illustrates the principle of a training method for a memory data line provided in an embodiment of this application.

[0037] Figure 9 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.

[0039] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0040] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0041] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.

[0042] Given that existing technologies struggle to select the optimal balance point when the data line eye diagram exhibits an irregular shape due to signal integrity degradation, the selected center point is prone to bias towards one direction in the time or voltage domain, leading to a reduction in noise margin in the other direction. This poses a risk of decreased memory system stability due to point selection bias, thereby affecting the long-term operational stability of the memory system. Therefore, this application provides a point selection algorithm that is independent of preset patterns, adapts to the eye diagram shape, and balances timing and voltage margins, thereby improving the reliability and robustness of multi-rank, high-data-rate memory systems in complex environments.

[0043] For ease of explanation, this application uses Double Data Rate (DDR) Synchronous Dynamic Random Access Memory, i.e., DDR memory, as an example. It is understood that the memory used in this application includes, but is not limited to, DDR memory, and the method shown in this application can be applied to various memories that interact with the memory controller based on DQS clock signals and DQ data signals. The DQS clock signal and DQ data signal are interaction signals between the memory and the memory controller. The DQS clock signal is the data sampling clock signal between the memory controller and the memory, used to sample the data transmitted by the DQ data signal. The DQ data signal serves as the data transmission carrier, used to transmit the actual data content.

[0044] As a critical peripheral component of processors (such as CPUs), DDR memory's data line eye diagrams are prone to irregular and complex shapes due to signal integrity degradation. This places higher demands on the accurate selection of eye diagram points during read / write training. This issue is closely related to the physical structure of the DDR link: the complete signal path is long, including not only the CPU's internal traces but also motherboard traces, DIMM gold fingers, the DIMM module itself, and the DRAM (Dynamic Random Access Memory) chips on it. Figure 2 As shown, the memory module connects to the memory slot on the motherboard via gold fingers, and the memory module itself consists of a DIMM module and the DRAM chips it carries. Furthermore, factors such as power supply quality can further affect the shape of the eye diagram. The PHY can be integrated into the memory controller, and the PHY and the memory interface of the memory module interact via the DQS clock signal and the DQ data signal.

[0045] Typically, a single memory module can support one or more memory ranks, and a rank is a collection of DRAM chips that provide a 64-bit data width. For example, if a DRAM chip has a data width of 4 bits (x4), then a rank contains 16 DRAM chips; if a DRAM chip has a data width of 8 bits (x8), then a rank contains 8 DRAM chips. All chips within the same rank share the same control signals, such as being controlled by the same chip select signal (CS), and are simultaneously selected to work together.

[0046] Each Rank is a logically and electrically independent working unit. The memory controller activates the target Rank through an independent chip select (CS) signal, thereby enabling communication with a specific Rank. During read / write training, the memory controller uses this mechanism to sequentially select and activate each Rank and train the data lines of that Rank.

[0047] The connection diagram between the physical layer interface (PHY) and the DDR memory is shown below. Figure 2 As shown, OB (Output Buffer) is the output driver for the chip select signal CS and the command signal CA, while IB (Input Buffer) is the receiver for the CS signal and CA command in the DDR memory. The DDR memory determines the read / write direction by parsing the CA command to control the I / O (Input / Output) modules. When the CA command is a read command, the I / O modules on the DDR memory side are configured in output drive mode, and the I / O modules on the PHY side are configured in input mode. The DDR memory sends the DQS clock signal and DQ data signal to the PHY. When the CA command is a write command, the I / O modules on the DDR memory side are configured in input mode, and the I / O modules on the PHY side are configured in output drive mode. The DDR memory receives the DQS clock signal and DQ data signal from the PHY.

[0048] Figure 2 The diagram only shows the signal flow when the CA command is a read command. The DQ data signal enters the PHY, passes through the delay adjustment module S01, and is then sent to the data sampler S03 on the DQ link. The DQS clock signal enters the PHY, passes through the delay adjustment module S02, and is then sent to the data sampler S03 on the DQ link to sample data. Because the delays of modules S01 and S02 affect whether DQ data can be sampled correctly, training is required (the purpose of training is to adjust the phase of DQS or DQ to ensure that DQS can stably sample the correct DQ data).

[0049] In the following example, this application uses adjusting the delay of the S01 module to optimize the DQ data signal of the memory as an example for illustration. The following is combined with... Figure 3The training method for memory data lines provided in the embodiments of this application will be described, and the method can be applied to memory controllers.

[0050] S1: Obtain the two-dimensional eye diagram corresponding to the target data line of the memory.

[0051] The two-dimensional eye diagram includes multiple test points located in a two-dimensional space consisting of the voltage dimension (Vref, i.e., the dimension where the voltage domain is located) and the time delay dimension (Delay, i.e., the dimension where the time domain is located). Each test point corresponds to a combination of a voltage value and a transmission delay value.

[0052] The target data line is the data line of the memory's storage rank. When the memory includes multiple storage ranks, the target data line can be the data line of the rank that needs to be trained. The rank that needs to be trained can be selected by the chip select signal CS.

[0053] In some possible implementations, the two-dimensional eye diagram corresponding to the target data line of the acquired memory may be a relatively regular eye diagram, such as... Figure 4 The image shown is a relatively regular eye diagram for DQ read directions. For Figure 4 The relatively regular eye diagram shown can be optimized using conventional point selection methods (such as center point selection) to ensure that the sampling window has sufficient timing margin and voltage noise tolerance.

[0054] In some other possible implementations, the two-dimensional eye diagram corresponding to the target data line of the acquired memory may be an irregular eye diagram, such as... Figure 5 , Figure 6 As shown. For Figure 5 or Figure 6 The irregular eye diagram shown makes it difficult to select the optimal balance point using the conventional center point selection method.

[0055] In some possible implementations, the two-dimensional eye diagram corresponding to the target data line of the memory can be obtained from a database or storage device, and this two-dimensional eye diagram has been tested and saved in advance.

[0056] In some possible implementations, the process of obtaining a two-dimensional eye diagram corresponding to the target data line of the memory may include: firstly, performing a two-dimensional scan test on the target data line within a preset voltage range (e.g., DDQ / 2~VDDQ) and a preset delay range (e.g., 0UI~4UI (UnitInterval)). During the two-dimensional scan test, the voltage value and transmission delay value of each test point are within the aforementioned preset voltage range and preset delay range. The voltage value and transmission delay value can be gradually increased (or decreased) according to a preset step size to perform the scan test until the combination test of each voltage value and transmission delay value is completed; then, recording the test results of each test point combining each voltage value within the preset voltage range and each transmission delay value within the preset delay range, including test pass or test fail; finally, obtaining the two-dimensional eye diagram corresponding to the target data line based on the area formed by all the test points that passed the test.

[0057] The transmission delay of DQ data can be changed by adjusting the delay parameter of the delay adjustment module connected to the target data line in the physical layer interface of the memory controller. The transmission performance of DQ data can be affected by adjusting the reference voltage of the physical layer interface corresponding to the target data line in the memory controller. When adjusting the reference voltage, it can be adjusted at fixed intervals within a preset voltage range. Similarly, when adjusting the transmission delay, it can be adjusted at fixed intervals within a preset delay range.

[0058] When performing a scan test on the memory data lines, you can first write specified data to the memory, and then read it out and compare it with the written specified data. If they match, the test passes; if they do not match, the test fails.

[0059] In one possible implementation, combined with Figure 7 Taking the acquisition of a two-dimensional eye diagram of the data line DQ0 (target data line) in DDR5 as an example, the shaded area in the diagram is the Pass area, and the area outside the shaded area is the Fail area. The test points in the Pass area are the test points that have passed the test, while the test points in the Fail area are the test points that have failed the test.

[0060] In some implementations, before performing a two-dimensional scan test on the target data line within a preset voltage range and a preset time delay range, a basic training process for the memory (i.e., one-dimensional read / write training) needs to be completed first. After completing the basic one-dimensional read / write training, two-dimensional read / write training is then performed. During the one-dimensional read / write training, optimization is mainly focused on the time domain, while the voltage domain remains unadjusted. For example, the reference voltage of the data line received by the memory controller is maintained at a preset initial voltage value (e.g., 750mV) and is not adjusted temporarily. Instead, the delay adjustment module used for sampling the data line is fine-tuned in the time domain (i.e.,...). Figure 2 The S02 module in the middle) and the delay adjustment module connected to the data line for fine-tuning (i.e. Figure 2 (S01 module in the memory). At each set delay point, the memory controller performs write and read tests on the memory to determine whether the data can be correctly sampled. By scanning, a delay interval is found. If both read and write tests pass within this interval, a center point or optimal position is selected from this interval, and its corresponding delay is configured as the working parameter of the delay adjustment module (S01 module or S02 module).

[0061] Next, two-dimensional training is performed to simultaneously optimize the voltage and time domains, thereby determining the optimal sampling point on the voltage-time delay two-dimensional plane. During two-dimensional training, scanning is required in both the voltage and time domains.

[0062] Voltage domain: On the voltage axis, scanning is performed in a certain step (e.g., 0.01VDDQ) within a preset voltage range (e.g., from VDDQ / 2 to VDDQ).

[0063] Temporal domain: On the time axis, scanning is performed in increments (e.g., 0.1 UI) within a preset time delay range (e.g., 0 to 4 UI). This preset time delay range covers the delay corresponding to the center point or optimal position selected during the one-dimensional training mentioned above.

[0064] For each individual data line, the memory controller iterates through all combinations of the voltage and delay mentioned above, forming a two-dimensional test matrix. At each point (voltage, delay), a complete write and read test is performed. The result of the test at each coordinate point is recorded as "Pass" or "Fail". Then, based on the positions of all "Pass" points in the voltage-delay coordinate system, the two-dimensional eye diagram of the data line is determined.

[0065] S2: Determine the centroid of the two-dimensional eye diagram.

[0066] When determining the centroid of a two-dimensional eye diagram, the geometric centroid of the two-dimensional eye diagram can be determined based on the spatial distribution of all test points in the two-dimensional eye diagram; the geometric centroid is then used as the centroid of the two-dimensional eye diagram.

[0067] When determining the geometric centroid of a two-dimensional eye diagram, the formula for calculating the centroid of a planar figure can be used as a reference: ; In this equation, A represents the total area of ​​the planar figure, dA represents the area of ​​any infinitesimal element within the planar figure, with coordinates (x, y), xc being the abscissa of the centroid, and yc being the ordinate of the centroid. The total area of ​​the planar figure can be considered as the sum of the areas of multiple infinitesimal elements. For irregular planar figures, they can be transformed into a series of tiny parts that can be approximated as regular figures through "segmentation," and the total area of ​​the figure can be obtained by summing the areas of all these tiny parts.

[0068] Referring to the centroid calculation formula above, the process of determining the geometric centroid of a two-dimensional eye diagram may include: determining the total area A of the two-dimensional eye diagram, which can be calculated using the formula ∑(R.Δx.Δy); determining the first product of the time delay coordinate value of each test point within the two-dimensional eye diagram and the unit area represented by that test point, and summing the first products of all test points to obtain the first summation value (if the first summation value is denoted by B), i.e., B=∑(RxΔx.Δy); determining the voltage coordinate value of each test point within the two-dimensional eye diagram and the unit area represented by that test point. The second product per unit area is calculated, and the second product is summed over all test points to obtain the second summation value (denoted as C), i.e., C = ∑(RyΔx.Δy). The quotient of the first summation value and the total area is used to obtain the time delay coordinate of the geometric centroid (i.e., the centroid's abscissa X); the quotient of the second summation value and the total area is used to obtain the voltage coordinate of the geometric centroid (i.e., the centroid's ordinate Y). Therefore, the centroid's abscissa X = B / A = ∑(RxΔx.Δy) / A; the centroid's ordinate Y = C / A = ∑(RyΔx.Δy) / A.

[0069] Where R is the weight of each test point. In the eye diagram scenario, the weight of the Pass region (Pass point) is usually set to 1 (the weights of different test points in the Pass region can also be different; this example only uses the case where the weights are the same), and the weight of the Fail region (Fail point) is set to 0. Δx.Δy represents the unit area represented by the test point, and Δx and Δy are the scan step sizes in the time delay direction and voltage direction, respectively. If the step size is uniform and normalized, it can be regarded as Δx.Δy=1; x and y are the time delay coordinates and voltage coordinates of the test point in two-dimensional space, respectively.

[0070] In some possible implementations, when the unit areas represented by the test points in the two-dimensional eye diagram are equal, the time delay coordinate of the centroid is the average of the time delay coordinate values ​​of all test points within the two-dimensional eye diagram; the voltage coordinate of the centroid is the average of the voltage coordinate values ​​of all test points within the two-dimensional eye diagram. In this implementation, the process of determining the geometric centroid of the two-dimensional eye diagram can be as follows: add the voltage coordinate values ​​of all points passing through it, then divide by the total number of points passing through it to obtain the average value in the voltage direction; add the time delay coordinate values ​​of all points passing through it, then divide by the total number of points passing through it to obtain the average value in the time delay direction.

[0071] for Figure 7 The centroid of the two-dimensional eye diagram shown can be determined using the centroid determination method proposed in this application. Figure 7 The location of the black dot in the middle.

[0072] S3: Based on the coordinates of the centroid in the voltage and time delay dimensions, determine the reference voltage configuration value and transmission delay configuration value corresponding to the target data line.

[0073] Once the centroid of the entire two-dimensional eye diagram is determined, the reference voltage configuration value and transmission delay configuration value corresponding to the target data line can be determined based on the coordinates (x, y) of the centroid in two-dimensional space (i.e., voltage dimension and delay dimension).

[0074] In one possible implementation, if the actual physical value is recorded during scanning, then the transmission delay configuration value is equal to the horizontal coordinate of the centroid in two-dimensional space, and the reference voltage configuration value is equal to the vertical coordinate of the centroid in two-dimensional space.

[0075] In one possible implementation, if the step number is recorded during scanning, a conversion is required. The conversion formula is: Actual configuration value = Starting value + Step number × Step size. For example, if the horizontal axis of the test point recorded during scanning represents the time step number, and the vertical axis represents the voltage step number, then the horizontal axis of the centroid in two-dimensional space still represents the time step number, and the vertical axis of the centroid in two-dimensional space still represents the voltage step number. Therefore, the conversion needs to be performed according to the above formula. Then, based on the converted actual configuration value, the reference voltage configuration value and transmission delay configuration value corresponding to the target data line are determined.

[0076] In one possible implementation, the reference voltage configuration value and transmission delay configuration value corresponding to the target data line can also be determined by looking up a table based on the coordinates of the centroid in the voltage and delay dimensions. This implementation requires establishing a conversion relationship between the coordinates and the configuration values ​​beforehand. After obtaining the coordinates of the centroid in the voltage and delay dimensions, the corresponding reference voltage configuration value and transmission delay configuration value can be found based on this conversion relationship. It is understood that the conversion relationship between the coordinates and the reference voltage configuration value may differ from the conversion relationship between the coordinates and the transmission delay configuration value.

[0077] It is understood that when determining the reference voltage configuration value and transmission delay configuration value corresponding to the target data line based on the coordinates of the centroid in the voltage and delay dimensions, the specific implementation method is not limited to the several implementation methods in the examples above. Any method or variation whose core lies in using the centroid coordinates to simultaneously determine the voltage and delay configuration values ​​falls within the protection scope of this technical solution.

[0078] When the target data line is a data line of the memory's storage rank, if the memory includes multiple storage ranks, the above method further includes: sequentially performing the steps of obtaining the two-dimensional eye diagram, determining the centroid, and determining the configuration value for each data line of the memory's rank. In other words, each data line of the memory's rank needs to be trained independently, and the training process for each data line of the rank is consistent, all involving the steps of obtaining the two-dimensional eye diagram, determining the centroid, and determining the configuration value.

[0079] In some possible implementations, after determining the reference voltage configuration value and transmission delay configuration value corresponding to the target data line based on the coordinates of the centroid in the voltage and delay dimensions, the above method further includes: configuring the transmission link (e.g., the one where the target data line is located) in the physical layer interface of the memory controller according to the transmission delay configuration value. Figure 2 The delay parameters of the S01 module in the memory controller are configured according to the reference voltage configuration value; the physical layer interface corresponding to the target data line in the memory controller (such as...) is configured according to the reference voltage configuration value. Figure 2 The reference voltage of the PHY in the memory, or the memory chip corresponding to the target data line in the memory (i.e., Figure 2 The reference voltage of the DRAM chips contained in the DDR memory is configured according to the reference voltage configuration value. If the CA command is a read command, the reference voltage of the physical layer interface corresponding to the target data line in the memory controller is configured according to the reference voltage configuration value; if the CA command is a write command, the reference voltage of the memory chip corresponding to the target data line in the memory is configured according to the reference voltage configuration value.

[0080] In one possible implementation, the principle of the above-described data line training method can be as follows: Figure 8As shown, basic one-dimensional read / write training is first performed on the memory. After completing the basic one-dimensional read / write training, two-dimensional read / write training is then performed. During training, two-dimensional scan tests are performed in both the voltage and time domains. The voltage domain scan range is VDDQ / 2 to VDDQ (e.g., corresponding to 32 scan steps), and the time domain scan range is 0UI to 4UI (e.g., corresponding to 20 scan steps). 640 scan test results (including pass and fail tests) are saved. Then, based on the Pass region formed by all pass test points (or scan points), a two-dimensional eye diagram corresponding to the data line is obtained. The centroid algorithm is then used to determine the centroid of the eye diagram. Finally, based on the coordinates of the centroid in the voltage and delay dimensions, the reference voltage configuration value Vref and the transmission delay configuration value Delay corresponding to the data line are determined. Then, the delay of the link where the data line in the PHY is located is configured based on the transmission delay configuration value Delay, and the voltage of the PHY is configured based on the reference voltage configuration value Vref (configuring the PHY voltage when reading memory) or the voltage of the DRAM chip is configured based on the DRAM chip (configuring the DRAM chip voltage when writing memory).

[0081] This application embodiment also provides a memory controller, which can receive training instructions sent by a processor (or processor core) and execute the above-described memory data line training method in response to the training instructions. The memory controller includes a voltage regulation module, a delay regulation module, and a control and processing module. The control and processing module is connected to the delay regulation module and the voltage regulation module, respectively, and the training is completed through the delay regulation module, the voltage regulation module, and the control and processing module.

[0082] The delay adjustment module, located on the transmission link where the target data line is located, is used to adjust the delay of the target data line. The voltage adjustment module is used to adjust the reference voltage of the physical layer interface in the memory controller corresponding to the target data line.

[0083] The control and processing module is used to acquire a two-dimensional eye diagram corresponding to a target data line of the memory, wherein the two-dimensional eye diagram includes multiple test points located in a two-dimensional space composed of voltage and delay dimensions, and each test point corresponds to a combination of a voltage value and a transmission delay value; determine the centroid of the two-dimensional eye diagram; and determine the reference voltage configuration value and transmission delay configuration value corresponding to the target data line based on the coordinates of the centroid in the voltage and delay dimensions.

[0084] Specifically, the control and processing module is used to: control the delay adjustment module to adjust the delay of the target data line, and control the voltage adjustment module to adjust the reference voltage of the physical layer interface corresponding to the target data line; perform a two-dimensional scan test on the target data line within a preset voltage range and a preset delay range; record the test results of each test point combining each voltage value within the preset voltage range and each transmission delay value within the preset delay range, the test results including test pass or test failure; and obtain a two-dimensional eye diagram corresponding to the target data line based on the area formed by all the test points that passed the test.

[0085] In addition, in some implementations, the number of delay adjustment modules may be two, one of which is located on the clock link where the DQS clock signal is located.

[0086] The implementation principle and technical effects provided by the memory controller embodiment are the same as those of the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the memory controller embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0087] This application also provides a processor, which includes a processor core and the aforementioned memory controller. In this embodiment, the memory controller is integrated into the processor. In some implementations, the processor and the memory controller may be parallel devices rather than being inclusive.

[0088] The processor core is used to send training instructions to the memory controller; the memory controller is used to execute training in response to the training instructions, thereby executing the training method of the memory data lines described above.

[0089] Based on the same inventive concept, this application also provides an electronic device, which includes a memory and a processor. The memory is connected to a memory controller in the processor. In this case, the processor core in the processor is used to send training instructions to the memory controller; the memory controller is used to execute training in response to the training instructions, thereby executing the above-described training method for the memory data line.

[0090] In one embodiment, when the memory controller is no longer integrated into the processor, the electronic device includes: a processor, a memory, and the aforementioned memory controller, wherein the memory controller is connected to both the processor and the memory; the processor is configured to send training instructions to the memory controller; and the memory controller is configured to execute training in response to the training instructions, thereby executing the aforementioned memory data line training method.

[0091] In some possible implementations, the memory described above may be RAM, and the memory controller described above may be a memory controller.

[0092] In one implementation, such as Figure 9 As shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor.

[0093] The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, including at least one software functional module that can be stored in the memory as software or firmware or embedded in the operating system (OS) of the electronic device. The processor executes the software functional module or computer program stored in the memory. For example, the processor executes the training method described above for the memory data line.

[0094] The memory can be, but is not limited to, Random Access Memory (RAM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0095] The processor may be an integrated circuit chip with signal processing capabilities. The aforementioned processor can be a general-purpose processor, including a Central Processing Unit (CPU), Network Processor (NP), Graphics Processing Unit (GPU), Accelerated Processing Unit (ACCU), Multimedia Application Processor (MAP), microprocessor, etc.; it can also be a Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the processor can also be any conventional processor.

[0096] The aforementioned electronic devices include, but are not limited to, smartphones, tablets, servers, base stations, smart cameras, and autonomous vehicles.

[0097] This application also provides a non-volatile computer-readable storage medium (hereinafter referred to as the storage medium) storing a computer program, which, when run by a computer such as the electronic device described above, executes the memory data line training method described above.

[0098] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0099] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative; for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0100] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0101] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, laptop, server, or electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A training method for a memory data line, characterized in that, include: Obtain a two-dimensional eye diagram corresponding to the target data line of the memory, wherein the two-dimensional eye diagram includes multiple test points located in a two-dimensional space composed of voltage and delay dimensions, and each test point corresponds to a combination of a voltage value and a transmission delay value; Determine the centroid of the two-dimensional eye diagram; Based on the coordinates of the centroid in the voltage dimension and the delay dimension, the reference voltage configuration value and transmission delay configuration value corresponding to the target data line are determined.

2. The method according to claim 1, characterized in that, Determining the centroid of the two-dimensional eye diagram includes: Based on the spatial distribution of all test points in the two-dimensional eye diagram, the geometric centroid of the two-dimensional eye diagram is determined; The geometric centroid is used as the centroid of the two-dimensional eye diagram.

3. The method according to claim 2, characterized in that, Determining the geometric centroid of the two-dimensional eye diagram includes: Determine the total area of ​​the two-dimensional eye diagram; Determine the time delay coordinate value of each test point in the two-dimensional eye diagram and the first product of the unit area represented by the test point, and sum the first products of all test points to obtain the first sum value; Determine the voltage coordinate value of each test point within the two-dimensional eye diagram and the second product of the unit area represented by that test point, and sum the second products of all test points to obtain the second sum value; The time-delay coordinates of the geometric centroid are obtained by determining the quotient of the first summation value and the total area; The voltage coordinates of the geometric centroid are obtained by determining the quotient of the second summation value and the total area.

4. The method according to claim 3, characterized in that, When the unit areas represented by the test points in the two-dimensional eye diagram are equal, the time delay coordinate of the centroid is the average of the time delay coordinate values ​​of all test points in the two-dimensional eye diagram; the voltage coordinate of the centroid is the average of the voltage coordinate values ​​of all test points in the two-dimensional eye diagram.

5. The method according to claim 1, characterized in that, The acquisition of the two-dimensional eye diagram corresponding to the target data line of the memory includes: The target data line is subjected to a two-dimensional scanning test within a preset voltage range and a preset time delay range; The test results are recorded for each combination of voltage value within the preset voltage range and transmission delay value within the preset delay range. The test results include whether the test passes or fails. Based on the area formed by all the test points that passed the tests, a two-dimensional eye diagram corresponding to the target data line is obtained.

6. The method according to claim 1, characterized in that, The target data line is the data line of the memory's storage rank; The method further includes: sequentially performing the above-described steps of obtaining a two-dimensional eye diagram, determining the centroid, and determining the configuration value on the data lines of each Rank of the memory.

7. The method according to any one of claims 1-6, characterized in that, The method further includes: Configure the delay parameters of the transmission link where the target data line is located in the physical layer interface of the memory controller according to the transmission delay configuration value; Based on the reference voltage configuration value, configure the reference voltage of the physical layer interface corresponding to the target data line in the memory controller, or configure the reference voltage of the memory chip corresponding to the target data line in the memory.

8. The method according to any one of claims 1-7, characterized in that, The memory is a double data rate synchronous dynamic random access memory.

9. A memory controller, characterized in that, include: A control and processing module is used to acquire a two-dimensional eye diagram corresponding to the target data line of the memory, wherein the two-dimensional eye diagram includes multiple test points located in a two-dimensional space composed of voltage and delay dimensions, and each test point corresponds to a combination of a voltage value and a transmission delay value; and to determine the centroid of the two-dimensional eye diagram. Based on the coordinates of the centroid in the voltage dimension and the delay dimension, the reference voltage configuration value and transmission delay configuration value corresponding to the target data line are determined.

10. The memory controller according to claim 9, characterized in that, The memory controller also includes: A delay adjustment module, located on the transmission link where the target data line is located, is used to adjust the delay of the target data line; A voltage regulation module is used to regulate the reference voltage of the physical layer interface corresponding to the target data line in the memory controller; Specifically, the control and processing module is used for: The delay adjustment module is controlled to adjust the delay of the target data line, and the voltage adjustment module is controlled to adjust the reference voltage of the physical layer interface corresponding to the target data line; The target data line is subjected to a two-dimensional scanning test within a preset voltage range and a preset time delay range; The test results are recorded for each combination of voltage value within the preset voltage range and transmission delay value within the preset delay range. The test results include whether the test passes or fails. Based on the area formed by all the test points that passed the tests, a two-dimensional eye diagram corresponding to the target data line is obtained.

11. A processor, characterized in that, include: The processor core and the memory controller as described in any one of claims 9 or 10; The processor core is used to send training instructions to the memory controller; The memory controller is used to execute a training method for the memory data lines in response to the training instructions.

12. An electronic device, characterized in that, include: The memory and the processor as described in claim 11, wherein the memory is connected to a memory controller in the processor.

13. An electronic device, characterized in that, include: A processor, a memory, and a memory controller as described in any one of claims 9 or 10, wherein the memory controller is connected to the processor and the memory, respectively. The processor is used to send training instructions to the memory controller; The memory controller is used to execute a training method for the memory data lines in response to the training instructions.

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