Failure determination method and device of core particle packaging structure and electronic equipment

Abstract

The invention provides a failure determination method and device for a core particle packaging structure and electronic equipment, and the method comprises the steps: obtaining a historical core particle packaging structure, and determining the actual state data; judging whether the historical core particle packaging structure has a failure risk or not according to the actual state data; in response to the failure risk of the historical core particle packaging structure, determining a first failure probability corresponding to the historical core particle packaging structure according to the actual state data; inputting the historical core particle packaging structure into the initial failure probability determination model to obtain a second failure probability corresponding to the historical core particle packaging structure; adjusting the initial failure probability determination model according to the first failure probability and the second failure probability until a preset end condition is met, and obtaining a failure probability determination model; and obtaining a to-be-tested core particle packaging structure, and inputting the to-be-tested core particle packaging structure into the failure probability determination model to obtain a target failure probability of the to-be-tested core particle packaging structure. According to the invention, whether the core particle packaging structure fails or not is accurately determined.

Description

Technical Field

[0001] This disclosure relates to the field of packaging and testing, and in particular to a method, apparatus and electronic device for determining the failure of a chip packaging structure. Background Technology

[0002] With the rapid development of integrated circuit packaging towards high-density and heterogeneous integration, chip-level packaging, as an important path to achieve system-level integration, is being widely used in high-performance computing, artificial intelligence, and 5G communications. However, its complex structure, multiple layers, and heterogeneous material systems, coupled with significant thermal, mechanical, and electrical field coupling, make it prone to failures such as interface delamination, solder joint fatigue, microcracks, and void evolution during service.

[0003] Traditional package failure analysis often relies on destructive testing (such as cross-sectional observation and SEM scanning) or single-mode signal analysis (such as simple thermal imaging and telecommunications testing), making it difficult to achieve full-domain characterization and quantitative failure tracking of the package's internal structure at the micrometer scale. On the other hand, while finite element simulation can predict thermal stress distribution and crack evolution trends, its accuracy depends on the accuracy of the model's input parameters and lacks a high-fidelity correspondence with actual test data. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide a method, apparatus and electronic device for determining the failure of a chip packaging structure, so as to solve or partially solve the above problems.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a method for determining the failure of a chip packaging structure, comprising: Obtain historical chip packaging structures and determine the actual state data corresponding to the historical chip packaging structures; Based on the actual status data, determine whether the historical chip packaging structure has a risk of failure; In response to the risk of failure of the historical chip packaging structure, a first failure probability corresponding to the historical chip packaging structure is determined based on the actual state data. The historical chip packaging structure is input into the initial failure probability determination model, and after processing by the initial failure probability determination model, the second failure probability corresponding to the historical chip packaging structure is obtained. The initial failure probability determination model is adjusted based on the first failure probability and the second failure probability until a preset termination condition is met, thereby obtaining the failure probability determination model. The chip packaging structure to be tested is obtained, and the chip packaging structure to be tested is input into the failure probability determination model. After processing by the failure probability determination model, the target failure probability of the chip packaging structure to be tested is obtained.

[0006] Based on the same inventive concept, a second aspect of this disclosure proposes a failure determination device for a chip packaging structure, comprising: The data acquisition module is configured to acquire historical core packaging structures and determine the actual state data corresponding to the historical core packaging structures. The judgment module is configured to determine whether the historical chip packaging structure has a failure risk based on the actual state data. The first failure probability determination module is configured to determine the first failure probability corresponding to the historical chip packaging structure based on the actual state data in response to the risk of failure of the historical chip packaging structure. The second failure probability determination module is configured to input the historical chip packaging structure into the initial failure probability determination model, and obtain the second failure probability corresponding to the historical chip packaging structure through the initial failure probability determination model. The model adjustment module is configured to adjust the initial failure probability determination model according to the first failure probability and the second failure probability until a preset termination condition is met, thereby obtaining the failure probability determination model. The failure probability determination module is configured to acquire the chip packaging structure to be tested, input the chip packaging structure to be tested into the failure probability determination model, and process it through the failure probability determination model to obtain the target failure probability of the chip packaging structure to be tested.

[0007] Based on the same inventive concept, a third aspect of this disclosure proposes an electronic device including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method described above when executing the computer program.

[0008] Based on the same inventive concept, a fourth aspect of this disclosure provides a non-transitory computer-readable storage medium that stores computer instructions for causing a computer to perform the methods described above.

[0009] As can be seen from the above, this disclosure proposes a method, apparatus, and electronic device for determining the failure of a chip packaging structure. It acquires historical chip packaging structures and determines the actual state data corresponding to the historical chip packaging structures. Based on the actual state data, it determines whether the historical chip packaging structure has a failure risk. After acquiring the historical chip packaging structure, it first determines whether the historical chip packaging structure has a failure risk. If it does, subsequent steps are performed to optimize and adjust the initial failure probability model using the historical chip packaging structure. If it does not, subsequent steps are stopped, reducing the waste of computational resources. In response to the existence of a failure risk in the historical chip packaging structure, a first failure probability corresponding to the historical chip packaging structure is determined based on the actual state data. The historical chip packaging structure is input into the initial failure probability determination model, and processed by the initial failure probability determination model to obtain a second failure probability corresponding to the historical chip packaging structure. The initial failure probability determination model is adjusted based on the first failure probability and the second failure probability until a preset termination condition is met, resulting in a failure probability determination model. The first failure probability determined from actual state data is taken as the true failure probability. Then, based on the first failure probability and the second failure probability output by the initial failure probability determination model, the model is adjusted to make the second failure probability output by the initial failure probability model closer to the first failure probability, until a preset termination condition is met, i.e., the error between the two approaches infinitesimal, thus obtaining the failure probability determination model. The chip packaging structure to be tested is obtained and input into the failure probability determination model. The model processes the data to obtain the target failure probability of the chip packaging structure to be tested. The target failure probability corresponding to the chip packaging structure is output through the trained failure probability determination model, resulting in a more accurate target failure probability. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of a failure determination method for a chip packaging structure according to an embodiment of the present disclosure; Figure 2 The following is a logic diagram of the initial failure probability determination model in the embodiments of this disclosure; Figure 3 This is a schematic diagram of the failure determination device for the chip packaging structure according to an embodiment of the present disclosure; Figure 4This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0013] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0014] With the rapid development of integrated circuit packaging towards high-density and heterogeneous integration, chip-level packaging, as an important path to achieve system-level integration, is being widely used in high-performance computing, artificial intelligence, and 5G communications. However, its complex structure, multiple layers, and heterogeneous material systems, coupled with significant thermal, mechanical, and electrical field coupling, make it prone to failures such as interface delamination, solder joint fatigue, microcracks, and void evolution during service.

[0015] Traditional package failure analysis often relies on destructive testing (such as cross-sectional observation and SEM scanning) or single-mode signal analysis (such as simple thermal imaging and telecommunications testing), making it difficult to achieve full-domain characterization and quantitative failure tracking of the package's internal structure at the micrometer scale. On the other hand, while finite element simulation can predict thermal stress distribution and crack evolution trends, its accuracy depends on the accuracy of the model's input parameters and lacks a high-fidelity correspondence with actual test data.

[0016] Therefore, there is an urgent need for a unified analysis framework that can integrate multimodal high-precision non-destructive testing data with multiphysics simulation results to achieve accurate identification and design optimization of chip packaging failure mechanisms, thereby improving the scientific nature and predictability of packaging reliability assessment.

[0017] Based on the above description, this embodiment proposes a failure determination method for chip packaging structures, such as... Figure 1 As shown, the method includes: Step 101: Obtain historical chip packaging structures and determine the actual state data corresponding to the historical chip packaging structures.

[0018] In practice, historical chip packaging structures are acquired, whereby these historical chip packaging structures are data from the training dataset used to train the subsequent initial failure probability model. Chip packaging is an advanced packaging technology that integrates multiple small chips (chips) together, aiming to improve chip performance and reduce design complexity.

[0019] The historical chip packaging structure corresponds to multiple state data, which are used to describe the potential state, temperature state, frequency domain response state, and structural defects of the chip packaging structure. Specifically, the state data includes potential, temperature, frequency domain response, and structural defects.

[0020] Determine the actual state data corresponding to the historical chip packaging structure, wherein the actual state data represents the real state data corresponding to the historical chip packaging structure.

[0021] Step 102: Based on the actual state data, determine whether the historical chip packaging structure has a risk of failure.

[0022] In practice, based on the actual state data, it is determined whether the historical chip packaging structure has a failure risk. The determination of failure risk can be based on comparisons with preset failure prediction indicators to determine whether a failure risk exists.

[0023] Step 103: In response to the risk of failure of the historical chip packaging structure, determine the first failure probability corresponding to the historical chip packaging structure based on the actual state data.

[0024] In specific implementation, in response to the risk of failure of the historical chip packaging structure, that is, based on the actual state data, it is determined that the historical chip packaging structure has a risk of failure, and at this time, the first failure probability corresponding to the historical chip packaging structure is determined based on the actual state data.

[0025] In this embodiment, the first failure probability determined based on actual state data represents the true failure probability corresponding to the historical chip packaging structure. That is, in this embodiment, the first failure probability is considered to be the accurate failure probability.

[0026] Step 104: Input the historical chip packaging structure into the initial failure probability determination model, and process it through the initial failure probability determination model to obtain the second failure probability corresponding to the historical chip packaging structure.

[0027] In practice, the historical chip packaging structure is input into the initial failure probability determination model, and the historical chip packaging structure is analyzed and predicted by the initial failure probability determination model, and the second failure probability corresponding to the historical chip packaging structure is output.

[0028] In this embodiment, the second failure probability determined by the initial failure probability determination model is the failure probability obtained by the initial failure probability determination model from analyzing the historical chip packaging structure, which can be regarded as the probability value predicted by the initial failure probability determination model.

[0029] Step 105: Adjust the initial failure probability determination model according to the first failure probability and the second failure probability until the preset termination condition is met, and obtain the failure probability determination model.

[0030] In specific implementation, since the first failure probability is the actual failure probability corresponding to the historical chip packaging structure, and the second failure probability is the predicted failure probability obtained by the initial failure probability determination model through analysis of the historical chip packaging structure, the initial failure probability determination model is adjusted based on the first failure probability and the second failure probability. That is, the deviation between the predicted failure probability output by the initial failure probability determination model and the actual failure probability is compared, and the initial failure probability determination model is adjusted based on the deviation.

[0031] The initial failure probability determination model is adjusted based on the first failure probability and the second failure probability until a preset termination condition is met, thus obtaining the failure probability determination model. The preset termination condition is the condition for ending the adjustment of the initial failure probability determination model.

[0032] In this embodiment, the preset termination condition is to minimize the deviation between the predicted failure probability output by the initial failure probability determination model and the actual failure probability.

[0033] Step 106: Obtain the chip packaging structure to be tested, input the chip packaging structure to be tested into the failure probability determination model, and obtain the target failure probability of the chip packaging structure to be tested through the failure probability determination model.

[0034] In specific implementation, after obtaining the failure probability determination model, the chip packaging structure to be tested is obtained during the application of the failure probability determination model. The chip packaging structure to be tested is the chip packaging structure whose failure probability needs to be determined.

[0035] The chip packaging structure under test is input into the failure probability determination model, and the target failure probability of the chip packaging structure under test is obtained by processing it through the failure probability determination model.

[0036] The above scheme obtains historical chip packaging structures and determines the actual state data corresponding to these structures. Based on the actual state data, it is determined whether the historical chip packaging structure has a failure risk. After obtaining the historical chip packaging structure, it is first determined whether it has a failure risk. If so, subsequent steps are performed to optimize and adjust the initial failure probability model using the historical chip packaging structure. If not, subsequent steps are stopped, reducing the waste of computational resources. In response to the existence of a failure risk in the historical chip packaging structure, a first failure probability corresponding to the historical chip packaging structure is determined based on the actual state data. The historical chip packaging structure is input into the initial failure probability determination model, and processed by the initial failure probability determination model to obtain a second failure probability corresponding to the historical chip packaging structure. The initial failure probability determination model is adjusted based on the first and second failure probabilities until a preset termination condition is met, resulting in the final failure probability determination model. The first failure probability determined from actual state data is taken as the true failure probability. Then, based on the first failure probability and the second failure probability output by the initial failure probability determination model, the model is adjusted to make the second failure probability output by the initial failure probability model closer to the first failure probability, until a preset termination condition is met, i.e., the error between the two approaches infinitesimal, thus obtaining the failure probability determination model. The chip packaging structure to be tested is obtained and input into the failure probability determination model. The model processes the data to obtain the target failure probability of the chip packaging structure to be tested. The target failure probability corresponding to the chip packaging structure is output through the trained failure probability determination model, resulting in a more accurate target failure probability.

[0037] In some embodiments, the actual state data includes actual structural defects, actual potential, actual temperature, and actual frequency domain response. Step 101, determining the actual state data corresponding to the historical chip packaging structure, specifically includes: Step 1011: Perform X-ray scanning on the historical chip packaging structure to obtain the actual structural defects corresponding to the historical chip packaging structure; Step 1012: Perform voltage detection on the historical chip packaging structure to obtain the actual potential corresponding to the historical chip packaging structure; Step 1013: Perform infrared imaging detection on the historical chip packaging structure to obtain the actual temperature corresponding to the historical chip packaging structure; Step 1014: Perform electroacoustic coupling detection on the historical chip packaging structure to obtain the actual frequency domain response corresponding to the historical chip packaging structure.

[0038] In specific implementation, the historical core packaging structure is subjected to X-ray scanning to obtain the three-dimensional structural distribution inside the historical core packaging structure, that is, to obtain the actual structural defects corresponding to the historical core packaging structure. The X-ray scanning method is performed by X-ray CT imaging and voxel reconstruction algorithm.

[0039] Specifically, the actual structural defects are determined using X-ray CT imaging and voxel reconstruction algorithms. These defects include local volume distribution and pore density, and are represented using geometric feature functions, specifically:

[0040] in, This is an actual structural defect. For local volume distribution, The pore density.

[0041] In this embodiment, a gray-level gradient-based edge segmentation algorithm is used to identify structural defects and form a voxel-level void distribution matrix.

[0042] Voltage detection is performed on the historical chip packaging structure to obtain the actual potential corresponding to the historical chip packaging structure. The voltage detection can be performed using a high-precision voltage detector.

[0043] In this embodiment, the conductivity corresponding to the historical chip packaging structure can be determined using a conductivity meter, and then the actual potential corresponding to the historical chip packaging structure can be calculated based on the conductivity. The actual potential is expressed by the formula:

[0044] in, For electrical conductivity, This is the actual electric potential. It is a partial differential function.

[0045] Infrared thermal imaging is performed on the historical chip packaging structure to obtain the actual temperature corresponding to the historical chip packaging structure. The workflow of infrared thermal imaging is as follows: the historical chip packaging structure emits infrared radiation, the optical system of the infrared thermal imager collects and focuses this radiation onto a detector, the detector converts the radiation signal into an electrical signal, and after processing, the temperature distribution information of the surface of the historical chip packaging structure, i.e., the actual temperature, is obtained.

[0046] Electroacoustic coupling detection was performed on the historical chip packaging structure to obtain the actual frequency domain response corresponding to the historical chip packaging structure, wherein the actual frequency domain response is expressed by the formula:

[0047] in, For the actual frequency domain response, The initial amplitude of the applied acoustic signal, The preset interface reflection coefficient, is the preset attenuation coefficient, and f is the sound wave frequency.

[0048] In some embodiments, step 102, determining whether the historical chip packaging structure has a failure risk based on the actual state data, specifically includes: Step 1021: Obtain the actual strain data and actual stress data corresponding to the historical chip packaging structure, and determine the energy loss based on the actual stress data, the actual strain data and the actual potential. Step 1022: Determine the equivalent stress corresponding to the historical chip packaging structure based on the actual stress data; Step 1023: Obtain the crack surface area corresponding to the historical chip packaging structure, and determine the energy release rate corresponding to the historical chip packaging structure based on the energy loss and the crack surface area. Step 1024: In response to the equivalent stress being greater than a preset stress threshold and the energy release rate being greater than a preset energy release rate threshold, it is determined that the historical chip packaging structure has a failure risk.

[0049] In specific implementation, the actual strain data and actual stress data corresponding to the historical chip packaging structure are obtained, and the energy loss is determined based on the actual stress data, the actual strain data and the actual potential. The energy loss represents the energy consumed by the historical chip packaging structure during deformation due to mechanisms such as current, heat conduction or interface friction.

[0050] In this embodiment, the energy loss utilization formula is expressed as:

[0051] in, To consume energy, Let be the volume in three-dimensional space, and let represent the integral over that volume. For actual stress data, For actual strain data, For current density, This represents the actual electric potential.

[0052] The stress deviator tensor is determined based on the actual stress data, wherein the stress deviator tensor is expressed by the formula:

[0053] in, For the stress deviator tensor, These are the components of the Cauchy stress tensor. The sum of the stresses in the three positive directions represents the hydrostatic pressure. For the Kronecker delta function, when i=j, =1; when i≠j =0.

[0054] Then, the equivalent stress corresponding to the historical chip packaging structure is determined based on the stress deviator tensor, wherein the equivalent stress is expressed by the formula:

[0055] in, For equivalent stress, For stress deviatoric tensor.

[0056] Obtain the crack surface area corresponding to the historical chip packaging structure, and determine the energy release rate corresponding to the historical chip packaging structure based on the energy loss and the crack surface area, wherein the energy release rate is expressed by the formula:

[0057] in, Energy release rate, This represents the surface area of ​​the crack.

[0058] The equivalent stress is compared to a preset stress threshold, and the energy release rate is compared to an energy release rate threshold. If the equivalent stress is greater than the preset stress threshold and the energy release rate is greater than the preset energy release rate threshold, it is determined that the historical chip packaging structure has a failure risk.

[0059] In this embodiment, the preset stress threshold is a preset yield strength, wherein the preset yield strength corresponds to the material of the historical chip packaging structure, that is, different materials correspond to different preset yield strengths. The yield strength of a material is a key mechanical performance indicator for measuring the initiation of plastic deformation, defined as the stress value corresponding to the transition from the elastic deformation stage to the plastic deformation stage. In other words, when the stress borne by the material exceeds the elastic limit, deformation continues even if the stress no longer increases; the corresponding stress at this point is the yield strength.

[0060] In some embodiments, the step 103, which involves determining the first failure probability corresponding to the historical chip packaging structure based on the actual state data in response to the risk of failure of the historical chip packaging structure, specifically includes: Step 1031: In response to the failure risk of the historical chip packaging structure, obtain a preset first failure probability model; Step 1032: Input the actual temperature and actual stress data into the first failure probability model to obtain the first failure probability corresponding to the historical chip packaging structure, wherein the first failure probability model is expressed by the formula:

[0061] in, The first failure probability, To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, This is the actual temperature. For actual stress data, For time.

[0062] In specific implementation, in response to the failure risk of the historical chip packaging structure, a preset first failure probability model is obtained, wherein the first failure probability model is expressed by the formula:

[0063] in, The first failure probability, To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, This is the actual temperature. For actual stress data, For time.

[0064] In this embodiment, Expressed in power law form as:

[0065] Where n is an index related to the material of the historical chip packaging structure, representing the cumulative rate of reaction damage.

[0066] In some embodiments, step 104, which involves inputting the historical chip packaging structure into an initial failure probability determination model and processing it through the initial failure probability determination model to obtain a second failure probability corresponding to the historical chip packaging structure, includes: Step 1041: Obtain the conductivity corresponding to the historical chip packaging structure, and input the conductivity and the historical chip packaging structure into the initial failure probability determination model; Step 1042: The initial failure probability determination model determines the predicted temperature corresponding to the historical chip packaging structure based on the conductivity. Step 1043: Determine the predicted stress data corresponding to the historical chip packaging structure based on the predicted temperature; Step 1044: Obtain a preset second failure probability model. Input the predicted temperature and predicted stress data into the second failure probability model to obtain the second failure probability corresponding to the historical chip packaging structure. The second failure probability model is expressed by the formula:

[0067] in, This represents the second failure probability. To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, To predict temperature, To predict stress data, For time.

[0068] In specific implementation, the conductivity corresponding to the historical chip packaging structure is obtained, and the conductivity and the historical chip packaging structure are input into the initial failure probability determination model. The initial failure probability model is a model that analyzes the historical chip packaging structure based on the conductivity to finally obtain the failure probability corresponding to the historical chip packaging structure.

[0069] The initial failure probability determination model determines the predicted temperature corresponding to the historical chip packaging structure based on the conductivity. The specific method for determining the predicted temperature includes: The initial failure probability determination model determines the predicted potential corresponding to the historical chip packaging structure based on the conductivity, wherein the predicted potential is expressed by the formula:

[0070] in, For electrical conductivity, To predict electric potential; The predicted temperature corresponding to the historical chip packaging structure is determined based on the predicted potential, wherein the predicted temperature is expressed by the formula:

[0071] in, Thermal conductivity, For external heat field, For density, Specific heat capacity.

[0072] The predicted stress data corresponding to the historical chip packaging structure is determined based on the predicted temperature, wherein the process of determining the predicted stress data includes: Thermal strain data is determined based on the predicted temperature, and the thermal strain data represents the thermal strain caused by the temperature gradient. The thermal strain data is expressed using the following formula:

[0073] in, For thermal strain data, The coefficient of thermal expansion is Preset reference temperature; Obtain the elastic strain data and plastic strain data corresponding to the historical chip packaging structure. Determine the overall strain data based on the thermal strain data, the elastic strain data, and the plastic strain data. The overall strain data is expressed by the formula:

[0074] in, For overall strain data, For elastic strain data, This is plastic strain data; Based on the overall strain data, a target bulk force density corresponding to the overall strain data is determined. Based on the target bulk force density, predicted stress data corresponding to the historical chip packaging structure is determined. The predicted stress data is expressed using the following formula:

[0075] in, Target physical density.

[0076] A preset second failure probability model is obtained, and the predicted temperature and predicted stress data are input into the second failure probability model to obtain the second failure probability corresponding to the historical chip packaging structure. The second failure probability model is expressed by the formula:

[0077] in, This represents the second failure probability. To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, To predict temperature, To predict stress data, For time.

[0078] In this embodiment, Expressed in power law form as:

[0079] Where n is an index related to the material of the historical chip packaging structure, representing the cumulative rate of reaction damage.

[0080] In some embodiments, step 105, adjusting the initial failure probability determination model based on the first failure probability and the second failure probability until a preset termination condition is met to obtain the failure probability determination model, includes: Step 1051: Determine the target weight coefficient corresponding to each state data in the historical chip packaging structure, and perform fusion processing on the actual state data according to the target weight coefficient to obtain the actual state matrix; Step 1052: Input the historical chip packaging structure into the initial failure probability determination model, and process it through the initial failure probability determination model to obtain the predicted state data corresponding to the historical chip packaging structure. Step 1053: The predicted state data is fused according to the target weight coefficients to obtain the predicted state matrix; Step 1054: Using the minimum deviation method, determine the registration error matrix based on the actual state matrix and the predicted state matrix; Step 1055: Determine the model error based on the registration error matrix, the first failure probability, and the second failure probability; adjust the initial failure probability determination model based on the model error until a preset termination condition is met, thereby obtaining the failure probability determination model.

[0081] In specific implementation, such as Figure 2 As shown, Figure 2 This is a logic diagram of the initial failure probability determination model in this embodiment. The target weight coefficient corresponding to each state data in the historical chip packaging structure is determined. Specifically, the target weight coefficient corresponding to each state data can be determined by combining the energy loss. The target weight coefficient is expressed by the formula:

[0082] in, Let i be the target weight coefficient, and i be each state data. For each state data point, U represents the specific numerical value, where U is the energy loss. In this embodiment, the target weight coefficients corresponding to the actual state data and the predicted state data are the same.

[0083] The actual state data is fused based on the target weight coefficients to obtain an actual state matrix, wherein the actual state matrix is ​​expressed by the formula:

[0084] in, The actual state matrix, This is an actual structural defect. This is the actual electric potential. This is the actual temperature. This is the actual frequency domain response.

[0085] The historical chip packaging structure is input into the initial failure probability determination model. After processing by the initial failure probability determination model, the predicted state data corresponding to the historical chip packaging structure is obtained. The predicted state data includes predicted structural defects, predicted potential, predicted temperature, and predicted frequency domain response.

[0086] In this embodiment, the predicted structural defects are data determined based on the initial failure probability determination model. Specifically, this can be obtained by identifying defects in historical chip packaging structures. The defect identification method can be based on the defect identification model in the initial failure probability determination model.

[0087] The predicted state data are fused based on the target weight coefficients to obtain a predicted state matrix, wherein the predicted state matrix is ​​expressed by the formula:

[0088] in, To predict the state matrix, To predict structural defects, To predict electric potential, To predict temperature, To predict the frequency domain response.

[0089] Using the minimum deviation method, the registration error matrix is ​​determined based on the actual state matrix and the predicted state matrix, wherein the registration error matrix is ​​expressed by the formula:

[0090] in, It represents multimodal nondestructive testing signal field data obtained from X-ray, CT, infrared thermography, or electroacoustic detection, and represents the actual observed values. This represents the output results from multiphysics simulation calculations, such as stress, temperature, and acoustic energy distribution.

[0091] The model error is determined based on the registration error matrix, the first failure probability, and the second failure probability. The initial failure probability determination model is then adjusted based on the model error until a preset termination condition is met, thus obtaining the failure probability determination model.

[0092] In this embodiment, key physical parameters are inverted and optimized to minimize the simulation output error, i.e., to minimize the model error. The model error is expressed by the formula:

[0093] in, The parameters representing errors in the above calculation steps include the target weight coefficient corresponding to each state data in the historical chip packaging structure, the preset empirical parameters and preset activation energy in the first failure probability model and the second failure probability model. These represent empirical estimates of these parameters. and The weighting coefficient is used to balance two errors, namely the error between the first failure probability and the second failure probability, and the error between the actual state matrix and the predicted state matrix. Represents the regularization coefficient; This represents the objective function, which is minimized by adjusting parameters during the calculation process, thereby approximating the failure assessment results of experiments and simulations.

[0094] In this embodiment, a probability distribution of the parameters is established through Bayesian optimization, a satisfactory solution is found with the fewest number of evaluations, and adaptive convergence of the parameters is achieved. This can be expressed by the following formula:

[0095] In this embodiment, a nonlinear mapping model between experimental signals and simulation parameters is established using machine learning methods. Rapid parameter updates and model generalization are achieved through training samples. This can be expressed by the following formula:

[0096] in, Represents the output of machine learning predictions. () represents experimental data With parameter set The nonlinear mapping relationship from the simulation output is obtained, and this step uses a convolutional neural network to accelerate model calibration and prediction.

[0097] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0098] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0099] Based on the same inventive concept, another embodiment of this disclosure proposes a failure determination device for a chip packaging structure, such as... Figure 3 As shown, it specifically includes: The data acquisition module 201 is configured to acquire historical chip packaging structures and determine the actual state data corresponding to the historical chip packaging structures. The judgment module 202 is configured to determine whether the historical chip packaging structure has a failure risk based on the actual state data. The first failure probability determination module 203 is configured to determine the first failure probability corresponding to the historical chip packaging structure based on the actual state data in response to the risk of failure of the historical chip packaging structure. The second failure probability determination module 204 is configured to input the historical chip packaging structure into the initial failure probability determination model, and obtain the second failure probability corresponding to the historical chip packaging structure through the initial failure probability determination model. The model adjustment module 205 is configured to adjust the initial failure probability determination model according to the first failure probability and the second failure probability until a preset termination condition is met, thereby obtaining the failure probability determination model. The failure probability determination module 206 is configured to acquire the chip packaging structure to be tested, input the chip packaging structure to be tested into the failure probability determination model, and obtain the target failure probability of the chip packaging structure to be tested through the failure probability determination model.

[0100] In some embodiments, the actual state data includes actual structural defects, actual electric potential, actual temperature, and actual frequency domain response, and the data acquisition module 201 is specifically configured to: X-ray scanning was performed on the historical chip packaging structure to obtain the actual structural defects corresponding to the historical chip packaging structure. Voltage detection is performed on the historical chip packaging structure to obtain the actual potential corresponding to the historical chip packaging structure. Infrared thermal imaging detection was performed on the historical chip packaging structure to obtain the actual temperature corresponding to the historical chip packaging structure. Electroacoustic coupling detection is performed on the historical chip packaging structure to obtain the actual frequency domain response corresponding to the historical chip packaging structure.

[0101] In some embodiments, the determination module 202 is specifically configured as follows: Obtain the actual strain data and actual stress data corresponding to the historical chip packaging structure, and determine the energy loss based on the actual stress data, the actual strain data and the actual potential; Based on the actual stress data, determine the equivalent stress corresponding to the historical chip packaging structure; Obtain the crack surface area corresponding to the historical chip packaging structure, and determine the energy release rate corresponding to the historical chip packaging structure based on the energy loss and the crack surface area. In response to the equivalent stress being greater than a preset stress threshold and the energy release rate being greater than a preset energy release rate threshold, it is determined that the historical chip packaging structure has a failure risk.

[0102] In some embodiments, the first failure probability determination module 203 is specifically configured to: In response to the risk of failure in the historical chip packaging structure, a preset first failure probability model is obtained; The actual temperature and actual stress data are input into the first failure probability model to obtain the first failure probability corresponding to the historical chip packaging structure. The first failure probability model is expressed by the formula:

[0103] in, The first failure probability, To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, This is the actual temperature. For actual stress data, For time.

[0104] In some embodiments, the second failure probability determination module 204 is specifically configured to: Obtain the electrical conductivity corresponding to the historical chip packaging structure, and input the electrical conductivity and the historical chip packaging structure into the initial failure probability determination model; The initial failure probability determination model determines the predicted temperature corresponding to the historical chip packaging structure based on the conductivity. The predicted stress data corresponding to the historical chip packaging structure is determined based on the predicted temperature. A preset second failure probability model is obtained, and the predicted temperature and predicted stress data are input into the second failure probability model to obtain the second failure probability corresponding to the historical chip packaging structure. The second failure probability model is expressed by the formula:

[0105] in, This represents the second failure probability. To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, To predict temperature, To predict stress data, For time.

[0106] In some embodiments, the second failure probability determination module 204 is specifically configured to: The initial failure probability determination model determines the predicted potential corresponding to the historical chip packaging structure based on the conductivity, wherein the predicted potential is expressed by the formula:

[0107] in, For electrical conductivity, To predict electric potential; The predicted temperature corresponding to the historical chip packaging structure is determined based on the predicted potential, wherein the predicted temperature is expressed by the formula:

[0108] in, Thermal conductivity, For external heat field, For density, Specific heat capacity.

[0109] In some embodiments, the second failure probability determination module 204 is specifically configured to: Thermal strain data are determined based on the predicted temperature, wherein the thermal strain data is expressed by the formula:

[0110] in, For thermal strain data, The coefficient of thermal expansion is Preset reference temperature; Obtain the elastic strain data and plastic strain data corresponding to the historical chip packaging structure. Determine the overall strain data based on the thermal strain data, the elastic strain data, and the plastic strain data. The overall strain data is expressed by the formula:

[0111] in, For overall strain data, For elastic strain data, This is plastic strain data; Based on the overall strain data, a target bulk force density corresponding to the overall strain data is determined. Based on the target bulk force density, predicted stress data corresponding to the historical chip packaging structure is determined. The predicted stress data is expressed using the following formula:

[0112] in, Target physical density.

[0113] In some embodiments, the model adjustment module 205 is specifically configured as follows: Determine the target weight coefficient corresponding to each state data in the historical chip packaging structure, and perform fusion processing on the actual state data according to the target weight coefficient to obtain the actual state matrix; The historical chip packaging structure is input into the initial failure probability determination model, and the predicted state data corresponding to the historical chip packaging structure is obtained through the initial failure probability determination model. The predicted state data are fused according to the target weight coefficients to obtain the predicted state matrix; The registration error matrix is ​​determined using the minimum deviation method based on the actual state matrix and the predicted state matrix. The model error is determined based on the registration error matrix, the first failure probability, and the second failure probability. The initial failure probability determination model is then adjusted based on the model error until a preset termination condition is met, thus obtaining the failure probability determination model.

[0114] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing this disclosure, the functions of each module can be implemented in one or more software and / or hardware.

[0115] The apparatus described above is used to implement the failure determination method of the corresponding chip packaging structure in any of the following embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0116] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the failure determination method of the chip packaging structure described in any of the above embodiments.

[0117] Figure 4 This embodiment illustrates a more specific hardware structure of an electronic device. The device may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0118] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0119] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0120] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0121] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0122] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0123] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0124] The electronic devices described above are used to implement the failure determination method of the corresponding chip packaging structure in any of the foregoing embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0125] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the failure determination method of the chip packaging structure as described in any of the above embodiments.

[0126] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0127] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the failure determination method of the chip packaging structure as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0128] It is understood that before using the technical solutions of the various embodiments in this disclosure, users will be informed of the type, scope of use, and usage scenarios of the personal information involved in an appropriate manner, and user authorization will be obtained.

[0129] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose, based on the prompt message, whether to provide personal information to the software or hardware such as electronic devices, applications, servers, or storage media performing the operations of this disclosed technical solution.

[0130] As an optional but not limited implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device.

[0131] It is understood that the above notification and user authorization process are merely illustrative and do not constitute a limitation on the implementation of this disclosure. Other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0132] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0133] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0134] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0135] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for determining the failure of a chip packaging structure, characterized in that, include: Obtain historical chip packaging structures and determine the actual state data corresponding to the historical chip packaging structures; Based on the actual status data, determine whether the historical chip packaging structure has a risk of failure; In response to the risk of failure of the historical chip packaging structure, a first failure probability corresponding to the historical chip packaging structure is determined based on the actual state data. The historical chip packaging structure is input into the initial failure probability determination model, and after processing by the initial failure probability determination model, the second failure probability corresponding to the historical chip packaging structure is obtained. The initial failure probability determination model is adjusted based on the first failure probability and the second failure probability until a preset termination condition is met, thereby obtaining the failure probability determination model. The chip packaging structure to be tested is obtained, and the chip packaging structure to be tested is input into the failure probability determination model. After processing by the failure probability determination model, the target failure probability of the chip packaging structure to be tested is obtained.

2. The method according to claim 1, characterized in that, The actual state data includes actual structural defects, actual electric potential, actual temperature, and actual frequency domain response. The determination of the actual state data corresponding to the historical chip packaging structure includes: X-ray scanning was performed on the historical chip packaging structure to obtain the actual structural defects corresponding to the historical chip packaging structure. Voltage detection is performed on the historical chip packaging structure to obtain the actual potential corresponding to the historical chip packaging structure. Infrared thermal imaging detection was performed on the historical chip packaging structure to obtain the actual temperature corresponding to the historical chip packaging structure. Electroacoustic coupling detection is performed on the historical chip packaging structure to obtain the actual frequency domain response corresponding to the historical chip packaging structure.

3. The method according to claim 2, characterized in that, The step of determining whether the historical chip packaging structure has a failure risk based on the actual state data includes: Obtain the actual strain data and actual stress data corresponding to the historical chip packaging structure, and determine the energy loss based on the actual stress data, the actual strain data and the actual potential; Based on the actual stress data, determine the equivalent stress corresponding to the historical chip packaging structure; Obtain the crack surface area corresponding to the historical chip packaging structure, and determine the energy release rate corresponding to the historical chip packaging structure based on the energy loss and the crack surface area. In response to the equivalent stress being greater than a preset stress threshold and the energy release rate being greater than a preset energy release rate threshold, it is determined that the historical chip packaging structure has a failure risk.

4. The method according to claim 3, characterized in that, In response to the risk of failure of the historical chip packaging structure, determining the first failure probability corresponding to the historical chip packaging structure based on the actual state data includes: In response to the risk of failure in the historical chip packaging structure, a preset first failure probability model is obtained; The actual temperature and actual stress data are input into the first failure probability model to obtain the first failure probability corresponding to the historical chip packaging structure. The first failure probability model is expressed by the formula: in, The first failure probability, To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, This is the actual temperature. For actual stress data, For time.

5. The method according to claim 1, characterized in that, The step of inputting the historical chip packaging structure into the initial failure probability determination model, and processing it through the initial failure probability determination model to obtain the second failure probability corresponding to the historical chip packaging structure, includes: Obtain the electrical conductivity corresponding to the historical chip packaging structure, and input the electrical conductivity and the historical chip packaging structure into the initial failure probability determination model; The initial failure probability determination model determines the predicted temperature corresponding to the historical chip packaging structure based on the conductivity. The predicted stress data corresponding to the historical chip packaging structure is determined based on the predicted temperature. A preset second failure probability model is obtained, and the predicted temperature and predicted stress data are input into the second failure probability model to obtain the second failure probability corresponding to the historical chip packaging structure. The second failure probability model is expressed by the formula: in, This represents the second failure probability. To preset the empirical coefficient, To preset activation energy, Boltzmann's constant, To predict temperature, To predict stress data, For time.

6. The method according to claim 5, characterized in that, The initial failure probability determination model determines the predicted temperature corresponding to the historical chip packaging structure based on the conductivity, including: The initial failure probability determination model determines the predicted potential corresponding to the historical chip packaging structure based on the conductivity, wherein the predicted potential is expressed by the formula: in, For electrical conductivity, To predict electric potential; The predicted temperature corresponding to the historical chip packaging structure is determined based on the predicted potential, wherein the predicted temperature is expressed by the formula: in, Thermal conductivity, For external heat field, For density, Specific heat capacity.

7. The method according to claim 5, characterized in that, The step of determining the predicted stress data corresponding to the historical chip packaging structure based on the predicted temperature includes: Thermal strain data are determined based on the predicted temperature, wherein the thermal strain data is expressed by the formula: in, For thermal strain data, The coefficient of thermal expansion is Preset reference temperature; Obtain the elastic strain data and plastic strain data corresponding to the historical chip packaging structure. Determine the overall strain data based on the thermal strain data, the elastic strain data, and the plastic strain data. The overall strain data is expressed by the formula: in, For overall strain data, For elastic strain data, This is plastic strain data; Based on the overall strain data, a target bulk force density corresponding to the overall strain data is determined. Based on the target bulk force density, predicted stress data corresponding to the historical chip packaging structure is determined. The predicted stress data is expressed using the following formula: in, Target physical density.

8. The method according to claim 1, characterized in that, The step of adjusting the initial failure probability determination model based on the first failure probability and the second failure probability until a preset termination condition is met to obtain the failure probability determination model includes: Determine the target weight coefficient corresponding to each state data in the historical chip packaging structure, and perform fusion processing on the actual state data according to the target weight coefficient to obtain the actual state matrix; The historical chip packaging structure is input into the initial failure probability determination model, and the predicted state data corresponding to the historical chip packaging structure is obtained through the initial failure probability determination model. The predicted state data are fused according to the target weight coefficients to obtain the predicted state matrix; The registration error matrix is ​​determined using the minimum deviation method based on the actual state matrix and the predicted state matrix. The model error is determined based on the registration error matrix, the first failure probability, and the second failure probability. The initial failure probability determination model is then adjusted based on the model error until a preset termination condition is met, thus obtaining the failure probability determination model.

9. A failure determination device for a chip packaging structure, characterized in that, include: The data acquisition module is configured to acquire historical core packaging structures and determine the actual state data corresponding to the historical core packaging structures. The judgment module is configured to determine whether the historical chip packaging structure has a failure risk based on the actual state data. The first failure probability determination module is configured to determine the first failure probability corresponding to the historical chip packaging structure based on the actual state data in response to the risk of failure of the historical chip packaging structure. The second failure probability determination module is configured to input the historical chip packaging structure into the initial failure probability determination model, and obtain the second failure probability corresponding to the historical chip packaging structure through the initial failure probability determination model. The model adjustment module is configured to adjust the initial failure probability determination model according to the first failure probability and the second failure probability until a preset termination condition is met, thereby obtaining the failure probability determination model. The failure probability determination module is configured to acquire the chip packaging structure to be tested, input the chip packaging structure to be tested into the failure probability determination model, and process it through the failure probability determination model to obtain the target failure probability of the chip packaging structure to be tested.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor, when executing the program, implements the method as claimed in any one of claims 1 to 8.

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