Quantum circuit generation method and related device

Abstract

The embodiment of the invention discloses a quantum circuit generation method and a related device, and relates to the technical field of quantum computing, in each entanglement layer, each quantum bit is acted by a CNOT gate or a CZ gate or a quantum entanglement gate in other forms, so that the quantum entanglement gate is generated according to the magnitude relationship between the total number of quantum bits to be acted by a quantum circuit and the power of 2. The number of entanglement layers can be determined, and after the quantum bit pair acted by each quantum entanglement gate in the first entanglement layer on the action time sequence is determined, the quantum bit pair acted by each quantum entanglement gate in the next entanglement layer can be determined according to the quantum bit pair acted by each quantum entanglement gate in the previous entanglement layer on the action time sequence. And the quantum bit pair acted by the quantum entanglement gate in the next entanglement layer is different from the quantum bit pair acted by each quantum entanglement gate in the previous entanglement layer, so that the number of the quantum entanglement gates in each entanglement layer can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, and in particular to a quantum circuit generation method and related apparatus. BACKGROUND

[0002] A quantum computer implements computation by operating on quantum states. For example, by changing the state of a quantum bit through specific quantum gate operations (such as Hadamard gates, quantum entanglement gates (CNOT gates, CZ gates), etc.), the processing and operation of information are achieved.

[0003] A quantum state is a prerequisite for the correct operation of a quantum computer. If the preparation of a quantum state is inaccurate or disturbed, it may lead to incorrect computation results. For example, in a quantum computing experiment, if there is a deviation in the preparation of an initial quantum state, the subsequent computation process and results will be affected to varying degrees.

[0004] In the preparation process of a quantum state, a quantum circuit is usually required to act on a quantum bit to obtain a specific quantum state, and the more complex the quantum circuit, the more interference it will suffer, which may affect the final obtained quantum state. Therefore, the complexity of a quantum circuit is related to the accuracy of the final obtained quantum state. SUMMARY

[0005] Embodiments of the present application provide a quantum circuit generation method and related apparatus, which can simplify the structure of a quantum circuit used to generate a specific quantum state to some extent, thereby facilitating the implementation of the quantum circuit at the chip level. That is, the quantum circuit generated by the quantum circuit generation method disclosed in the present application can more accurately and efficiently prepare a specific quantum state.

[0006] A first aspect of embodiments of the present application provides a quantum circuit generation method, comprising: determining the number of entanglement layers according to the size relationship between the total number of quantum bits to be acted on by a quantum circuit and the power of 2; wherein each entanglement layer includes a plurality of quantum entanglement gates acting on two quantum bits, and in each entanglement layer, each quantum bit is acted on by a quantum entanglement gate at least once; determining the quantum bit pairs acted on by the quantum entanglement gates in the first entanglement layer along the action time sequence, and determining the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer according to the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer along the action time sequence; wherein the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer are different from the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer; and generating the quantum circuit based on the determined number of entanglement layers and the quantum bit pairs acted on by the quantum entanglement gates in each entanglement layer.

[0007] Optionally, the determining the pairs of quantum bits acted on by the quantum entanglement gates in the first entanglement layer comprises: queuing the quantum bits in the total set of quantum bits; and determining the pairs of quantum bits acted on by the quantum entanglement gates in the first entanglement layer according to the queuing result.

[0008] Alternatively,

[0009] When the total number of quantum bits is even, the quantum bits in the total set of quantum bits are paired two by two.

[0010] Optionally, the determining the pairs of quantum bits acted on by the quantum entanglement gates in the next entanglement layer according to the pairs of quantum bits acted on by the quantum entanglement gates in the previous entanglement layer comprises: generating two pairs of quantum bits in the next entanglement layer according to the two pairs of quantum bits in the previous entanglement layer; and determining the pairs of quantum bits acted on by the quantum entanglement gates in the next entanglement layer in response to detecting that the pairs of quantum bits in the previous entanglement layer are all selected at least once to generate the two pairs of quantum bits in the next entanglement layer.

[0011] Optionally, the generating the two pairs of quantum bits in the next entanglement layer according to the two pairs of quantum bits in the previous entanglement layer comprises: queuing the first quantum bits of the pairs of quantum bits in the two pairs of quantum bits in the previous entanglement layer, and queuing the last quantum bits of the pairs of quantum bits in the two pairs of quantum bits in the previous entanglement layer.

[0012] Optionally, the determining the number of entanglement layers according to the relationship between the total number of quantum bits to be acted on by the quantum circuit and the size of the power of 2 comprises: when the total number of quantum bits is greater than a first power of 2 and less than or equal to a second power of 2, determining the number of entanglement layers as the exponent value corresponding to the second power of 2, wherein the first power of 2 and the second power of 2 are adjacent powers of 2 in a set of powers of 2.

[0013] Optionally, in the quantum circuit, a rotation logic gate acting on each quantum circuit is arranged before each entanglement layer.

[0014] The second aspect of the embodiments of the present application provides a quantum circuit, which is generated by the quantum circuit generation method of the first aspect.

[0015] The third aspect of the embodiment of the present application provides a quantum circuit generation device, comprising: a first determination unit configured to determine the number of entanglement layers according to the size relationship between the total number of quantum bits to be acted on by a quantum circuit and the power of 2; wherein each entanglement layer comprises a plurality of quantum entanglement gates acting on two quantum bits, and each quantum bit in each entanglement layer is acted on by a quantum entanglement gate at least once;

[0016] a second determination unit configured to determine the quantum bit pairs acted on by the quantum entanglement gates in the first entanglement layer along the action time sequence, and determine the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer according to the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer along the action time sequence; wherein the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer are different from the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer;

[0017] a generation unit configured to generate the quantum circuit based on the determined number of entanglement layers and the quantum bit pairs acted on by the quantum entanglement gates in each entanglement layer.

[0018] The fourth aspect of the embodiment of the present application provides an electronic device, comprising: a processor and a memory;

[0019] The processor and the memory are connected, wherein the memory is configured to store a computer program, and the processor is configured to call the computer program to execute the method in the first aspect of the embodiment of the present application.

[0020] The fifth aspect of the embodiment of the present application provides a computer readable storage medium, the computer readable storage medium stores a computer program, the computer program comprises program instructions, and the program instructions are executed by a processor to execute the method in the first aspect of the embodiment of the present application.

[0021] The quantum circuit generation method and the related device provided by the present application are characterized in that each quantum bit in each entanglement layer is acted on by a quantum entanglement gate, and therefore, the number of entanglement layers can be determined according to the size relationship between the total number of quantum bits to be acted on by a quantum circuit and the power of 2, and after the quantum bit pairs acted on by the quantum entanglement gates in the first entanglement layer along the action time sequence are determined, the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer can be determined according to the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer along the action time sequence, and the quantum bit pairs acted on by the quantum entanglement gates in the next entanglement layer are different from the quantum bit pairs acted on by the quantum entanglement gates in the previous entanglement layer, so that the number of quantum entanglement gates in each entanglement layer can be reduced. In this way, not only the number of entanglement layers can be reduced, but also the number of quantum entanglement gates in the entanglement layers can be reduced, so that the complexity of the finally obtained quantum circuit is low.

[0022] Further, the quantum circuit with lower complexity can be implemented at a chip level, and is conducive to completing the operation on the quantum bit within the coherence time of the quantum bit, thereby helping to ensure the accuracy of the prepared quantum state. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0024] Figure 1 An example system block diagram for implementing the quantum circuit generation method provided by an embodiment of the present application is shown;

[0025] Figure 2 A flowchart of the quantum circuit generation method provided by an embodiment of the present application is shown;

[0026] Figure 3 A quantum circuit diagram acting on 8 quantum bits provided by another embodiment of the present application is shown;

[0027] Figure 4 An effect comparison diagram of the quantum circuit of the present disclosure provided by another embodiment of the present application is shown;

[0028] Figure 5 An effect comparison diagram of the quantum circuit of the present disclosure provided by another embodiment of the present application is shown;

[0029] Figure 6 A structural diagram of the quantum circuit generation device provided by an embodiment of the present application is shown;

[0030] Figure 7 A structural diagram of the computer device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0032] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches to drive the functions of a classical computer. If there are n bits of data, there are 2^n possible classical states, and one state is represented at a time.

[0033] Quantum computers use quantum processors that operate on data represented by qubits, also known as quantum bits. A single qubit can represent the classical binary states "0" or "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both "0" and "1" states simultaneously. For example, if there are n bits of data, then 2^n qubits can represent n bits of data. n A quantum state can be represented simultaneously. Furthermore, qubits in a superposition can be correlated with each other, a phenomenon known as entanglement, where the state of one qubit (whether 1, 0, or both) depends on the state of another qubit, and more information can be encoded within two entangled qubits. Based on the principles of superposition and entanglement, qubits enable quantum computers to perform functions that might be relatively complex and time-consuming for classical computers.

[0034] Please refer to Figure 1 This illustrates an example system block diagram for implementing a quantum circuit generation method according to an embodiment of this application. System 100 may be a hybrid computing system comprising a combination of one or more quantum computers, quantum systems, and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one implementation, the quantum system 110 and the classical computer 120 may be configured to communicate via one or more wired and / or wireless connections (e.g., wireless networks). The quantum system 110 may include a quantum chipset consisting of one or more quantum chips, comprising various hardware components for processing data encoded in qubits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chips from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that can degrade the performance of the quantum chips. The classical computer 120 may be electronically integrated with the quantum system 110 via any suitable wired and / or wireless electronic connection.

[0035] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of qubits to evolve and / or become entangled. Figure 1In the example embodiment shown, quantum system 110 can include a control- measurement unit 111, an interface 112, and a quantum chip 113. In some embodiments, all or portions of each of control-measurement unit 111, interface 112, and quantum chip 113 can be located in a cryogenic environment to assist in performing quantum operations. Quantum chip 113 can be any hardware capable of processing information using quantum states. This hardware can include a plurality of qubits and devices that couple or entangle the qubits in order to process information using quantum states. Qubits can include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip can include a set of quantum logic gates configured to perform quantum logic operations on qubits stored in a quantum register. The quantum gates can include one or more single-qubit gates, two-qubit gates, and / or other multi-qubit gates.

[0036] Control-measurement unit 111 can be any combination of digital computing devices capable of performing quantum computations (e.g., executing quantum circuits) in conjunction with interface 112. The digital computing devices can include digital processors and memory for storing and executing quantum instructions using interface 112. The digital computing devices can also include a communication protocol device for receiving instructions and sending results of executed quantum computations to a classical computer. Additionally, the digital computing devices can also include a communication interface with interface 112. In one embodiment, control-measurement unit 111 can be configured to receive classical instructions (e.g., from classical computer 120) and convert the classical instructions into control-measurement instructions for interface 112. The control-measurement instructions provided by control-measurement unit 111 to interface 112 can be, for example, digital signals that indicate which of the quantum gates need to act on the qubits to perform a particular function. Interface 112 can be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses) that can be used to apply quantum gates on the qubits to manipulate the interactions between the qubits.

[0037] Interface 112 can be a classical-quantum interface including a combination of devices capable of receiving instructions from control machine 111 and converting the instructions into a device for implementing quantum operations. In one embodiment, interface 112 can transform instructions from control machine 111 into drive signals that can drive or manipulate qubits, and / or act quantum gates on qubits. Additionally, interface 112 can be configured to convert signals received from quantum chip 113 into digital signals that can be processed and transmitted by control machine 111. Devices included in interface 112 can include, but are not limited to, digital-to-analog converters, analog-to-digital converters, waveform generators, attenuators, amplifiers, optical fibers, lasers, and filters. Interface 112 can further include circuit components configured to measure a plurality of qubits after a quantum gate has acted on the qubits, where the measurement can produce a result represented in classical bits. Each measurement performed by interface 112 can be read out to a device connected to quantum system 110, such as classical computer 120. Multiple measurement results provided by interface 112 can represent probabilistic results.

[0038] Classical computer 120 can include hardware components such as processors and storage devices (e.g., including memory devices and classical registers) for processing data encoded in classical bits. In one embodiment, classical computer 120 can be configured to provide various control signals, instructions, and data encoded in classical bits to quantum system 110. Further, quantum states measured by quantum system 110 can be read out by classical computer 120, and classical computer 120 can store the measured quantum states as classical bits in classical registers. In one embodiment, classical computer 120 can be any suitable combination of computer executable hardware and / or computer executable software capable of executing preparation module 121 to perform quantum computations using data stored in data storage module 122 as part of a build and compute. Data storage module 122 can be a repository for data to be analyzed using quantum computing algorithms and results of that analysis. Preparation module 121 can be a program or module capable of preparing classical data from data storage module 122 as part of a quantum circuit implementation. Preparation module 121 can be instantiated as part of a larger algorithm, such as a function call of an application programming interface (API), or by parsing a hybrid classical-quantum computation into quantum and classical computing aspects. For example, preparation module 121 can generate instructions for creating a quantum circuit using quantum gates. In embodiments, such instructions can be stored by control machine 111 and components of interface 112 can be instantiated to execute such that quantum operations of the quantum gates can be performed on quantum chip 113.

[0039] The classic computer 120 may be a laptop computer, desktop computer, vehicle-integrated computer, smart mobile device, tablet device, and / or any other suitable classic computing device. Additionally or alternatively, the classic computer 120 may also operate as part of a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS). The classic computer 120 may also reside in a cloud computing deployment model, such as a private cloud, community cloud, public cloud, or hybrid cloud.

[0040] As can be seen from the above background technology, the accuracy of quantum state preparation directly affects the accuracy of quantum computing. In the process of quantum state preparation, multiple qubits need to be entangled and superimposed. Usually, by using a specific quantum circuit to act on multiple qubits, the entanglement and superposition of multiple qubits can be completed, thereby obtaining a specific quantum state.

[0041] The complexity of a quantum circuit is related to the ease with which it can be implemented on a quantum chip. The more complex the quantum circuit, the more difficult it is to implement on a quantum chip, and thus the more difficult it is to implement. Conversely, the simpler the quantum circuit, the easier it is to implement at the chip level.

[0042] At the same time, the simpler the quantum circuit, the higher its operating efficiency, which allows it to complete its function within the coherence time of the qubit, and also helps to obtain a more accurate quantum state.

[0043] Please refer to Figure 2 The illustration shows a flowchart of a quantum circuit generation method according to an embodiment of this application. This method can be applied to computer devices, which refer to electronic devices with data computing and processing capabilities. For example, the entity executing each step can be... Figure 1 The method may include the following steps: (A quantum computer or a classical computer, selected as needed).

[0044] Step 201: Determine the number of entanglement layers based on the relationship between the total number of qubits to be used in the quantum circuit and powers of 2.

[0045] Step 202: Determine the pairs of qubits that act on each quantum entanglement gate in the first entanglement layer along the action sequence, and determine the pairs of qubits that act on each quantum entanglement gate in the next entanglement layer based on the pairs of qubits that act on each quantum entanglement gate in the previous entanglement layer along the action sequence.

[0046] Step 203: Based on the determined number of entanglement layers and the pairs of qubits acting by each quantum entanglement gate in each entanglement layer, generate a quantum circuit.

[0047] Here, each entanglement layer includes multiple quantum entanglement gates acting on two qubits. In each entanglement layer, each qubit is acted on by a quantum entanglement gate at least once.

[0048] It should be understood that the quantum entanglement gates here can include, but are not limited to, CNOT gates, CZ gates, etc. Of course, in practical applications, each quantum entanglement gate can be determined according to the specific circumstances.

[0049] Here, the qubit pairs acting through the quantum entanglement gates in the next entanglement layer along the action sequence are different from the qubit pairs acting through the quantum entanglement gates in the previous entanglement layer.

[0050] As an example, in each entanglement layer, each qubit is acted upon by a quantum entanglement gate at least once, so that at least half of the qubits in each entanglement layer can be entangled. To complete the entanglement of all qubits and thus achieve the superposition of the states corresponding to each qubit, multiple entanglement layers can be used.

[0051] As an example, the qubit pairs acted by the quantum entanglement gates in the later entanglement layer are different from the qubit pairs acted by the quantum entanglement gates in the previous entanglement layer. In this way, by setting up multiple entanglement layers, entanglement for all qubits can be achieved.

[0052] It should be understood that since the quantum entanglement gate operates on 2 qubits, the minimum number of entanglement layers can be determined based on the relationship between the total number of qubits and powers of 2. For example, with 8 qubits, then 2... 3 Since the number equals 8, a minimum of three layers are required. The principle can be understood as follows: the first entanglement layer pairs the qubits together to obtain 4 qubit pairs; the second entanglement layer can then cross-pair these 4 qubit pairs to obtain another 4 qubit pairs; and the third entanglement layer can then cross-pair the 4 qubit pairs from the second entanglement layer. In this way, the information exchange of all qubits is completed.

[0053] For example, if 8 qubits are numbered 1, 2, 3, 4, 5, 6, 7, and 8, the qubit pairs in the first entanglement layer can be: [1, 2], [3, 4], [5, 6], and [7, 8]. The second entanglement layer differs from the first; it pairs qubits based on the first digit of the pairing result from the previous entanglement layer, resulting in: [1, 3], [5, 7], [2, 4], and [6, 8]. Similarly, the third entanglement layer pairs qubits based on the first digit of the pairing result from the second entanglement layer, resulting in: [1, 5], [2, 6], [3, 7], and [4, 8]. In this way, in the first entanglement layer, qubit numbered 1 and qubit numbered 2 are entangled. In the first entanglement layer, qubit 1 is entangled with qubit 3, and qubit 2 is entangled with qubit 4 (while in the first entanglement layer, qubit 4 is entangled with qubit 3). In the third entanglement layer, qubit 1 is entangled with qubit 5 (in the second entanglement layer, qubit 5 is entangled with qubit 7), and qubit 2 is entangled with qubit 6 (in the second entanglement layer, qubit 6 is entangled with qubit 8).

[0054] In other words, when 8 qubits need to be superimposed in quantum states, only 3 entanglement layers are required.

[0055] As can be seen, in this disclosure, each qubit in each entanglement layer is acted upon by a quantum entanglement gate. Therefore, based on the relationship between the total number of qubits to be acted in the quantum circuit and powers of 2, the number of entanglement layers can be determined. After determining the qubit pairs acted by each quantum entanglement gate in the first entanglement layer along the action sequence, the qubit pairs acted by each quantum entanglement gate in the next entanglement layer can be determined based on the qubit pairs acted by each quantum entanglement gate in the previous entanglement layer along the action sequence. Furthermore, the qubit pairs acted by each quantum entanglement gate in the next entanglement layer are different from those in the previous entanglement layer. In this way, the number of quantum entanglement gates in each entanglement layer can be reduced. Through this method, not only the number of entanglement layers can be reduced, but also the number of quantum entanglement gates in the entanglement layers can be reduced, which is beneficial for obtaining a quantum circuit with lower complexity.

[0056] It should be understood that quantum circuits with lower complexity can be easily implemented at the chip level and are more conducive to completing the action on the qubit within the coherence time of the qubit, thereby helping to ensure the accuracy of the prepared quantum state.

[0057] In some embodiments, step 202 (determining the pairs of qubits acting by each quantum entanglement gate in the first entanglement layer along the action sequence) may specifically include:

[0058] Group the individual qubits in the total set of qubits;

[0059] Based on the team formation results, determine the qubit pairs that act on each quantum entanglement gate in the first entanglement layer;

[0060] Specifically, the grouping of qubits in the total set of qubits can include:

[0061] When the total number of qubits is odd, the first qubit is selected from the total set of qubits according to the positional relationship between each qubit in the total set of qubits. The remaining qubits in the total set of qubits other than the first qubit are paired up in pairs. The first qubit is paired up with any of the remaining qubits mentioned above.

[0062] Alternatively, when the total number of qubits is even, the qubits in the total set of qubits can be grouped into pairs.

[0063] As an example, the total set of qubits can be composed of qubits that a quantum circuit needs to operate on; that is, the quantum circuit needs to operate on any one of the qubits in the total set of qubits.

[0064] As an example, the total number of qubits may be odd or even. When the total number of qubits is odd, after pairing the qubits in pairs, there may be one qubit that is not paired, and this qubit can be understood as the first qubit.

[0065] As an example, the first qubit can be determined based on its positional relationship with other qubits, such as if it is located at the edge of the chip topology. That is, the number of qubits that may be adjacent to the first qubit is relatively small, so this qubit can be used as the first qubit and randomly paired with any other qubit.

[0066] As an example, one group corresponds to one quantum entanglement gate. That is, when the total number of qubits is even, the number of quantum entanglement gates in the first entangled layer along the action sequence is equal to half the total number of qubits; while when the total number of qubits is odd, the number of quantum entanglement gates in the first entangled layer along the action sequence is equal to half the total number of qubits rounded up.

[0067] In other words, this method avoids the situation where multiple qubits are grouped together multiple times in the first entanglement layer (it is only possible when the total number of qubits is odd, in which case one qubit is acted upon by two quantum entanglement gates), thereby greatly reducing the number of quantum entanglement gates in an entanglement layer, which helps to make the final quantum circuit simpler.

[0068] In some embodiments, step 202 (determining the qubit pairs acting on each quantum entanglement gate in the next entanglement layer based on the qubit pairs acting on each quantum entanglement gate in the previous entanglement layer along the action time sequence) may specifically include:

[0069] Based on the two qubit pairs in the previous entanglement layer, generate two qubit pairs in the next entanglement layer;

[0070] In response to the detection that each pair of qubits in the previous entangled layer has been selected at least once to generate two pairs of qubits in the next entangled layer, the qubit pairs that have obtained the quantum entanglement gates in the next entangled layer are determined.

[0071] As an example, based on the two qubit pairs in the previous entanglement layer, two qubit pairs in the next entanglement layer are generated. This is equivalent to assembling the two qubit pairs in the previous entanglement layer as a whole when assembling for the next entanglement layer. Since each qubit pair contains two qubits, the two qubit pairs correspond to four qubits, thus generating two more qubit pairs.

[0072] This method ensures that the qubit pairs acted by the quantum entanglement gates in the next entanglement layer are different from the qubit pairs acted by the quantum entanglement gates in the previous entanglement layer, and can determine the qubit pairs acted by the quantum entanglement gates in the next entanglement layer more efficiently.

[0073] In some embodiments, the generation of the two qubit pairs in the subsequent entangled layer based on the two qubit pairs in the previous entangled layer may specifically include:

[0074] The first qubit of each qubit pair in the previous entangled layer is grouped together, and the last qubit of each qubit pair in the previous entangled layer is grouped together.

[0075] For example, if the two qubit pairs in the previous entanglement layer are numbered [a, b] and [c, d], then the two qubit pairs in the next entanglement layer can also be numbered [a, c] and [b, d]. This method allows for a convenient and efficient determination of the two qubit pairs in the next entanglement layer.

[0076] As an example, this method of determination allows the number of quantum entanglement gates in each entanglement layer to be the same, which in turn makes it possible to add other logic gates (such as quantum rotation gates) at the intervals between each entanglement layer in order to obtain a specific quantum state.

[0077] In some embodiments, step 202 (determining the pairs of qubits acting by each quantum entanglement gate in the first entanglement layer along the action sequence) may specifically include:

[0078] It can be determined that by pairing adjacent qubits together, qubit pairs with each quantum entanglement gate can be obtained.

[0079] As an example, pairing adjacent qubits together in the first entanglement layer can reduce the overhead of swap gates to some extent, thus simplifying quantum circuits.

[0080] In some embodiments, in a quantum circuit, each entanglement layer is preceded by a rotating logic gate that acts on each quantum circuit.

[0081] As an example, since some quantum states are quite special, a rotating logic gate acting on each quantum circuit is included before each entanglement layer. This allows the quantum circuit to prepare most quantum states, and thus facilitates its application to fields such as image processing and text translation (fields that require joint analysis of multiple feature information).

[0082] In some embodiments, step 201 (determining the number of entanglement layers based on the relationship between the total number of qubits to be used in the quantum circuit and powers of 2) may specifically include:

[0083] When the total number of qubits is greater than a first power of 2 and less than or equal to a second power of 2, the exponent value corresponding to the second power is determined as the number of entanglement layers.

[0084] For example, powers of 2 can include 2, 4, 8, 16, 32, etc., and the first and second powers can be two consecutive powers. For instance, when the total number of qubits is 5, the first power can be 4, and the second power can be 8. Correspondingly, 2... 3 =8, therefore, the number of entanglement layers can be 3. For example, if the total number of qubits is 11, then the first power can be 8, and the second power can be 16. In this case, the number of entanglement layers can be 4.

[0085] As an example, determining the number of entanglement layers based on powers of 2 can avoid both an excessive number of quantum entanglement gates in each entanglement layer and an excessive number of entanglement layers.

[0086] That is, the exponent value of 2 can indicate the number of entanglement layers. In this way, each entanglement layer usually only needs half the number of quantum entanglement gates of the total number of qubits (when it is an odd number, the number of quantum entanglement gates can be half the number of qubits rounded up), thereby reducing the number of quantum entanglement gates in each layer.

[0087] Furthermore, since rotating logic gates can be set before each entanglement layer, it helps to achieve precise superposition of quantum states, which helps to make the final quantum state more accurate.

[0088] The following examples will be provided to better illustrate the ideas presented in this disclosure:

[0089] Assume the number of qubits to be used in the quantum circuit is n, and n = 2. m Here, m is a positive integer. And if the qubits are ordered sequentially as 1, 2, 3, 4…n, then entanglement and connection can be established as follows:

[0090] The pairwise entangled bits of the first entangled layer are:

[0091] [1, 2], [3, 4], ..., [2 m -1,2 m ]

[0092] The pairwise entangled bits of the second entanglement layer are:

[0093] [1, 3], [5, 7], ..., [2] m -3,2 m -1],[2,4],[6,8],...,[2 m -2,2 m ]

[0094] Entanglement continues according to this pattern. For example, the entanglement method for the k-th layer is as follows:

[0095] For the (k-1)th layer of entangled pairs, pair the first position with each pair and the second position with each pair.

[0096] For example, the second layer is [1,3],[5,7],...,[2] m -3,2 m -1],[2,4],[6,8],...,[2 m -2,2 m ].

[0097] This method allows for the entanglement of all qubits with fewer entanglement layers and fewer quantum entanglement gates.

[0098] We can continue to combine Figure 3To explain, Figure 3 This disclosure can be understood as a schematic diagram of a quantum circuit operating on 8 qubits, provided by... Figure 3 It is evident that only 3 entanglement layers (a dashed box can be understood as one entanglement layer) are needed to complete the entanglement of all qubits.

[0099] Furthermore, let's consider a case where the total number of qubits to be used is not a power of 2. For example, when the total number of qubits to be used is 11, 2 3 <11<2 4 Therefore, the number of entanglement layers can be determined to be 4, and the design scheme can be as follows:

[0100] The first entangled layer along the temporal direction sequentially creates entangled pairs (qubit pairs):

[0101] [1,2],[3,4],[5,6],[7,8],[9,10],11

[0102] Since it is an odd number, we remove the first one from the positive direction, and then entangle it according to the first position in the list (the entanglement method of the second entanglement layer):

[0103] 1,[3,5],[7,9],[2,4],[6,8],[10,11]

[0104] Now, removing the last one, we get (the entanglement pattern of the third entanglement layer):

[0105] [1,3][2,7][6,10][5,9][4,8],11

[0106] Then, by removing the first one in the above order, we get (the entanglement method of the fourth entanglement layer).

[0107] 1,[3,7],[9,10],[8,11],[2,6],[4,5]

[0108] Taken together, this completes the four layers of entanglement.

[0109] Similarly, it can be easily expanded from 11 bits to 16 bits, then entangled with the 16 bits as described above, and finally all entangled pairs containing bits 12-16 are removed. That is, when a superposition state of 11 qubits is needed, it can also be accomplished using 16 bits, and this method makes it easier and more efficient to determine the construction of quantum circuits.

[0110] It should be noted that each layer in the above method produces a separate qubit, which can be entangled with any other qubit.

[0111] We can continue to combine Figure 4 and Figure 5 Explain the effects of this disclosure. Figure 4 A comparison diagram of quantum circuits generated based on the ideas of this disclosure and quantum circuits configured based on chip hardware in related technologies, showing the preparation of quantum states. Figure 4 In the diagram, the vertical axis represents the difference from the real quantum state, and the horizontal axis represents the number of qubits. The blue line can characterize the difference between the quantum state prepared by the quantum circuit of this disclosure and the real quantum state (ideal quantum state), while the yellow line can characterize the difference between the quantum state prepared by the quantum circuit in related technologies and the real quantum state. It can be seen that the overall difference between the quantum state prepared by the quantum circuit of this disclosure and the real quantum state is slightly smaller.

[0112] And continue to combine Figure 5 , Figure 5 A comparison chart showing the ability of quantum circuits generated by the ideas of this disclosure to solve for the Hamiltonian ground state with quantum circuits based on chip hardware configurations in related technologies is presented. Figure 5 In the figure, the vertical axis represents the loss value and the horizontal axis represents the number of iterations. The blue line represents the ability of the quantum circuit of this disclosure to solve for the Hamiltonian ground state, while the yellow line represents the ability of the quantum circuit in related technologies to solve for the Hamiltonian ground state. It can be seen that the method of this disclosure has certain advantages in solving for the Hamiltonian ground state.

[0113] In some embodiments, this disclosure also provides a quantum circuit that can be generated using the quantum circuit generation method described above. Since the quantum circuit generated by the quantum circuit generation method has a relatively simple structure, it is more conducive to the realization of the quantum circuit at the quantum chip level.

[0114] Figure 6 A schematic diagram of a quantum circuit generation apparatus according to an embodiment of this application is shown. The apparatus includes:

[0115] The first determining unit 601 is used to determine the number of entanglement layers based on the relationship between the total number of qubits to be acted on in the quantum circuit and the power of 2; wherein each entanglement layer includes multiple quantum entanglement gates acting on two qubits, and in each entanglement layer, each qubit is acted on by a quantum entanglement gate at least once.

[0116] The second determining unit 602 is used to determine the qubit pairs acting by each quantum entanglement gate in the first entanglement layer along the action sequence, and to determine the qubit pairs acting by each quantum entanglement gate in the next entanglement layer based on the qubit pairs acting by each quantum entanglement gate in the previous entanglement layer along the action sequence; wherein the qubit pairs acting by each quantum entanglement gate in the next entanglement layer are different from the qubit pairs acting by each quantum entanglement gate in the previous entanglement layer.

[0117] The generation unit 603 is used to generate the above-mentioned quantum circuit based on the determined number of entanglement layers and the qubit pairs of each quantum entanglement gate in each entanglement layer.

[0118] In some embodiments, the second determining unit 602 is further configured to: group the qubits in the total set of qubits;

[0119] Based on the team formation results, determine the qubit pairs that act on each quantum entanglement gate in the first entanglement layer;

[0120] The above-mentioned teaming of qubits includes:

[0121] When the total number of qubits is odd, the first qubit is selected from the total set of qubits according to the positional relationship between each qubit in the total set of qubits. The remaining qubits in the total set of qubits, except for the first qubit, are paired up in pairs. The first qubit is paired with any of the remaining qubits.

[0122] or,

[0123] When the total number of qubits is even, the qubits in the total set of qubits are paired up.

[0124] In some embodiments, the second determining unit 602 is further configured to: generate two qubit pairs in the next entangled layer based on the two qubit pairs in the previous entangled layer.

[0125] In response to the detection that each quantum bit pair in the previous entanglement layer has been selected at least once to generate two quantum bit pairs in the next entanglement layer, the quantum bit pairs that have obtained the quantum entanglement gates in the next entanglement layer are determined.

[0126] In some embodiments, generating two qubit pairs for the next entangled layer based on two qubit pairs in the previous entangled layer includes:

[0127] The first qubit of each qubit pair in the previous entangled layer is grouped together, and the last qubit of each qubit pair in the previous entangled layer is grouped together.

[0128] In some embodiments, the first determining unit 601 is further configured to: determine the exponent value corresponding to the second power as the number of entangled layers when the total number of qubits is greater than a first power of 2 and less than or equal to a second power of 2, wherein the first power and the first power are adjacent powers in the set of powers of 2.

[0129] In some embodiments, in the above-described quantum circuit, each entanglement layer is preceded by a rotating logic gate that acts on each quantum circuit.

[0130] Figure 7 A schematic diagram of the structure of a computer device provided in one embodiment of this application is shown, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the functions of the computer system of the quantum circuit generation method in any of the above embodiments.

[0131] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the functions of the computer system of the quantum circuit generation method in any of the above embodiments.

[0132] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the functions of the computer system of the quantum circuit generation method in any of the above embodiments.

[0133] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0134] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0135] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0136] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0137] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0138] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0139] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0140] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0141] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0142] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0143] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0144] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0145] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for generating quantum circuits, characterized in that, include: The number of entanglement layers is determined based on the relationship between the total number of qubits to be acted on in the quantum circuit and powers of 2. Each entanglement layer includes multiple quantum entanglement gates acting on two qubits. In each entanglement layer, each qubit is acted on by a quantum entanglement gate at least once. Determine the qubit pairs acting with each quantum entanglement gate in the first entanglement layer along the action sequence, and, based on the qubit pairs acting with each quantum entanglement gate in the previous entanglement layer along the action sequence, determine the qubit pairs acting with each quantum entanglement gate in the next entanglement layer; wherein the qubit pairs acting with each quantum entanglement gate in the next entanglement layer are different from the qubit pairs acting with each quantum entanglement gate in the previous entanglement layer. The quantum circuit is generated based on the determined number of entanglement layers and the pairs of qubits acting by each quantum entanglement gate in each entanglement layer.

2. The method according to claim 1, characterized in that, The determination of the qubit pairs acting by each quantum entanglement gate in the first entanglement layer along the action sequence includes: Group the individual qubits in the total set of qubits; Based on the team formation results, determine the qubit pairs that act on each quantum entanglement gate in the first entanglement layer; The process of grouping the qubits together includes: When the total number of qubits is odd, according to the positional relationship between each qubit in the total set of qubits, the first qubit is selected from the total set of qubits, the remaining qubits in the total set of qubits except the first qubit are paired up, and the first qubit is paired with any of the remaining qubits. or, When the total number of qubits is even, the qubits in the total set of qubits are grouped into pairs.

3. The method according to claim 1, characterized in that, The step of determining the qubit pairs acting with each quantum entanglement gate in the next entanglement layer based on the qubit pairs acting with each quantum entanglement gate in the previous entanglement layer along the action time sequence includes: Based on the two qubit pairs in the previous entanglement layer, generate the two qubit pairs in the next entanglement layer; In response to the detection that each quantum bit pair in the previous entangled layer has been selected at least once to generate two quantum bit pairs in the next entangled layer, the quantum bit pairs that are used to obtain each quantum entanglement gate in the next entangled layer are determined.

4. The method according to claim 3, characterized in that, The step of generating two qubit pairs for the next entangled layer based on two qubit pairs in the previous entangled layer includes: The first qubit of each qubit pair in the previous entangled layer is grouped together, and the last qubit of each qubit pair in the previous entangled layer is grouped together.

5. The method according to claim 1, characterized in that, The determination of the number of entanglement layers based on the relationship between the total number of qubits to be used in the quantum circuit and powers of 2 includes: When the total number of qubits is greater than a first power of 2 and less than or equal to a second power of 2, the exponent value corresponding to the second power is determined as the number of entangled layers, wherein the first power and the first power are adjacent powers in the set of powers of 2.

6. The method according to claim 1, characterized in that, In the quantum circuit, each entanglement layer is preceded by a rotating logic gate that acts on each quantum circuit.

7. A quantum circuit, characterized in that, The quantum circuit is generated using the quantum circuit generation method described in any one of claims 1-6.

8. A quantum circuit generation device, characterized in that, include: The first determining unit is used to determine the number of entanglement layers based on the relationship between the total number of qubits to be acted on in the quantum circuit and the power of 2; wherein each entanglement layer includes multiple quantum entanglement gates acting on two qubits, and in each entanglement layer, each qubit is acted on by a quantum entanglement gate at least once; The second determining unit is used to determine the qubit pairs acting by each quantum entanglement gate in the first entanglement layer along the action sequence, and to determine the qubit pairs acting by each quantum entanglement gate in the next entanglement layer based on the qubit pairs acting by each quantum entanglement gate in the previous entanglement layer along the action sequence; wherein the qubit pairs acting by each quantum entanglement gate in the next entanglement layer are different from the qubit pairs acting by each quantum entanglement gate in the previous entanglement layer. A generation unit is used to generate the quantum circuit based on a determined number of entangled layers and the pairs of qubits acting by each quantum entanglement gate in each entangled layer.

9. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to perform the method as described in any one of claims 1-6.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in any one of claims 1-6.

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