Shift register and display panel

Abstract

The invention discloses a shift register and a display panel. The shift register comprises an output adjusting module, a first input end of the output adjusting module inputs a first clock signal, a second input end of the output adjusting module inputs a first power supply signal, and the output adjusting module is used for adjusting the shift register to output the first clock signal or the first power supply signal according to signals on a first control node and a second control node; the trigger write-in module is used for writing a trigger signal into a second control node according to a clock signal of a control end of the trigger write-in module; the node adjusting module is used for adjusting a signal on the first control node, and the node adjusting module comprises a power supply introduction sub-module and a first adjusting sub-module; the power supply lead-in sub-module is used for leading a first power supply signal to the control end of the first adjusting sub-module according to a second clock signal; the first adjusting sub-module is used for adjusting the signal on the first control node according to the signal of the control end of the first adjusting sub-module. The shift register disclosed by the embodiment of the invention outputs a multi-pulse signal.

Description

[0001] This application is a divisional application of application number 202011356073.6, filed on 2020 / 11 / 26. Technical Field

[0002] This invention relates to the field of shift register technology, and more particularly to a shift register and a display panel. Background Technology

[0003] Shift registers can shift input signals and output them. In modern electronic circuits, shift registers, such as those used in display panels, can provide the necessary scanning signals for the display panel and have important applications in display panels.

[0004] However, existing display panels use multi-pulse scanning signals, while existing shift registers can only output single-pulse scanning signals, limiting the further application of shift registers. Summary of the Invention

[0005] The present invention provides a shift register and a display panel, so that the shift register can output a multi-pulse scanning signal.

[0006] In a first aspect, embodiments of the present invention provide a shift register, the shift register comprising: an output adjustment module, wherein a first clock signal is input to a first input terminal of the output adjustment module, and a first power supply signal is input to a second input terminal of the output adjustment module, the output adjustment module being configured to adjust the output of the shift register to the first clock signal or the first power supply signal according to signals on a first control node and a second control node; a trigger write module, wherein the trigger write module is configured to write a trigger signal to the second control node according to a clock signal on its control terminal; and a node adjustment module, wherein the node adjustment module is configured to adjust signals on the first control node, the node adjustment module comprising a power supply submodule and a first adjustment submodule; the power supply submodule being configured to lead the first power supply signal to the control terminal of the first adjustment submodule according to a second clock signal; and the first adjustment submodule being configured to adjust signals on the first control node according to signals on its own control terminal.

[0007] Optionally, the trigger write module includes: a first trigger write submodule, the first trigger write submodule being connected between the input terminal and the output terminal of the trigger write module, and the control terminal of the first trigger write submodule being connected to the first clock signal; and / or, the trigger write module includes a second trigger write submodule, the second trigger write submodule being connected between the input terminal and the output terminal of the trigger write module, and the control terminal of the second trigger write submodule being connected to the second clock signal.

[0008] Optionally, the trigger write module includes a first trigger write submodule and a second trigger write submodule, wherein the first trigger write submodule and the second trigger write submodule are connected in series between the input and output terminals of the trigger write module; the first clock signal includes a first turn-on pulse for turning on the first trigger write submodule, and the second clock signal includes a second turn-on pulse for turning on the second trigger write submodule, wherein the first turn-on pulse and the second turn-on pulse at least partially overlap.

[0009] Optionally, the shift register further includes: a second adjustment submodule, the control terminal of the second adjustment submodule being electrically connected to the second control node, the first terminal of the second adjustment submodule being connected to a second power supply signal or the first clock signal, and the second terminal of the second adjustment submodule being electrically connected to the first control node.

[0010] Optionally, the first terminal of the first adjustment submodule is connected to a third clock signal, and the second terminal of the first adjustment submodule is electrically connected to the first control node; the shift register further includes: a third adjustment submodule and a first storage module; the input terminal of the third adjustment submodule is connected to a second power supply signal, the first control terminal of the third adjustment submodule is electrically connected to the control terminal of the first adjustment submodule, the second control terminal of the third adjustment submodule is electrically connected to the second control node, the first output terminal of the third adjustment submodule is electrically connected to the first terminal of the first storage module, and the second output terminal of the third adjustment submodule is electrically connected to the first terminal of the first adjustment submodule; the third adjustment submodule is used to provide the second power supply signal to the first storage module and to provide the third clock signal to the first adjustment submodule.

[0011] Optionally, the shift register further includes: a first holding module, the first end of which is electrically connected to the second control node, and the second end of which is connected to a third clock signal.

[0012] Optionally, the output adjustment module includes: a first output module, the control terminal of the first output module being electrically connected to the first control node, and the first terminal of the first output module being connected to the first clock signal; and a second output module, the control terminal of the second output module being electrically connected to the second control node, the first terminal of the second output module being connected to the first power signal, and the second terminal of the second output module being shorted to the second terminal of the first output module for outputting the output signal of the shift register.

[0013] Optionally, the control terminal of the power supply submodule is connected to a second clock signal, the first terminal of the power supply submodule is connected to the first power signal, and the second terminal of the power supply submodule is electrically connected to the control terminal of the first adjustment submodule; the node adjustment module further includes: a second holding submodule, the first terminal of the second holding submodule is electrically connected to the control terminal of the first adjustment module, and the second terminal of the second holding submodule is electrically connected to the first control node.

[0014] Optionally, the shift register further includes a clock writing module, the control terminal of which is electrically connected to the second control node, the first terminal of which is connected to a second clock signal, and the second terminal of which is electrically connected to the control terminal of the first adjustment submodule.

[0015] In a second aspect, embodiments of the present invention also provide a display panel, including at least one gate driving circuit located in the non-display area of ​​the display panel, the gate driving circuit including a plurality of cascaded shift registers as described in the first aspect.

[0016] The technical solution of this embodiment of the invention employs a shift register including an output adjustment module. The first terminal of the output adjustment module receives a first clock signal, and the second terminal receives a first power signal. The output adjustment module is used to adjust the shift register outputting the first clock signal or the first power signal according to signals on its first and second control nodes. A trigger write module is used to write a trigger signal to the second control node according to the clock signal at its control terminal. A node adjustment module is used to adjust the signal on the first control node. The node adjustment module includes a power input submodule and a first adjustment submodule. The power input submodule is used to introduce the first power signal to the control terminal of the first adjustment submodule according to the second clock signal. The first adjustment submodule is used to adjust the signal on the first control node according to the signal at its own control terminal. Through the coordinated control of the trigger write module, the power input submodule, and the first adjustment submodule, the shift register's output signal can output the first clock signal at certain times and the first power signal at certain times, thereby enabling the shift register to output an output signal containing multiple pulses within one frame, i.e., the shift register can output a multi-pulse scan signal. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the circuit structure of a shift register provided in an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention; Figure 3A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention; Figure 4 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention; Figure 5 A schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention; Figure 6 A timing diagram of a shift register provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 8 for Figure 7 The timing diagram. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0019] Figure 1 This is a schematic diagram of the circuit structure of a shift register provided in an embodiment of the present invention, with reference to... Figure 1 The shift register includes: an output adjustment module 101, whose first terminal receives a first clock signal CLK1 and whose second terminal receives a first power signal VGL. The output adjustment module 101 is used to adjust the shift register output of the first clock signal or the first power signal according to the signals on its first control node N1 and second control node N2; a trigger write module 102, which is used to write a trigger signal to the second control node N2 according to the clock signal on its control terminal; and a node adjustment module, which is used to adjust the signal on the first control node N1. The node adjustment module includes a power input submodule 103 and a first adjustment submodule 104. The power input submodule 103 is used to lead the first power signal VGL to the control terminal of the first adjustment submodule 104 according to the second clock signal CLK2. The first adjustment submodule 104 is used to adjust the signal on the first control node N1 according to the signal on its own control terminal. Furthermore, the number of pulses contained in a frame of the scan signal can be controlled by controlling the duty cycle of the first clock signal CLK1 and the effective trigger signal IN (in this embodiment, for example, a high level).

[0020] Specifically, the output adjustment module 101 can control the output signal OUT of the shift register to the first clock signal CLK1 according to the control signal on the first control node N1 (e.g., active low level), and can also control the output signal OUT of the shift register to the first power signal VGL according to the control signal on the second control node N2 (e.g., active low level). The first power signal VGL can be low level. The power supply submodule 103 can be low level turned on, with its first terminal connected to the first power signal VGL, its control terminal connected to the second clock signal CLK2, and its second terminal electrically connected to the control terminal of the first adjustment submodule 104. When the power supply submodule 103 is turned on, the control terminal of the first adjustment submodule 104 is connected to the first power signal VGL, making the first adjustment submodule 104 turn on. The first terminal of the first adjustment submodule 104 is connected to the third clock signal CLK3, and its second terminal is electrically connected to the first control node N1. When the first adjustment submodule 104 is low level turned on, its first terminal is connected to the third clock signal CLK3, and its second terminal is electrically connected to the first control node N1. When 4 is turned on, the potential on the first control node N1 is adjusted, thereby causing the output signal OUT of the output adjustment module 101 to output the first clock signal CLK1; the first terminal of the trigger write module 102 is input with the trigger signal IN, the control terminal is connected to the first clock signal CLK1 and / or the second clock signal CLK2, and the second terminal is electrically connected to the second control node N2. It is turned on by the control action of the first clock signal CLK1 and / or the second clock signal CLK2, thereby controlling the potential on the second control node N2; that is, through the coordinated control of the trigger write module 102, the power supply submodule 103 and the first adjustment submodule 104, the output signal OUT of the shift register can output the first clock signal CLK1 at some times and output the first power signal VGL at some times, thereby enabling the shift register to output an output signal containing multiple pulses in one cycle (i.e., one frame), that is, the shift register can output a multi-pulse scan signal.

[0021] The technical solution of this embodiment employs a shift register including an output adjustment module. The first terminal of the output adjustment module receives a first clock signal, and the second terminal receives a first power signal. The output adjustment module is used to adjust the shift register outputting the first clock signal or the first power signal according to the signals on its first and second control nodes. A trigger write module is used to write a trigger signal to the second control node according to the clock signal at its control terminal. A node adjustment module is used to adjust the signals on the first control node. The node adjustment module includes a power input submodule and a first adjustment submodule. The power input submodule is used to introduce the first power signal to the control terminal of the first adjustment submodule according to the second clock signal. The first adjustment submodule is used to adjust the signals on the first control node according to the signals at its own control terminal. Through the coordinated control of the trigger write module, the power input submodule, and the first adjustment submodule, the shift register's output signal can output the first clock signal at certain times and the first power signal at certain times, thereby enabling the shift register to output an output signal containing multiple pulses within one frame, i.e., the shift register can output a multi-pulse scan signal.

[0022] Optionally, Figure 2 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, referred to... Figure 2 The trigger write module 102 includes: a first trigger write submodule 1021, which is connected between the input and output terminals of the trigger write module 102, and the control terminal of the trigger write submodule 102 is connected to a first clock signal CLK1; and / or, the trigger write module 102 includes a second trigger write submodule 1022, which is connected between the input and output terminals of the trigger write module 102, and the control terminal of the second trigger write submodule 1022 is connected to a second clock signal CLK2.

[0023] Specifically, the first trigger write submodule can turn its first and second terminals on or off under the control of the first clock signal CLK1 connected to its control terminal, and the second trigger write submodule 1022 can turn its first and second terminals on or off under the control of the second clock signal CLK2 connected to its control terminal; the trigger write module 102 may include at least one of the first trigger write submodule 1021 and the second trigger write submodule 1022. When the trigger write module 102 includes the first trigger write submodule 1021 and the second trigger write submodule 1022, the first trigger write submodule 1021 and the second trigger write submodule 1022 may be connected in series or in parallel; Preferably, the first trigger write submodule and the second trigger write submodule can be connected in series between the input and output terminals of the trigger write module 102. Since both the first trigger write submodule 1021 and the second trigger write submodule 1022 need to be simultaneously turned on to connect the input and output terminals of the trigger write module, the first clock signal can include a first turn-on pulse to turn on the first trigger write submodule, and the second clock signal can include a second turn-on pulse to turn on the second trigger write submodule. The first and second turn-on pulses at least partially overlap. In this embodiment, the positional relationship between the first trigger write submodule 1021 and the second trigger write submodule 1022 is not specifically limited. Figure 2 In this example, the first trigger write submodule 1021 is electrically connected to the input terminal of the trigger write module 102. In other embodiments, a second trigger write submodule 1022 may also be electrically connected to the input terminal of the trigger write module 102. By configuring the trigger write module 102 to include the first trigger write submodule 1021 and the second trigger write submodule 1022 connected in series, the resistance of the trigger write module can be increased, and the leakage current can be reduced.

[0024] Optionally, Figure 3 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, referred to... Figure 3 The shift register also includes a second adjustment submodule 105, the control terminal of the second adjustment submodule 105 is electrically connected to the second control node N2, the first terminal of the second adjustment submodule 105 is connected to the second power supply signal VGH or the first clock signal, and the second terminal of the second adjustment submodule 105 is electrically connected to the first control node N1.

[0025] Specifically, the second control node N2 can control the first control node N1 through the second adjustment submodule 105. When the second control node N2 is at a low level, that is, when the output adjustment module 101 outputs the first power signal VGL, the second adjustment submodule 105 is turned on. The second power signal VGH can be at a high level. If the first terminal of the second adjustment submodule 105 is connected to the second power signal VGH, then the first control node N1 is at a high level, further preventing the shift register from outputting the first clock signal CLK1. If the first terminal of the second adjustment submodule 105 is connected to the first clock signal CLK1, when the first clock signal CLK1 is at a low level, although the first control node N1 is at a low level, the output terminal of the shift register also outputs a low level because the first clock signal CLK1 is at a low level. When the first clock signal CLK1 is at a high level, the first control node N1 is at a high level, that is, the shift register will not output a high level at this time. In this embodiment, if the first terminal of the second adjustment submodule 105 is input with the second power signal VGH, the number of conduction cycles between the first input terminal and the output terminal of the output adjustment module can be reduced, thus extending the usage time. If the first terminal of the second adjustment submodule is connected to the first clock signal CLK1, since the potential of the first terminal of the second adjustment submodule changes frequently at this time, the hysteresis effect caused by long-term bias can be avoided.

[0026] For example, Figure 4 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, referred to... Figure 4 The output adjustment module 101 may include: a first output module 1011, the control terminal of the first output module 1011 being electrically connected to the first control node N1, and the first terminal of the first output module 1011 being connected to the first clock signal CLK1; and a second output module 1012, the control terminal of the second output module 1012 being electrically connected to the second control node N2, the first terminal of the second output module 1012 being connected to the first power supply signal VGL, and the second terminal of the second output module 1012 being shorted to the second terminal of the first output module 1011 and used to output the output signal of the shift register.

[0027] Specifically, both the first output module 1011 and the second output module 1012 can be transistors. For example, the first output module 1011 can be a first transistor M1, and the second output module 1012 can be a second transistor M2. Both the first transistor M1 and the second transistor M2 can be P-type transistors or N-type transistors. In this embodiment, the first output module 1011 and the second output module 1012 are both P-type transistors. When the first control node N1 receives a low level, the first transistor M1 turns on, causing the shift register to output the first clock signal CLK1. When the second control node N2 receives a low level, the second transistor M2 turns on, causing the shift register to output the second power supply signal VGH.

[0028] For example, both the first trigger write submodule 1021 and the second trigger write submodule 1022 can be transistors. For instance, the first trigger write submodule 1021 can be a third transistor M3, and the second trigger write submodule 1022 can be a fourth transistor M4. Both can be P-type or N-type transistors, preferably both the third transistor M3 and the fourth transistor M4 are P-type transistors. The power supply submodule 103 can be a fifth transistor M5, and the first adjustment submodule 104 can be a sixth transistor M6. Both the fifth transistor M5 and the sixth transistor M6 can be P-type or N-type transistors, preferably both are P-type transistors. The second adjustment submodule 105 can be a seventh transistor M7, which can be a P-type or N-type transistor, preferably a P-type transistor.

[0029] Optionally, continue to refer to Figure 4 The shift register also includes a third adjustment submodule and a first storage module 1081; the input terminal of the third adjustment submodule is connected to the second power supply signal VGH, the first control terminal of the third adjustment submodule is electrically connected to the control terminal of the first adjustment submodule 104, the second control terminal of the third adjustment submodule is electrically connected to the second control node N2, and the second output terminal of the second adjustment submodule is electrically connected to the first terminal of the first adjustment submodule; the third adjustment submodule is used to provide the second power supply signal VGH to the first storage module 1081 and to provide the third clock signal CLK3 to the first adjustment submodule.

[0030] Specifically, in this embodiment, the second clock signal CLK2 and the third clock signal CLK3 can be signals with opposite timing sequences. It is understood that the second clock signal CLK2 and the third clock signal CLK3 can also have a certain time margin. In this embodiment, the first storage module 1081 can be the first capacitor C1, and the third adjustment submodule can include the first switch module 106 and the second switch module 107. Both the first switch module 106 and the second switch module 107 can be P-type transistors or N-type transistors. For example, the first switch module is a P-type eighth transistor M8, and the second switch module is a P-type ninth transistor M9. The first terminal of the eighth transistor M8 serves as the input terminal of the third adjustment submodule, the control terminal of the eighth transistor M8 serves as the first control terminal of the third adjustment submodule, and the second terminal of the eighth transistor M8 serves as the first output terminal of the third adjustment submodule. The first terminal of the ninth transistor M9 is electrically connected to the second terminal of the eighth transistor M8, the control terminal of the ninth transistor M9 serves as the second control terminal of the third adjustment submodule, and the second terminal of the ninth transistor M9 serves as the second output terminal of the third adjustment submodule. In this embodiment, the first terminal of the first storage module 1081 is electrically connected to the third adjustment submodule. When the third clock signal CLK3 changes, the changing signal will not be coupled to the output terminal of the shift register, thereby improving the stability of the shift register.

[0031] Optionally, Figure 5 This is a schematic diagram of the circuit structure of another shift register provided in an embodiment of the present invention, and... Figure 4 The structure shown is different in that, Figure 5 In the shift register shown, the second terminal of the ninth transistor M9 is electrically connected to the second control node, the control terminal of the ninth transistor M9 is connected to the third control signal CLK3, and it also includes a first holding module 1082. The first terminal of the first holding module 1082 is electrically connected to the second control node, and the second terminal of the first holding module 1082 is connected to the third clock signal.

[0032] Specifically, in this embodiment, the eighth transistor M8 and the ninth transistor M9 can serve as the control path for the first control node N1 to feed back and control the second control node N2. When the first control node N1 is at a low level, the eighth transistor M8 is controlled to turn on, and at the same time, the third clock signal CLK3 controls the ninth transistor M9 to turn on or off. Through the cooperation of the first holding module 1082, the control terminal of the second transistor M2 is kept at a high level, that is, kept off, to prevent the shift register from outputting the first power supply signal VGL.

[0033] Optionally, continue to refer to Figure 4 and Figure 5 The control terminal of the power supply submodule 103 is connected to the second clock signal CLK2, the first terminal of the power supply submodule 103 is connected to the first power signal VGL, and the second terminal of the power supply submodule 103 is electrically connected to the control terminal of the first adjustment submodule 104. The node adjustment module also includes a second holding submodule 109, the first terminal of the second holding submodule 109 is electrically connected to the control terminal of the first adjustment submodule 104, and the second terminal of the second holding submodule 109 is electrically connected to the first control node.

[0034] Specifically, the second holding submodule 109 can be a second capacitor C2. The second capacitor C2 can maintain the potential of the control terminal of the first adjustment submodule 104, keeping it on or off, thereby improving the stability of the shift register output signal.

[0035] Optionally, continue to refer to Figure 4 and Figure 5 The shift register also includes a clock writing module 110, the control terminal of which is electrically connected to the second control node, the first terminal of which is connected to the second clock signal CLK2, and the second terminal of which is electrically connected to the control terminal of the first adjustment submodule.

[0036] Specifically, the clock writing module 110 can be turned on when the second clock signal CLK2 is high and the trigger signal IN is low, inputting a high-level signal to the control terminal of the first adjustment module to prevent the first adjustment module from being mistakenly turned on, thereby preventing the first output module 1011 from being mistakenly turned on, and further improving the stability of the shift register operation. The clock writing module can be, for example, the tenth transistor M10, which can be, for example, a P-type transistor or an N-type transistor, preferably a P-type transistor with a dual-gate structure.

[0037] Optionally, the shift register may also include a third capacitor C3, with the first end of the third capacitor C3 connected to the first clock signal CLK1, and the second end of the third capacitor C3 electrically connected to the first control node.

[0038] The third capacitor C3 can be a capacitor to maintain the potential on the first control node N1, so that when the first adjustment module 104 is turned off, the control terminal of the first output module 1011 can be kept at a low level, thereby ensuring that the shift register outputs the first clock signal CLK1 normally.

[0039] Optionally, continue to refer to Figure 4 and Figure 5 The shift register may also include one or more of the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15, and the sixteenth transistor M16; the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, the fifteenth transistor M15, and the sixteenth transistor M16 are all normally open transistors, which can be used to block current to reduce the leakage current of the shift register and further improve stability.

[0040] Optionally, the shift register may also include a fourteenth transistor M16, which is connected between the first control node and the second terminal of the first adjustment submodule. It is used to isolate the second capacitor C2 from the first transistor M1, so as to avoid the influence of the signal on the second capacitor C2 on the signal on the control terminal of the first transistor M1 when the third clock signal CLK3 is high, and further improve the stability of the shift register operation.

[0041] For example, Figure 6 A timing diagram of a shift register provided in an embodiment of the present invention can correspond to... Figure 4 or Figure 5 The shift register shown is, for example Figure 6 As shown, During the first time period T1, when the trigger signal IN is low and the first clock signal CLK1 and the third clock signal CLK3 are both at low levels, the second transistor M2 is turned on, and the shift register outputs the first power supply signal VGL. When the trigger signal IN is high, the high level is written to the control terminal of the second transistor M2, and the shift register has no output. At this time, the output terminal of the shift register is kept low by the load capacitor of the display area of ​​the display panel, and the tenth transistor M10 is turned off, and the control terminal of the sixth transistor M6 stores a low potential. During the second time period T2: the third clock signal CLK3 changes from high to low potential. The low potential of the third clock signal CLK3 is written into the control electrode of the first transistor M1, and the output signal OUT starts to output the first clock signal CLK1. It should be noted that whether the first clock signal CLK1 changes from high to low potential or from low to high potential, the output signal OUT will follow the first clock signal CLK1. During the third time period T3, the trigger signal IN is low and has been pre-written to the control terminal of the second transistor M2. The third clock signal CLK3 transitions from high to low, causing the second transistor M2 to output a low level. This achieves the output of a multi-pulse scan signal S1 within one frame. The scan signal S1 can be shifted using a cascaded shift register.

[0042] This invention also provides a display panel, such as... Figure 7 As shown, Figure 7 This is a schematic diagram of a display panel structure provided in an embodiment of the present invention. The display panel 100 includes at least one gate driving circuit located in the non-display area NAA. Figure 7 An exemplary gate driving circuit is shown, each gate driving circuit including multiple cascaded shift registers 100 as provided in any embodiment of the invention. Therefore, the display panel provided by the present invention has the aforementioned beneficial effects, which will not be repeated here. The output terminal of each shift register 100 is electrically connected to the corresponding scan signal line 260 in the display panel. The output signal of each shift register 100 is transmitted to the corresponding scan signal line 260 in the display panel. The pixel unit 1 located in the display area 1 emits light under the control of the scan signal transmitted by the corresponding scan signal line 260 and the data signal transmitted by the corresponding data signal line. Exemplarily, Figure 8 for Figure 7 The timing diagram, combined with Figure 7 and Figure 8The display panel may also include multiple clock signal lines, such as a first clock signal line 210, a second clock signal line 220, a third clock signal line 230, and a fourth clock signal line 240. The display panel may also include a trigger input signal line 250, which is used to input a trigger signal IN. The first clock signal line is used to input a first clock signal CLK1, the second clock signal line is used to input a second clock signal CLK2, the third clock signal line is used to input a third clock signal CLK3, and the fourth clock signal line is used to input a fourth clock signal CLK4. For example... Figure 8 As shown, the first clock signal CLK1 and the second clock signal CLK2 can be inverted clock signals, and the third clock signal CLK3 and the fourth clock signal CLK4 can be opposite clock signals. The shift register 100 includes a first clock signal input terminal Clk01, a second clock signal input terminal Clk02, and a third clock signal input terminal Clk03, which are used to input the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3, respectively. In this embodiment, the first clock signal input terminal Clk01 of the even-numbered shift register can be electrically connected to the first clock signal line 210, and the second clock signal input terminal Clk02 of the even-numbered shift register can be electrically connected to the second clock signal line 210. The even-level shift register's third clock signal input terminal Clk03 is electrically connected to the third clock signal line 230, the odd-level shift register's first clock signal input terminal Clk01 is electrically connected to the second clock signal line 220, the odd-level shift register's second clock signal input terminal Clk02 is electrically connected to the first clock signal line 210, and the odd-level shift register's third clock signal input terminal Clk03 is electrically connected to the fourth clock signal line 240, thereby realizing the step-by-step shift output of the shift register output signals (first-level shift register output signal S1, second-level shift register output signal S2, third-level shift register output signal S3, and fourth-level shift register output signal S4).

[0043] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A shift register, characterized in that, The shift register includes: An output adjustment module is provided, wherein a first clock signal is input to the first input terminal of the output adjustment module, and a first power supply signal is input to the second input terminal of the output adjustment module. The output adjustment module is used to adjust the output of the shift register to the first clock signal or the first power supply signal according to the signals on its first control node and second control node. The signal used by the output adjustment module to output a high level is the same as the first clock signal. The first power supply signal is a low level. A trigger write module is used to write a trigger signal to the second control node according to the clock signal of its control terminal; A node adjustment module, which is used to adjust the signal on the first control node, includes a power supply submodule and a first adjustment submodule. The power input submodule is used to direct the first power signal to the control terminal of the first adjustment submodule according to the second clock signal; The first adjustment submodule is used to adjust the signal on the first control node according to the signal from its own control terminal; The trigger write module includes: A first trigger write submodule and a second trigger write submodule are connected in series. The first trigger write submodule and the second trigger write submodule are connected between the input terminal and the output terminal of the trigger write module. The control terminal of the first trigger write submodule is connected to the first clock signal. The control terminal of the second trigger write submodule is connected to the second clock signal; The shift register also includes: The second adjustment submodule has its control terminal electrically connected to the second control node, its first terminal connected to the first clock signal, and its second terminal electrically connected to the first control node.

2. The shift register according to claim 1, characterized in that, The trigger write module includes a first trigger write submodule and a second trigger write submodule, wherein the first trigger write submodule and the second trigger write submodule are connected in series between the input and output terminals of the trigger write module; The first clock signal includes a first turn-on pulse for turning on the first trigger write submodule, and the second clock signal includes a second turn-on pulse for turning on the second trigger write submodule, wherein the first turn-on pulse and the second turn-on pulse at least partially overlap.

3. The shift register according to claim 1, characterized in that, The first terminal of the first adjustment submodule is connected to a third clock signal, and the second terminal of the first adjustment submodule is electrically connected to the first control node; the shift register further includes: a third adjustment submodule and a first storage module; The input terminal of the third adjustment submodule is connected to a second power signal. The first control terminal of the third adjustment submodule is electrically connected to the control terminal of the first adjustment submodule. The second control terminal of the third adjustment submodule is electrically connected to the second control node. The first output terminal of the third adjustment submodule is electrically connected to the first terminal of the first storage module. The second output terminal of the third adjustment submodule is electrically connected to the first terminal of the first adjustment module. The third adjustment submodule is used to provide the second power signal to the first storage module and to provide the third clock signal to the first adjustment submodule.

4. The shift register according to claim 1, characterized in that, The shift register also includes: The first holding module has its first end electrically connected to the second control node, and its second end connected to a third clock signal.

5. The shift register according to claim 1, characterized in that, The output adjustment module includes: The first output module has its control terminal electrically connected to the first control node, and its first terminal is connected to the first clock signal. The second output module has its control terminal electrically connected to the second control node. The first terminal of the second output module is connected to the first power signal, and the second terminal of the second output module is shorted to the second terminal of the first output module to output the output signal of the shift register.

6. The shift register according to claim 1, characterized in that, The control terminal of the power supply submodule is connected to the second clock signal, the first terminal of the power supply submodule is connected to the first power signal, and the second terminal of the power supply submodule is electrically connected to the control terminal of the first adjustment submodule. The node adjustment module also includes: The second holding submodule has a first end electrically connected to the control end of the first regulating submodule, and a second end electrically connected to the first control node.

7. The shift register according to claim 1, characterized in that, The shift register also includes: A clock writing module, wherein the control terminal of the clock writing module is electrically connected to the second control node, the first terminal of the clock writing module is connected to a second clock signal, and the second terminal of the clock writing module is electrically connected to the control terminal of the first adjustment submodule.

8. The shift register according to claim 1, characterized in that, The third adjustment submodule includes a first switch module and a second switch module. The first switch module includes an eighth transistor, and the second switch module includes a ninth transistor. The first terminal of the eighth transistor is connected to a second power supply signal, the voltage of which is greater than the voltage of the first power supply signal. The control terminal of the eighth transistor is electrically connected to the control terminal of the first adjustment submodule. The second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor. The control terminal of the ninth transistor is electrically connected to the second control node. The second terminal of the ninth transistor is connected to the third clock signal.

9. A shift register, characterized in that, The shift register includes: An output adjustment module is provided, wherein a first clock signal is input to the first input terminal of the output adjustment module, and a first power supply signal is input to the second input terminal of the output adjustment module. The output adjustment module is used to adjust the output of the shift register to the first clock signal or the first power supply signal according to the signals on its first control node and second control node. The signal used by the output adjustment module to output a high level is the same as the first clock signal. The first power supply signal is a low level. A trigger write module is used to write a trigger signal to the second control node according to the clock signal of its control terminal; A node adjustment module is used to adjust the signal on the first control node. The node adjustment module includes a power supply submodule and a first adjustment submodule. The power supply submodule is used to lead the first power signal to the control terminal of the first adjustment submodule according to a second clock signal. The first adjustment submodule is used to adjust the signal on the first control node according to the signal at its own control terminal. The shift register also includes: The second adjustment submodule has its control terminal electrically connected to the second control node, its first terminal connected to the first clock signal, and its second terminal electrically connected to the first control node. The trigger write module includes: a first trigger write submodule and a second trigger write submodule connected in series. The first trigger write submodule and the second trigger write submodule are connected between the input terminal and the output terminal of the trigger write module. The control terminal of the first trigger write submodule is connected to the first clock signal. The control terminal of the second trigger write submodule is connected to the second clock signal. The third adjustment submodule includes a first switch module and a second switch module. The first switch module includes an eighth transistor, and the second switch module includes a ninth transistor. The first terminal of the eighth transistor is connected to a second power supply signal, the voltage of which is greater than the voltage of the first power supply signal. The control terminal of the eighth transistor is electrically connected to the control terminal of the first adjustment submodule. The second terminal of the eighth transistor is electrically connected to the first terminal of the ninth transistor. The control terminal of the ninth transistor is electrically connected to the second control node. The second terminal of the ninth transistor is connected to the third clock signal.

10. A display panel, characterized in that, It includes at least one gate driving circuit located in the non-display area of ​​the display panel, the gate driving circuit including a plurality of cascaded shift registers as described in any one of claims 1-9.

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