H-bridge driving control circuit and driving method thereof

Abstract

The invention provides an H-bridge driving control circuit and a driving method thereof, and the driving circuit comprises the steps: providing an initial driving signal and a digital signal through a control module, carrying out the logic conversion of the initial driving signal through a logic conversion module, thereby outputting a power driving signal, and responding to the power driving signal through an H-bridge power level module. And the current management module is used for providing bidirectional driving current for the load and controlling the driving current under the driving of the digital signal and the power driving signal. According to the H-bridge driving control circuit provided by the invention, a logic control design of'software + hardware 'is used, only two control ports are used, and compared with the prior art, the H-bridge driving control circuit has the advantages that the resource utilization is reduced, the abnormal risk of a system is reduced, the condition of'same-side' conduction is avoided, and the robustness of the circuit is improved; the reverse induced voltage of the load is reduced, so that the reliability of the circuit is improved; by adjusting the value of the digital signal, the change speed and magnitude of the driving current are adjusted so as to adapt to different speed and load conditions, and the response performance is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit drive design, and in particular to an H-bridge drive control circuit and its driving method. Background Technology

[0002] H-bridge circuits, as a classic driver for inductive loads such as DC motors and electromagnetic coils, are widely used in industrial automation, robotics, and automotive electronics due to their ability to control current direction and provide dynamic braking. However, as system requirements for drive efficiency, stability, and response speed increase, the challenges of inductive shock suppression and bridge arm shoot-through protection in practical operation are becoming increasingly prominent, posing a key technical bottleneck to their further adoption in high-reliability applications.

[0003] Currently, there are three limitations in suppressing the discharge of reverse induced electromotive force from inductive loads and protecting against short-circuit risks in the same-side arms of an H-bridge: First, the reverse induced energy generated when the inductive load is turned off is generally addressed by using the freewheeling current of the bridge arm power transistors or external freewheeling devices to construct a current path, while a passive absorption circuit is added at the load end to reduce induced voltage surges. Although this method can maintain basic freewheeling, the absorption circuit has high energy consumption and cannot actively suppress voltage spikes, resulting in low energy utilization efficiency. Second, in H-bridge drive control, four externally input drive levels are generally used to drive the upper and lower bridge arm MOSFETs in the H-bridge. After switching levels, bidirectional current drive of the load is achieved. Although this method is simple in structure, it does not fully consider the potential for drive logic disorder caused by software malfunctions or main control chip hardware failures, which can easily lead to simultaneous conduction of the same-side arms, forming a shoot-through short circuit and seriously threatening circuit reliability. Thirdly, the protection mechanisms of H-bridge circuits mostly employ reactive strategies, such as using TVS diodes for overvoltage clamping or implementing system shutdown through overcurrent detection. This type of protection is passive and delayed, only intervening after a voltage spike or shoot-through current fault occurs. While it can prevent complete system damage, it cannot eliminate the impact stress and shoot-through risk at the root. In some precision current control scenarios, it is necessary to combine the H-bridge circuit with a constant current source circuit to provide a stable and controllable drive current.

[0004] Therefore, how to provide a technical solution for an H-bridge drive control circuit that can not only cope with reverse induced energy and avoid bridge arm shoot-through, but also provide active protection is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This invention provides an H-bridge drive control circuit and its driving method to solve the problems of insufficient reduction of reverse induction energy, shoot-through short circuit in bridge arms, and slow response of protection mechanisms in existing H-bridges.

[0006] The present invention provides an H-bridge drive control circuit, comprising:

[0007] The control module provides initial drive signals and digital signals; A logic conversion module, connected to the control module, performs logic conversion on the initial drive signal to obtain a power drive signal; The H-bridge power stage module is connected to the logic conversion module and provides bidirectional drive current to the load in response to the power drive signal. The current management module is connected to both the control module and the logic conversion module, and controls the drive current under the influence of the digital signal and the power drive signal.

[0008] In one embodiment of the present invention, the H-bridge power stage module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and the load. The source of the first PMOS transistor is connected to a first power supply voltage, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. A first terminal of the load is connected to the drain of the first PMOS transistor, a second terminal of the load is connected to the drain of the second PMOS transistor, and the source of the first NMOS transistor is connected to the source of the second NMOS transistor. The gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are the control terminals of the H-bridge power stage module.

[0009] In one embodiment of the present invention, the current management module includes a voltage acquisition unit and a feedback adjustment unit. The voltage acquisition unit is connected to the H-bridge power stage module and the feedback adjustment unit to sample the voltage of the H-bridge power stage module to obtain a sampled voltage. The feedback adjustment unit is connected to the control module and generates a reference voltage under the drive of the digital signal. It then generates a drive voltage based on the reference voltage and the sampled voltage. Under the control of the power drive signal, the drive voltage is input to the corresponding switching transistor to drive the H-bridge power stage module to operate.

[0010] In one embodiment of the present invention, the voltage acquisition unit includes a first transient voltage suppression diode and a first resistor. The first terminal of the first transient voltage suppression diode is connected to the first terminal of the first resistor, and the second terminal of the first transient voltage suppression diode is connected to the second terminal of the first resistor. The second terminal of the first resistor is also grounded. The first terminal of the first resistor outputs the sampling voltage.

[0011] In one embodiment of the present invention, the feedback adjustment unit includes a first chip, a second chip, a second resistor, a third resistor, a fourth resistor, a first capacitor, and an operational amplifier. The power supply terminal of the first chip is connected to a second power supply voltage. The analog ground terminal and digital ground terminal of the first chip are both grounded. The output terminal of the first chip is connected to the first terminal of the second resistor. The second terminal of the second resistor is connected to the non-inverting input terminal of the operational amplifier. The inverting input terminal of the operational amplifier is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the first test terminal and the second test terminal of the second chip. The first common terminal of the second chip is connected to the first terminal of the third resistor. The second common terminal of the chip is connected to the first terminal of the fourth resistor. The power supply terminal of the second chip is connected to the second power supply voltage. The ground terminal and two floating terminals of the second chip are grounded. The reference voltage terminal of the first chip is connected to the reference voltage. The input terminal, startup terminal, and clock control terminal of the first chip are the first input terminals of the feedback adjustment unit. The inverting input terminal of the operational amplifier is the second input terminal of the feedback adjustment unit. The first input terminal of the second chip is the third input terminal of the feedback adjustment unit. The second input terminal of the second chip is the fourth input terminal of the feedback adjustment unit. The second terminal of the third resistor is the first output terminal of the feedback adjustment unit. The second terminal of the fourth resistor is the second output terminal of the feedback adjustment unit.

[0012] In one embodiment of the present invention, the power drive signal includes four H-bridge drive signals, the initial drive signal includes a first initial drive signal and a second initial drive signal, and the logic conversion module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a second capacitor, a third capacitor, a fourth capacitor, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first NPN transistor, a second NPN transistor, and a third chip. The first terminal of the fifth resistor is grounded, the first terminal of the fifth resistor is connected to the first terminal of the sixth resistor, the second terminal of the fifth resistor is connected to the first input terminal of the first NOR gate, and the second terminal of the fifth resistor is also connected to... The second input terminal of the first NOR gate is connected to the first input terminal of the second NOR gate. The output terminal of the second NOR gate is connected to the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to the gate of the first NPN transistor. The second terminal of the seventh resistor is also connected to the emitter of the first NPN transistor via the second capacitor. The emitter of the first NPN transistor is grounded. The first terminal of the eighth resistor is connected to the first power supply voltage. The second terminal of the eighth resistor is connected to the first terminal of the ninth resistor. The collector of the first NPN transistor is connected to the second terminal of the eighth resistor. The second terminal of the sixth resistor is connected to the first input terminal of the third NOR gate. The second input terminal of the third NOR gate is grounded. The output of the third NOR gate is connected to the first input of the fourth NOR gate, the second input of the fourth NOR gate is connected to the first input of the second NOR gate, the output of the fourth NOR gate is connected to the first terminal of the tenth resistor, the second terminal of the tenth resistor is connected to the gate of the second NPN transistor, the second terminal of the tenth resistor is also connected to the emitter of the second NPN transistor via the third capacitor, the emitter of the second NPN transistor is grounded, the first terminal of the eleventh resistor is connected to the first power supply voltage, the second terminal of the eleventh resistor is connected to the first terminal of the twelfth resistor, the collector of the second NPN transistor is connected to the second terminal of the eleventh resistor, and the second terminal of the ninth resistor is connected to the third core. The first input terminal of the chip is connected to the second input terminal of the twelfth resistor. The ground terminal of the third chip is grounded. The power supply terminal of the third chip is connected to the second power supply voltage. The power supply terminal of the third chip is grounded after passing through the fourth capacitor. The first input terminal of the first NOR gate is connected to the first initial drive signal. The second input terminals of the second NOR gate and the first input terminal of the third NOR gate are connected to the second initial drive signal. The second terminal of the ninth resistor outputs the first H-bridge drive signal. The second terminal of the twelfth resistor outputs the second H-bridge drive signal. The first output terminal of the third chip outputs the third H-bridge drive signal. The second output terminal of the third chip outputs the fourth H-bridge drive signal.

[0013] In one embodiment of the present invention, the H-bridge drive control circuit further includes a power protection module, which includes a fifth capacitor, a sixth capacitor, a seventh capacitor and a second transient voltage suppression diode. The first terminal of the fifth capacitor is connected to the first power supply voltage, the second terminal of the fifth capacitor is grounded, the sixth capacitor is connected in parallel with the fifth capacitor, the seventh capacitor is connected in parallel with the fifth capacitor, and the second transient voltage suppression diode is connected in parallel with the fifth capacitor.

[0014] The present invention also provides a driving method for an H-bridge drive control circuit, the driving method being applied to the H-bridge drive control circuit as described above, the driving method comprising: Acquire the initial drive signal and digital signal; The initial drive signal is logically transformed to obtain the power drive signal; Under the control of the power drive signal and the digital signal, a bidirectional drive current is provided to the load in the H-bridge power stage module, and the drive current of the load is controlled by adjusting the digital signal.

[0015] In one embodiment of the present invention, before performing logic conversion on the initial drive signal, the method further includes: acquiring a sampled voltage; generating a reference voltage based on the digital signal and the sampled voltage; and comparing the reference voltage and the sampled voltage to generate a drive voltage.

[0016] In one embodiment of the present invention, the power drive signal includes a first H-bridge drive signal, a second H-bridge drive signal, a third H-bridge drive signal, and a fourth H-bridge drive signal. The H-bridge power stage module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. Under the control of the power drive signal and the digital signal, a bidirectional drive current is provided to the load in the H-bridge power stage module, including: when the first H-bridge drive signal is low, the second H-bridge drive signal is high, the third H-bridge drive signal is high, and the fourth H-bridge drive signal is low, driving the load based on the first H-bridge drive signal. When the second PMOS transistor is turned on, the driving voltage is input to the gate of the first NMOS transistor based on the third H-bridge driving signal, so that the first NMOS transistor is turned on and a positive driving current flows through the load; when the first H-bridge driving signal is high, the second H-bridge driving signal is low, the third H-bridge driving signal is low and the fourth H-bridge driving signal is high, the first PMOS transistor is driven to turn on based on the second H-bridge driving signal, and the driving voltage is input to the gate of the second NMOS transistor based on the fourth H-bridge driving signal, so that the second NMOS transistor is turned on and a negative driving current flows through the load.

[0017] The beneficial effects of this invention are as follows: This invention provides an H-bridge drive control circuit and its driving method. The drive circuit includes: an initial drive signal and a digital signal provided by a control module; a logic conversion module performing logic conversion on the initial drive signal to output a power drive signal; an H-bridge power stage module responding to the power drive signal to provide bidirectional drive current to the load; and a current management module controlling the drive current under the drive of the digital signal and the power drive signal. The H-bridge drive control circuit provided by this invention uses a "software + hardware" logic control design and only uses two control ports, reducing resource utilization compared to existing technologies, lowering the risk of system anomalies, preventing "same-side" conduction, and improving circuit robustness. During actual operation, the reverse induced voltage of the load decreases, reducing the requirements for the H-bridge's MOSFETs and clamping circuits, thus improving circuit reliability. The speed and magnitude of the drive current change can be adjusted by adjusting the value of the digital signal, adapting to different speeds and load conditions, and improving response performance. The magnitude of the drive current can be monitored in real time by the logic conversion module, and the drive load can be stopped promptly when an anomaly occurs. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] In the attached diagram: Figure 1 This is a block diagram of an H-bridge drive control circuit provided in one embodiment of the present invention; Figure 2 This is a detailed structural diagram of the H-bridge power stage module and current management module in an H-bridge drive control circuit provided in one embodiment of the present invention; Figure 3 This is a detailed structural diagram of the logic conversion module provided in one embodiment of the present invention; Figure 4 This is a drive control logic diagram of an H-bridge drive control circuit provided in one embodiment of the present invention.

[0020] The attached figures are labeled as follows: 110 - Control module; 120 - Logic conversion module; 130 - H-bridge power stage module; 140 - Current management module; L1 - Load; VDD - First power supply voltage; VSS - Second power supply voltage; Vs - Sampling voltage; Vn - Reference voltage; VREF - Reference voltage; Vd - Drive voltage; EXT - First initial drive signal; EXP - Second initial drive signal; P1 - First H-bridge drive signal; P2 - Second H-bridge drive signal; P3 - Third H-bridge drive signal; P4 - Fourth H-bridge drive signal. Detailed Implementation

[0021] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0022] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0023] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0024] H-bridge circuits, as a classic driver for inductive loads such as DC motors and electromagnetic coils, are widely used in industrial automation, robotics, and automotive electronics due to their ability to control current direction and provide dynamic braking. However, with increasing demands for drive efficiency, stability, and response speed, the challenges of inductive surge suppression and bridge arm shoot-through protection in practical operation have become increasingly prominent, posing a key technical bottleneck to their further adoption in high-reliability applications.

[0025] Currently, there are three limitations in suppressing the discharge of reverse induced electromotive force from inductive loads and protecting against short-circuit risks in the same-side arms of an H-bridge: First, the reverse induced energy generated when the inductive load is turned off is generally addressed by using the freewheeling current of the bridge arm power transistors or external freewheeling devices to construct a current path, while a passive absorption circuit is added at the load end to reduce induced voltage surges. Although this method can maintain basic freewheeling, the absorption circuit has high energy consumption and cannot actively suppress voltage spikes, resulting in low energy utilization efficiency. Second, in H-bridge drive control, four externally input drive levels are generally used to drive the upper and lower bridge arm MOSFETs in the H-bridge. After switching levels, bidirectional current drive of the load is achieved. Although this method is simple in structure, it does not fully consider the potential for drive logic disorder caused by software malfunctions or main control chip hardware failures, which can easily lead to simultaneous conduction of the same-side arms, forming a shoot-through short circuit and seriously threatening circuit reliability. Thirdly, the protection mechanisms of H-bridge circuits mostly employ reactive strategies, such as using TVS diodes for overvoltage clamping or implementing circuit shutdown through overcurrent detection. This type of protection is passive and delayed, only intervening after a voltage spike or shoot-through current fault occurs. While it can prevent complete system damage, it cannot eliminate the impact stress and shoot-through risk at the root. In some precision current control scenarios, it is necessary to combine the H-bridge circuit with a constant current source circuit to provide a stable and controllable drive current.

[0026] To solve the above problems, such as Figure 1 As shown, this application provides an H-bridge drive control circuit, including: Control module 110 provides initial drive signals and digital signals; The logic conversion module 120, connected to the control module 110, performs logic conversion on the initial drive signal to obtain a power drive signal; The H-bridge power stage module 130 is connected to the logic conversion module 120 and provides bidirectional drive current to the load L1 in response to the power drive signal. The current management module 140 is connected to the control module 110 and the logic conversion module 120 respectively, and controls the drive current Id under the drive of the digital signal and the power drive signal.

[0027] In detail, such as Figure 2As shown, the H-bridge power stage module 130 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor PN1, a second NMOS transistor PN2, and a load L1. The source of the first PMOS transistor PM1 is connected to the first power supply voltage VDD, and the source of the first PMOS transistor PM1 is also connected to the source of the second PMOS transistor PM2. The drain of the first PMOS transistor PM1 is connected to the drain of the first NMOS transistor PN1, and the drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor PN2. The first terminal of the load L1 is connected to the drain of the first PMOS transistor PM1, the second terminal of the load L1 is connected to the drain of the second PMOS transistor PM2, and the source of the first NMOS transistor PN1 is connected to the source of the second NMOS transistor PN2. The gates of the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor PN1, and the second NMOS transistor PN2 are the control terminals of the H-bridge power stage module 130. The load L1 can be an inductive load such as a DC motor or an electromagnetic coil.

[0028] More in detail, such as Figure 2 As shown, the current management module 140 includes a voltage acquisition unit and a feedback regulation unit. The voltage acquisition unit is connected to the H-bridge power stage module 130 and the feedback regulation unit to sample the voltage of the H-bridge power stage module 130 and obtain the sampled voltage Vs. The feedback regulation unit is connected to the control module 110 and generates a reference voltage Vn under the drive of digital signals (DIN, SCLK, CS, VREF). Based on the reference voltage Vn and the sampled voltage Vs, a drive voltage Vd is generated. Under the control of the power drive signal, the drive voltage Vd is input to the corresponding switching transistor to drive the H-bridge power stage module 130 to the working state.

[0029] More in detail, such as Figure 2 As shown, the voltage acquisition unit includes a first transient voltage suppression diode TVS1 and a first resistor R1. The first terminal of the first transient voltage suppression diode TVS1 is connected to the first terminal of the first resistor R1, and the second terminal of the first transient voltage suppression diode TVS1 is connected to the second terminal of the first resistor R1. The second terminal of the first resistor R1 is also grounded. The first terminal of the first resistor R1 outputs the sampling voltage Vs.

[0030] More in detail, such as Figure 2As shown, the feedback adjustment unit includes a first chip U1, a second chip U2, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and an operational amplifier COMP. The power supply terminal of the first chip U1 is connected to the second power supply voltage VSS. The analog ground and digital ground terminals of the first chip U1 are both grounded. The output terminal of the first chip U1 is connected to the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the non-inverting input terminal of the operational amplifier COMP. The inverting input terminal of the operational amplifier COMP is connected to the first terminal of the first capacitor C1. The second terminal of the first capacitor C1 is connected to the output terminal of the operational amplifier COMP. The output terminal of the operational amplifier COMP is connected to the first test terminal (NO1) and the second test terminal (NO2) of the second chip U2. The first common terminal (COM1) of the second chip U2 is connected to the first terminal of the third resistor R3. The second common terminal (COM2) of the second chip U2 is connected to the first terminal of the fourth resistor R4. The power supply terminal of the second chip U2 is connected to the second power supply voltage VS. S, the ground terminal of the second chip U2 and the two floating terminals (NC1, NC2) of the second chip U2 are grounded. The reference voltage terminal of the first chip U1 is connected to the reference voltage VREF. The input terminal (DIN), the start terminal (CS), and the clock control terminal (SCLK) of the first chip U1 are the first input terminals of the feedback adjustment unit. The first input terminal of the feedback adjustment unit is connected to a digital signal. The inverting input terminal of the operational amplifier COMP is the second input terminal of the feedback adjustment unit. The second input terminal of the feedback adjustment unit is connected to the first terminal of the first resistor R1. The first input terminal of the second chip U2 is the third input terminal of the feedback adjustment unit. The second input terminal of the second chip U2 is the fourth input terminal of the feedback adjustment unit. The second terminal of the third resistor R3 is the first output terminal of the feedback adjustment unit. The first output terminal of the feedback adjustment unit is connected to the gate of the first NMOS transistor PN1. The second terminal of the fourth resistor R4 is the second output terminal of the feedback adjustment unit. The second output terminal of the feedback adjustment unit is connected to the gate of the second NMOS transistor PN2. The first chip U1 can be an AD5541, the second chip U2 can be a BL1555MM, and the operational amplifier can be an OPA365AIDBVR. Other chips can also be used to achieve the same function, and no restrictions are imposed here.

[0031] More in detail, such as Figure 3As shown, the power drive signals include four H-bridge drive signals (P1, P2, P3, P4), and the initial drive signals include the first initial drive signal EXT and the second initial drive signal EXP. The logic conversion module 120 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a first NPN transistor Q1, a second NPN transistor Q2, and a third chip U3. The first terminal of the fifth resistor R5 is grounded. The first terminal of the first resistor is connected to the first terminal of the sixth resistor R6. The second terminal of the fifth resistor R5 is connected to the first input terminal of the first NOR gate NOR1. The second terminal of the fifth resistor R5 is also connected to the second input terminal of the first NOR gate NOR1. The output terminal of the first NOR gate NOR1 is connected to the first input terminal of the second NOR gate NOR2. The output terminal of the second NOR gate NOR2 is connected to the first terminal of the seventh resistor R7. The second terminal of the seventh resistor R7 is connected to the gate of the first NPN transistor Q1. The second terminal of the seventh resistor R7 is also connected to the emitter of the first NPN transistor Q1 via the second capacitor C2. The emitter of the first NPN transistor Q1 is grounded. The first terminal of the eighth resistor R8 is connected to the first power supply voltage VDD. The second terminal of the eighth resistor R8 is connected to the first terminal of the ninth resistor R9. The collector of NPN transistor Q1 is connected to the second terminal of the eighth resistor R8. The second terminal of the sixth resistor R6 is connected to the first input terminal of the third NOR gate NOR3. The second input terminal of the third NOR gate NOR3 is grounded. The output terminal of the third NOR gate NOR3 is connected to the first input terminal of the fourth NOR gate NOR4. The second input terminal of the fourth NOR gate NOR4 is connected to the first input terminal of the second NOR gate NOR2. The output terminal of the fourth NOR gate NOR4 is connected to the first terminal of the tenth resistor R10. The second terminal of the tenth resistor R10 is connected to the gate of the second NPN transistor Q2. The second terminal of the tenth resistor R10 is also connected to the emitter of the second NPN transistor Q2 via the third capacitor C3. The emitter of the second NPN transistor Q2 is grounded. The eleventh resistor R11... The first terminal is connected to the first power supply voltage VDD. The second terminal of the eleventh resistor R11 is connected to the first terminal of the twelfth resistor R12. The collector of the second NPN transistor Q2 is connected to the second terminal of the eleventh resistor R11. The second terminal of the ninth resistor R9 is connected to the first input terminal of the third chip U3. The second terminal of the twelfth resistor R12 is connected to the second input terminal of the third chip U3. The ground terminal of the third chip U3 is grounded. The power supply terminal of the third chip U3 is connected to the second power supply voltage VSS. The power supply terminal of the third chip U3 is grounded after passing through the fourth capacitor C4. Among these, the first input terminal of the first NOR gate NOR1 is connected to the first initial drive signal EXT, and the second input terminals of the second NOR gate NOR2 and the first input terminals of the third NOR gate NOR3 are connected to the second initial drive signal EXP.The second terminal of the ninth resistor R9 outputs the first H-bridge drive signal P1, which is connected to the gate of the second PMOS transistor PM2. The second terminal of the twelfth resistor R12 outputs the second H-bridge drive signal P2, which is also connected to the gate of the first PMOS transistor PM1. The first input terminal of the third chip U3 outputs the third H-bridge drive signal P3, which is connected to the first input terminal of the second chip U2. The second input terminal of the third chip U3 outputs the fourth H-bridge drive signal P4, which is connected to the second input terminal of the second chip U2. The third chip U3 can be a 74HC2G14, or other models can be selected to achieve the same function; no limitation is made here.

[0032] In detail, such as Figure 2 As shown, the H-bridge drive control circuit also includes a power protection module, which includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and a second transient voltage suppression diode TVS2. The first terminal of the fifth capacitor C5 is connected to the first power supply voltage VDD, and the second terminal of the fifth capacitor C5 is grounded. The sixth capacitor C6 is connected in parallel with the fifth capacitor C5, the seventh capacitor C7 is connected in parallel with the fifth capacitor C5, and the second transient voltage suppression diode TVS2 is connected in parallel with the fifth capacitor C5. The power protection module provides surge protection for the first power supply voltage VDD.

[0033] Please refer to Figures 1 to 4 As shown, the working principle of the H-bridge drive control circuit provided in this application is as follows: The control module 110 provides an initial drive signal and a digital signal. The logic conversion module 120 is connected to the control module 110 and performs logic conversion on the initial drive signal to obtain a power drive signal. Under the control of the power drive signal, the H-bridge power stage module 130 provides a bidirectional drive current Id to the load L1. The current management module 140 is connected to the digital signal and the power drive signal. Based on the digital signal, it generates a drive voltage Vd. Under the control of the power drive signal, it inputs the drive voltage Vd to the lower bridge arm of the corresponding H-bridge power stage module 130. The current management module 140 establishes a current feedback loop with the lower bridge arm of the H-bridge power stage module 130. It can directly control the magnitude of the drive current Id of the H-bridge power stage module 130 by adjusting the input digital signal.

[0034] The first initial drive signal EXT and the second initial drive signal EXP provided by the control module 110 are converted by the logic conversion module 120 to obtain four H-bridge drive signals (P1, P2, P3, P4), and their truth table is shown in Table 1: Table 1 Truth Table

[0035] The H-bridge drive control circuit provided by this invention includes three operating states: non-drive state, forward drive state, and reverse drive state, as detailed below: Non-driving state: As shown in Table 1, when the control module 110 provides the first initial drive signal EXT at a low level and the second initial drive signal EXP at a low level, or when the first initial drive signal EXT at a low level and the second initial drive signal EXP at a high level, the logic conversion module 120 is affected by the pull-down of the fifth resistor R5 and the sixth resistor R6. The second XOR gate NOR2 outputs a low level, and the fourth XOR gate NOR4 outputs a low level. After logic conversion, the first H-bridge drive signal P1 is at a high level, and the second H-bridge drive signal P2 is at a high level. The first H-bridge drive signal P1 and the second H-bridge drive signal P2 are inverted by the third chip U3, and the third H-bridge drive signal P3 and the fourth H-bridge drive signal P4 are at a high level. The first PMOS transistor PM1 and the second PMOS transistor PM2 in the upper arm of the H-bridge power stage module 130 are not turned on, and the first NMOS transistor PN1 and the second NMOS transistor PN2 in the lower arm are not turned on.

[0036] Positive drive state: such as Figure 4 As shown, during the time period t0, the control module 110 writes a pre-programmed digital signal to the first chip U1. Therefore, at this time, the upper and lower bridge arms in the H-bridge power stage module 130 are not turned on, the voltage at the non-inverting input terminal of the operational amplifier COMP is greater than the voltage at its inverting input terminal (sampling voltage Vs), and the driving voltage Vd is at a high level. During the initial time period t1, as shown in Table 1, control module 110 provides a first initial drive signal EXT at a high level and a second initial drive signal EXP at a low level. The second XOR gate NOR2 outputs a high level, and the fourth XOR gate NOR4 outputs a low level. After logic conversion, the first H-bridge drive signal P1 is low, and the second H-bridge drive signal P2 is high. The third chip U3 inverts the first H-bridge drive signal P1 and the second H-bridge drive signal P2, making the third H-bridge drive signal P3 high and the fourth H-bridge drive signal P4 low. The first H-bridge drive signal P1 controls the second PMOS transistor PM2 to turn on, and the second H-bridge drive signal P2 controls the first PMOS transistor PM1 to turn off. The third H-bridge drive signal P3 inputs the drive voltage Vd to the gate of the first NMOS transistor PN1, controlling PN1 to turn on. The fourth H-bridge drive signal P4 keeps the second NMOS transistor PN2 in the off state. Current flows from the first power supply voltage VDD. Second PMOS transistor PM2 Load L1 First NMOS transistor PN1 The voltage acquisition unit allows a positive drive current to flow through the load L1.

[0037] The current feedback loop includes a forward current feedback loop and a reverse current feedback loop, such as... Figure 2 As shown, when the H-bridge drive control circuit is in the forward drive state, the forward current feedback loop is formed by the voltage acquisition unit, operational amplifier COMP, second chip U2, third resistor R3 and first NMOS transistor PN1. Since the input terminal of operational amplifier COMP has the "virtual short" characteristic, that is, the voltage at the non-inverting input terminal of operational amplifier COMP is the same as the voltage at the inverting input terminal, the sampling voltage Vs can be obtained as equal to the reference voltage Vn, and the forward drive current Id can be obtained as Id=Vn / R1.

[0038] Reverse drive state: At time t0 before the control module outputs the initial drive signal, the control module 110 writes a pre-programmed digital signal to the first chip U1. At this time, the upper and lower bridge arms in the H-bridge power stage module 130 are not turned on, the voltage at the non-inverting input terminal of the operational amplifier COMP is greater than the voltage at its inverting input terminal, and the drive voltage Vd is high. During the initial time period t1, control module 110 provides a first initial drive signal EXT at a high level and a second initial drive signal EXP at a high level. The second XOR gate NOR2 outputs a low level, and the fourth XOR gate NOR4 outputs a high level. After logic conversion, the first H-bridge drive signal P1 is high, and the second H-bridge drive signal P2 is low. The third chip U3 inverts the first H-bridge drive signal P1 and the second H-bridge drive signal P2, making the third H-bridge drive signal P3 low and the fourth H-bridge drive signal P4 high. The first H-bridge drive signal P1 controls the second PMOS transistor PM2 to be off, the second H-bridge drive signal P2 controls the first PMOS transistor PM1 to be on, the third H-bridge drive signal P3 keeps the first NMOS transistor PN1 off, and the fourth H-bridge drive signal P4 inputs the drive voltage Vd to the gate of the second NMOS transistor PN2, controlling PN2 to be on. The drive current flows from the first power supply voltage VDD. First PMOS transistor PM1 Load L1 The second NMOS transistor PN2 The voltage acquisition unit allows a reverse drive current Id to flow through the load L1.

[0039] The current feedback loop includes a forward current feedback loop and a reverse current feedback loop, such as... Figure 2As shown, when the H-bridge drive control circuit is in the reverse drive state, the voltage acquisition unit, operational amplifier COMP, second chip U2, fourth resistor R4 and second NMOS transistor PN2 form a reverse current feedback loop. Since the input terminal of operational amplifier COMP has a "virtual short" characteristic, that is, the voltage at the non-inverting input terminal of operational amplifier COMP is the same as the voltage at the inverting input terminal, the sampling voltage Vs can be obtained as equal to the reference voltage Vn, and the reverse drive current Id can be obtained as Id=Vn / R1.

[0040] like Figure 4 As shown, the reference voltage Vn output by the second resistor R2 exhibits a trapezoidal change within one driving cycle. It has a certain voltage change slope at the beginning and end of the driving cycle, causing the operating current of the current feedback loop to exhibit a trapezoidal characteristic. It slowly rises at the beginning of the driving cycle t1 and slowly decreases at the end. At the end of the driving cycle t1, the reverse induced voltage across the load L1 drops significantly, greatly alleviating the impact stress on the H-bridge drive control circuit, reducing the requirements for the H-bridge MOSFETs and clamping circuits, and improving the reliability of the H-bridge drive control circuit. Furthermore, the smooth current change can better reduce electromagnetic interference in the circuit.

[0041] The present invention also provides a driving method for an H-bridge drive control circuit, the driving method being applied to the H-bridge drive control circuit as described above, the driving method comprising: Acquire the initial drive signal and digital signal; The initial drive signal is logically transformed to obtain the power drive signal; Under the control of power drive signals and digital signals, bidirectional drive current is provided to the load in the H-bridge power stage module, and the drive current of the load is controlled by adjusting the digital signals.

[0042] Specifically, the initial drive signal and digital signal provided by the control module 110 are acquired, and the initial drive signal is converted into a power drive signal by the logic conversion module 120. Under the drive of the power drive signal and digital signal, the H-bridge power stage module 130 provides a bidirectional drive current Id to the load L1. By adjusting the digital signal input to the control module 110, the rate of change of the drive current Id of the load L1 can be adjusted. When the load L1 changes, the magnitude of the drive current Id can also be adjusted by adjusting the digital signal to better adapt to different speed and load conditions.

[0043] In detail, before performing logic conversion on the initial drive signal, the process includes: acquiring a sampled voltage; generating a reference voltage based on the digital signal and the sampled voltage; and comparing the reference voltage and the sampled voltage to generate a drive voltage. Specifically, before inputting the initial drive signal, a sampled voltage Vs is acquired through a voltage acquisition unit. The initial sampled voltage Vs is 0V. The first chip U1 receives the digital signal sent by the control module 110. Driven by the digital signal, the first chip U1 outputs a high level, and the first terminal of the second resistor R2 outputs a reference voltage Vn. Since the reference voltage Vn is greater than the initial sampled voltage Vs (0V), the operational amplifier COMP outputs a high-level drive voltage Vd.

[0044] More specifically, the power drive signals include a first H-bridge drive signal P1, a second H-bridge drive signal P2, a third H-bridge drive signal P3, and a fourth H-bridge drive signal P4. The H-bridge power stage module 130 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor PN1, and a second NMOS transistor PN2. Under the control of the power drive signals and digital signals, a bidirectional drive current is provided to the load L1 in the H-bridge power stage module 130, including: when the first H-bridge drive signal P1 is low, the second H-bridge drive signal P2 is high, the third H-bridge drive signal P3 is high, and the fourth H-bridge drive signal P4 is low, based on the first H-bridge drive signal P1... The second PMOS transistor PM2 is driven to turn on, and the driving voltage Vd is input to the gate of the first NMOS transistor PN1 based on the third H-bridge driving signal P3, so that the first NMOS transistor PN1 turns on and a forward driving current Id flows through the load L1. When the first H-bridge driving signal P1 is high, the second H-bridge driving signal P2 is low, the third H-bridge driving signal P3 is low and the fourth H-bridge driving signal P4 is high, the first PMOS transistor PM1 is driven to turn on based on the second H-bridge driving signal P2, and the driving voltage Vd is input to the gate of the second NMOS transistor PN2 based on the fourth H-bridge driving signal P4, so that the second NMOS transistor PN2 turns on and a reverse driving current Id flows through the load L1.

[0045] This invention provides an H-bridge drive control circuit and its driving method. The drive circuit includes: an initial drive signal and a digital signal provided by a control module; a logic conversion module that performs logic conversion on the initial drive signal to output a power drive signal; an H-bridge power stage module that responds to the power drive signal and provides bidirectional drive current to the load; and a current management module that controls the drive current under the drive of the digital signal and the power drive signal. The H-bridge drive control circuit provided by this invention uses a "software + hardware" logic control design and only uses two control ports, reducing resource utilization compared to existing technologies, lowering the risk of system anomalies, preventing "same-side" conduction, and improving circuit robustness. During actual operation, the reverse induced voltage of the load decreases, reducing the requirements for the H-bridge's MOSFETs and clamping circuits, thus improving circuit reliability. The speed and magnitude of the drive current change can be adjusted by adjusting the value of the digital signal, adapting to different speeds and load conditions, and improving response performance. The magnitude of the drive current can be monitored in real time by the logic conversion module, and the drive load can be stopped promptly in case of an anomaly.

[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An H-bridge drive control circuit, characterized in that, include: The control module provides initial drive signals and digital signals; A logic conversion module, connected to the control module, performs logic conversion on the initial drive signal to obtain a power drive signal; The H-bridge power stage module is connected to the logic conversion module and provides bidirectional drive current to the load in response to the power drive signal. The current management module is connected to both the control module and the logic conversion module, and controls the drive current under the influence of the digital signal and the power drive signal.

2. The H-bridge drive control circuit according to claim 1, characterized in that, The H-bridge power stage module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and the load. The source of the first PMOS transistor is connected to a first power supply voltage, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor. The first terminal of the load is connected to the drain of the first PMOS transistor, the second terminal of the load is connected to the drain of the second PMOS transistor, and the source of the first NMOS transistor is connected to the source of the second NMOS transistor. The gates of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are the control terminals of the H-bridge power stage module.

3. The H-bridge drive control circuit according to claim 1, characterized in that, The current management module includes a voltage acquisition unit and a feedback adjustment unit. The voltage acquisition unit is connected to the H-bridge power stage module and the feedback adjustment unit to sample the voltage of the H-bridge power stage module and obtain a sampled voltage. The feedback adjustment unit is connected to the control module and generates a reference voltage under the drive of the digital signal. Based on the reference voltage and the sampled voltage, it generates a drive voltage. Under the control of the power drive signal, the drive voltage is input to the corresponding switching transistor to drive the H-bridge power stage module to the working state.

4. The H-bridge drive control circuit according to claim 3, characterized in that, The voltage acquisition unit includes a first transient voltage suppression diode and a first resistor. The first end of the first transient voltage suppression diode is connected to the first end of the first resistor, and the second end of the first transient voltage suppression diode is connected to the second end of the first resistor. The second end of the first resistor is also grounded. The first end of the first resistor outputs the sampled voltage.

5. The H-bridge drive control circuit according to claim 3, characterized in that, The feedback adjustment unit includes a first chip, a second chip, a second resistor, a third resistor, a fourth resistor, a first capacitor, and an operational amplifier. The power supply terminal of the first chip is connected to a second power supply voltage. Both the analog ground terminal and the digital ground terminal of the first chip are grounded. The output terminal of the first chip is connected to the first terminal of the second resistor. The second terminal of the second resistor is connected to the non-inverting input terminal of the operational amplifier. The inverting input terminal of the operational amplifier is connected to the first terminal of the first capacitor. The second terminal of the first capacitor is connected to the output terminal of the operational amplifier. The output terminal of the operational amplifier is connected to the first test terminal and the second test terminal of the second chip. The first common terminal of the second chip is connected to the first terminal of the third resistor. The second common terminal of the second chip... The first terminal of the fourth resistor is connected to the common terminal. The power supply terminal of the second chip is connected to the second power supply voltage. The ground terminal and two floating terminals of the second chip are grounded. The reference voltage terminal of the first chip is connected to the reference voltage. The input terminal, start terminal, and clock control terminal of the first chip are the first input terminals of the feedback adjustment unit. The inverting input terminal of the operational amplifier is the second input terminal of the feedback adjustment unit. The first input terminal of the second chip is the third input terminal of the feedback adjustment unit. The second input terminal of the second chip is the fourth input terminal of the feedback adjustment unit. The second terminal of the third resistor is the first output terminal of the feedback adjustment unit. The second terminal of the fourth resistor is the second output terminal of the feedback adjustment unit.

6. The H-bridge drive control circuit according to claim 1, characterized in that, The power drive signal includes four H-bridge drive signals, the initial drive signal includes a first initial drive signal and a second initial drive signal, and the logic conversion module includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a second capacitor, a third capacitor, a fourth capacitor, a first NOR gate, a second NOR gate, a third NOR gate, a fourth NOR gate, a first NPN transistor, a second NPN transistor, and a third chip. The first terminal of the fifth resistor is grounded, and the first terminal of the fifth resistor is connected to the first terminal of the sixth resistor. The second terminal of the fifth resistor is connected to the first input terminal of the first NOR gate, and the second terminal of the fifth resistor is also connected to the first input terminal of the first NOR gate. The second input terminal is connected to the first input terminal of the first NOR gate. The output terminal of the second NOR gate is connected to the first terminal of the seventh resistor. The second terminal of the seventh resistor is connected to the gate of the first NPN transistor. The second terminal of the seventh resistor is also connected to the emitter of the first NPN transistor via the second capacitor. The emitter of the first NPN transistor is grounded. The first terminal of the eighth resistor is connected to the first power supply voltage. The second terminal of the eighth resistor is connected to the first terminal of the ninth resistor. The collector of the first NPN transistor is connected to the second terminal of the eighth resistor. The second terminal of the sixth resistor is connected to the first input terminal of the third NOR gate. The second input terminal of the third NOR gate is grounded. The output of the NOR gate is connected to the first input of the fourth NOR gate, the second input of the fourth NOR gate is connected to the first input of the second NOR gate, the output of the fourth NOR gate is connected to the first terminal of the tenth resistor, the second terminal of the tenth resistor is connected to the gate of the second NPN transistor, the second terminal of the tenth resistor is also connected to the emitter of the second NPN transistor via the third capacitor, the emitter of the second NPN transistor is grounded, the first terminal of the eleventh resistor is connected to the first power supply voltage, the second terminal of the eleventh resistor is connected to the first terminal of the twelfth resistor, the collector of the second NPN transistor is connected to the second terminal of the eleventh resistor, and the second terminal of the ninth resistor is connected to the third chip. One input terminal, the second terminal of the twelfth resistor is connected to the second input terminal of the third chip, the ground terminal of the third chip is grounded, the power supply terminal of the third chip is connected to the second power supply voltage, and the power supply terminal of the third chip is grounded after passing through the fourth capacitor. The first input terminal of the first NOR gate is connected to the first initial drive signal, the second input terminal of the second NOR gate and the first input terminal of the third NOR gate are connected to the second initial drive signal, the second terminal of the ninth resistor outputs the first H-bridge drive signal, the second terminal of the twelfth resistor outputs the second H-bridge drive signal, the first output terminal of the third chip outputs the third H-bridge drive signal, and the second output terminal of the third chip outputs the fourth H-bridge drive signal.

7. The H-bridge drive control circuit according to claim 2, characterized in that, The H-bridge drive control circuit also includes a power protection module, which includes a fifth capacitor, a sixth capacitor, a seventh capacitor, and a second transient voltage suppression diode. The first terminal of the fifth capacitor is connected to the first power supply voltage, and the second terminal of the fifth capacitor is grounded. The sixth capacitor is connected in parallel with the fifth capacitor, the seventh capacitor is connected in parallel with the fifth capacitor, and the second transient voltage suppression diode is connected in parallel with the fifth capacitor.

8. A driving method for an H-bridge drive control circuit, characterized in that, The driving method is applied to the H-bridge drive control circuit as described in any one of claims 1-7, and the driving method includes: Acquire the initial drive signal and digital signal; The initial drive signal is logically transformed to obtain the power drive signal; Under the control of the power drive signal and the digital signal, a bidirectional drive current is provided to the load in the H-bridge power stage module, and the drive current of the load is controlled by adjusting the digital signal.

9. The driving method for the H-bridge drive control circuit according to claim 8, characterized in that, Before performing logic conversion on the initial drive signal, the following is also included: Obtain the sampled voltage; A reference voltage is generated based on the digital signal and the sampled voltage; The reference voltage and the sampled voltage are compared to generate a drive voltage.

10. The driving method for the H-bridge drive control circuit according to claim 9, characterized in that, The power drive signals include a first H-bridge drive signal, a second H-bridge drive signal, a third H-bridge drive signal, and a fourth H-bridge drive signal. The H-bridge power stage module includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. Under the control of the power drive signals and the digital signals, a bidirectional drive current is provided to the load in the H-bridge power stage module, including: When the first H-bridge drive signal is low, the second H-bridge drive signal is high, the third H-bridge drive signal is high, and the fourth H-bridge drive signal is low, the second PMOS transistor is driven to turn on based on the first H-bridge drive signal, and the drive voltage is input to the gate of the first NMOS transistor based on the third H-bridge drive signal, so that the first NMOS transistor turns on, and a positive drive current flows through the load; When the first H-bridge drive signal is high, the second H-bridge drive signal is low, the third H-bridge drive signal is low, and the fourth H-bridge drive signal is high, the first PMOS transistor is driven to turn on based on the second H-bridge drive signal, and the drive voltage is input to the gate of the second NMOS transistor based on the fourth H-bridge drive signal, so that the second NMOS transistor turns on, and a negative drive current flows through the load.

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