Driving technology of capacitive switching power supply

Abstract

The invention relates to a driving technology for realizing electric energy conversion by taking a capacitor as a transduction element. A hardware circuit of the driving technology consists of an operation control unit such as an MCU (Microprogrammed Control Unit), two multiplexing switches M1 and M2, and two driving chips D1 and D2. The operation control unit generates a PWM signal and bit selection address codes LADDR [1: 0] and RADDR [1: 0] of the two multiplexing switches, and only one group of bit selection address codes GPIO [3: 0] exists in each PWM signal period, so that the two multiplexing switches respectively select driving outputs (such as LBIT2 and RBIT3) in the two driving chips to perform paired control according to the address codes (high 2 bits of the GPIO [3: 0] are connected with the LADDR [1: 0] and low 2 bits of the GPIO [3: 0] are connected with the RADDR [1: 0]), and the two multiplexing switches are controlled in pairs. Therefore, the two ends of the capacitor are connected or disconnected at the same time, and the purpose of charging and discharging is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of electric energy conversion drive technology, belongs to the drive technology of the power supply with capacitor as transducer element in electric energy conversion. BACKGROUND

[0002] The biggest superiority of capacitor type switching power supply compared with inductance type switching power supply is that there is no electromagnetic radiation problem, and the conversion mode of electric energy is directly converted with high efficiency.

[0003] The essential difference between capacitor type switching power supply and capacitor type charge pump is the difference of electric energy conversion mode, load capacity, modulation precision and response time. Figure 1 As shown in the capacitor type voltage doubler charge pump, it contains 4 switches and 1 pump capacitor, and its function is to realize Uout=2*Uin, i.e. the output voltage is equal to twice the input voltage.

[0004] To realize Figure 1 2 times voltage output, the driving circuit shown in Figure 2 is needed to complete the synchronous action of the switch: S1 and S4 are closed and S2 and S3 are disconnected during the high level of the square wave SW signal, and the charging of C1 is completed; S1 and S4 are disconnected and S2 and S3 are closed during the low level of the square wave SW, and the charging of C1 plus Uin to the output filter capacitor C2 is completed. Then repeat the above process to achieve Uout times voltage output.

[0005] In the circuit composed of the voltage doubler charge pump shown in Figure 1 , when the load is light or heavy, the SW of the driving circuit can realize the access of the load with different degrees in the form of frequency modulation or width modulation, which is reflected in the effect of Uout that the output ripple voltage is large; the voltage doubler type charge pump only has half cycle to do work, and both the response time and the load capacity are limited by the working mode; in the modulation precision, the fluctuation of Uin will be directly transmitted to the output Uout and then to the load to form the ripple voltage, since the input power Uin is directly connected in series with the output.

[0006] From the above analysis, in the capacitor-based charge pump circuit, the output ripple voltage, half cycle work mode, load response time, modulation precision, and the influence of power fluctuation on the load, to realize the application of high power, some technical improvements are needed to meet the requirements of practical application of capacitor type switching power supply. SUMMARY

[0007] Figure 3It is a switching power supply principle diagram with a capacitor as a transducer element, which can realize Uout=2*Uin*D of output voltage, wherein D represents the duty cycle of the switch and can be taken in 0%-100%, and the output range of Uout is 0 to 2Uin. The principle is described in the typical 2 times voltage output mode.

[0008] Figure 3 There are left and right two columns of switches, the left column of switches are S5, S7 respectively, the right column of switches are S8, S10 respectively, and a column of capacitors C3 and C4. The left and right two columns of switches need to be combined to realize 2 times voltage output, for example, S5 and S8 are closed at the same time, and other switches are opened to realize charging of the capacitor C3, and S7 and S10 are closed at the same time, and other switches are opened to realize charging of the capacitor C4, C3 and C4 can be charged to Uin, and Uout=2*Uin, that is, the voltage output of the voltage doubler.

[0009] The working principle of the capacitor type switching power supply shown in Figure 3 It can be known that during the charging of C3 and C4, the output voltage Uout is continuously output, that is, the load is energized in the whole cycle; since C3 and C4 are directly connected in series in the output loop, they can both participate in the adjustment of the output voltage, and therefore the output ripple and the modulation accuracy are better than those of the voltage doubler charge pump shown in Figure 1 ; since Uout has output during the charging of C3 and C4, and not half-cycle output as shown in Figure 1 , the load fluctuation can be responded in the whole cycle, so that the response time to the load change is shortened.

[0010] Figure 4 It is one of the driving circuits constructed by the application, and the internal logic of the MCU subsystem is described in detail Figure 8 , and the internal driving of the MCU is not described in detail for the convenience of describing the driving principle (this part is described in the embodiment), and the simplified diagram is shown in Figure 5 . The working principle of the driving circuit shown in Figure 3 will be described below in combination with the capacitor type switching power supply shown in Figure 4 .

[0011] The purpose of the application is to realize the driving technology of the high-power capacitor type switching power supply with a capacitor as a transducer, and the beneficial effect is to improve the defects of the traditional capacitor type charge pump, so that the capacitor type switching power supply can meet the technical requirements of practical application in the key indicators of switching power supply such as output ripple voltage, energizing mode, load response time, modulation accuracy, etc.

[0012] Figure 4As shown: by the operational amplifier circuit AM1 to AM3, operation control unit (such as MCU, CPLD, etc., the figure with MCU for brief) MCU, multiplexing switch M1 and M2, drive array D1 and D2 and their connection mode constitute. Among them, the operational amplifier circuit is responsible for the conversion of analog signal in switching power supply, MCU is responsible for logic control and operation, multiplexing switch is responsible for distribution of PWM signal, drive chip is responsible for power amplification; Figure 4 With Figure 3 Formed a complete closed loop control system, its closed loop path by operation control unit (MCU) → multiplexing switch (M1, M2) → drive chip (D1, D2) → power switch (S5 to S10) → operational amplifier circuit (AM1 to AM3) → back to operation control unit (MCU).

[0013] The following will be combined Figure 3 The capacitor type switching power supply shown in the figure, the working principle of Figure 4 The drive circuit is described.

[0014] After initialization, the state is as follows.

[0015] As Figure 5 The MCU internal logic initialization makes DRV[3:0]→GPIO[3:0]→

[0000] , then Figure 4 M1 of L_ADDR[1:0] =

[00] and M2 of R_ADDR[1:0] =

[00] in.

[0016] Figure 4 In, the multiplexing switch makes the L_PWM signal of M1 in L_BIT0 position (the default output of multiplexing switch is low, the same below) according to the address code; the output signal of drive chip D1 controls the left column switch S5, S7 to be in the off state (the drive logic of switch is high closed, low open, the same below). The R_PWM signal of multiplexing switch M2 is placed in R_BIT0 position; the output signal of drive chip D2 controls the right column switch S8, S10 to be in the off state.

[0017] Figure 3 In, because the left and right column switches are in the off state, the initialization voltages UC3 and UC4 of C3 and C4 are both 0; Uout, Iout and Iin are all 0, and Uin is the actual measured input voltage; then Figure 5 In, the ADC channel input of MCU is Uin, which is the actual input voltage, and the rest of the analog quantities are all 0.

[0018] Figure 5 The MCU TIMER0 is started and reaches stable PWM output - fixed frequency F and minimum duty cycle Dmin (D represents the duty cycle of PWM, and Dmin represents the minimum duty cycle) after the figure.

[0019] After initialization, the program will complete the first output based on the set output value.

[0020] Assume the rated output is DC18V / 0.36A, i.e., Uout = 18VDC, Iout = 0.36ADC; Figure 3 The Uin input shown is 12VDC.

[0021] Step 1 - Write the duty cycle (Duty) to the timer: Figure 5 In the MCU, the minimum duty cycle of D is set to Dmin = 5%, such as... Figure 6 The topmost PWM waveform is shown.

[0022] Step 2 - Write the C3 charging driver address to GPIO[3:0]: Figure 5 In the MCU, DRV

[0110] is written to GPIO[3:0]; Figure 4 In the MCU, GPIO[3:2] =

[01] and GPIO[1:0] =

[10] . It can be seen that M1 loads L_PWM onto the left column switch S5 and S7 is off, and M2 loads R_PWM onto the right column switch S8 and S10 is off.

[0023] Step 3-C3 Charging: Because the L_PWM and R_PWM loaded by switches S5 and S8 originate from the same PWM signal from the MCU ( Figure 4 As shown), during the PWM high level, S5 and S8 will close synchronously (during the PWM low level, because there is no high-level drive, the default low output of the drive circuits D1 and D2 will cause S5 and S8 to open), while other switches are in the open state, so C3 is charged by Uin. Equation 1. UC3 = Uin * Dmin = 12 * 5% = 0.6VDC

[0024] Step 4 - Write the charging driver address of C4 to GPIO[3:0]: Figure 5 In the MCU, DRV

[1011] is written to GPIO; Figure 6 In the MCU, GPIO[3:2] =

[10] and GPIO[1:0] =

[11] , so it can be seen that the left column switch S5 is open and L_PWM is loaded to S7, and the right column switch S8 is open and R_PWM is loaded to S10.

[0025] Step 5-C4 Charging: Because the L_PWM of switch S7 and the R_PWM of switch S10 come from the same PWM signal from the MCU, S7 and S10 will be turned on simultaneously during the PWM high level period, and charging will occur under PWM drive. Formula 2. UC4 = Uin * D = 12 * 5% = 0.6 VDC.

[0026] Therefore, the output voltage at this time is Formula 3. Uout = UC3 + UC4 = 0.6 + 0.6 = 1.2 VDC

[0027] Step 7 - Measure voltage and current: After the first output, the ADC input of the MCU is Uin = 12 VDC, UC3 = 0.6 VDC, UC4 = 0.6 VDC, Uout = 1.2 VDC, Iin = Iout = 0 ADC.

[0028] Keep the duty cycle Dmin unchanged, after multiple Step1 to Step5 operations, because of the no-load, the voltage on the capacitor UC3 and UC4 will eventually reach the input voltage 12V due to the charging accumulation, as shown in Figure 7 , that is Formula 4. Uout = UC3 + UC4 = 12 + 12 = 24 VDC

[0029] That is, in the case of no load, no matter what the duty cycle is, the output voltage Uout will eventually be equal to the input voltage Uin due to the charging accumulation of the capacitor Formula 5. Uout = 2 * Uin

[0030] Figure 3 When the load RL is connected, the output current Iout = IL. At this time Figure 3 The load capacity of the circuit is shown in the figure, in the case of constant input voltage, the discharge current of the capacitor determines it. Set the frequency F of the PWM = 20 kHz, C3 and C4 discharge alternately, the duty cycle D = Dmin = 5%, set the capacity of C3 and C4 to be 470uF, the maximum ripple voltage of the output voltage is 50mV.

[0031] The maximum output voltage under the current setting parameters Formula 6. Uout = UC3 + UC4 = Uin * D + Uin * D = 2 * Uin * D = 2 * 12 * 0.05 = 1.2 VDC

[0032] In the above formula: because the capacity of C3 and C4 is the same, UC3 = UC4, the output voltage Uout is twice the voltage of a single capacitor UC3 or UC4. The maximum current that can be supplied to the load is determined by the discharge formula of the capacitor, that is Formula 7. Iout = C * du / dt

[0033] Where, Iout is the output current; C is the capacitance of the load port, i.e. the capacity after C3 and C4 are connected in series, 470uF / 2=235uF; du is the ripple voltage of the load port, which is required to be 50mV; dt is the discharge time of the load port, i.e. the time of a PWM cycle minus the charging time. Formula 8. dt=(1 / F)-(1 / F)*D=(1 / F)*(1-D) =(1 / 20000)*(1-0.05)=47.5us Substitute all parameters into Formula 7 to obtain the theoretical output current Formula 9. Iout=C*du / dt=235uF*0.05 / 47.5us=0.2474ADC

[0034] For the convenience of subsequent calculation and analysis, the rated resistance is set to Formula 10. RL=Uout / IL=18V / 0.36A=50ohm

[0035] RL is 50ohm as the basis for subsequent voltage adjustment. As can be seen from the above, in the case of ensuring the output ripple voltage of 50mV, the current output voltage should be Uout=IL*RL=0.2474A*50R=12.37V, which has not reached the set 18V. (When the load is connected, C3 and C4 are charged more and discharged less, and vice versa, Uout rises.)

[0036] The following will illustrate Figure 4 the driving process of the driving circuit shown in the figure to reach the rated output voltage of 18V under the condition that the output load is unchanged, still taking the above-mentioned parameters as an example. Figure 5 the internal process of the MCU, Figure 4 the driving method of the driving circuit will not be repeated, and only the process of adjusting the output voltage will be described to reach the set output voltage.

[0037] As can be seen from the foregoing process, when the initialization is completed and the driving starts, Figure 5 the ADC of the MCU will detect the output voltage Uout: when Uout is lower than the set value DC 18V, it means that the output voltage is too low, and according to Figure 3 it can be known that Formula 11. Uout=IL*RL

[0038] Under the condition that the load RL is unchanged, the value of IL needs to be increased to increase Uout; similarly, when Uout is higher than the set value DC 18V, IL should be reduced.

[0039] From Figure 6It can be seen that in the case of constant capacitance and output voltage ripple, the output current can only be adjusted by changing the PWM duty cycle (more charging or less discharging) according to formula 7, so as to achieve the purpose of adjusting the output voltage according to formula 11.

[0040] Taking Uout less than the set value as an example, the process of adjusting Uout to 18V is as follows (after the aforementioned operation step Step7).

[0041] Step8- Figure 5 In the MCU, it is detected that Uout is less than the output target voltage 18VDC.

[0042] Step9-Increase the duty cycle D to 6%, and write the timer to change the duty cycle of the PWM output to 6%.

[0043] Step10-At the outside of the MCU Figure 4 In the MCU, the address drive code of the switch is still C3 and C4 alternately charging, and the Figure 5 The front edge of each PWM is sent out in the MCU.

[0044] Step11-From formula 7, the discharge current Iout theoretical value is adjusted to Formula 12. Iout = C * du / dt = C * du / (T * (1 - D)) = 235uF * 0.05V / (50us * (1 - D)) = 0.235 / (1 - D) = 0.235 / (1 - 0.06) = 0.25ADC

[0045] Step12-MCU continues to detect Uout, and according to formula 10 and formula 11, the output voltage theoretical value is adjusted to Formula 13. Uout = IL * RL = 0.25A * 50R = 12.5VDC

[0046] Repeat the process of Step8-Step12 until Uout = 18VDC.

[0047] The adjustment period is completed.

[0048] According to the foregoing analysis, in the case of constant load resistance of 50 ohms, when the output current reaches the rated current of 0.36A, the output voltage Uout reaches the target output voltage of 18V. From formula 7, Formula 14. dt = C * du / Iout = 235uF * 0.05V / 0.36A = 32.6us

[0049] That is, the discharge time Tf = 32.6us, then the duty cycle Equation 15. D = Charging time / PWM period = (T – Tf) / T = (50us – 32.6us) / 50us =34.8%

[0050] As can be seen from the above analysis, using Figure 4 The drive circuit shown controls Figure 3 The capacitor-type switching power supply shown has the following beneficial effects.

[0051] The output ripple voltage is only half that of a single capacitor. Figure 6 As shown, this is 1 / N, where N is the number of capacitors connected in series in the output capacitor column (the same applies below).

[0052] During the charging and discharging of C3 and C4, since the output is directly connected to both ends of the working capacitor column, it does work on the load regardless of whether the capacitor is charging or not, that is, it does work throughout the entire cycle (in fact, no matter how many capacitors are connected in series in the output column, all output capacitors do work throughout the entire cycle).

[0053] Because it performs work throughout the entire cycle, it can respond promptly to any load fluctuations. Moreover, according to Equation 7 of the capacitor discharge current formula, the required duty cycle can be calculated in advance, thereby enabling the output current to reach the required level as quickly as possible and shortening the response time to load changes.

[0054] The output Uout is directly connected to both ends of the output capacitor array. The output ripple voltage is only 1 / N of that of a single capacitor. Therefore, the voltage modulation accuracy can be adjusted by the number of series capacitors, compensating for the high ripple voltage of the charge pump. Intuitively, a higher output voltage does not necessarily mean a higher ripple voltage; rather, it can be physically compensated for by the number of capacitors. Although increasing the number of capacitors also increases the number of switches, it does not increase the power switching losses, nor does it change the energy conversion efficiency of the capacitor-type switching power supply (which is determined by...). Figure 3 As determined by the hardware circuit topology shown, only one pair of switches can operate at any given time.

[0055] As can be seen from the above analysis, for changes in power supply voltage, since the output ripple voltage is only 1 / N of the ripple voltage of a single capacitor, the power supply fluctuations are physically dispersed when they are transmitted to the output. At the same time, since the control circuit can directly pre-modulate the duty cycle according to Equation 7 and the changes in input voltage, the actual voltage ripple component transmitted to the output will be less (in actual control, the control quantity that generates the PWM signal should include the actual output voltage Uout to improve output accuracy; for the sake of simplicity, Uout is not included here). Attached Figure Description

[0056] Figure 1 - Capacitive voltage multiplier charge pump

[0057] Figure 2 - Voltage multiplier charge pump drive circuit

[0058] Figure 3 - Schematic diagram of a capacitor switching power supply

[0059] Figure 4 -Capacitor-based switching power supply-Power equals the drive circuit

[0060] Figure 5 - Simplified logic diagram of the control unit

[0061] Figure 6 - Figure 3 The diagram shows the charging and discharging of capacitors C3 and C4 in the capacitor-type switching power supply.

[0062] Figure 7 - Output voltage accumulation process of capacitor switching power supply under no-load conditions

[0063] Figure 8 -AC / DC capacitor-type switching power supply driver block diagram

[0064] Figure 9 -Schematic diagram of AC / DC non-isolated synchronous rectification and regulation power supply

[0065] Figure 10 -Schematic diagram of AC / DC synchronous rectification and voltage regulation control logic

[0066] Figure 11 - Generation of synchronous rectification drive signal and synchronous drive timing diagram Detailed Implementation

[0067] Figure 8 This is one of the application examples of a capacitor-type switching power supply driver circuit. Its function is to drive two rows of switches to operate synchronously according to PWM, with no more than 3 switches in each row. Figure 9 The AC / DC capacitor-type switching power supply shown is one such circuit that can be driven, enabling AC / DC synchronous rectification with voltage regulation. With an input of AC220V and an output of DC24V / 5A, this is a non-isolated switching power supply.

[0068] For ease of explanation Figure 8 The driving principle needs to be explained first. Figure 9 How the AC input to DC output conversion works is clearly explained in the patent "An AC-DC Synchronous Rectifier Circuit and Its Control Method: 202011325997X", which is briefly described here.

[0069] Figure 9The circuit is essentially an AC-DC synchronous rectification and can be regulated, capacitors C5 and C7 in parallel, C6 and C8 in parallel is to improve the frequency response of the working capacitor. For ease of description, simplified as C5 instead of C5 / / C7, C6 instead of C6 / / C8. C5 in series with C6 directly connected to Uin formed a AC220V AC capacitor voltage divider, that is Formula 16. Uc5=Uc6=AC220V / 2=AC110V

[0070] Switch LS1, LS2, RS1, RS2 constitutes a full-bridge rectification of capacitor C5: In the positive half cycle of Uin, RS2 and LS1 are closed and the other switches are open, the capacitor C9 on the negative positive power supply is loaded to Uout to make it positive on the negative; In the negative half cycle of Uin, RS1 and LS2 are closed and the other switches are open, the capacitor C9 on the negative positive power supply is loaded to Uout to make it positive on the negative.

[0071] Thus, the full-bridge BRG1 composed of switches LS1, LS2, RS1, RS2 completes the full-bridge rectification of the AC power supply divided by capacitor C5, and the output Uout can obtain positive polarity power supply in the positive and negative half cycle of Uin.

[0072] Similarly, LS2, LS3, RS2, RS3 constitute a full-bridge BRG2 that can complete the full-bridge rectification of the AC power supply divided by capacitor C6. The reason for using a voltage divider is that it can improve the control accuracy. When using PWM signal driving, the minimum increment of its duty cycle D determines the control accuracy of the output; suppose Figure 9 If a capacitor is used, the accuracy of D change 1% is Formula 17. Δu=Uin*ΔD=AC220V*1%=AC2.2V

[0073] After using two capacitors in series to form a voltage divider, the accuracy of D change 1% is Formula 18. Δu=(Uin / 2)*ΔD=(AC220V / 2)*1%=1.1V

[0074] Figure 9 The voltage regulation control principle of the circuit shown: during the positive half cycle of Uin, use PWM signal to switch RS2 and LS1 multiple times, while adjusting the duty cycle D of the PWM signal, so as to obtain the required output DC voltage Formula 19. Uout=(Uin / 2)*D=((Uin_max*Sin(θ)) / 2)*D

[0075] From formula 19, as long as the instantaneous value of (Uin / 2) is greater than Uout, the duty ratio D will have a suitable value to make the modulation result of Uin equal to the set Uout. For example, at 73° in the positive half cycle Formula 20. D = Uout / ((Uin_max*Sinθ / 2) = 24 / ((311*Sin(73°)) / 2) = 16.1%

[0076] That is, in Figure 9 Uin, the positive half cycle of 73°, the switch RS2 and LSI simultaneously load the PWM duty ratio D of 16.1% drive signal, then can get DC 24V voltage at Uout.

[0077] From the above brief, Figure 9 the AC / DC conversion circuit shown, as long as the appropriate driving method, can realize the function of synchronous rectification and voltage stabilization.

[0078] Figure 8 The drive circuit shown, the reason for the use of a unified PWM is two: one is to facilitate the program control and adjustment; the second is to avoid Figure 9 the switch shown in the same moment multiple closure caused by short circuit. The following will be described Figure 8 the embodiment of the drive Figure 9 to achieve the process of electric energy conversion.

[0079] Figure 8 Each module function description: AnaC - complete the level and polarity conversion of the voltage signal of the analog quantity of the capacitor type switching power supply, so that it can adapt the level of the ADC input signal of the MCU, the sampling signal is obtained by isolated sampling (optocoupler, etc.); MCU - hardware system for implementing operation and logic control (such as MCU, CPLD, etc., the drawing is marked with MCU for brief description), its sub-modules include - ADC - analog sampling filter circuit, from the input Uin, output current Iout, output voltage Uout, after filtering calculation, the output current Iout_avr, output voltage Uout_avr, input voltage Uin_ins, MMR - comparator preset value memory, including output voltage preset value Uout_set = DC24V, CMP_SWx segmented preset threshold +25V, -25V, +100V, -100V, CMP_SWx - segmented switch comparator, according to Uin_ins and Uin_set analysis and output corresponding switch combination result R_SW[x], L_SW[x], (where x = 0, 1, 2, 3, same below) IO_OVC - output over-current comparator, limit output current to protect switching power supply and load, SGL_DUTY - single cycle duty cycle generator, calculated and output PWM by Uout_avr, Uin_ins, Uout_set Duty cycle value of the signal D_ins, ADDR_CDR - switch bit address encoder, where output GPIO[3:0] =

[0000] indicates that no switch is selected, TIMER - PWM signal generation timer, generates PWM signal according to D_ins and outputs synchronization signal Sync, ADDR_SYNC - address code synchronization driver, enables GPIO[3:0] and PWM signal to be output to the IO port of the MCU synchronously; M3 / M4 - PWM pulse distribution circuit for left and right columns of switches (equivalent to a multiplexing switch), which is also a hardware interlocking circuit to prevent multiple switches from closing simultaneously; D3 / D4 - PWM signal execution circuit, responsible for amplification and driving output, loading PWM signal to Figure 9 the drive end R / L_SW[x] of each switch shown, completing the driving execution; L / RSx - Figure 9 power switch in; (note that this is an AC circuit application, requiring a bidirectional power switch such as a solid-state relay); the leakage current should be as small as possible; L_SWx is the drive end corresponding to the left column switch LSx, and R_SWx is the drive end corresponding to the right column switch RSx.

[0080] After power-on initialization, Figure 9 each switch in is in the default open state, and capacitors C5 and C6 each receive AC 110V power supply voltage, with output current Iout being 0 and output voltage Uout being 0. Therefore, after initialization, the analog quantity input by AnaC: Uin is AC 220V, Uout is 0, and Iout is 0.

[0081] Figure 10 is the waveform timing diagram of synchronous rectification and voltage stabilization. Due to the symmetry of the sine wave, the time period described in the driving principle is only from t3 to t9, i.e. the driving method between positive 90° and negative 90° of the sine wave.

[0082] Figure 10From top to bottom, the switch number (only the switch number that needs to be actuated is indicated), a sine wave of the mains input (for the convenience of description and calculation, the voltage value corresponding to the angle of the sine wave is simplified), the PWM signal waveform (immediately below it is an enlarged view of the t4-t8 time period in the sine wave time, for the convenience of marking), and the Uout voltage waveform diagram (the output voltage in the t3-t9 time period). Their horizontal axes are time t, and the unit is ms.

[0083] The process of synchronous rectification driving of the drive circuit shown in the following will be described Figure 8 The timing chart is shown in the following Figure 11 Figure 11 The number of PWM pulses in the t3-t9 time period is simplified in the following Figure 10 The number of PWM pulses in the t3-t9 time period is simplified in the following In the t3-t4 time period, Uin is greater than +100V and takes 4 pulses No1-No4, indicating that the switch RS3 / LS2 is actuated. Figure 10 In the t3-t4 time period, Uin is greater than +100V and takes 4 pulses No1-No4, indicating that the switch RS3 / LS2 is actuated. In the t4-t5 time period, Uin is between +100V and +25V and takes 2 pulses No5 and No6, indicating that the switch RS3 / LS1 is actuated. In the t5-t7 time period, the absolute value of Uin is lower than the set value of 25V, and the switch needs to be completely closed, and any switch is selected, taking 1 pulse No7. In the t7-t8 time period, the absolute value of Uin is between 100V and 25V and takes 2 pulses No8 and No9, indicating that the switch RS1 / LS3 is actuated. In the t8-t9 time period, the absolute value of Uin is greater than 100V and takes 4 pulses No10-No13, indicating that Figure 10 In the t8-t9 time period, the absolute value of Uin is greater than 100V and takes 4 pulses No10-No13, indicating that

[0084] Figure 11 In the t8-t9 time period, the absolute value of Uin is greater than 100V and takes 4 pulses No10-No13, indicating that Figure 8 The hardware circuit shown in the following is the driving timing in the software logic. From the timer TIMER, write D_ins (such as No4 of TIMER), and give the synchronization signal Sync to the ADDR_SYNC output GPIO[3:0]=

[0110] , Figure 8 As shown in the following, L_PWM and L_ADDR[1:0] decompose

[01] , and then the left column switch driving bit LDx=1 in the multiplexing switch M3, and L_SWx=1 in the drive circuit D3; at the same time, R_PWM and R_ADDR[1:0] decompose

[10] , and then the right column switch driving bit RDx=2 in the multiplexing switch M4, and R_SWx=2 in the drive circuit D4.

[0085] ​Figure 9 When the driving signals L_SWx = 1, R_SWx = 2 of the left and right rows of switches make the switches LS1 and RS2 conduct simultaneously at the duty ratio D_ins of No 4, C5 is output to Uout through the pair of switches, i.e. Uout = (Uin / 2)*D_ins.

[0086] In the driving block diagram, Figure 8 Figure 9 The analog quantities Uin, Uout and Iout shown in the figure are sampled in real time, and Uin and Uout are main parameters, determining the value of the duty ratio D of the PWM, and Iout is a secondary parameter, which makes all the power switches in the figure turn off (achieved by disabling the outputs of ADDR_SYNC and TIMER by triggering the OVC_Trig signal) when overcurrent occurs in the load. Figure 9

[0087] SyncRec_1 - MCU samples the analog signals ADC_CHx (x = 0, 1, 2), and obtains the values of the analog quantities through filtering and calculation, including the instantaneous value Uin_ins of the input voltage Uin, the average value Uout_avr of the output voltage Uout, and the average value Iout_avr of the output current Iout (the filtering output is not limited to instantaneous value and average value according to the needs of the circuit). Figure 8 SyncRec_2 - MCU reads the output set value Uout_set, and sends it together with the input voltage instantaneous value Uin_ins and the output voltage average value Uout_avr to the single-cycle duty ratio calculation module SGL_DUTY.

[0088] In SGL_DUTY: first calculate the main duty ratio D_Main, then calculate the adjustment ratio D_Adj, and the generated single-cycle duty ratio D_ins is composed of D_Main and D_Adj.

[0089] Equation 21. D_ins = D_Main * D_Adj SyncRec_3 - calculate the main duty ratio D_Main according to the input voltage instantaneous value Uin_ins and the output voltage set value Uout_set, Equation 22. D_Main = Uout_set / Uin_ins

[0090] SyncRec_4 - generate the adjustment ratio D_Adj according to the output set value Uout_set and the actually sampled Uout average value Uout_avr

[0091] Equation 23. D_Adj = Uout_set / Uout_avr

[0092] ​​​SyncRec_5 - Generate the PWM comparator value D_ins finally written to timer TIMER using Equation 21 based on the calculated main duty cycle and adjustment ratio.

[0093] SyncRec_6 - In the segmented switch address encoder CMP_SWx, perform segmented comparison on the threshold Uin_set set for the input voltage and the instantaneous value Uin_ins of the input voltage, and output a pair of switch combination codes R / L_SW[x]. Refer to Figure 10 and Figure 11 for the description: SyncRec_6.1 - Figure 10 During t3 to t4, +311V >= Uin_ins > +100V, positive polarity voltage division working mode. C5 and C6 work alternately, so the switch combinations are RS3 / LS2 and RS2 / LS1. After the switch codes are generated, they are R_SW[3] / L_SW[2], and R_SW[2] / L_SW[1]; SyncRec_6.2 - During t4 to t5, +100V > uin_ins > +25V, positive polarity series connection working mode. C5 and C6 are charged as a whole, so the switch combination is RS3 / LS1 working in a cycle. After the switch code is generated, it is R_SW[3] / L_SW[1]; SyncRec_6.3 - During t5 to t7, +25V > uin_ins > -25V. Since the input Uin_ins is lower than the set voltage Uout_set = DC25V, pause working mode, no switch is selected. Then the switch combination is RS0 / LS0. After the switch code is generated, it is R_SW[0] / L_SW[0]; This can be seen from the drive circuit Figure 8 that at this time, the multiplexing switches in both the left and right columns set the PWM signal to the 0 position, that is, no switch will be driven. Because Figure 9 the default of the switches in it is off, so all switches will be off; SyncRec_6.4 - During t7 to t8, -100V < Uin_ins < -25V, negative polarity series connection working mode, C5 and C6 overall charging mode. The inverter rectification is completed by the switch. Then the switch combination is RS1 / LS3 working in a cycle. After the switch code is generated, it is R_SW[1] / L_SW[3]; During the period from SyncRec_6.5–t8 to t9, -100V<=Uin_ins<-311V, negative polarity voltage divider working mode, C5 and C6 work in turn, then the switch combination is RS2 / LS3 and RS1 / LS2 work in turn, and the switch codes are generated as R_SW[2] / L_SW[3] and R_SW[1] / L_SW[2] respectively.

[0094] SyncRec_7 – A set of switch combination codes R / L_SW[x] generated by the 6th synchronous rectification control step SyncRec_6, will be encoded as the address drive code of the multiplexed switch in the switch address encoder; the high 2 bits of GPIO[3:2] correspond to the address code of the left column multiplexed switch M3, and the low 2 bits of GPIO[1:0] correspond to the address code of the right column multiplexed switch driver M4. (See reference) Figure 8 Encoding method description: SyncRec_7.1 – Right column switch encoding: simply convert the sequence number of the right column switches to binary, for example, R_SW[1] = R_GPIO

[01] , R_SW[2] = R_GPIO

[10] , etc., the right column switches output the lower two bits of GPIO[3:0]; SyncRec_7.2 – Left column switch encoding: simply convert the sequence number of the left column switch to binary, for example, L_SW[1] = L_GPIO

[01] , L_SW[2] = L_GPIO

[10] , etc., the left column switches output the values ​​of the two high bits of GPIO[3:0]; SyncRec_7.3 – By concatenating the address code values ​​of the left and right columns of switches, we can obtain the address drive code of GPIO[3:0] for the left and right columns of switches: GPIO[3:0] = L_GPIO[xx00]|R_GPIO[00xx].

[0095] SyncRec_8 – as Figure 8 In the internal logic of the MCU, the timer writes the value of D_ins at the end of each PWM waveform cycle, and sends the address drive code GPIO[3:0] from the synchronous driver through the synchronization signal Sync at the beginning of the next cycle.

[0096] SyncRec_9– Figure 8In the middle, the PWM signal and GPIO [3:0] are synchronous to the multiplexer switch M3 and M4, that is, in each PWM signal period, the duty cycle D_ins and the switch address driving code ADDR [3:0] correspond to a group of switch combinations with pulse width value, when M3 and M4 distribute the PWM signal to the corresponding data port, a group of synchronous driving signals for the left and right columns of switches are formed from the hardware. For example: LD1 and RD3 work with 30% duty cycle; LD3 and RD1 work with 80% duty cycle, etc.

[0097] SyncRec_10- Figure 8 In the middle, when the driving signals LDx and RDx are loaded into the left and right two column driving chips D3 and D4, they are amplified and output as the driving signals L_SWx and R_SWx of the power switch. In the hardware circuit, D3 and D4 have the same delay performance, so that they maintain the consistency of the driving function when reaching the driving end R / L_SWx of the switch (note: the driving logic of R_SWx and L_SWx is designed according to the power switch driving logic, one driving circuit corresponds to one switch, which can be high open low close or high close low open; but it must be ensured that the function of the power switch in time is synchronous, that is, the closing and opening of the left and right two rows of switches are synchronous, and only one switch in the same row is closed in a PWM period). Figure 9 In the middle, the power switch driving logic is designed, one driving circuit corresponds to one switch, which can be high open low close or high close low open; but it must be ensured that the function of the power switch in time is synchronous, that is, the closing and opening of the left and right two rows of switches are synchronous, and only one switch in the same row is closed in a PWM period).

[0098] SyncRec_11- Figure 9 In the middle, when the driving signal is loaded into the power switch driving end R / L_SWx, the input power transient voltage Uin_ins, the capacitors C5, C6 and the duty cycle D_ins of the switch together determine the value of the output voltage Uout Formula 24. Uout_set = (|Uin_ins| / N)*D_ins

[0099] Wherein, Uout represents the set output voltage, |Uin_ins| represents the absolute value of the input voltage transient value, N represents the current driving switch division coefficient (such as division charging N=2, whole series charging N=1, etc.), D_ins represents the duty cycle value in the current PWM signal period.

[0100] SyncRec_12- Figure 9 In the middle, when a PWM period driving ends, a new group of Uin, Iout, Uout is generated, which enters the ADC circuit of the MCU again after passing through the AnaC circuit for sampling, completing a control closed loop, and then repeats SyncRec_1 to SyncRec_11 to achieve the target output voltage set by Uout_set.

[0101] In addition, in Figure 8 , the output current I_out is processed to obtain an average value Iout_avr of the output current in the MCU, and is sent to the overcurrent comparator IO_OVC. When the set overcurrent value is exceeded, the overcurrent protection signal OVC_Trig is triggered, the output of the timer TIMER and the synchronous driver ADDR_SYNC are stopped, and the power switch is turned off, so as to protect the switch power supply and the load. Figure 9

[0102] For the output current, it can be seen from Figure 9 that C5 and C6 are always in series in the input power supply Uin loop, that is, they are always charging, and do not need charging time in the control period. From Figure 10 the lowermost Uout waveform diagram, it can be seen that the discharge time completely depends on the duty cycle of the PWM given by the control circuit, so when in the alternate working mode, it is the minimum current that the circuit can output, and this current is limited by the discharge current of the capacitor (ignoring the current generated by the Uin charging neutralization), that is, formula 12, and the required capacitance can be calculated by formula 25. C = Iout*dt / du

[0103] . Assuming that the output ripple is 1% of the output voltage, the single capacitor allows a ripple of 2%, the PWM frequency is still 20kHz and works at 50%, and the output current requirement reaches 5A, then the parameters can be determined as du = 24*2% = 0.48V; dt = (1 / F)*0.5 = 25us; Iout = 5A.

[0104] Substituting formula 25 gives formula 26. C = 5A*25us / 0.48V = 260uF, the capacitance can be selected as 330uF / 200V

[0105] 2 330uF / 200V, whether from the volume, cost, is practical engineering application. And from the foregoing analysis can be known, the conduction angle of the switch is not like the traditional rectifier bridge plus capacitor filter mode, which is basically in the input voltage sine wave form above 60 degrees to be turned on, and as long as the instantaneous value is greater than the output voltage, it can be turned on to output formula 27. Sin(theta) = Uin_set / Uin_max = 25V / 311V = 0.08 formula 28. theta = arcsin(0.08) = 4.5°

[0106] ​At about θ = 4.5°, normal output voltage DC 24V can be obtained, that is, PFC circuit is not needed.

[0107] From the foregoing analysis, Figure 8 The capacitor type switching power supply driving circuit shown can completely drive Figure 9 The AC / DC capacitor type switching power supply shown realizes synchronous rectification and voltage stabilization functions, and realizes non-isolated DC 24V / 5A output from AC 220V; and the power Formula 29. P = 24V * 5A = 120W

[0108] In the case of θ = 4.5°, PFC circuit is not needed (in fact, PFC circuit is not needed for larger power), the structure of large power non-isolated switching power supply is simplified, and digital switching power supply is fundamentally realized.

Claims

1. A driving technology for realizing electrical energy conversion using capacitors as transducer elements, characterized by: 1) The hardware module includes: a) A timer that can generate a pulse width signal (PWM), the duty cycle (D) of which is set by an input (D_ins), and can output a synchronization signal (Sync) at the leading edge of each PWM cycle; and has an enable terminal (OVC_Trig) for control output. b) A synchronous driver (ADDR_SYNC) driven by a synchronization signal (Sync), whose output (GPIO_x, where x = 0, 1, 2, 3) is determined by the input switch address code values ​​(GPIO[3:0]), and is driven by the synchronization signal (Sync) according to the pulse width signal (PWM) cycle. Each PWM cycle has a corresponding set of switch address code values ​​(GPIO[3:0]); and It has an enable terminal (OVC_Trig) with control output; c) The pulse width signal (L_PWM) of the first multiplexer (M3) is generated by the pulse width signal (PWM) of the aforementioned timer (TIMER). The address code (L_ADDR[1:0]) pins of the first multiplexer (M3) are respectively connected to the high-order pins of the output (GPIO_x, where x = 0, 1, 2, 3) of the aforementioned synchronous driver (ADDR_SYNC) (L_ADDR1 is connected to GPIO_3, and L_ADDR0 is connected to GPIO_2); d) The pulse width signal (R_PWM) of the second multiplexer (M4) is generated by the pulse width signal (PWM) of the aforementioned timer (TIMER). The address code (R_ADDR[1:0]) pins of the second multiplexer (M4) are respectively connected to the low-order pins of the output (GPIO_x, where x = 0, 1, 2, 3) of the aforementioned synchronous driver (ADDR_SYNC) (R_ADDR1 is connected to GPIO_1, and L_ADDR0 is connected to GPIO_0). e) The function of the aforementioned multiplexer (M3) is to output the input pulse width signal (L_PWM) to the specified pin (LD1) according to the input address code (L_ADDR[01]), and the other output pins (LD3, LD2, LD0) of the multiplexer do not output pulse width signal (L_PWM); f) The first driver chip column (D1) contains the same number of driver circuits (S5 driver, S7 driver) as the number of output signals required by the first multiplex switch (M1) (L_BIT1 corresponds to S5, L_BIT2 corresponds to S7), and the input logic (L_BIT2 is active high) and output logic (LB2 is active high) of each driver circuit (S7 driver) and the driving logic of the power switch (S7) (S7 driver is high level closed) are in a corresponding relationship (L_BIT2 high level eventually closes switch S7); g) The second driver chip column (D2) contains the same number of driver circuits (S8 driver, S10 driver) as the number of output signals required by the second multiplex switch (M2) (R_BIT2 corresponds to S8, R_BIT3 corresponds to S10), and the input logic (R_BIT2 is active high) and output logic (RB2 is active high) of each driver circuit (S8 driver) and the driving logic of the power switch (S8) (S8 driver is high level closed) are in a corresponding relationship (R_BIT2 high level eventually closes switch S8); 2) Hardware interlock function for drive signals a) The input signal (L_PWM) of the multiplex switch (M1) is uniquely determined by the drive address code (L_ADDR[1:0]=[01]) and output to the designated pin (L_BIT1), while other pins have no output signal (L_BIT3, L_BIT2, L_BIT0); 3) Hardware synchronization driver function a) Using the timer pulse width signal (PWM) as the beat, the synchronization signal (Sync) controls the synchronous driver (ADDR_SYNC) to output the corresponding switch address code according to the beat of the pulse width signal (PWM) (ADDR[3:0] outputs according to the period of the PWM signal); and the delay of the two pulse width signals (L_PWM, R_PWM) when they pass through their entire drive path (L_PWM passes through multiplex switch M3 to LD3, and then through the drive circuit to L_SW3, R_PWM passes through multiplex switch M4 to RD2, and then through the drive circuit to R_SW2) and are finally loaded onto the power switch (L_SW3 is loaded onto LS3, R_SW2 is loaded onto RS2) is consistent, and they are closed at the same time (LS3 and RS2 are closed at the same time).

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