Amplitude shift keying phase demodulation method and device

Abstract

The invention provides an amplitude shift keying phase demodulation device, which comprises a zero-crossing comparator used for extracting a zero-crossing point position of a voltage difference between two ends of an output capacitor of a power transmission circuit; the pulse construction circuit is used for constructing a zero crossing point pulse signal by taking the zero crossing point position as a starting point; the phase signal construction circuit is used for generating an original phase signal according to the zero crossing point pulse signal and a square wave sequence output by a power inverter of the power transmitting circuit; and the bit data extraction circuit extracts the pulse width of the original phase signal by using a pulse counter to obtain multi-bit phase information, and obtains a single-bit ASK signal according to a comparison result of the multi-bit phase information. According to the device disclosed by the invention, a digital-to-analog converter commonly used in phase demodulation is directly canceled, the design cost and the production cost are reduced, and meanwhile, the communication quality problem of a large number of communication requirements in a wireless charging process is solved.

Description

Technical Field

[0001] This invention belongs to the field of wireless charging for small devices, specifically relating to an amplitude-shift keying (ASK) phase demodulation method and apparatus, which is used in the power transmission circuit of a wireless charging system to receive and process amplitude-shift keying (ASK) signals. Background Technology

[0002] Early wireless charging systems only transmitted power and did not include communication between devices. Power was output from a power transmitter and received by a power receiver. Power transmission was wireless, typically using a sinusoidal signal with a specific frequency. Internally, the power transmitter usually used digital pulse width modulation (PWM) signals to control an analog half-bridge or full-bridge to regulate the output power. PWM signals regulated power in dimensions such as frequency, duty cycle, voltage, and phase. However, without communication, the power transmitter could not know how much power the power receiver received, whether there was significant power loss during wireless transmission, whether this power loss would translate into heat affecting the system's safety, or the acceptable power level for the power receiver itself. Therefore, introducing a communication mechanism into wireless charging devices is essential for improving system efficiency and safety.

[0003] To promote the standardization and safety of wireless charging, power supply equipment manufacturers have successively launched various wireless charging protocols, including the currently dominant Qi protocol. This protocol was introduced by the Wireless Power Consortium (WPC), established in 2008. Due to Apple's involvement and support, the protocol's iteration and evolution have accelerated significantly in recent years, making it the most mainstream wireless charging protocol. The Qi 2.2 protocol, released in 2025, has increased the charging power from 15W to 25W and imposed more stringent requirements on charging safety and power regulation accuracy.

[0004] The communication quality between the power transmitting and receiving devices is fundamental to ensuring the reliable execution of the aforementioned protocol. Communication occurs in two directions, such as... Figure 1As shown. One direction of communication is transmitted from the power transmitter and received by the power receiver, using Frequency Shift Keying (FSK). This direction of communication is used for the complex control handshake in the protocol. The other direction is transmitted from the power receiver and received by the power transmitter, using Amplitude Shift Keying (ASK). This direction of communication is the basic communication link of the wireless charging system. It contains information about the power receiver's power demand (the requirement to increase or decrease the power transmission) and the actual power measurement value obtained by the power receiver. If communication in this direction is not smooth, charging will stop within a few seconds.

[0005] ASK communication is crucial for wireless charging. Therefore, both the ASK transmitting side (power receiver) and the ASK receiving side (power transmitter) have multiple modulation and demodulation circuits that work simultaneously or in a time-division manner to cope with complex wireless communication environments. Factors such as the charging coil, the remaining battery level of the device being charged, and the state during charging (whether the screen is on for operation or in standby mode) all affect the ASK communication performance. Therefore, different modulation and demodulation methods need to be selected.

[0006] On the receiving side of ASK, common demodulation methods include voltage demodulation, current demodulation, and phase demodulation. Furthermore, to ensure communication quality and prevent packet loss and errors, these demodulation methods are typically enabled simultaneously, and the successfully decrypted packet is then sent to the protocol layer.

[0007] There is a physical correspondence between the modulation method on the ASK transmitter side and the demodulation method on the ASK receiver side. Specifically: When the transmitter uses resistive modulation, under light load conditions, the phase change is more significant, while the amplitude change is not, making phase demodulation suitable; under heavy load conditions, the phase change is not significant, while the amplitude change is significant, making voltage or current demodulation suitable. When the transmitter uses capacitive modulation, under light load conditions, the amplitude change is significant, making voltage or current demodulation suitable; under heavy load conditions, the phase change is significant, making phase demodulation suitable. Here, "light load" refers to the charging power; low-power charging is called light load, and high-power charging is called heavy load. The above patterns can be summarized in Table 1.

[0008] Table 1: Suitable Decoding Types Under Different Charging Conditions

[0009] Light load Heavy load Resistance modulation Suitable for phase decoding Suitable for voltage / current decoding Capacitor modulation Suitable for voltage / current decoding Suitable for phase decoding

[0010] On the ASK receiver side, i.e., the power transmitter side, ASK demodulation has long been a key focus and challenge in the wireless charging field, requiring continuous improvement. Relatively simple methods include voltage demodulation and current demodulation. However, because the ASK transmitter may switch between the two modulation methods at any time, and the load state of the device being charged changes frequently during charging, voltage and current demodulation alone cannot guarantee stable and reliable demodulation quality under all conditions. This situation has made phase demodulation a new hot topic in wireless charging demodulation methods.

[0011] Existing power transmission circuits and phase demodulation circuits commonly have the following structures: Figure 2 As shown. Figure 2 As shown, the power transmission circuit includes a digital intelligent PWM module 101, a power inverter 102, a transmitting coil L0, and an output capacitor C0. The digital intelligent PWM module 101 sends a PWM signal to the input terminal of the power inverter 102 and controls the transmission power by adjusting factors such as the PWM frequency and duty cycle. Figure 2 and Figure 3 In the power inverter 102, a transmitting coil L0 and an output capacitor C0 are connected in series between the two output terminals SW0 and SW1. The transmitting coil L0 and the output capacitor C0 form a transmitting coil LC oscillator. The power inverter 102 is configured to output a square wave sequence with an amplitude of PVIN through the output terminals SW0 and SW1. It is an analog circuit and is commonly implemented using a half-bridge or full-bridge structure, such as... Figure 3 As shown, the power inverter 102 can be composed of four N-type MOS switches S0 to S3. The power output of the power inverter 102 is released in the form of a sine wave through the transmitting coil L0 for charging. During this process, the mobile phone being charged can also use the ASK signal to modulate the sine wave of the transmitting coil L0. The phase demodulation circuit includes a differential amplifier circuit 103 and an ADC sampling circuit 104. For the output capacitor C0 connected in series with the transmitting coil L0, the voltage across its terminals is acquired by the ADC and used for phase demodulation. The voltage difference between the output terminals SW0 and SW1 of the power inverter 102, together with the voltage across the output capacitor C0, is used for phase demodulation identification.

[0012] According to existing technology, the specific identification process of phase demodulation identification is as follows: Figure 4 As shown. Figure 4 In the diagram, the square wave represents the voltage difference between the output terminals SW0 and SW1. The triangular wave in the diagram is actually more similar to a sine wave, representing the voltage across C0. Figure 4It can be seen that there is a phase difference between the central axis of the square wave pulse width and the peak value of the C0 voltage, manifested as the difference between two times t1 and t2. Phase demodulation involves knowing the position of the square wave's central axis on one hand, and detecting the peak value of the C0 voltage on the other, to calculate the time difference between the two (e.g., the time difference between times t1 and t2). By continuously measuring, the difference between t1 and t2 can be found, thereby reconstructing the ASK signal represented by the phase. The ASK signal can be represented by the digital strings corresponding to t1 and t2, such as "t1t1t1t1 t2 t2t2t2t2t2t2t2t2t2t2 t1 t1t1t1t1t1" using an ADC. The above phase demodulation calculation process requires measuring the position of the square wave's central axis and detecting the peak value of the sine wave, which requires the assistance of an ADC, increasing the system design and manufacturing costs.

[0013] Furthermore, to reduce design costs and complexity, a simplified method involves using a comparator to detect the zero-crossing point of the square wave (the voltage difference between SW0 and SW1) in Figure 4. Then, starting from this point, an ADC is used to continuously sample the C0 voltage over a short range to find the peak value. Compared to the commonly used method, which requires finding the central axis of the square wave, this simplified method only needs to find the zero-crossing point, making it simpler. It also eliminates the need for continuous ADC sampling; sampling only needs to be performed for a short period starting from the zero-crossing point, and the sampling frequency requirement can be appropriately reduced.

[0014] However, both the commonly used and simplified methods mentioned above require ADC sampling, resulting in relatively high demodulation costs. Furthermore, the subsequent demodulation steps are complex, requiring down-converting of the I and Q channels to extract the baseband signal, followed by decimation filtering and phase extraction. Such methods place high demands on the ADC sampling rate (at least 3.6MHz) and involve complex digital processing.

[0015] Therefore, it is necessary to provide a new amplitude shift keying signal demodulation method and apparatus to simplify the processing flow, reduce the computational scale, and at the same time obtain better demodulation results. Summary of the Invention

[0016] The purpose of this invention is to provide an amplitude shift keying phase demodulation method and apparatus to improve communication quality and avoid or reduce phenomena such as charging interruption and reduced power charging caused by poor communication quality.

[0017] To achieve the above objectives, the present invention provides an amplitude shift keying phase demodulation device for use in the power transmission circuit of a wireless charging system, comprising:

[0018] A zero-crossing comparator is used to determine the zero-crossing position of the voltage difference across the output capacitor of a power transmitting circuit.

[0019] A pulse construction circuit that uses the zero-crossing position as the starting point to construct a zero-crossing pulse signal;

[0020] A phase signal construction circuit includes a trigger that generates an original phase signal based on a zero-crossing pulse signal and a square wave sequence output from the power inverter of the power transmitting circuit; and

[0021] The bit data extraction circuit uses a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtains a single-bit ASK signal based on the comparison result of the multi-bit phase information.

[0022] The zero-crossing pulse signal is a fixed-width zero-crossing pulse signal; the pulse construction circuit includes a delay unit, an inverter, and an input of an AND gate connected in sequence to the output of the zero-crossing comparator, and the other input of the AND gate is connected to the output of the zero-crossing comparator.

[0023] The phase signal construction circuit includes a D flip-flop, the clock input of which is connected to a square wave sequence, the reset input of which is connected to the output of the pulse construction circuit, and the signal input of which is connected to a pull-high level, so that the D flip-flop outputs the original phase signal.

[0024] The bit data extraction circuit includes a phase flip automatic detector, which includes a forward counting circuit and a reverse counting circuit connected to the original phase signal, and a polarity selector connected to both the forward and reverse counting circuits. Both the forward and reverse counting circuits include pulse counters and count the phase pulses in the forward and reverse directions, respectively. The polarity selector is used to determine the polarity of the phase to decide whether to output a forward or reverse counting result.

[0025] When the polarity selector uses relative judgment, the polarity selector is set to compare the counting results of the positive and negative directions and take the smaller count value as the multi-bit phase information of the output;

[0026] When the polarity selector uses absolute judgment, the polarity selector is set as follows: based on the preset absolute standard of polarity judgment and the counting results of positive and negative directions, if one of the counting results of positive and negative directions is greater than the absolute standard and the other is less than the absolute standard, then the counting result less than the absolute standard is selected as the output.

[0027] The bit data extraction circuit includes an amplifier, an averaging device, a averaging removal device, and a comparator connected in sequence to the multi-bit phase information. The amplifier amplifies the multi-bit phase information as a signal to be amplified to obtain amplified multi-bit phase information. The averaging device calculates the mean of the amplified multi-bit phase information. The averaging removal device removes the mean from the amplified multi-bit phase information to obtain a signed number. The comparator compares the signed number with 0 to obtain the comparison result of the multi-bit phase information, and the comparison result of the multi-bit phase information is used as a single-bit ASK signal.

[0028] One input of the amplifier receives multi-bit phase information, and the other input is connected to an automatic gain controller. This automatic gain controller is connected to an averaging device via a pre-amplification mean recovery device. The pre-amplification mean recovery device calculates the mean of the signal before amplification based on the amplified multi-bit phase information. The amplifier is configured to determine the corresponding gain value based on the mean of the signal before amplification, and finally obtain the amplified multi-bit phase information according to the gain value.

[0029] The automatic gain controller is further configured to: after each gain value adjustment is completed, maintain a cool-down period of a fixed duration, during which no secondary gain adjustment is performed; after the preamble of the ASK signal is identified, receive a feedback signal to cause the automatic gain controller to stop adjusting the gain until the message of the ASK signal ends.

[0030] On the other hand, an amplitude shift keying phase demodulation method, used in the power transmission circuit of a wireless charging system, includes:

[0031] S1: Use a zero-crossing comparator to extract the zero-crossing position of the voltage difference across the output capacitor of the power transmitting circuit;

[0032] S2: Construct a zero-crossing pulse signal starting from the zero-crossing position;

[0033] S3: Using a trigger, a phase signal is generated based on the zero-crossing pulse signal and the square wave sequence output by the power inverter of the power transmitting circuit;

[0034] S4: Use a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtain a single-bit ASK signal based on the comparison result of the multi-bit phase information.

[0035] The pulse width of the original phase signal is extracted using a pulse counter to obtain multi-bit phase information. Specifically, this involves using a forward counting circuit and a reverse counting circuit to count the phase pulses in the forward and reverse directions, respectively, and using a polarity selector to determine the polarity of the phase to decide whether to output the forward or reverse count result.

[0036] The process of obtaining a single-bit ASK signal based on the comparison result of multi-bit phase information includes: performing a mean removal operation on the multi-bit phase information to convert it into a signed number; then using a comparator to compare the signed number with 0 to obtain the comparison result of the multi-bit phase information, which is used as the single-bit ASK signal.

[0037] Perform a mean removal operation on the multi-bit phase information to convert it into a signed number, specifically including:

[0038] Step A0: Set the initial gain value;

[0039] Step A1: Amplify the multi-bit phase information as the signal to be amplified to obtain amplified multi-bit phase information;

[0040] Step A2: Calculate the mean value of the amplified multi-bit phase information;

[0041] Step A3: Remove the mean from the amplified multi-bit phase information to obtain the signed number; at the same time, calculate the mean of the signal before amplification;

[0042] Step A4: Determine the corresponding gain value based on the mean of the signal before amplification, and return to step A1.

[0043] The amplitude shift keying phase demodulation device of the present invention directly eliminates the digital-to-analog converter commonly used in phase demodulation, reducing design and production costs. At the same time, it solves the communication quality problem of the large number of communication needs in the wireless charging process, avoids or reduces phenomena such as charging interruption and reduced power charging caused by poor communication quality, and avoids dangerous accidents caused by ultra-high power charging. Attached Figure Description

[0044] Figure 1 This is a diagram showing the power and communication message transmission direction in existing Qi wireless charging.

[0045] Figure 2 This is a block diagram of an existing power transmission circuit and phase demodulation circuit.

[0046] Figure 3 This is a circuit diagram of an existing full-bridge power inverter.

[0047] Figure 4 This is a waveform diagram of existing phase demodulation identification.

[0048] Figure 5 This is a schematic diagram illustrating the principle of phase information extraction in the amplitude shift keying phase demodulation device of the present invention.

[0049] Figure 6 This is an overall structural block diagram of the amplitude shift keying phase demodulation device of the present invention.

[0050] Figure 7 This is a circuit diagram of the pulse construction circuit for the output signal of a zero-crossing comparator.

[0051] Figure 8 This is a circuit block diagram of the bit data extraction circuit of the present invention.

[0052] Figure 9 This is a flowchart of the automatic gain control method of the amplitude shift keying phase demodulation method of the present invention. Detailed Implementation

[0053] This invention provides an amplitude shift keying (ASK) phase demodulation method and apparatus, which are applied to ASK signals from power receiving devices in a wireless charging system. The ASK signal addressed in this invention is extracted from phase information during power transmission; demodulation of this type of ASK signal is generally referred to as "phase demodulation." Phase demodulation has always been a critical and difficult problem to solve in wireless charging systems. The ASK phase demodulation method and apparatus of this invention can solve problems such as low phase identification and phase inversion encountered during phase demodulation, and can significantly improve the success rate of phase demodulation.

[0054] The wireless charging system described herein is used for wireless charging of various small devices. These small devices refer to portable devices with wireless charging capabilities, such as smartphones, smartwatches, smart bracelets, electronic pens, heated teacups, and wireless mice, as well as non-portable electronic devices such as robots with wireless charging capabilities. This invention only improves the receiving side (power transmitter) of ASK communication, thereby improving the demodulation method of ASK communication.

[0055] First embodiment: An amplitude shift keying phase demodulation device

[0056] According to a first embodiment of the present invention, an amplitude shift keying phase demodulation device is proposed for extracting phase information from the transmitted power of a power transmission circuit. For example... Figure 4 As shown, the power transmitting circuit is existing, comprising a power inverter 102. A transmitting coil L0 and an output capacitor C0 are connected in series between the two output terminals SW0 and SW1 of the power inverter 102, forming a transmitting coil LC oscillator. The power inverter 102 is configured to output a square wave sequence with an amplitude of PVIN based on the voltage difference between the output terminals SW0 and SW1 according to a PWM signal. It is an analog circuit, commonly implemented using a half-bridge or full-bridge structure, such as... Figure 3 As shown, the power inverter 102 can be composed of four N-type MOS switches S0 ~ S3.

[0057] like Figure 5 and Figure 6As shown, the amplitude shift keying phase demodulation device of the present invention includes a method for extracting the zero-crossing position of the voltage difference across the output capacitor C0 of the power transmitting circuit (e.g., Figure 5 The circuit includes a zero-crossing comparator 10 (points A, B, C, and D in the circuit), a pulse construction circuit 20 connected to the output signal of the zero-crossing comparator, a phase signal construction circuit 30 connected to the output of the pulse construction circuit 20 and the square wave sequence output by the power inverter 102 of the power transmission circuit, and a bit data extraction circuit 40 connected to the phase signal construction circuit 30.

[0058] The voltage across the output capacitor C0 is connected to a differential amplifier circuit to obtain the voltage difference signal across the output capacitor C0; one input terminal of the zero-crossing comparator 10 is connected to the voltage difference signal across the output capacitor C0, and the other input terminal is grounded to extract the zero-crossing position of the voltage difference across the output capacitor C0 of the power transmitting circuit.

[0059] The pulse construction circuit 20 is used to construct a zero-crossing pulse signal with a fixed width, starting from the zero-crossing position. The pulse construction circuit 20 is implemented using analog circuitry. For example... Figure 7 As shown, the pulse construction circuit 20 has a simple structure, comprising a delay unit 21, an inverter 22, and one input of an AND gate 23, all connected in sequence to the output of the zero-crossing comparator 10. The other input of the AND gate 23 is connected to the output of the zero-crossing comparator 10. The width of the zero-crossing pulse signal is determined by the delay unit 21. Therefore, the constructed zero-crossing pulse signal is... Figure 5 The pulse signals passing through points A, B, C, and D.

[0060] The phase signal construction circuit 30 is configured to use a trigger to generate the original phase signal based on the zero-crossing pulse signal and the square wave sequence output by the power inverter 102 of the power transmission circuit.

[0061] The phase signal construction circuit 30 includes a D flip-flop, the clock input of which is connected to a square wave sequence, the reset input of which is connected to the output of the pulse construction circuit 20, and the signal input of which is connected to a pull-high level, so that the D flip-flop outputs the original phase signal.

[0062] exist Figure 5 middle, Figure 5 The upper part includes a square wave formed by the voltage difference between the output terminals SW0 and SW1 of the power inverter, and a sine wave formed by the voltage across the output capacitor C0 (represented by a triangular wave in the figure). Figure 5 The lower half is the original phase signal extracted by this invention.

[0063] In other words, the amplitude shift keying (ASK) phase demodulation device of this invention has undergone a conceptual shift based on the commonly used phase definition. The time difference corresponding to the original phase signal has shifted from the square wave midline to the sine wave peak point to the square wave rising edge to the sine wave zero crossing point. Experiments show that although the time difference corresponding to the original phase signal (i.e., t1 ~ t4) differs from the time difference corresponding to the original phase signal in the prior art, the changing trends of the two are the same. Therefore, the phase information of the ASK phase demodulation device of this invention can still be preserved, and the phase change of the ASK signal will be converted into... Figure 5 The pulse width t1 to t4 of the original phase signal is varied. Therefore, the amplitude shift keying phase demodulation device of this invention further simplifies existing phase demodulation circuits. The method of this invention does not require the ADC to sample the voltage across the output capacitor C0, nor does it require digitally finding the voltage peak. Phase extraction is achieved using only a common zero-crossing comparator and a flip-flop.

[0064] The bit data extraction circuit 40 is configured to use a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtain a single-bit ASK signal based on the comparison result of the multi-bit phase information, thereby processing the multi-bit phase information into single-bit phase information.

[0065] In existing technology, the peak value of the voltage across the output capacitor C0 is detected by an ADC, therefore it is a multi-bit data, the position of the square wave's central axis is also multi-bit, and the phase information obtained by subtracting the two is also directly multi-bit data. Since this invention omits the ADC, therefore, in Figure 5 The original phase signal is represented as a single-bit pulse. To obtain accurate phase information, a pulse counter must be used to extract the pulse widths t1 to t4 of the original phase signal, thus obtaining multi-bit phase data similar to ADC sampling. Specifically, a pulse counter is used to count the pulse widths of the phase signal to recover the multi-bit phase information.

[0066] like Figure 8 As shown, the bit data extraction circuit 40 includes a phase reversal automatic detector. This detector comprises two parallel pulse counters used to extract the pulse width of the original phase signal to obtain multi-bit phase information and correct phase polarity reversal, thus avoiding interference with phase demodulation. Both commonly used phase recognition methods and the phase recognition method of this invention may encounter phase polarity reversal problems. The principle is... Figure 5 The zero-crossing points A to D of a sine wave will not always be after or before the rising edge of the square wave; they may vary back and forth. This variation leads to... Figure 5The phase pulse width signal in the lower part is inconsistent, making it impossible to clearly distinguish the ASK signal. In other embodiments, the phase reversal autodetector can also be replaced with a single pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, but this carries the risk of phase polarity reversal.

[0067] The phase-flipping automatic detector includes a forward counting circuit and a reverse counting circuit connected to the original phase signal, and a polarity selector 44 connected to both the forward and reverse counting circuits. Both the forward and reverse counting circuits include pulse counters that count the phase pulses in the forward and reverse directions, respectively. The forward counting circuit includes a first pulse counter 41, and the reverse counting circuit includes an inverter 42 and a second pulse counter 43. The polarity selector 44 is used to determine the polarity of the phase to decide whether to output a forward or reverse counting result.

[0068] Within the polarity selector 44, there are two ways to determine the polarity of the phase: relative determination and absolute determination. The polarity selector 44 can simultaneously possess both switchable polarity determination methods, or it can employ only one polarity determination method.

[0069] When the polarity selector 44 uses relative judgment, it is configured to compare the forward and reverse counting results and take the smaller count value as the output multi-bit phase information. The advantage of this method is its simplicity and, because its judgment standard is relative, it can adapt to different PWM carrier frequencies at different wireless charging stages (e.g., the 100kHz band in the initial stage of the Qi protocol and the 360kHz band during fast charging). The disadvantage is that because the bidirectional counting does not output the results simultaneously, there is a time difference. This can lead to inaccurate polarity judgment at the polarity switching point, ultimately resulting in glitches in the final processed single-bit ASK signal.

[0070] When the polarity selector 44 uses absolute judgment, it is configured to: based on a preset absolute standard for polarity judgment and the counting results of the forward and reverse directions, if one of the forward and reverse counting results is greater than the absolute standard and the other is less than the absolute standard, then the counting result less than the absolute standard is selected as the output. Under appropriate standard settings, the two values ​​of the forward and reverse counting results cannot be simultaneously greater than or simultaneously less than the standard. For example, if the PWM frequency of wireless charging is within the 100kHz band, the pulse counting clock is 100MHz, and assuming the duty cycle of the phase signal is 50%, then the maximum count value range is 250 ~ 625 (the PWM frequency varies within the range of 80 ~ 200kHz). In this case, setting the polarity judgment standard to 625 is sufficient. If the PWM frequency is fixed at 360kHz, then the maximum count value is 278, and the standard can be set to 278. The advantage of the absolute judgment method is its accuracy; it avoids polarity judgment errors. The disadvantage is the lack of adaptive capability; the polarity judgment standard needs to be modified when switching PWM frequency bands.

[0071] Furthermore, to reduce judgment errors caused by relative judgments, the polarity selector 44 in this invention can also have a multiple judgment mechanism. Specifically, the polarity selector 44 is configured to: perform a polarity judgment in each PWM cycle based on the lower limit of the number of judgments input by the user; only when the number of polarity judgments reaches the lower limit and the results of the polarity judgments in these judgments are consistent, will a true polarity reversal occur, that is, the forward counting result or the reverse counting result is selected based on the result of the polarity judgment. If the current polarity judgment is inconsistent with the result of the previous polarity judgment, the number of polarity judgments is reset to zero, and the counting of the number of polarity judgments restarts. This approach has a certain lag in response to polarity changes, but since polarity reversals do not occur frequently, this processing method is acceptable.

[0072] Since multi-bit phase information is generated by extracting the pulse width of the original phase signal, and its minimum value is zero and does not contain negative numbers, in order to obtain a single-bit ASK signal, the multi-bit phase information must be processed into single-bit phase information based on the comparison result of the multi-bit phase information.

[0073] In this embodiment, obtaining a single-bit ASK signal based on the comparison result of multi-bit phase information specifically includes: performing a mean removal operation on the multi-bit phase information to convert it into a signed number; then using a comparator to compare the signed number with 0 to obtain the comparison result of the multi-bit phase information, which serves as the single-bit ASK signal. Specifically, any non-positive signal is identified as 0, and any positive signal is identified as 1; the resulting signal is the single-bit ASK signal.

[0074] The signal form of this single-bit ASK signal can be processed by various existing methods, such as using a general ASK unpacker. The aforementioned mean removal operation can be achieved in several ways. For example, the simplest mean removal operation involves subtracting the mean from the original signal. Mean removal can also be implemented using a multi-tap high-pass filter or band-pass filter to suppress low-frequency components, thereby removing low-frequency interference and high-frequency noise from the line while removing the mean. The sampling rate for mean calculation is not limited, for example, it can be 40kHz, and the sampling duration must be at least the duration of two bits of the ASK signal.

[0075] It should be noted that the present invention will be derived from... Figure 5 The original phase signal generated by the phase signal construction circuit 30 is processed from a single-bit signal into multi-bit phase information and then back into single-bit phase information in order to generate another form of single-bit phase information (a single-bit ASK signal).

[0076] Although the original phase signal generated by the phase signal construction circuit 30 is a single-bit signal, it represents whether it is 0 or 1 through pulse width, rather than through level. The final processed single-bit ASK signal then represents 0 or 1 through level. For example, the pulse width sequence of the original phase signal is 10 10 10 6 6 6 6 10, and the processed single-bit ASK signal is: 1 1 1 0 0 0 0 1, that is, the output signal is: 3 beats high level, 4 beats low level, and 1 beat high level. The method of obtaining multi-bit phase information is to extract the current pulse width of the original phase signal. The method of processing multi-bit phase information into single-bit phase information is to determine whether it actually corresponds to 0 or 1 based on the comparison result of the multi-bit phase information (whose value is the pulse width of the original phase signal). In the process of obtaining the comparison result of the pulse width of the phase signal, it is necessary to calculate the average value, which is used as a comparator reference and compared with the pulse width of the phase signal to obtain the single-bit ASK signal in the form of 0 / 1.

[0077] In the process of generating an ASK signal from a phase signal, calculating the mean of the phase signal is unavoidable. The accuracy of the mean directly affects the accuracy of the ASK signal; therefore, the accuracy of the mean must be guaranteed in a phase demodulation system.

[0078] However, the phase signal behaves differently in various wireless charging applications. One situation is where the overall pulse width of the phase signal is relatively narrow (manifested as...). Figure 5 The pulse widths (T1 and T4) are relatively narrow, but the difference in pulse width before and after modulation is significant (manifested as...). Figure 5 The difference between pulse widths t1 and t4 is large. Another situation is where the overall pulse width of the phase signal is relatively wide (manifested as...). Figure 5The pulse widths (T1 and T4) are both relatively wide, but the difference in pulse width before and after modulation is not significant (manifested as...). Figure 5 The difference between the pulse widths t1 and t4 is small, even less than 1 ns.

[0079] Of the two scenarios described above, the first is the desired outcome of the system design. A narrower overall pulse width means a smaller overall phase count, eliminating the risk of numerical overflow and allowing for further amplification. A significant difference in pulse width before and after modulation indicates a larger pulse count amplitude, stronger anti-interference capability, and less susceptibility to interference and noise in the recovered ASK signal. Further amplification of this signal further enhances its anti-interference ability. A larger amplitude also means higher accuracy when calculating the averaging. The second scenario is undesirable in the system design. It is characterized by a larger overall phase count value but a very low modulation depth (i.e., amplitude). A larger overall count value means that the originally low amplitude cannot be increased through amplification due to the limited data bit width, which carries the risk of overflow and modulation clipping. A lower amplitude means that an accurate averaging cannot be obtained, and interference and noise will be more significantly superimposed on the amplitude, causing misjudgments of ASK flips. Therefore, in this invention, to enable the demodulation system to adapt to changes in the charging conditions and avoid frequent software probing and parameter modifications, an automatic gain control mechanism is incorporated to automatically control the amplifier's gain value. The average value reflects the average magnitude of the signal and serves as the basis for determining the amplifier's gain value. A smaller mean value means the signal to be amplified can be amplified more; a larger mean value means the signal to be amplified can be amplified less or not at all. The goal of the amplifier's gain value is to make the signal as large as possible, as long as it does not exceed the maximum value that the register can represent.

[0080] In this embodiment, as Figure 8 As shown, the bit data extraction circuit 40 includes an amplifier 45, an averaging device 46, a averaging removal device 47, and a comparator, all connected in sequence to the multi-bit phase information. The amplifier 45, averaging device 46, and averaging removal device 47 perform a mean removal operation on the multi-bit phase information, converting it into a signed number. Specifically, the amplifier 45 amplifies the multi-bit phase information as a signal to be amplified, the averaging device 46 calculates the mean of the amplified multi-bit phase information, and the averaging removal device 47 removes the mean from the amplified multi-bit phase information to obtain a signed number. The comparator compares the signed number with 0 to obtain the comparison result of the multi-bit phase information, which serves as a single-bit ASK signal.

[0081] Furthermore, one input of amplifier 45 receives multi-bit phase information, and the other input is connected to an automatic gain controller 48. This automatic gain controller 48 is connected to an averaging device 46 via a pre-amplification mean recovery device 49. The pre-amplification mean recovery device 49 calculates the mean of the pre-amplified signal based on the amplified multi-bit phase information. The mean of the pre-amplification signal is used as the basis for the amplifier's gain value, and the pre-amplification mean recovery device 49 is preferably a divider. Amplifier 45 is configured to determine the corresponding gain value based on the mean of the pre-amplification signal by looking up a table, and finally obtain the amplified multi-bit phase information according to the gain value.

[0082] The reason for calculating the mean after amplification rather than before is that the amplified value is larger, resulting in higher accuracy in the mean calculation. Furthermore, the amplified value is relatively constant, while the value before amplification varies depending on the charging conditions, making it unsuitable for calculating the mean and using it as a basis for automatic gain control. Based on the mean before amplification, the magnitude of the current input signal can be determined. Within the output limiting range, a gain table can be constructed, matching different gain values ​​according to different signal magnitudes. For example, if the output amplitude is limited to 1023, then when the input signal mean is 10 and the maximum value does not exceed 20, the gain value is 52 times; when the input signal mean is 70 and the maximum value does not exceed 140, the gain value is 7 times.

[0083] Since the automatic gain control mechanism itself does not recognize ASK messages, automatic gain adjustment is performed on both message-containing and non-message-containing background signals. This aligns with the application background of this invention. For phase demodulation, regardless of whether a message is present, the phase information is expressed as... Figure 5 The pulse widths in the lower part are t1 to t4. The message is merely hidden in the width difference between t4 and t1. Even without a message, the pulse width still exists. The purpose of automatic gain control is to prevent digital overflow caused by inappropriate gain. The background pulse width without a message can also reflect the average amplitude of the current phase signal, thus preparing the gain for subsequent messages in advance. Therefore, gain adjustment can be completed in the background signal part, and the gain will not be readjusted in the message part. This reduces the consumption of the preamble, because the number of ASK signal preambles is limited, and the number of preambles recognized at the receiver is even smaller. It is mainly used for bit alignment. If too long a preamble is consumed in gain adjustment, it will affect the demodulation quality of subsequent ASK signals.

[0084] To prevent frequent gain adjustments that could lead to signal instability, the automatic gain controller 48 is configured to: after each gain adjustment is completed, maintain a cool-down period of a fixed duration during which no further gain adjustments are made; in addition, after the preamble of the ASK signal is identified, a feedback signal is received to stop the automatic gain controller 48 from adjusting the gain until the message of the ASK signal ends.

[0085] Second embodiment: A method for amplitude shift keying phase demodulation

[0086] On the other hand, the present invention provides an amplitude shift keying phase demodulation method for use in the power transmission circuit of a wireless charging system, comprising:

[0087] Step S1: Use a zero-crossing comparator to extract the zero-crossing position of the voltage difference across the output capacitor C0 of the power transmitting circuit;

[0088] Step S2: Construct a zero-crossing pulse signal starting from the zero-crossing position;

[0089] The zero-crossing pulse signal is a zero-crossing pulse signal with a fixed width. Step S2 is implemented using a phase signal construction circuit, the specific structure of which is consistent with the specific structure of the phase signal construction circuit in the first embodiment.

[0090] Step S3: Using a trigger, a phase signal is generated based on the zero-crossing pulse signal and the square wave sequence output by the power inverter 102 of the power transmitting circuit.

[0091] Step S3 is specifically implemented using a D flip-flop. The clock input of the D flip-flop is connected to a square wave sequence, the reset terminal of the D flip-flop is connected to the output of the pulse construction circuit 20, and the signal input of the D flip-flop is connected to a pull-high level, so that the D flip-flop outputs the original phase signal.

[0092] Step S4: Use a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtain a single-bit ASK signal based on the comparison result of the multi-bit phase information, thereby processing the multi-bit phase information into single-bit phase information.

[0093] Specifically, the pulse width of the original phase signal is extracted using a pulse counter to obtain multi-bit phase information. This includes: using a forward counting circuit and a reverse counting circuit to count the phase pulses in the forward and reverse directions respectively, and using a polarity selector 44 to determine the polarity of the phase to decide whether to output the forward counting result or the reverse counting result.

[0094] The polarity selector 44 can employ relative or absolute judgment. When the polarity selector 44 uses relative judgment, it is configured to compare the forward and reverse counting results and take the smaller count value as the output multi-bit phase information. When the polarity selector 44 uses absolute judgment, it is configured to, based on a preset absolute standard for polarity judgment and the forward and reverse counting results, if one of the forward and reverse counting results is greater than the absolute standard and the other is less than the absolute standard, then the count result less than the absolute standard is selected as the output.

[0095] The polarity selector 44 is configured to perform a polarity check in each PWM cycle based on a user-inputted lower limit for the number of checks. Only when the number of polarity checks reaches the lower limit and the results of all polarity checks are consistent will a true polarity reversal occur; that is, the forward or reverse counting result is selected based on the polarity check result. If the current polarity check result is inconsistent with the previous polarity check result, the polarity check count is reset to zero, and the counting of polarity checks restarts.

[0096] The process of obtaining a single-bit ASK signal based on the comparison result of multi-bit phase information includes: performing a mean removal operation on the multi-bit phase information to convert it into a signed number; then using a comparator to compare the signed number with 0 to obtain the comparison result of the multi-bit phase information, which is used as the single-bit ASK signal.

[0097] like Figure 9 As shown, the mean removal operation is performed on the multi-bit phase information to convert it into a signed number. Specifically, this includes:

[0098] Step A0: Set the initial gain value m;

[0099] Step A1: Amplify the multi-bit phase information as the signal to be amplified to obtain amplified multi-bit phase information;

[0100] Step A2: Calculate the mean value of the amplified multi-bit phase information;

[0101] Step A3: Remove the mean from the amplified multi-bit phase information to obtain the signed number; at the same time, calculate the mean of the signal before amplification;

[0102] Step A4: Based on the mean of the signal before amplification, determine the corresponding gain value by looking up a table, and then return to step A1. This yields a stable signal confined to a certain amplitude range.

[0103] In summary, the amplitude shift keying phase demodulation method and apparatus of the present invention have made the following improvements for the phase demodulation scenario of wireless charging systems: First, the present invention directly eliminates the digital-to-analog converter (ADC) commonly used in phase demodulation, reducing design and production costs. Simultaneously, it solves the communication quality problem caused by the large number of communication demands during wireless charging, avoiding or reducing phenomena such as charging interruptions and reduced power charging caused by poor communication quality, and preventing dangerous accidents caused by ultra-high power charging. Second, when the phase signal is transmitted as a single-bit pulse, the present invention introduces... Figure 8 The digital circuit structure shown recovers the output of the ADC in the common method through a high-speed pulse width counter; furthermore, the present invention sets up an automatic phase flip detector and an automatic signal gain controller 48 to address the phase flip problem and environmental variability problem encountered in system applications, so as to realize automatic phase flip correction and automatic signal gain control.

[0104] Other commonly used components that may appear in the phase demodulation process are not described in this invention because they are not inventive points and are therefore omitted from the description. For example, PWM signals of different frequency bands often need to be processed at the same sampling rate to facilitate subsequent circuit design. Therefore, the common practice is to resample the phase signal with a uniform clock frequency before averaging, regardless of the PWM frequency. This is a common practice and is not within the scope of this invention, so it is not shown in the figures or described in the specification. Adding other devices and operating procedures based on this invention, or using any one of the inventive points of this invention individually, can all be considered as use of this invention.

[0105] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the invention. Various variations can be made to the above embodiments of the present invention. All simple and equivalent changes and modifications made in accordance with the claims and description of this application fall within the protection scope of the claims of this patent. All aspects not described in detail in this invention are conventional technical content.

Claims

1. An amplitude shift keying phase demodulation device, used in the power transmission circuit of a wireless charging system, characterized in that, include: A zero-crossing comparator is used to determine the zero-crossing position of the voltage difference across the output capacitor of a power transmitting circuit. A pulse construction circuit that uses the zero-crossing position as the starting point to construct a zero-crossing pulse signal; A phase signal construction circuit includes a trigger that generates the original phase signal based on the zero-crossing pulse signal and the square wave sequence output by the power inverter of the power transmitting circuit. as well as The bit data extraction circuit uses a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtains a single-bit ASK signal based on the comparison result of the multi-bit phase information.

2. The amplitude shift keying phase demodulation device according to claim 1, characterized in that, The zero-crossing pulse signal is a fixed-width zero-crossing pulse signal; the pulse construction circuit includes a delay unit, an inverter, and an input of an AND gate connected in sequence to the output of the zero-crossing comparator, and the other input of the AND gate is connected to the output of the zero-crossing comparator.

3. The amplitude shift keying phase demodulation device according to claim 1, characterized in that, The phase signal construction circuit includes a D flip-flop, the clock input of which is connected to a square wave sequence, the reset input of which is connected to the output of the pulse construction circuit, and the signal input of which is connected to a pull-high level, so that the D flip-flop outputs the original phase signal.

4. The amplitude shift keying phase demodulation device according to claim 1, characterized in that, The bit data extraction circuit includes a phase flip automatic detector, which includes a forward counting circuit and a reverse counting circuit connected to the original phase signal, and a polarity selector connected to both the forward and reverse counting circuits. Both the forward and reverse counting circuits include pulse counters and count the phase pulses in the forward and reverse directions, respectively. The polarity selector is used to determine the polarity of the phase to decide whether to output a forward or reverse counting result.

5. The amplitude shift keying phase demodulation device according to claim 4, characterized in that, When the polarity selector uses relative judgment, the polarity selector is set to compare the counting results of the positive and negative directions and take the smaller count value as the multi-bit phase information of the output; When the polarity selector uses absolute judgment, the polarity selector is set as follows: based on the preset absolute standard of polarity judgment and the counting results of positive and negative directions, if one of the counting results of positive and negative directions is greater than the absolute standard and the other is less than the absolute standard, then the counting result less than the absolute standard is selected as the output.

6. The amplitude shift keying phase demodulation device according to claim 1, characterized in that, The bit data extraction circuit includes an amplifier, an averaging device, a averaging removal device, and a comparator connected in sequence to the multi-bit phase information. The amplifier is used to amplify the multi-bit phase information as a signal to be amplified to obtain amplified multi-bit phase information. The averaging device is used to calculate the mean of the amplified multi-bit phase information. The averaging removal device is used to remove the mean from the amplified multi-bit phase information to obtain a signed number. The comparator is used to compare a signed number with 0 to obtain a comparison result of multi-bit phase information, which is then used as a single-bit ASK signal. One input of the amplifier receives multi-bit phase information, and the other input is connected to an automatic gain controller. This automatic gain controller is connected to an averaging device via a pre-amplification mean recovery device. The pre-amplification mean recovery device calculates the mean of the signal before amplification based on the amplified multi-bit phase information. The amplifier is configured to determine the corresponding gain value based on the mean of the signal before amplification, and finally obtain the amplified multi-bit phase information according to the gain value.

7. The amplitude shift keying phase demodulation device according to claim 6, characterized in that, The automatic gain controller is further configured to: after each gain value adjustment is completed, maintain a cool-down period of a fixed duration, during which no secondary gain adjustment is performed; after the preamble of the ASK signal is identified, receive a feedback signal to cause the automatic gain controller to stop adjusting the gain until the message of the ASK signal ends.

8. An amplitude shift keying phase demodulation method, used in the power transmission circuit of a wireless charging system, characterized in that, include: Step S1: Use a zero-crossing comparator to extract the zero-crossing position of the voltage difference across the output capacitor of the power transmitting circuit; Step S2: Construct a zero-crossing pulse signal starting from the zero-crossing position; Step S3: Using a trigger, generate a phase signal based on the zero-crossing pulse signal and the square wave sequence output by the power inverter of the power transmitting circuit; Step S4: Use a pulse counter to extract the pulse width of the original phase signal to obtain multi-bit phase information, and obtain a single-bit ASK signal based on the comparison result of the multi-bit phase information.

9. The amplitude shift keying phase demodulation method according to claim 8, characterized in that, The pulse width of the original phase signal is extracted using a pulse counter to obtain multi-bit phase information. Specifically, this involves using a forward counting circuit and a reverse counting circuit to count the phase pulses in the forward and reverse directions, respectively, and using a polarity selector to determine the polarity of the phase to decide whether to output the forward or reverse count result.

10. The amplitude shift keying phase demodulation method according to claim 8, characterized in that, The process of obtaining a single-bit ASK signal based on the comparison result of multi-bit phase information includes: performing a mean removal operation on the multi-bit phase information to convert it into a signed number; then using a comparator to compare the signed number with 0 to obtain the comparison result of the multi-bit phase information, which is used as the single-bit ASK signal. Perform a mean removal operation on the multi-bit phase information to convert it into a signed number, specifically including: Step A0: Set the initial gain value; Step A1: Amplify the multi-bit phase information as the signal to be amplified to obtain amplified multi-bit phase information; Step A2: Calculate the mean value of the amplified multi-bit phase information; Step A3: Remove the mean from the amplified multi-bit phase information to obtain the signed number; at the same time, calculate the mean of the signal before amplification; Step A4: Determine the corresponding gain value based on the mean of the signal before amplification, and return to step A1.

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