Memory element and manufacturing method thereof

Abstract

The invention provides a memory element and a manufacturing method thereof. The memory element includes: an access transistor; and a capacitor contact structure configured to connect a drain / source of the access transistor to the upper storage capacitor, and including: a bottom contact structure; and a top contact structure disposed over the bottom contact structure and including a barrier layer and a conductor fill material connected to the bottom contact structure via the barrier layer. The barrier layer extends along the bottom and two opposite sidewalls of the conductor filler material. The lower portion of the conductor filling material is filled in the recess defined by the barrier layer, and the upper portion of the conductor filling material is higher than the topmost end of the barrier layer and has a larger width than the lower portion of the conductor filling material.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of fabricating the same, and more particularly, to a memory device and a method of fabricating the same. BACKGROUND

[0002] With the development of dynamic random access memory (DRAM) technology, the integration density of DRAMs is continuously increasing. This allows DRAMs to store larger amounts of data in a given area. However, as the storage density increases, the DRAM cells are greatly scaled down, which greatly reduces the size of the capacitor contact structure in each DRAM cell for connecting the access transistor and the storage capacitor. Based on being confined in a relatively small size, it is easy to generate a hole in the capacitor contact structure, and this hole has the opportunity to extend to the surface of the capacitor contact structure. This is not conducive to the electrical connection between the access transistor and the storage capacitor, and affects the operating performance of the DRAM. SUMMARY

[0003] The present disclosure provides a memory device and a method of fabricating the same, which can maintain or even improve the electrical connection between the access transistor and the storage capacitor while pursuing the scaling down of the memory device.

[0004] According to some embodiments of the present disclosure, a memory device includes: an access transistor; a capacitor contact structure configured to connect a drain / source of the access transistor to an overlying storage capacitor, and including: a bottom contact structure; and a top contact structure disposed over the bottom contact structure and including a barrier layer and a conductor fill material connected to the bottom contact structure via the barrier layer, wherein the barrier layer extends along a bottom surface and two opposite sidewalls of the conductor fill material, a lower portion of the conductor fill material is filled in a recess defined by the barrier layer, and an upper portion of the conductor fill material is higher than a topmost end of the barrier layer and has a greater width relative to the lower portion; and a bit line stack structure adjacent to the capacitor contact structure and having a bit line connected to another drain / source of the access transistor.

[0005] According to some embodiments of the present disclosure, a method of manufacturing a memory element includes: forming a plurality of access transistors in a substrate; forming a bit line stack structure on the substrate, wherein the bit line stack traverses a plurality of the access transistors; and forming a plurality of capacitor contact structures on the substrate along two sides of the bit line stack structure, wherein the plurality of capacitor contact structures respectively include: a bottom contact structure; and a top contact structure disposed above the bottom contact structure and including a barrier layer and a conductor fill material connecting the bottom contact structure via the barrier layer, wherein the barrier layer extends along a bottom surface and two opposite sidewalls of the conductor fill material, a lower portion of the conductor fill material is filled in a recess defined by the barrier layer, and an upper portion of the conductor fill material is higher than a topmost end of the barrier layer and has a greater width relative to the lower portion. BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1A is a plan view schematic of a memory element according to some embodiments of the present disclosure;

[0007] FIG. 1B is a cross-sectional view schematic taken along FIG. 1A the X-X' line of

[0008] FIG. 1C is a cross-sectional view schematic taken along FIG. 1A the Y-Y' line of

[0009] FIG. 1D is a perspective view schematic showing a plurality of memory cells arranged along a bit line;

[0010] FIG. 2 is a flowchart of a method for forming a memory element according to some embodiments;

[0011] FIGS. 3A-3G is a perspective view schematic of a series of intermediate structures during a manufacturing flow shown in FIG. 2

[0012] FIGS. 4A-4G is a cross-sectional view schematic in a second direction showing a patterning operation for forming a capacitor contact structure according to some embodiments. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to the exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0014] FIG. 1A is a plan view schematic of a memory element 10 according to some embodiments of the present disclosure. Please refer to FIG. 1A ​DRAM) includes a plurality of active regions 100 arranged along a first direction D1 and a second direction D2 that is transverse to the first direction. As will be described below with reference to FIGS. 2A and 2B, each active region 100 includes a plurality of memory cells. As will be described below with reference to FIGS. 3A and 3B, each memory cell includes an access transistor AT and a storage capacitor SC. As will be described below with reference to FIGS. 4A and 4B, each access transistor AT is connected to a bit line BL and a storage capacitor SC. FIGS. 1B-1D As illustrated, the active regions 100 can be portions of a substrate separated by isolation structures. In some embodiments, the extension directions D3, D4 of the active regions 100 are transverse to the first direction D1 and the second direction D2. In such embodiments, the active regions 100 of each column can extend along one of the directions D3, D4, while the active regions 100 of adjacent columns extend along the other of the directions D3, D4. In this way, the active regions 100 of two adjacent columns are symmetric with respect to a mid-axis between them.

[0015] A plurality of word lines 102 extend along the first direction D1 and pass through each active region 100. An access transistor AT of a memory cell is defined at a transverse region of an active region 100 and a word line 102. For each access transistor AT, the passing word line 102 serves as a gate, and the portions of the active region 100 on opposite sides of the passing word line 102 serve as a drain and a source. In some embodiments, each active region 100 is passed by two word lines 102 and shared by two access transistors AT. In such embodiments, the portion of each active region 100 between the two passing word lines 102 can serve as a common source / drain for the two shared access transistors AT.

[0016] A plurality of bit lines 104 extend along the second direction D2 and cross each active region 100. One source / drain of each access transistor AT is connected to a transverse bit line 104 via a bit line contact structure 106. In embodiments where each active region 100 is shared by two access transistors AT, the bit line 104 is connected to the portion of each active region 100 that serves as a common source / drain via a bit line contact structure 106.

[0017] The other source / drain of each access transistor AT is connected to an overlying storage capacitor (not shown) via a capacitor contact structure 108. In this way, one source / drain of each access transistor AT is connected to a bit line 104, and the other source / drain is connected to a storage capacitor. In embodiments where each active region 100 is shared by two access transistors AT, the portions of each active region 100 on opposite sides of the two passing word lines 102 that serve as non-shared source / drains are connected to corresponding storage capacitors via two capacitor contact structures 108.

[0018] FIG. 1B is a cross-sectional view taken along the X-X' line of FIG. 1A is a cross-sectional view taken along the X-X' line of FIG. 1C is a cross-sectional view taken along the X-X' line of FIG. 1AThe cross-sectional view is shown by the Y-Y' line. Additionally, FIG. 1D This is a three-dimensional schematic diagram showing multiple memory cells arranged along bit line 104.

[0019] like FIGS. 1B-1D As shown, the active regions 100 are portions of the substrate 110, and are laterally spaced from each other by isolation structures 112. Furthermore, as... FIG. 1C As shown, word lines 102 are embedded in substrate 110 and laterally penetrate the active region 100 and the isolation structure 112. Each word line 102 includes a gate conductor structure 114 and a gate dielectric layer 116 covering the sidewalls and bottom surface of the gate conductor structure 114. In some embodiments, the word lines 102 are deeply embedded in substrate 110 such that the top surface of the word lines 102 is lower than the top surface of substrate 110. In these embodiments, insulating plugs 118 may be filled in substrate 110 and cover the top surface of word lines 102. As an example, the material of insulating plugs 118 may include silicon nitride, silicon oxide (tetraethoxysilane (TEOS), spin-on glass (SOG), the like or combinations thereof), or combinations thereof.

[0020] like FIG. 1C As shown, bit line 104 is disposed above substrate 110. In some embodiments, bit line 104 includes a first conductor layer 104a and a second conductor layer 104b extending along the bottom surface of the first conductor layer 104a. As an example, the first conductor layer 104a includes tungsten, while the second conductor layer 104b includes titanium and titanium nitride. Additionally, in some embodiments, an insulating layer 120 is disposed between bit line 104 and substrate 110. Additionally, in some embodiments, one or more insulating layers 122 are stacked above bit line 104. The sidewalls of insulating layer 122 may be substantially flush with the sidewalls of bit line 104 and / or the sidewalls of insulating layer 120. For illustrative purposes, each bit line 104 and the insulating layers 120, 122 below and above it are also referred to herein as a bit line stack structure GC.

[0021] In some embodiments, spacer walls 124 made of insulating material are provided along the sidewalls of the bit line stack structure GC to ensure that the bit lines 104 are properly electrically isolated from the surrounding conductor structure. For example, such as FIG. 1D and FIGS. 1B-1D As shown, the bit line stack structure GC is suitably separated from the capacitor contact structure 108 via spacer walls 124. As an example, the insulating material 124 may include silicon nitride, silicon oxide (tetraethoxysilane (TEOS), spin-on glass (SOG), the like, or combinations thereof), or combinations thereof.

[0022] FIG. 1C As shown, the capacitor contact structure 108 contacts the active region 100 above the substrate 110. The capacitor contact structure 108 is formed by a bottom contact structure 126 contacting the active region 100 and a top contact structure 128 stacked above the bottom contact structure 126 and contacting a storage capacitor (not shown). In some embodiments, the bottom contact structure 126 is composed of a conductor material such as polysilicon. In the example where the bottom contact structure 126 is composed of polysilicon, the bottom contact structure 126 can contact the top contact structure 128 via a metal silicide layer 130. On the other hand, the top contact structure 128 includes a barrier layer 132 and a conductor fill material 134. The conductor fill material 134 contacts the bottom contact structure 126 via the barrier layer 132. In some embodiments, the conductor fill material 134 is composed of a conductor material such as tungsten, and the barrier layer 132 is composed of a conductor material such as titanium and titanium nitride. FIG. 1D As shown, the capacitor contact structure 108 contacts the active region 100 above the substrate 110. The capacitor contact structure 108 is formed by a bottom contact structure 126 contacting the active region 100 and a top contact structure 128 stacked above the bottom contact structure 126 and contacting a storage capacitor (not shown). In some embodiments, the bottom contact structure 126 is composed of a conductor material such as polysilicon. In the example where the bottom contact structure 126 is composed of polysilicon, the bottom contact structure 126 can contact the top contact structure 128 via a metal silicide layer 130. On the other hand, the top contact structure 128 includes a barrier layer 132 and a conductor fill material 134. The conductor fill material 134 contacts the bottom contact structure 126 via the barrier layer 132. In some embodiments, the conductor fill material 134 is composed of a conductor material such as tungsten, and the barrier layer 132 is composed of a conductor material such as titanium and titanium nitride. FIG. 1D As shown, the capacitor contact structure 108 contacts the active region 100 above the substrate 110. The capacitor contact structure 108 is formed by a bottom contact structure 126 contacting the active region 100 and a top contact structure 128 stacked above the bottom contact structure 126 and contacting a storage capacitor (not shown). In some embodiments, the bottom contact structure 126 is composed of a conductor material such as polysilicon. In the example where the bottom contact structure 126 is composed of polysilicon, the bottom contact structure 126 can contact the top contact structure 128 via a metal silicide layer 130. On the other hand, the top contact structure 128 includes a barrier layer 132 and a conductor fill material 134. The conductor fill material 134 contacts the bottom contact structure 126 via the barrier layer 132. In some embodiments, the conductor fill material 134 is composed of a conductor material such as tungsten, and the barrier layer 132 is composed of a conductor material such as titanium and titanium nitride.

[0023] The conductor fill material 134 has a lower portion 134b and an upper portion 134t. The lower portion 134b fills in the recess defined by the barrier layer 132. Specifically, the barrier layer 132 extends along the bottom surface of the lower portion 134b of the conductor fill material 134 and further extends to the sidewalls of the lower portion 134b. As a result of the particular process sequence, the barrier layer 132 does not completely laterally surround the lower portion 1324b of the conductor fill material 134, but only covers two sidewalls of the lower portion 134b. As shown, the barrier layer 132 only covers the two opposite sidewalls of the lower portion 134b of the conductor fill material 134 that are substantially parallel to the bit line stack structure GC, but does not cover the other two sidewalls of the lower portion 134b that are substantially perpendicular to the bit line stack structure GC. FIG. 1B The conductor fill material 134 has a lower portion 134b and an upper portion 134t. The lower portion 134b fills in the recess defined by the barrier layer 132. Specifically, the barrier layer 132 extends along the bottom surface of the lower portion 134b of the conductor fill material 134 and further extends to the sidewalls of the lower portion 134b. As a result of the particular process sequence, the barrier layer 132 does not completely laterally surround the lower portion 1324b of the conductor fill material 134, but only covers two sidewalls of the lower portion 134b. As shown, the barrier layer 132 only covers the two opposite sidewalls of the lower portion 134b of the conductor fill material 134 that are substantially parallel to the bit line stack structure GC, but does not cover the other two sidewalls of the lower portion 134b that are substantially perpendicular to the bit line stack structure GC.

[0024] The conductor fill material 134 has a lower portion 134b and an upper portion 134t. The lower portion 134b fills in the recess defined by the barrier layer 132. Specifically, the barrier layer 132 extends along the bottom surface of the lower portion 134b of the conductor fill material 134 and further extends to the sidewalls of the lower portion 134b. As a result of the particular process sequence, the barrier layer 132 does not completely laterally surround the lower portion 1324b of the conductor fill material 134, but only covers two sidewalls of the lower portion 134b. As shown, the barrier layer 132 only covers the two opposite sidewalls of the lower portion 134b of the conductor fill material 134 that are substantially parallel to the bit line stack structure GC, but does not cover the other two sidewalls of the lower portion 134b that are substantially perpendicular to the bit line stack structure GC. 134t The conductor fill material 134 has a lower portion 134b and an upper portion 134t. The lower portion 134b fills in the recess defined by the barrier layer 132. Specifically, the barrier layer 132 extends along the bottom surface of the lower portion 134b of the conductor fill material 134 and further extends to the sidewalls of the lower portion 134b. As a result of the particular process sequence, the barrier layer 132 does not completely laterally surround the lower portion 1324b of the conductor fill material 134, but only covers two sidewalls of the lower portion 134b. As shown, the barrier layer 132 only covers the two opposite sidewalls of the lower portion 134b of the conductor fill material 134 that are substantially parallel to the bit line stack structure GC, but does not cover the other two sidewalls of the lower portion 134b that are substantially perpendicular to the bit line stack structure GC. 134bIn this way, the upper part 134t is less likely to form recesses or holes, and can have a flat top surface. In this way, even if there are recesses or holes in the lower part 134b of the conductor filling material 134, the conductor filling material 134 can still contact the storage capacitor (not shown) with the flatter and larger top surface of the upper part 134t. Therefore, the electrical connection between the capacitor contact structure 108 and the storage capacitor can be maintained or even improved while the memory element 10 is continuously miniaturized.

[0025] In addition to covering the lower portion 134b of the conductor filler material 134, the upper portion 134t of the conductor filler material 134 may extend laterally to cover the top of the sidewall portion of the barrier layer 132. Furthermore, in some embodiments, the upper portion 134t of the conductor filler material 134 also laterally contacts the gap wall 124 extending along the sidewall of the bit line stack structure GC.

[0026] like FIG. 2 As further shown, an insulating filler material 136 may be filled between adjacent capacitor contact structures 108. Although not shown, it should be understood that the insulating filler material 136 may, in addition to laterally contacting the capacitor contact structures 108, also laterally contact the gap walls 124 extending along the sidewalls of the bit line stack structure. As an example, the insulating filler material 136 may include silicon nitride, silicon oxide (tetraethoxysilane (TEOS), spin-on glass (SOG), the like, or combinations thereof), or combinations thereof.

[0027] As described above, the conductive filling material 134 and the barrier layer 132 based on the capacitor contact structure 108 have a special structure that ensures good electrical connection between the capacitor contact structure 108 and the storage capacitor.

[0028] FIGS. 3A-3G This is a flowchart of a method for forming a memory element 10 according to some embodiments. FIG. 2 Is FIG. 2 A three-dimensional schematic diagram of a series of intermediate structures during the manufacturing process shown.

[0029] Please refer to FIG. 3A and FIG. 2 In operation S200, an active region 100 is defined in the substrate 110 and a word line 102 is formed, and a bit line stack structure GC is formed above the substrate 110. As described above, the active region 100 can be defined by forming an isolation structure 112 in the substrate 110. Furthermore, the word line 102 can be deeply buried in the substrate 110 and covered by an insulating plug 118. Moreover, a series of deposition processes can be performed and the deposited material layers can then be patterned to form the bit line stack structure GC. In some embodiments, spacer walls 124 are further formed along the sidewalls of the bit line stack structure GC.

[0030] Referring to FIG. 3B with FIGS. 1B-1D At operation S202, a first conductor material 300 is formed to cover the substrate 110 and the bit line stack structure GC. In subsequent steps, the first conductor material 300 will be patterned into the bottom contact structure 126 of the capacitor contact structure 108 described with reference to FIG. 2 At the present stage, the first conductor material 300 is formed to a height above the height of the bit line stack GC, completely covering the bit line stack structure GC.

[0031] Referring to FIG. 3C with FIG. 2 At operation S204, portions of the first conductor material 300 above the bit line stack structure GC are removed. In some embodiments, the first conductor material 300 is thinned by a planarization process. As an example, the planarization process described herein can include a grinding process, an etching process, or a combination thereof.

[0032] Referring to FIG. 3D with FIGS. 1B-1D At operation S206, the first conductor material 300 is further thinned. As a result, the first conductor material 300 is recessed with respect to the bit line stack structure GC. In some embodiments, the recessing of the first conductor material 300 is achieved by an etching process. Furthermore, in embodiments where the first conductor material 300 is composed of polysilicon, a surface portion of the first conductor material 300 can be further silicided to form a metal silicide material layer 301. In subsequent steps, the metal silicide material layer 301 will be patterned into the metal silicide layer 130 described with reference to FIG. 2

[0033] Referring to FIG. 3E with FIGS. 1B-1D At operation S208, a tie material layer 302 is formed. In subsequent steps, the tie material layer 302 will be patterned into the tie layer 132 described with reference to FIG. 3E ​The barrier layer 132 is described. At this stage, the layer of glue material 302 conformally extends along the bottom and sidewalls of the recess defined by the first conductor material 300 (including the layer of metal silicide material 301 of the surface portion) and the bit line stack structure GC. However, the topmost end of the layer of glue material 302 is not flush with the topmost end of the recess, but is slightly lower than the top surface of the bit line stack structure GC. In some embodiments, the formation of the layer of glue material 302 includes a conformal deposition process and a non-isotropic etching process. As a result of the conformal deposition process, the layer of glue material 302 can fully cover the conductor material 300 (including the layer of metal silicide material 301 of the surface portion) and the bit line stack structure GC. After the non-isotropic etching process, the portion of the layer of glue material 302 covering the top of the bit line stack structure GC is removed, and a recess structure as shown in FIG. 2 is formed.

[0034] Referring to FIG. 3F and FIGS. 1B-1D , at operation S210, a second conductor material 304 is formed. In subsequent steps, the second conductor material 304 will be patterned into the capacitor contact structure 108 as described below. FIG. 2 The conductor fill material 134 of the capacitor contact structure 108 is described. At this stage, the conductor material fills the recess defined by the layer of glue material 302, and further forms to a height above the top surface of the bit line stack structure GC, fully covering the layer of glue material 302 and the bit line stack structure GC.

[0035] Referring to FIG. 3G and FIG. 1D , at operation S212, the portion of the second conductor material 304 above the bit line stack structure GC is removed. As a result, the top surface of the bit line stack structure GC is exposed, and the top surface of the second conductor material 304 is substantially flush with the top surface of the bit line stack structure GC. In some embodiments, the second conductor material 304 is thinned by a planarization process.

[0036] Subsequently, at operation S214, the first conductor material 300 (including the layer of metal silicide material 301 of the surface portion), the layer of glue material 302 and the second conductor material 304 are patterned. As a result of the patterning, the bottom contact structure 126, the metal silicide layer 130, the barrier layer 132 of the top contact structure 128 and the conductor fill material 134 of the top contact structure 128 of the capacitor contact structure 208 are formed, as shown in FIG. 1B As a result of being patterned in the same step, the conductor fill material 134 of the top contact structure and the barrier layer 132, the metal silicide layer 130 and the bottom contact structure 126 can have sidewalls that are substantially flush with each other.

[0037] Next, at operation S216, an insulating material 306 can be filled in between the capacitor contact structures 208, as shown inFIG. 3G The insulating fill material 136 is shown. Furthermore, although not shown, a storage capacitor is subsequently formed over the capacitor contact structure 208 to form a complete memory element 10.

[0038] In some embodiments, the patterning operations described with reference to FIG. 1D 、 FIGS. 4A-4F are implemented in a multiple patterning technique.

[0039] FIG. 4A A cross-sectional view in the second direction D2 illustrates the patterning operation of the capacitor contact structure 108.

[0040] At the stage shown, a first shield pattern 400, for example formed from photoresist, is formed over the conductor material 304. In some embodiments, prior to forming the first shield pattern 400, at least one functional layer 402 and a hard shield layer 404 are sequentially stacked over the conductor material 304. FIG. 4B At the stage shown, a second shield layer 406 is formed over the current structure. The second shield layer 406 conformally covers the first shield pattern 400 and the structure thereunder. In embodiments where the hard shield layer 404 is formed under the first shield pattern 400, the second shield layer 406 conformally extends along the surfaces of the first shield pattern 400 and the hard shield layer 404.

[0041] FIG. 4C At the stage shown, a non-isotropic etching operation is performed. As a result, the horizontally extending portions of the second shield layer 406 are removed, leaving the second shield pattern 408 extending longitudinally along the sidewalls of the first shield pattern 400. Since this patterning operation does not involve a lithography operation, it is also referred to as a self-aligned patterning operation. Furthermore, since the second shield pattern 408 is positioned between the first shield pattern 400, the pitch of the second shield pattern 408 can be shorter than the pitch of the first shield pattern 400. In situations where the pitch of the first shield pattern 400 has approached the process limit, the pitch of the second shield pattern 408 can break through the process limit.

[0042] At the stage shown, the first shield pattern 400 is removed by any suitable process, leaving the second shield pattern 408. At this point, the transfer from the shield pattern 400 with a larger pitch to the second shield pattern 408 with a shorter pitch has been accomplished. FIG. 4D At the stage shown, the first shield pattern 400 is removed by any suitable process, leaving the second shield pattern 408. At this point, the transfer from the shield pattern 400 with a larger pitch to the second shield pattern 408 with a shorter pitch has been accomplished.

[0043] FIG. 4E At the stage shown, the first shield pattern 400 is removed by any suitable process, leaving the second shield pattern 408. At this point, the transfer from the shield pattern 400 with a larger pitch to the second shield pattern 408 with a shorter pitch has been accomplished.

[0044] At the stage shown, the first shield pattern 400 is removed by any suitable process, leaving the second shield pattern 408. At this point, the transfer from the shield pattern 400 with a larger pitch to the second shield pattern 408 with a shorter pitch has been accomplished. FIG. 4F ​​At the stage shown, an etching operation is performed using the second shielding pattern 408. In some embodiments, portions of the hard shielding layer 404 and the functional layer 402 not shielded by the second shielding pattern 408 are removed, while the portions overlapping the second shielding pattern 408 are retained. In some instances, the second shielding pattern 408 and the hard shielding layer 404 are composed of the same material, and the two layers may be collectively referred to as the second shield 410.

[0045] exist FIG. 4G At the stage shown, an etching operation is performed using the second shield 410 and the patterned functional layer 402. As a result, the conductor material 304 and the bonding material layer 302 are patterned into the conductor filling material 134 and the barrier layer 132 of the top contact structure 128 of the capacitor contact structure 108. At this time, the second shield 410 can be thinned or completely consumed to expose the functional layer 402.

[0046] Finally, ​ At the stage shown, the remaining shielding (e.g., functional layer 402) is etched along with the underlying conductor filler material 134 and barrier layer 132 to pattern the metal silicide material layer 301 into the metal silicide layer 130, and the conductor material 300 into the bottom contact structure 126 of the capacitor contact structure 108. If the shielding is not completely consumed at this point, a suitable process can be performed to remove the remaining shielding (e.g., functional layer 402).

[0047] It should be understood that, in addition to the dual patterning operation described above, any other suitable patterning operation can also be used to pattern the capacitive contact structure 108. This invention is not limited thereto.

[0048] In summary, this disclosure provides a memory element and a method for forming the same. In each cell of the memory element, a capacitor contact structure for connecting the access transistor and the storage capacitor has a bottom contact structure and a top contact structure. The top contact structure has a recessed barrier layer and a conductor filler material that fills the recess in the barrier layer and extends above the top of the barrier layer. Due to the confinement within the recess of the barrier layer, the lower part of the conductor filler material may develop pits or holes during formation. However, the upper part of the conductor filler material is not confined to the recess of the barrier layer and has a larger area, making it less prone to pits or holes. Thus, the upper part of the conductor filler material can have a larger and flatter surface. Therefore, even if pits or holes exist in the lower part of the conductor filler material, the conductor filler material can still contact the storage capacitor with its flatter and larger top surface, thereby maintaining or even improving the electrical connection between the capacitor contact structure and the storage capacitor while continuously miniaturizing the memory element.

[0049] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory element, comprising: Access transistors; A capacitor contact structure, configured to connect the drain / source of the access transistor to the storage capacitor above, and includes: Bottom contact structure; and A top contact structure, disposed above the bottom contact structure, includes a barrier layer and a conductive filler material connected to the bottom contact structure via the barrier layer. The barrier layer extends along the bottom surface and two opposite sidewalls of the conductive filler material. The lower portion of the conductive filler material fills a recess defined by the barrier layer, and the upper portion of the conductive filler material is higher than the top of the barrier layer and has a greater width relative to the lower portion. The bit line stack structure is adjacent to the capacitor contact structure and has a bit line connected to the other drain / source of the access transistor.

2. The memory element of claim 1, wherein the barrier layer does not completely surround the lower portion of the conductor-filling material.

3. The memory element of claim 1, wherein the barrier layer covers the two opposite sidewalls of the conductor filling material, but does not cover the other sidewalls of the conductor filling material.

4. The memory element of claim 1, wherein the barrier layer covers only the two opposite sidewalls of the lower portion of the conductor filling material parallel to the bit line stack structure, and does not cover the other two sidewalls of the lower portion of the conductor filling material perpendicular to the bit line stack structure.

5. The memory element of claim 1, wherein the upper portion of the conductor-filling material covers the topmost part of the barrier layer.

6. The memory element of claim 1, wherein the sidewalls of the conductor filling material are substantially coplanar with the sidewalls of the barrier layer and the sidewalls of the bottom contact structure.

7. The memory element according to claim 1, further comprising: A gap wall extends between the bit line stack structure and the capacitor contact structure.

8. The memory element of claim 7, wherein the upper portion of the conductor-filling material is in lateral contact with the gap wall.

9. The memory element of claim 1, wherein the top surface of the conductor filling material is substantially flush with the top surface of the bit line stack, and the topmost point of the barrier layer is lower than the top surface of the bit line stack.

10. The memory element of claim 1, wherein the capacitor contact structure further comprises a metal silicide layer extending between the bottom contact structure and the top contact structure.

11. The memory element of claim 1, wherein the conductor filling material comprises tungsten, and the barrier layer comprises titanium and titanium nitride.

12. A method of forming a memory element, comprising: Multiple access transistors are formed in the substrate; A bit line stack structure is formed on the substrate, wherein the bit line stack traverses multiple of the plurality of access transistors; as well as A plurality of capacitive contact structures are formed on the substrate along both sides of the bit line stack structure, wherein the plurality of capacitive contact structures respectively include: Bottom contact structure; as well as A top contact structure is disposed above the bottom contact structure and includes a barrier layer and a conductor filler material connected to the bottom contact structure via the barrier layer, wherein the barrier layer extends along the bottom surface and two opposite sidewalls of the conductor filler material, the lower part of the conductor filler material fills a recess defined by the barrier layer, and the upper part of the conductor filler material is higher than the top of the barrier layer and has a greater width relative to the lower part.

13. The method of forming a memory element according to claim 12, wherein forming the plurality of capacitive contact structures comprises: A first conductor material adjacent to the bit line stack structure is formed on the substrate, wherein the top surface of the first conductor material is lower than the top surface of the bit line stack structure; An adhesive layer is formed on the first conductor material, wherein the adhesive layer conformally extends along the top surface of the first conductor material and the sidewall of the bit line stack structure; A second conductor material is formed on the adhesive material layer, wherein the top surface of the second conductor material is higher than the topmost point of the adhesive material layer and substantially flush with the top surface of the bit line stack structure; as well as A patterning operation is performed to pattern the second conductor material into a plurality of top contact structures of the plurality of capacitor contact structures, to pattern the bonding material layer into a plurality of barrier layers of the plurality of capacitor contact structures, and to pattern the first conductor material into a plurality of bottom contact structures of the plurality of capacitor contact structures.

14. The method of forming a memory element according to claim 13, wherein forming the adhesive material layer includes performing a conformal deposition operation and includes performing an isotropic etching operation such that the topmost point of the adhesive material layer is lower than the top surface of the bit line stack structure.

15. The method of forming a memory element according to claim 13, wherein the patterning operation is a double patterning operation.

Images