Method for manufacturing semiconductor device

Abstract

The present disclosure provides a method for manufacturing a semiconductor device. The semiconductor device includes a first region in which a plurality of flash memory cells, each including two memory transistors and one gate transistor disposed between the two memory transistors, are formed, and a second region in which a metal oxide semiconductor (MOS) transistor is formed. The method for manufacturing the semiconductor device comprises the steps of providing a semiconductor substrate and forming an isolation structure in the semiconductor substrate; forming a storage gate dielectric lamination layer and a first gate electrode layer of the storage transistor; removing a part corresponding to a gate structure of the gate transistor in the first region and the storage gate dielectric lamination layer and the first gate electrode layer in the second region; concurrently forming a gate dielectric layer and a second gate electrode layer of the gate transistor and the MOS transistor; forming a gate structure of the gate transistor and forming hard mask blocking parts on two sides of the gate structure; and forming a gate structure of the memory transistor in the first region and the MOS transistor in the second region.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a semiconductor device including integrally formed non-volatile memory (NVM) transistors and metal-oxide-semiconductor (MOS) transistors. Background Technology

[0002] Flash memory, or non-volatile memory for short, is a type of non-volatile memory (NVM) that retains its stored data even when power is off. It is particularly suitable for applications such as mobile communications and computer storage components. Furthermore, some flash memory types offer high-density storage capabilities, making them suitable for applications involving large-capacity mobile storage media.

[0003] Traditional flash memory uses either a floating-gate cell structure or a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) cell structure. However, both existing floating-gate and SONOS flash memory suffer from limitations in process size reduction, large cell area, high write power consumption, and large array area overhead, making it impossible to achieve high-density integration with capacities exceeding gigabit (Gb).

[0004] Furthermore, for many applications such as systems-on-a-chip (SoCs), it is desirable to integrate metal-oxide-semiconductor (MOS) transistors and NVM transistors onto a single chip or substrate. However, such integration can significantly impact the manufacturing processes of both MOS and NVM transistors.

[0005] MOS transistors are typically fabricated using a benchmark complementary metal-oxide-semiconductor (CMOS) process, which involves the formation and patterning of conductor, semiconductor, and dielectric materials. The combination of these materials, the combination and concentration of processing reagents, and the temperature used in the CMOS process are strictly controlled at each process step to ensure the resulting MOS transistor functions correctly.

[0006] Furthermore, NVM transistors include a gate dielectric stack, which typically comprises two oxide layers and a nitride or oxynitride layer sandwiched between them. The materials and processes used to manufacture these two oxide layers are often different from those used in the benchmark CMOS process flow, which may adversely affect or be influenced by the manufacturing process of MOS transistors.

[0007] Therefore, the integration of NVM transistors and MOS transistors can significantly impact the baseline CMOS process flow and typically requires numerous mask setups and processing steps, which increases manufacturing costs and reduces production efficiency.

[0008] The information disclosed in this background section is only for understanding the background of the inventive concept and may therefore contain information that does not constitute prior art. Summary of the Invention

[0009] To address the aforementioned problems in the prior art, this disclosure proposes a novel method for manufacturing semiconductor devices including integrally formed non-volatile memory (NVM) transistors and metal-oxide-semiconductor (MOS) transistors.

[0010] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided. The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which metal-oxide-semiconductor (MOS) transistors are formed, and each flash memory cell includes two storage transistors and a gate transistor disposed between the two storage transistors. The method for manufacturing a semiconductor device according to this disclosure includes: providing a semiconductor substrate and forming an isolation structure therein; forming a storage gate dielectric stack and a first gate electrode layer of storage transistors; removing portions in the first region corresponding to the gate structure of the gate transistors and in the second region the storage gate dielectric stack and the first gate electrode layer; concurrently forming gate dielectric layers and second gate electrode layers of the gate transistors and the MOS transistors; forming the gate structure of the gate transistors and forming hard mask blocking portions on both sides thereon; and forming the gate structures of the storage transistors in the first region and the MOS transistors in the second region.

[0011] According to the method for manufacturing a semiconductor device disclosed herein, non-volatile memory (NVM) transistors can be integrated into the manufacturing process of MOS transistors.

[0012] However, the effects of this disclosure are not limited to those described above, and various extensions can be made without departing from the spirit and scope of this disclosure. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further illustration of the claimed disclosure. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and, together with the specification, serve to explain the inventive concept.

[0014] Figure 1 This is a cross-sectional view showing a flash memory cell according to an embodiment of the present disclosure.

[0015] Figure 2 An equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure is shown.

[0016] Figure 3A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0017] Figures 4A to 4P It shows Figure 3 Cross-sectional views of the semiconductor device shown in the various steps of the method for manufacturing a semiconductor device. Detailed Implementation

[0018] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of the various exemplary embodiments of this disclosure. As used herein, “implementation” is a non-limiting example of an apparatus or method using one or more inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent configurations. Furthermore, the exemplary embodiments may be different, but are not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0019] For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. Although terms such as "first," "second," etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0020] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising” and / or “including” mean the presence of the stated features, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximations rather than terms of degree, and are therefore used to account for inherent deviations in measurements, calculations, and / or values ​​provided that are recognized by those skilled in the art.

[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having meanings consistent with their meanings in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0022] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be exhaustive and complete, and will fully convey the scope of the disclosure to those skilled in the art. The same reference numerals denote the same elements throughout the drawings. Furthermore, in the drawings, for clarity, components are not necessarily drawn to scale, and the proportions and dimensions of components may be enlarged.

[0023] This document describes, with reference to the accompanying drawings, embodiments of a method for manufacturing a semiconductor device by integrating non-volatile memory (NVM) transistors into a complementary metal-oxide-semiconductor (CMOS) fabrication process or flow that includes metal-oxide-semiconductor (MOS) transistors. However, specific embodiments may be implemented without using one or more of these specific details, or may be combined with other known methods, materials, and apparatuses. In the following description, numerous specific details, such as specific materials, dimensions, and process parameters, are set forth to provide a thorough understanding of the invention. In the embodiments, well-known semiconductor design and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the invention. References to “in embodiments” throughout the specification mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase “in embodiments” appearing throughout the specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0024] The embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings.

[0025] Figure 1 A cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown. Figure 2 An equivalent circuit diagram of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown.

[0026] like Figure 1As shown, the flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101, which includes a second-doped deep well region DNW 103 and a first-doped storage well region CPW 102 disposed on the deep well region DNW 103.

[0027] Although the first doping type is defined as P-type and the second doping type as N-type by way of example herein, this disclosure is not limited thereto. In alternative embodiments of this disclosure, the first doping type may also be N-type, in which case the second doping type may be P-type.

[0028] According to embodiments of this disclosure, substrate 101 may be, for example, a silicon substrate.

[0029] In addition, refer to Figure 1 and Figure 2 The flash memory cell MC 100 includes a first storage transistor MS110, a gating transistor MG 120, and a second storage transistor MD 130 connected in series. The first storage transistor MS110 can be disposed on the storage well region CPW 102 and stores first data DATA1. The second storage transistor MD 130 can be disposed on the storage well region CPW 102 and stores second data DATA2. The gating transistor MG 120 is disposed horizontally along the direction DR1 on the storage well region CPW 102 between the first storage transistor MS110 and the second storage transistor MD 130, for isolating the first storage transistor MS110 and the second storage transistor MD 130 and performing a gating operation on the first storage transistor MS110 and the second storage transistor MD 130.

[0030] According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, so the flash memory cell MC 100 can realize the function of two-bit storage, that is, simultaneously storing the first data DATA1 and the second data DATA2.

[0031] In addition, such as Figure 1 As shown, the source region of the first storage transistor MS110 is connected to the first electrode S of the flash memory cell MC100, and it can also be referred to as the source S of the flash memory cell MC100. The drain region of the second storage transistor MD130 is connected to the second electrode D of the flash memory cell MC100, and it can also be referred to as the drain D of the flash memory cell MC100.

[0032] Those skilled in the art will recognize that the source and drain of a flash memory cell are defined herein for ease of description; however, the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" may be used interchangeably under different operating conditions.

[0033] In addition, such as Figure 1 As shown, the first storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask blocking portion 117 sequentially arranged along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. Furthermore, the second storage transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask blocking portion 137 sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked along the vertical direction.

[0034] According to embodiments of this disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130, thus enabling two-bit storage functionality.

[0035] According to embodiments of this disclosure, such as Figure 1 As shown, the flash memory cell MC 100 for two-bit storage can be composed of three closely arranged transistors: a gating transistor MG 120 located in the middle of the flash memory cell MC 100, a first storage transistor MS110 located at the first end of the flash memory cell MC 100, and a second storage transistor MD 130 located at the second end of the flash memory cell MC 100.

[0036] like Figure 1 As shown, the flash memory cell MC 100 can be formed on the memory well region CPW 102 within the semiconductor substrate 101. Furthermore, in order to isolate the memory well region CPW 102 from the substrate 101 so that a voltage can be applied to the memory well region CPW 102 under certain operating conditions, such as... Figure 1 As shown, the storage well region CPW 102 can be formed in the deep well region DNW 103.

[0037] like Figure 1 As shown, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 100. The source region 140 is connected to the upper metal source 142, i.e., the first electrode S, through a contact hole 141, and the drain region 150 is connected to the upper metal drain 152, i.e., the second electrode D, through a contact hole 151.

[0038] According to embodiments of this disclosure, the first electrode S and the second electrode D may comprise metal or highly doped polycrystalline silicon. When the first electrode S and the second electrode D are formed of metal, they may comprise at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0039] As mentioned above, Figure 1 As shown, the gate structure of the first storage transistor MS110 may, from bottom to top, include a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 for sidewall self-alignment. According to embodiments of this disclosure, the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. According to embodiments of this disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination of the above materials.

[0040] In addition, such as Figure 1 As shown, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (barrier oxide layer) 115 stacked sequentially along the vertical direction. According to embodiments of this disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide.

[0041] According to embodiments of this disclosure, the storage medium layer 114 may include one or more layers of storage media. Furthermore, according to embodiments of this disclosure, the storage medium forming the storage medium layer 114 may include: mono- or multi-component oxides, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; mono- or multi-component nitrides, such as silicon nitride; mono- or multi-component nitride oxides, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or combinations of the above materials.

[0042] According to embodiments of this disclosure, when the storage medium layer 114 is formed of, for example, silicon nitride, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS110 can be a SONOS-type storage transistor.

[0043] Furthermore, according to embodiments of this disclosure, the first storage transistor MS110 may be another trap charge-trapping storage transistor with a similar operating mechanism to conventional SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type storage transistors. This type of storage transistor uses a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., to replace silicon nitride in the SONOS memory as the storage medium layer 114.

[0044] Furthermore, according to embodiments of this disclosure, the first storage transistor MS110 may also be a floating-gate storage transistor. This type of storage transistor uses polysilicon instead of silicon nitride in the SONOS memory to form a floating gate for storing charge, as the storage medium layer 114.

[0045] Furthermore, according to embodiments of this disclosure, the first storage transistor MS110 may also be a nano-crystal memory, in which a nano-crystal with quantum dots is used to replace silicon nitride in the SONOS memory as the storage medium layer 114.

[0046] According to embodiments of this disclosure, the length of the gate electrode 116 of the first storage transistor MS110 can be defined by the length of the hard mask blocking portion 117 disposed on the gate electrode 116 through a self-alignment process. Those skilled in the art should note that, as used herein, "length" refers to the dimension of the described object in the horizontal direction DR1, and "thickness" refers to the dimension of the described object in the vertical direction DR2.

[0047] According to embodiments of this disclosure, except that it is disposed on the opposite side of the gate transistor MG 120, the second storage transistor MD 130 has the same structure as the first storage transistor MS110 and can be manufactured by the same process as the first storage transistor MS110. Therefore, for the sake of brevity, a detailed description of the structure of the second storage transistor MD 130 will be omitted here.

[0048] The gate structure of the gate transistor MG 120 may, from bottom to top, include a channel region 121, a gate dielectric layer 122, a gate electrode 123, and a metal silicide 126. According to embodiments of this disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to a word line, and the length of the gate electrode 123 is defined by the process dimensions of the photolithography process. According to embodiments of this disclosure, the gate dielectric layer 122 may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, or a combination of the above materials. Furthermore, according to embodiments of this disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. It should be noted that the gate structure of the gate transistor MG 120 includes the metal silicide 126 disposed above the gate electrode 123 only when the gate electrode 123 is formed of polysilicon.

[0049] According to embodiments of this disclosure, the channel regions 111, 131, and 121 of the first storage transistor MS110, the second storage transistor MD130, and the gating transistor MG120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may be lower than the doping concentration of the channel region 121 of the gating transistor MG120.

[0050] Furthermore, according to embodiments of this disclosure, the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may have a second doping type or an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0051] For example, such as Figure 1 As shown, when the first doping type is P-type and the second doping type is N-type, the doping concentration of the P-type channels 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 is lower than the doping concentration of the P-type channel 121 of the gate transistor MG120. Furthermore, according to embodiments of this disclosure, channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0052] According to an embodiment of the present disclosure, the flash memory cell MC 100 further includes: a first isolation section 124 disposed along the horizontal direction DR1 between the first storage transistor MS110 and the gate transistor MG 120, for isolating the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation section 125 disposed along the horizontal direction DR1 between the gate transistor MG 120 and the second storage transistor MD 130, for isolating the gate electrode 123 of the gate transistor MG 120 and the gate electrode 136 of the second storage transistor MD 130.

[0053] Specifically, such as Figure 1 As shown, a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120. They are used to electrically isolate the gate electrode 116 of the first storage transistor MS 110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length, respectively. According to an embodiment of this disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

[0054] like Figure 2 As shown, the flash memory cell MC 100 includes a first storage transistor MS110, a gating transistor MG 120, and a second storage transistor MD 130 connected in series. The gating transistor MG 120 can isolate the first storage transistor MS110 and the second storage transistor MD 130 and perform a gating operation on the first storage transistor MS110 and the second storage transistor MD 130.

[0055] The flash memory cell according to the embodiments of this disclosure can realize two storage transistors in one flash memory cell, thus greatly reducing the equivalent area of ​​each storage bit, thereby achieving lower cost and higher integration density.

[0056] Furthermore, the storage transistors in the flash memory cells according to embodiments of this disclosure can use a simple SONOS-type device structure, which has the advantages of simple process, low gate electrode operating voltage, and good data retention reliability.

[0057] Furthermore, in the flash memory cell according to the embodiments of this disclosure, the mutual influence between two memory bits is isolated by a gating transistor, and the distribution width and lateral diffusion of the storage charge are suppressed, thereby enabling a higher storage charge density to be obtained in the silicon nitride storage layer, significantly improving the storage window and data reliability.

[0058] Specifically, the equivalent channel length of the flash memory cell according to embodiments of this disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the gate electrode length of the gate transistor is defined by the process feature size of the photolithography process, and is typically approximately equal to or slightly larger than the critical feature size of the photolithography process, which is usually denoted as F (or CF). Furthermore, the gate electrode lengths of the first and second storage transistors are each defined by the length of the self-aligned sidewall hard mask blocking portion, and therefore their dimensions can be smaller than F. Thus, according to embodiments of this disclosure, a smaller channel length of the flash memory cell can be obtained with the same process feature size, thereby achieving the goal of reducing the area and manufacturing cost of the flash memory cell.

[0059] Furthermore, in a flash memory array composed of flash memory cells according to embodiments of the present disclosure, for flash memory cells not selected for operation, the gate electrodes of the selection transistor and the first and second storage transistors are grounded, thereby completely turning off the entire series channel of the flash memory cell and increasing the equivalent channel length. This avoids source-drain punch-through of the flash memory cell under high operating voltages at smaller process feature sizes, thus overcoming the problem that the gate electrode length of existing flash memory cells cannot be reduced as process feature sizes shrink. Therefore, the flash memory cells according to embodiments of the present disclosure have better process miniaturization capabilities, thereby enabling smaller cell areas and manufacturing costs by reducing process feature sizes.

[0060] Furthermore, in the flash memory cell according to embodiments of this disclosure, by reducing the doping concentration of the P-type channel regions of the first and second storage transistors or designing them as N-type doped channel regions, the threshold voltage of the storage transistors and the gate electrode operating voltage during erase, write, and read operations can be reduced, thereby improving the reliability of the storage transistors. Simultaneously, by increasing the doping concentration of the P-type channel region of the gate transistor, the punch-through voltage of the flash memory cell can be increased, and the leakage current in the source and drain regions of unselected flash memory cells can be reduced.

[0061] Next, we will refer to Figure 3 and Figures 4A to 4P A method for manufacturing a semiconductor device according to embodiments of the present disclosure is described. Figure 3 A flowchart of a method 300 for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown. Figures 4A to 4P It shows Figure 3 Cross-sectional views of the semiconductor device in each step of the method 300 for manufacturing a semiconductor device are shown.

[0062] Reference Figure 3 In step S301, as Figure 4AAs shown, a wafer is provided as a substrate 401. According to embodiments of the present disclosure, the wafer may be a first-doped wafer used as a semiconductor substrate, such as a silicon substrate. According to embodiments of the present disclosure, the first doping type may be defined as P-type and the second doping type may be defined as N-type; however, those skilled in the art will recognize that the present disclosure is not limited thereto, and the first doping type may also be N-type, in which case the second doping type may be P-type.

[0063] like Figure 4A As shown, the wafer can be pre-treated, for example, by sequentially forming a pad layer 402, for example, formed of silicon oxide, and a cap layer 403, for example, formed of silicon nitride, on a substrate 401. The pad layer 402 can be used to reduce the stress of the cap layer 403. According to embodiments of this disclosure, the pad layer 402 can be formed by, for example, thermal oxidation, in-situ water vapor oxidation (ISSG), or deposition processes, and its thickness is typically 10 nm to 100 nm. Furthermore, according to embodiments of this disclosure, the cap layer 403 can be formed by deposition processes, such as the commonly used low-pressure chemical vapor deposition (LPCVD) process, and its thickness is typically 20 nm to 200 nm.

[0064] Subsequently, referring to Figure 3 In step S302, as Figure 4B As shown, according to embodiments of the present disclosure, a plurality of isolation structures 404 defining active regions can be formed in a substrate 401 by active region patterning. According to embodiments of the present disclosure, the isolation structures 404 can divide the substrate 401 into a first region NVMR in which flash memory cells are disposed and a second region MSR adjacent to the first region NVMR in which metal-oxide-semiconductor (MOS) transistors are disposed.

[0065] According to embodiments of this disclosure, the flash memory cells disposed in the first region NVMR can correspond to, for example, those described above. Figure 1 and Figure 2 The described flash memory cell MC 100 includes two storage transistors, as shown in the reference above. Figure 1 and Figure 2 The first storage transistor MS110 and the second storage transistor MD130 are described, as well as a gating transistor, such as those mentioned above. Figure 1 and Figure 2 The described gating transistor 120.

[0066] According to embodiments of this disclosure, a plurality of components similar to those described above can be provided in the first region NVMR of the semiconductor device. Figure 1 and Figure 2The described flash memory cell MC 100 is a flash memory array composed of identical flash memory cells. Furthermore, although not shown in the figures, according to embodiments of this disclosure, each column of flash memory cells in the flash memory array disposed in the first region NVMR can also be isolated from adjacent columns of flash memory cells via isolation structure 404.

[0067] According to embodiments of this disclosure, the MOS transistor disposed in the second region MSR can be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor. According to embodiments of this disclosure, the MOS transistor in the second region MSR can constitute peripheral circuitry for the flash memory cell array in the first region NVMR.

[0068] Furthermore, according to embodiments of this disclosure, the MOS transistor disposed in the second region MORS can also be isolated from adjacent MOS transistors through the isolation structure 404.

[0069] According to embodiments of this disclosure, the active region patterns of the first region NVMR and the second region MORS can be simultaneously achieved using the same active region mask layer in a single photolithography process. Alternatively, the active region patterns of the first region NVMR and the second region MORS can also be achieved using different active region mask layers in two photolithography processes.

[0070] Despite Figure 4B As shown, according to embodiments of this disclosure, the isolation structure 404 can be implemented using a shallow trench isolation (STI) process, but this disclosure is not limited thereto. Those skilled in the art will recognize that the isolation structure can also be implemented using any isolation process commonly used in integrated circuit manufacturing, such as localized oxide isolation (LOCOS) process.

[0071] For example, according to embodiments of this disclosure, the isolation structure 404 can be formed by an STI process. Specifically, the STI process may include: sequentially removing a portion of the capping layer 403 and a portion of the padding layer 402 by an etching process to form a shallow trench structure with a specific depth in the substrate 401; filling the substrate surface with an isolation dielectric layer or a multilayer composite isolation dielectric layer, such as silicon oxide, silicon nitride, and / or polysilicon, by a thermal oxidation or low-pressure deposition process; and removing the isolation dielectric layer, capping layer 403, and padding layer 402 by a chemical mechanical polishing (CMP) process and / or an etching process to obtain a flat surface of the substrate 401.

[0072] According to embodiments of this disclosure, the isolation structure 404 in the first region NVMR and the second region MORS can be implemented using a single isolation process. Alternatively, the isolation structure 404 in the first region NVMR and the second region MORS can be implemented using two separate isolation processes to form isolation structures 404 with different widths or depths in the first region NVMR and the second region MORS, respectively.

[0073] Subsequently, referring to Figure 3 In step S303, as Figure 4C As shown, according to embodiments of this disclosure, a flash memory cell's well region, such as a deep well region (DNW) and a storage well region (CPW), can be formed in a first region NVMR using a first injection process. According to embodiments of this disclosure, the deep well region (DNW) of the flash memory cell can correspond to, for example, the region described above. Figure 1 The second doped type deep well region DNW 103 is described, and the well region CPW of the flash memory cell can correspond to, for example, the above reference. Figure 1 The first doped type of storage well region CPW 102 is described. Furthermore, according to embodiments of this disclosure, the MOS transistors of the second region MSR can also be disposed in the deep well region DNW.

[0074] In addition, such as Figure 4C As shown, according to embodiments of this disclosure, the first channel layer 405 of the flash memory cell can also be formed in the first region NVMR by a first implantation process. According to embodiments of this disclosure, the first channel layer 405 of the flash memory cell can be used to subsequently form, for example, the layer described above. Figure 1 The channel region 111 of the first storage transistor MS110, the channel region 121 of the gating transistor MG 120, and the channel region 131 of the second storage transistor MD 130 are described.

[0075] According to embodiments of this disclosure, the first implantation process may include at least one of the following process steps: first well implantation, first penetration-resistant implantation, and first adjustment-on implantation. According to embodiments of this disclosure, the first well implantation, first penetration-resistant implantation, and first adjustment-on implantation can all be implemented as ion implantation. Ion implantation refers to implanting an appropriate type of ion into an appropriate concentration using appropriate energy. According to embodiments of this disclosure, the ion type, dosage, and energy used in each process step of the first well implantation, first penetration-resistant implantation, and first adjustment-on implantation may be the same or different.

[0076] For example, for an N-type flash memory cell according to this embodiment, the first well region implantation can use a first doping type, namely P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type well region, such as a storage well region CPW, at a suitable depth inside the substrate of the first region NVMR.

[0077] According to embodiments of this disclosure, the first punch-through blocking implantation can use P-type impurity ions, such as boron ions or boron difluoride ions, to form a P-type first punch-through barrier (not shown) at a suitable depth on the substrate subsurface of the first region NVMR, thereby reducing the junction electric field of the source-drain junction and improving the device breakdown voltage capability.

[0078] According to embodiments of this disclosure, the first turn-on implantation can use P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, to form a P-type first channel layer 405 at the substrate surface of the first region NVMR, and to implant storage transistors (e.g., as described above). Figure 1 The initial threshold voltage of the first storage transistor MS110 and the second storage transistor MD130 described is adjusted to 0V or greater.

[0079] Alternatively, according to embodiments of the present disclosure, the first turn-on implantation may also use a second doping type, namely N-type impurity ions, such as phosphorus ions or arsenic ions, to form an N-type first channel layer 405 at the substrate surface of the first region NVMR, and adjust the initial threshold voltage of the storage transistor to 0V or less.

[0080] Alternatively, according to embodiments of the present disclosure, the first on-state injection to confine the substrate surface of the first region NVMR to an intrinsic or low-concentration doped state may be omitted, thereby adjusting the initial threshold voltage of the storage transistor to an intrinsic state close to 0V.

[0081] According to embodiments of this disclosure, by using storage transistors (e.g., as described above) Figure 1 The initial threshold voltage of the first storage transistor MS110 and the second storage transistor MD130 described is adjusted to be less than 0V or close to 0V, which can reduce the gate operating voltage of the storage transistor and thus improve the read and write operation performance.

[0082] Subsequently, referring to Figure 3 In step S304, as Figure 4D As shown, according to embodiments of this disclosure, a well region of a MOS transistor can be formed in a second region of the MSR using a second implantation process. As described above, according to embodiments of this disclosure, the MOS transistor in the second region of the MSR can be one or more of a low-voltage LV-MOS transistor, an interface IO-MOS transistor (not shown), and a high-voltage HV-MOS transistor. For example, as... Figure 4D As shown, the well regions PW and NW (not shown) of the low-voltage LV-MOS transistor and the well regions HVPW and HVNW (not shown) of the high-voltage HV-MOS transistor can be formed in the second region MSR through the second implantation process.

[0083] In addition, such as Figure 4D As shown, according to embodiments of this disclosure, a second channel layer 406 of a MOS transistor can also be formed in the second region MSR using a second implantation process. Figure 4D As shown, according to an embodiment of the present disclosure, the second channel layer 406 may include a channel region of a low-voltage LV-MOS transistor and a channel region of a high-voltage HV-MOS transistor.

[0084] Similar to the first implantation process described above, according to embodiments of this disclosure, the second implantation process may include at least one of the following process steps: second well region implantation, second penetration-blocking implantation, and second adjustment-on implantation. According to embodiments of this disclosure, the second well region implantation, the second penetration-blocking implantation, and the second adjustment-on implantation can all be implemented as ion implantation. Furthermore, the ion type, dosage, and energy used in each process step of the second well region implantation, the second penetration-blocking implantation, and the second adjustment-on implantation may be the same or different.

[0085] According to embodiments of this disclosure, in the second region MSR, the order of the second implantation process for the low-voltage LV-MOS transistor, the second implantation process for the interface IO-MOS transistor, and the second implantation process for the high-voltage HV-MOS transistor can be arbitrarily combined. For example, the second implantation process for the low-voltage LV-MOS transistor can be performed first, followed by the second implantation process for the interface IO-MOS transistor, and finally the second implantation process for the high-voltage HV-MOS transistor.

[0086] Furthermore, according to embodiments of this disclosure, the order of the first implantation process for the first region NVMR and the second implantation process for the second region MSR can be arbitrarily combined. For example, although in this embodiment the first implantation process for the first region NVMR is performed first and then the second implantation process for the second region MSR is performed, this disclosure is not limited thereto. Alternatively, the second implantation process for the second region MSR may be performed first, and then the first implantation process for the first region NVMR may be performed.

[0087] Furthermore, according to embodiments of this disclosure, the order of the first injection process for the first region NVMR, the second injection process for the low-voltage LV-MOS transistor in the second region MSR, the second injection process for the interface IO-MOS transistor in the second region MSR, and the second injection process for the high-voltage HV-MOS transistor in the second region MSR can be arbitrarily combined.

[0088] Subsequently, referring to Figure 3 In step S305, as Figure 4EAs shown, according to an embodiment of the present disclosure, the surface of the substrate 401 can be cleaned or pre-cleaned, and then a stacked structure 411 including a storage gate dielectric stack 407, a first gate electrode layer 408, a first hard mask barrier layer 409 and a sacrificial layer 410 can be sequentially formed on the surface of the substrate 401 by oxidation, deposition or sputtering processes.

[0089] For example, according to embodiments of this disclosure, the storage gate dielectric stack 407 can be used to subsequently form, for example, as described above. Figure 1 The described flash memory cell MC 100 has a gate dielectric stack 112 for the first storage transistor MS 110 and a gate dielectric stack 132 for the second storage transistor MS 130. Therefore, according to embodiments of the present disclosure, the storage gate dielectric stack 407 may include, from bottom to top in the vertical direction, a first oxide layer (tunneling oxide layer) 407a, a storage dielectric layer (charge storage layer) 407b, and a second oxide layer (barrier oxide layer) 407c.

[0090] According to embodiments of this disclosure, the first oxide layer 407a and the second oxide layer 407c may include, for example, silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or a combination of the above materials. For example, when the first oxide layer 407a and the second oxide layer 407c include silicon oxide, the first oxide layer 407a and the second oxide layer 407c may be formed using processes such as thermal oxidation, high-temperature thermal oxidation (HTO), low-pressure chemical vapor deposition, in-situ water vapor oxidation, and atomic layer deposition (ALD), and their thickness is typically 1 nm to 20 nm.

[0091] According to embodiments of this disclosure, the storage medium layer 407b may include one or more storage medium sublayers. Furthermore, as described above, according to embodiments of this disclosure, the storage medium forming the storage medium layer 407b may include: mono- or multi-component oxides, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, or hafnium aluminum oxide; mono- or multi-component nitrides, such as silicon nitride; mono- or multi-component oxynitrides, such as silicon oxynitride; polycrystalline silicon or nanocrystals; or combinations of the above materials. For example, when the storage medium layer 407b includes silicon nitride, it can be formed using processes such as low-pressure chemical vapor deposition or atomic layer deposition, and its thickness is typically 2 nm to 20 nm.

[0092] For example, according to embodiments of this disclosure, when the storage medium layer 407b comprises silicon nitride, a plurality of stacked storage medium sublayers can be formed as the storage medium layer 407b during its fabrication using a suitable reactive gas flow rate ratio. For example, as Figure 4EAs shown, according to embodiments of this disclosure, the storage medium layer 407b may include a first storage medium sublayer 407b1, a second storage medium sublayer 407b2, and a third storage medium sublayer 407b3 formed sequentially from bottom to top above the first oxide layer 407a. The second storage medium sublayer 407b2 has a higher silicon content than the first and third storage medium sublayers 407b1 and 407b3, and is therefore referred to as "silicon-rich silicon nitride". Furthermore, according to embodiments of this disclosure, the thickness of the first storage medium sublayer 407b1 is 1 nm to 3 nm, and the thicknesses of the second and third storage medium sublayers 407b2 and 407b3 are both 2 nm to 10 nm.

[0093] Preferably, such as Figure 4E As shown, according to embodiments of this disclosure, the storage medium layer 407b may further include a third storage medium sublayer 407b3 and a fourth storage medium sublayer 407b4 disposed on the third storage medium sublayer 407b3, wherein the fourth storage medium sublayer 407b4 has a higher silicon content than the third storage medium sublayer 407b3, and therefore may also be referred to as "silicon-rich silicon nitride". Furthermore, according to embodiments of this disclosure, the thickness of the fourth storage medium sublayer 407b4 may also be from 2 nm to 10 nm.

[0094] According to embodiments of this disclosure, one or more gases selected from nitrogen (or argon), hydrogen (and / or oxygen), nitrous oxide (or nitric oxide) can be combined in a suitable proportion to perform high-temperature annealing on the storage gate dielectric stack 407 to convert the silicon-rich silicon nitride of the fourth storage dielectric sublayer 407b4 below the second oxide layer 407c into silicon oxynitride, while simultaneously densifying the second oxide layer 407c to improve the leakage characteristics of the second oxide layer (barrier oxide layer) 407c. According to embodiments of this disclosure, the annealing temperature is 800°C to 950°C, and the annealing time is 10 minutes to one hour.

[0095] Those skilled in the art will recognize that although the embodiments of this disclosure have been described above with reference to the example of storage medium layer 407b comprising four storage medium sublayers 407b1 to 407b4, this disclosure is not limited thereto. For example, storage medium layer 407b may also comprise more or fewer storage medium sublayers than four.

[0096] It should be noted that the silicon content described in this article refers to the relative proportions of each chemical element in the storage medium sublayer, measured in atomic relative quantities. For example, the Si / N ratio in the second storage medium sublayer 407b2 is higher than that in the first storage medium sublayer 407b1. Therefore, the second storage medium sublayer 407b2 has properties closer to silicon, such as a higher refractive index and a higher trap density than Si3N4, while the first storage medium sublayer 407b1 and the third storage medium sublayer 407b3 have properties closer to Si3N4.

[0097] According to embodiments of this disclosure, the first gate electrode layer 408 can be used to subsequently form, for example, as described above. Figure 1 The described flash memory cell MC 100 includes the gate electrode 116 of the first storage transistor MS110 and the gate electrode 136 of the second storage transistor MS130. Therefore, as described above, according to embodiments of the present disclosure, the first gate electrode layer 408 may include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. According to embodiments of the present disclosure, the first gate electrode layer 408 may be formed by, for example, deposition or sputtering processes. For example, when the first gate electrode layer 408 comprises polysilicon, a low-pressure chemical vapor deposition process may be used to form the first gate electrode layer 408, with a thickness of 10 nm to 200 nm.

[0098] According to embodiments of the present disclosure, when the first gate electrode layer 408 comprises polysilicon, N-type impurities such as phosphorus or arsenic can be added to the first gate electrode layer 408 using methods such as in-situ doping or ion implantation. Alternatively, according to embodiments of the present disclosure, when the first gate electrode layer 408 comprises polysilicon, P-type impurities such as boron or indium can also be added to the first gate electrode layer 408 to reduce the Fermi potential of the first gate electrode layer 408, thereby increasing the electron barrier height of the first gate electrode layer 408 and the underlying second oxide layer (barrier oxide layer) 407c to improve the erase characteristics and reliability of the memory transistors in the flash memory cell.

[0099] Alternatively, although not shown in the figures, according to embodiments of the present disclosure, when the first gate electrode layer 408 comprises polysilicon, a high work function metal interface layer can be formed between the second oxide layer (barrier oxide layer) 407c and the first gate electrode layer 408. Alternatively, according to embodiments of the present disclosure, the first gate electrode layer 408 can be formed directly using a high work function metal material. According to embodiments of the present disclosure, the metal interface layer or metal material, such as titanium or titanium nitride, has a higher work function than polysilicon, which can increase the electron barrier height of the first gate electrode layer 408 and the underlying second oxide layer (barrier oxide layer) 407c to improve the erase characteristics and reliability of the memory transistors in the flash memory cell.

[0100] According to embodiments of the present disclosure, the first hard mask barrier layer 409 and the sacrificial layer 410 may comprise, for example, silicon oxide, silicon nitride, silicon glass, amorphous silicon, or a combination of the above materials. According to embodiments of the present disclosure, the first hard mask barrier layer 409 and the sacrificial layer 410 may be formed by processes such as oxidation, high-temperature thermal oxidation, deposition, or sputtering. For example, a first hard mask barrier layer 409 comprising silicon oxide and a sacrificial layer 410 comprising silicon nitride may be sequentially formed over the first gate electrode layer 408 by a low-pressure chemical vapor deposition process, wherein the thickness of the first hard mask barrier layer 409 is approximately 10 nm to 50 nm, and the thickness of the sacrificial layer 410 is approximately 20 nm to 100 nm. According to embodiments of the present disclosure, the first hard mask barrier layer 409 and the sacrificial layer 410 may have relatively high etch selectivity relative to each other.

[0101] Subsequently, referring to Figure 3 In step S306, as Figure 4F As shown, according to embodiments of this disclosure, the gating transistors of flash memory cells can be removed by patterning (e.g., as described above). Figure 1 The gate region of the gate transistor MG120 of the described flash memory cell MC 100 and the stacked structure 411 in the second region MSR are described by sequentially removing the sacrificial layer 410, the first hard mask barrier layer 409, the first gate electrode layer 408, and the storage gate dielectric stacked layer 407, so that the surface of the substrate 401 is exposed in the second region MSR, and a trench 412 is formed in the first region NVMR in which the gate structure of the gate transistor is subsequently formed, wherein the trench 412 also exposes the surface of the substrate 401 at the bottom. In addition, as further described below, the remaining stacked structure 411 in the first region NVMR can be used to form the storage transistor of the flash memory cell (e.g., referred to above). Figure 1 The gate structure of the first storage transistor MS110 and the second storage transistor MS130 of the described flash memory cell MC100.

[0102] Subsequently, as Figure 4F As shown, according to embodiments of the present disclosure, an isolation layer 413 can be formed on the exposed surface of the substrate 401 and the sidewalls and / or over the remaining stacked structure 411 by, for example, thermal oxidation, high-temperature thermal oxidation, or low-pressure chemical vapor deposition processes. According to embodiments of the present disclosure, the isolation layer 413 may comprise silicon oxide, silicon oxynitride, silicon nitride, or a combination of the above materials, with a thickness of approximately 5 nm to 30 nm.

[0103] Subsequently, as Figure 4FAs shown, according to embodiments of this disclosure, the isolation layer 413 above the substrate 401 and / or the stacked structure 411 can be removed by anisotropic and / or isotropic etching, while the isolation layer 413 is retained on the sidewalls of the stacked structure 411 to form isolation between the gate structure of the storage transistor and the gate structure of the select transistor of the flash memory cell, which can correspond to, for example, the above reference. Figure 1 The first isolation section 124 and the second isolation section 125 of the described flash memory cell MC 100.

[0104] Subsequently, referring to Figure 3 In step S307, as Figure 4G As shown, according to embodiments of this disclosure, the gate transistors of flash memory cells can be formed by performing a third injection process in trench 412 (e.g., as described above). Figure 1 The channel region 414 of the gate transistor MG 120 of the described flash memory cell MC 100 can correspond to, for example, the above reference. Figure 1 The described flash memory cell MC 100 has a gate transistor MG 120 with a channel region 121. According to embodiments of this disclosure, the third implantation process may include at least one of the following process steps: third punch-through implantation and third modulation-on implantation. According to embodiments of this disclosure, both third punch-through implantation and third modulation-on implantation can be implemented as ion implantation, wherein the ion type, dose, and energy used in third punch-through implantation and third modulation-on implantation may be the same or different.

[0105] For example, for the N-type flash memory cell (or NVM transistor) according to this embodiment, the third punch-through isolation implantation can use P-type impurity ions, such as boron ions or boron difluoride ions, in the gate transistor of the flash memory cell (e.g., referred to above). Figure 1 A second P-type punch-through barrier (not shown) is formed at a suitable depth on the subsurface of the substrate of the gate transistor MG 120 of the described flash memory cell MC 100, thereby suppressing leakage current and increasing the source-drain punch-through voltage. According to embodiments of this disclosure, the P-type impurity concentration of the second punch-through barrier can be higher than that of the first punch-through barrier.

[0106] Furthermore, according to embodiments of this disclosure, the third modulation-on implantation can use P-type impurity ions, such as boron ions, boron difluoride ions, or indium ions, to form the P-type channel region 414 of the flash memory cell's gate transistor on the substrate surface below the trench 412, thereby allowing the threshold voltage of the gate transistor to be adjusted to be greater than 0V and less than 1V. As described above, according to embodiments of this disclosure, the P-type impurity concentration of the channel region 414 of the flash memory cell's gate transistor can be higher than the P-type impurity concentration of the channel region of the flash memory cell's storage transistor.

[0107] According to embodiments of this disclosure, the first adjustment-on implantation step in the first implantation process and the third adjustment-on implantation step in the subsequent third implantation process can respectively adjust and control the storage transistors of the flash memory cell by controlling the doping concentration (e.g., as described above). Figure 1 The described flash memory cell MC 100 includes a first storage transistor MS110 and a second storage transistor MD 130, and a gating transistor (e.g., referred to above). Figure 1 The doping concentration of the channel region of the gating transistor MG 120 of the described flash memory cell MC 100 is, for example, as described above, such that the doping concentration of the channel region of the storage transistor is lower than the doping concentration of the channel region of the gating transistor. Furthermore, the threshold voltages of the storage transistor and the gating transistor of the flash memory cell can be adjusted and controlled, thereby achieving better cell read / write performance and off-state performance.

[0108] According to embodiments of this disclosure, the above references Figure 4D Description Figure 3 The second injection process in step S304 can also be referenced. Figure 4F The process is performed after step S306, that is, after removing the portion of the first region NVM corresponding to the gate structure of the gate transistor and the stacked structure 411 in the second region MSR, in order to avoid the high temperature in the fabrication process of the storage gate dielectric stack 407 of the storage transistor from adversely affecting the performance of the MOS transistor in the second region MSR.

[0109] Subsequently, referring to Figure 3 In step S308, as Figure 4H As shown, according to an embodiment of this disclosure, after pre-cleaning the wafer, the gate dielectric layer 415 of the flash memory cell in the first region NVMR can be simultaneously or sequentially formed on the surface of the exposed substrate 401 by one or more gate oxide processes, which can correspond to, for example, the above-described reference. Figure 1 The gate dielectric layer 122 of the gating transistor MG 120 of the described flash memory cell MC 100; and the gate dielectric layer of the MOS transistor in the second region MSR, for example... Figure 4H The gate dielectric layer 416 of the low-voltage LV-MOS transistor and the gate dielectric layer 417 of the high-voltage HV-MOS transistor are shown.

[0110] According to embodiments of this disclosure, gate dielectric layers 415, 416, and 417 may comprise silicon oxide, silicon oxynitride, hafnium oxide, or a combination of the above materials. Furthermore, according to embodiments of this disclosure, the gate oxide process used to form gate dielectric layers 415, 416, and 417 can be a gate oxide process commonly used in standard CMOS processes. For example, when using silicon oxide to form the gate dielectric layer, the gate oxide process can be thermal oxidation, high-temperature thermal oxidation, low-pressure chemical vapor deposition, in-situ water vapor oxidation, atomic layer deposition, etc., and the thickness of the formed gate dielectric layer is typically 1 nm to 20 nm.

[0111] According to embodiments of this disclosure, depending on the configuration requirements of the MOS transistors in the second region MSR, one, two or more gate oxide processes can be combined to form a gate dielectric layer 416 of a low-voltage LV-MOS transistor and / or a gate dielectric layer (not shown) of an interface IO-MOS transistor and / or a gate dielectric layer 417 of a high-voltage HV-MOS transistor with different thicknesses.

[0112] Furthermore, according to embodiments of this disclosure, the gate dielectric layer 415 can be formed simultaneously in the same gate oxide process as any one of the gate dielectric layer 416 of the low-voltage LV-CMOS transistor, the gate dielectric layer (not shown) of the interface IO-CMOS transistor, and the gate dielectric layer 417 of the high-voltage HV-CMOS transistor, such that the thickness of the gate dielectric layer 415 of the gate transistor can be the same as the thickness of any one of the gate dielectric layer 416 of the low-voltage LV-MOS transistor, the gate dielectric layer (not shown) of the interface IO-MOS transistor, and the gate dielectric layer 417 of the high-voltage HV-MOS transistor.

[0113] For example, in some implementations, it is necessary to form a low-voltage LV-MOS transistor and a high-voltage HV-MOS transistor (and / or an interface IO-MOS transistor) in the second region MSR, so a "double gate oxide process" can be performed to form the gate dielectric layer of the low-voltage LV-MOS transistor and the gate dielectric layer of the high-voltage HV-MOS transistor (and / or the interface IO-MOS transistor).

[0114] Specifically, such as Figure 4HAs shown, in one embodiment, a first gate dielectric layer can be grown on the surface of the substrate 401 in the second region MSR and on the surface of the channel region 414 of the gate transistor in the first region NVMR using a first gate oxide process. Subsequently, a patterned mask layer can be formed on the surface of the entire semiconductor device by patterning. This patterned mask layer can be a patterned photoresist layer formed using a standard photolithography process and includes openings corresponding to the channel regions of the low-voltage LV-MOS transistors in the second region MSR. The first gate dielectric layer on the surface of the channel regions of the low-voltage LV-MOS transistors in the second region MSR exposed through the openings can then be removed using a dry or wet etching process, and the patterned mask layer can be removed. A second gate dielectric layer can then be grown on the surface of the exposed channel regions of the low-voltage LV-MOS transistors using a second gate oxide process. In this way, the gate dielectric layer of the low-voltage LV-MOS transistor can have a different thickness than the gate dielectric layer of the flash memory cell's gating transistor and the high-voltage HV-MOS transistor (and / or interface IO-MOS transistor), and the gate dielectric layer of the flash memory cell's gating transistor can have the same thickness as the gate dielectric layer of the high-voltage HV-MOS transistor (and / or interface IO-MOS transistor).

[0115] In another embodiment, a first gate dielectric layer can be grown on the surface of the substrate 401 in the second region MSR and on the surface of the channel region 414 of the gate transistor in the first region NVMR using a first gate oxide process. Subsequently, a patterned mask layer can be formed on the surface of the entire semiconductor device by patterning, the patterned mask layer including openings corresponding to the channel regions 414 of the low-voltage LV-MOS transistors in the second region MSR and the gate transistors of the flash memory cells in the first region NVMR. The first gate dielectric layer exposed through the openings on the surface of the channel regions of the low-voltage LV-MOS transistors in the second region MSR and the surface of the channel regions 414 of the flash memory cells in the first region NVMR can then be removed using a dry or wet etching process, and the patterned mask layer can be removed. Subsequently, a second gate dielectric layer can be grown on the exposed surface of the channel regions of the low-voltage LV-MOS transistors and the surface of the channel regions 414 of the flash memory cells using a second gate oxide process. In this way, the gate dielectric layer of the low-voltage LV-MOS transistor can have a different thickness than the gate dielectric layer of the high-voltage HV-MOS transistor (and / or interface IO-MOS transistor), and the gate dielectric layer of the gate transistor of the flash memory cell can have the same thickness as the gate dielectric layer of the low-voltage LV-MOS transistor.

[0116] Similarly, in other embodiments, a triple gate oxide process can be used to form gate dielectric layers of different thicknesses for the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the high-voltage HV-MOS transistor, while the gate dielectric layer of the gate transistor of the flash memory cell can be formed to have the same thickness as the gate dielectric layer of any one of the low-voltage LV-MOS transistor, the interface IO-MOS transistor, and the high-voltage HV-MOS transistor.

[0117] Subsequently, referring to Figure 3 In step S309, as Figure 4I As shown, according to embodiments of the present disclosure, a second gate electrode layer 418 and a first etched hard mask layer 419 can be sequentially formed on the entire surface of the substrate 401, particularly over the gate dielectric layers 415, 416 and 417 and the stacked structure 411 (including the isolation layers 413 on both sides thereon).

[0118] According to embodiments of this disclosure, the second gate electrode layer 418 can be used to subsequently form, for example, as described above. Figure 1 The described flash memory cell MC 100 has a gate electrode 123 for the gate transistor MG 120. Furthermore, a second gate electrode layer 418 can be used to subsequently form the gate electrodes of various MOS transistors in the second region MSR. According to embodiments of this disclosure, the second gate electrode layer 418 can be formed by, for example, deposition or sputtering processes. According to embodiments of this disclosure, the second gate electrode layer 418 can include, for example, polysilicon, a metal gate, a metal silicide, or a combination of the above materials. According to embodiments of this disclosure, when the second gate electrode layer 418 comprises polysilicon, a low-pressure chemical vapor deposition process can be used to form the second gate electrode layer 418, with a thickness of 50 nm to 500 nm. It should be noted that, according to embodiments of this disclosure, the thickness of the second gate electrode layer 418 needs to be sufficiently large to fill the trench 412, so that the second gate electrode layer 418 has a flat upper surface in the first region NVMR, and the upper surface of the second gate electrode layer 418 in the first region NVMR is higher than the upper surface of the second gate electrode layer 418 in the second region MSR. Furthermore, according to embodiments of this disclosure, the upper surface of the second gate electrode layer 418 is higher than the upper surface of the first gate electrode layer 408.

[0119] According to embodiments of this disclosure, the first etched hard mask layer 419 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination of the above materials. According to embodiments of this disclosure, the first etched hard mask layer 419 may be formed by, for example, oxidation, high-temperature thermal oxidation, deposition, or sputtering processes. For example, the first etched hard mask layer 419 of silicon oxide may be formed on the second gate electrode layer 418 by a low-pressure chemical vapor deposition process, and its thickness may be 20 nm to 100 nm.

[0120] Subsequently, referring to Figure 3 In step S310, as Figure 4J As shown, according to embodiments of this disclosure, the first region NVMR can be exposed by patterning, and a portion of the first etched hard mask layer 419 and the second gate electrode layer 418 in the first region NVMR can be removed sequentially by dry or wet etching processes until the upper surface of the stacked structure 411, i.e., the upper surface of the sacrificial layer 410, is exposed. Subsequently, according to embodiments of this disclosure, the second gate electrode layer 418 in the trench 412 corresponding to the gate structure of the gate transistor of the flash memory cell can be etched to a suitable depth below the upper surface of the sacrificial layer 410 by an over-etching process to form a recess with a depth of 30 nm to 80 nm.

[0121] Alternatively, according to embodiments of the present disclosure, a portion of the first etched hard mask layer 419 and the second gate electrode layer 418 in the first region NVMR can be removed by a chemical mechanical polishing process until the upper surface of the stacked structure 411, i.e., the upper surface of the sacrificial layer 410, is exposed. Subsequently, according to embodiments of the present disclosure, the second gate electrode layer 418 in the trench 412 corresponding to the gate structure of the gate transistor of the flash memory cell can be etched to a suitable depth below the upper surface of the sacrificial layer 410 by an over-etching process to form a recess with a depth of 30 nm to 80 nm and greater than the thickness of the first etched hard mask layer 419.

[0122] Subsequently, as Figure 4J As shown, according to embodiments of the present disclosure, a second etched hard mask layer 420 with a suitable thickness can be formed by processes such as oxidation, high-temperature thermal oxidation, deposition, or sputtering. According to embodiments of the present disclosure, the second etched hard mask layer 420 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination of the above materials. For example, when the second etched hard mask layer 420 comprises silicon oxide, it can be formed by a low-pressure chemical vapor deposition process, with a thickness of 50 nm to 200 nm, sufficient to fill the recess of the trench 412 of the gate of the selected transistor, thereby giving the second etched hard mask layer 420 a flat upper surface in the first region NVMR.

[0123] According to embodiments of the present disclosure, the first etch hard mask layer 419 and the second etch hard mask layer 420 may have a different material than the sacrificial layer 410 in the stacked structure 411, i.e., have etch selectivity relative to the sacrificial layer 410. Preferably, according to embodiments of the present disclosure, the sacrificial layer 410 may comprise silicon nitride, while the first etch hard mask layer 419 and the second etch hard mask layer 420 may comprise silicon oxide.

[0124] Subsequently, as Figure 4JAs shown, according to embodiments of this disclosure, a portion of the second etched hard mask layer 420 can be removed by a dry or wet etching process until the upper surface of the stacked structure 411, i.e., the upper surface of the sacrificial layer 410, is exposed.

[0125] Subsequently, referring to Figure 3 In step S311, as Figure 4K As shown, according to embodiments of the present disclosure, all or a portion of the sacrificial layer 410 in the stacked structure 411 can be removed by a selective etching process. Subsequently, a second hard mask barrier layer 421 of suitable thickness can be conformally formed on the entire surface of the substrate 401 by, for example, oxidation, high-temperature thermal oxidation, deposition, or sputtering processes. According to embodiments of the present disclosure, the second hard mask barrier layer 421 may include, for example, silicon oxide, silicon nitride, silicon glass, or a combination of the above materials, and may have a different material than the first etched hard mask layer 419 and the second etched hard mask layer 420, i.e., have etching selectivity relative to the first etched hard mask layer 419 and the second etched hard mask layer 420. According to embodiments of the present disclosure, when the second hard mask barrier layer 421 comprises silicon nitride, the second hard mask barrier layer 421 can be formed by a low-pressure chemical vapor deposition process, having a thickness of 20 nm to 100 nm and should be less than half the width of the stacked structure 411.

[0126] Subsequently, referring to Figure 3 In step S312, as Figure 4L As shown, according to an embodiment of this disclosure, the second hard mask barrier layer 421 can be etched using an anisotropic etching process until the upper surface of the first hard mask barrier layer 409 of the stacked structure 411 in the first region NVMR is exposed, thereby forming hard mask barrier portions 422 of a specific length on both sides of the top of the gate structure of the select transistor. According to an embodiment of this disclosure, the length of the hard mask barrier portion 422 can typically be from 20 nm to 100 nm. Furthermore, according to an embodiment of this disclosure, in the second region MSR, the second hard mask barrier layer 421 can be etched using anisotropic etching until the upper surface of the first etched hard mask layer 419 in the second region MSR is exposed.

[0127] Subsequently, referring to Figure 3 In step S313, as Figure 4M As shown, according to embodiments of this disclosure, the portion of the first etched hard mask layer 419 in the portion outside the gate region of the MOS transistor in the second region MSR and the portion of the first hard mask barrier layer 409 in the stacked structure 411 in the first region NVMR that is not covered by the hard mask barrier portion 422 can be removed by, for example, patterning and selective etching processes. Figure 4MAs shown, the remaining first hard mask blocking layer 409 and the hard mask blocking portion 422 above it can together correspond to, for example, the above reference. Figure 1 The hard mask blocking portion 117 of the first storage transistor MS110 and the hard mask blocking portion 137 of the second storage transistor MD130 of the described flash memory cell MC 100.

[0128] Subsequently, as Figure 4M As shown, according to embodiments of the present disclosure, the second gate electrode layer 418 and its underlying gate dielectric layers 416 and 417 in the portion outside the gate region of the MOS transistor in the exposed second region MSR, as well as the first gate electrode layer 408 of the storage transistor in the first region NVMR not covered by the hard mask blocking portion 422 and its underlying storage gate dielectric stack 407, can be removed concurrently or sequentially using anisotropic etching processes. In this way, the gate structure of the MOS transistor in the second region MSR and the gate structure of the storage transistor in the first region NVMR can be formed concurrently or sequentially. Therefore, as described above, according to embodiments of the present disclosure, such as Figure 4M As shown, the length of the gate electrode of the storage transistor can be defined by the length of the hard mask blocking portion 422 through a self-aligned process. According to embodiments of this disclosure, the length of the gate electrode of the storage transistor can also typically be from 20 nm to 100 nm. Furthermore, as... Figure 4M As shown, the remaining second gate electrode layer 418 in the first region NVMR can correspond to, for example, the above reference. Figure 1 The gate electrode 123 of the gating transistor MG 120 of the described flash memory cell MC 100, while the remaining second gate electrode layer 418 in the second region MOR can form the gate electrode of the MOS transistor.

[0129] Subsequently, referring to Figure 3 In step S314, as Figure 4N As shown, according to an embodiment of the present disclosure, the lightly doped source / drain regions 423 of the first region NVMR flash memory cell and the second region MOSR transistor can be formed by one or more lightly doped source / drain (LDD) patterns.

[0130] According to embodiments of this disclosure, the lightly doped source / drain regions 423 can be formed, for example, by an ion implantation process. Furthermore, according to embodiments of this disclosure, the ion implantation process used to form the lightly doped source / drain regions 423 of the flash memory cells in the first region NVMR and the ion implantation process used to form the lightly doped source / drain regions 423 of the MOS transistors in the second region MSR can use the same or different ion types, doses, and energies. Furthermore, according to embodiments of this disclosure, the ion implantation process used to form the lightly doped source / drain regions 423 of the flash memory cells in the first region NVMR can be the same as the ion implantation process used to form the lightly doped source / drain regions 423 of at least one transistor (e.g., a low-voltage LV-MOS transistor, an interface IO-MOS transistor, or a high-voltage HV-MOS transistor) in the second region MSR, for example, using the same ion types, doses, and energies.

[0131] For example, for an N-type flash memory cell (or NVM transistor) according to this embodiment, the ion implantation process for forming its lightly doped source / drain regions 423 can use N-type impurity ions, such as phosphorus ions or arsenic ions, to form N-type lightly doped source / drain regions 423 on the surface of the source / drain regions of the flash memory cell.

[0132] Alternatively, according to embodiments of the present disclosure, prior to performing the ion implantation process for forming the lightly doped source / drain regions of the flash memory cell, additional P-type impurity ions, such as boron ions or boron difluoride ions, may be implanted to form a P-type encapsulation region (P-Halo) (not shown) outside the lightly doped source / drain region 423 of the flash memory cell, thereby improving the punch-through characteristics and storage characteristics of the flash memory cell.

[0133] Subsequently, referring to Figure 3 In step S315, as Figure 4O As shown, according to embodiments of this disclosure, sidewalls 424 can be formed concurrently on both sides of the gate structure of the flash memory cell in the first region NVMR and the MOS transistor in the second region MSR using a sidewall process commonly used in integrated circuit manufacturing. For example, the sidewall process can first deposit one or more isolation dielectric layers on the surface of the substrate structure, and then use an anisotropic etching process to remove the isolation dielectric layers above the substrate structure, thereby forming the sidewalls 424.

[0134] Subsequently, as Figure 4O As shown, according to an embodiment of the present disclosure, the heavily doped source-drain region 425 of the first region NVMR flash memory cell and the second region MSR transistor can be formed by a heavily doped source-drain implantation process.

[0135] like Figure 4O As shown, the lightly doped source / drain regions 423 and heavily doped source / drain regions 425 of the flash memory cells in the first region NVM can together correspond to, for example, the above reference. Figure 1 The described flash memory cell MC 100 has a source region 140 and a drain region 150.

[0136] Subsequently, referring to Figure 3 In step S316, as Figure 4P As shown, according to embodiments of this disclosure, the second etched hard mask layer 420 above the gate structure of the gate transistor of the flash memory cell in the first region NVMR and the first etched hard mask layer 419 above the gate structure of the transistor in the second region MSR can be simultaneously removed by an etching cleaning process. Subsequently, as... Figure 4P As shown, a metal layer, such as nickel, titanium, tungsten, molybdenum, cobalt, manganese, tantalum, platinum or palladium, can be formed on the surface of the substrate structure by deposition or sputtering processes. Furthermore, a metal silicide layer 426 is formed on the surface of the source and drain regions of the flash memory cells and the gate electrode of the gate transistor in the first region NVMR, and the source and drain regions and the gate electrode (second gate electrode layer 418) of the MOS transistor in the second region MOR, thereby reducing the contact resistance of the source and drain regions and the on-resistance of the gate electrode.

[0137] Alternatively, according to embodiments of this disclosure, although not shown, all or part of the first hard mask barrier layer 409 and hard mask barrier portion 422 above the gate electrode (first gate electrode layer 408) of the storage transistor of the flash memory cell in the first region NVMR can be further removed by an etching cleaning process to expose all or part of the surface of the gate electrode (i.e., the first gate electrode layer 408) of the storage transistor, and a metal silicide layer is concurrently formed on the exposed gate electrode surface of the storage transistor of the flash memory cell.

[0138] Thus, according to the embodiments of this disclosure, the front-end manufacturing process for the integration of flash memory cells in the first region NVMR and MOS transistors in the second region MSR has been completed.

[0139] Finally, according to embodiments of this disclosure, one or more metal interconnect layers and corresponding contact holes and vias can be formed by back-end manufacturing processes commonly used in integrated circuit manufacturing, thereby forming electrical connections between flash memory cells in the first region NVMR and transistors in the second region MORS.

[0140] Therefore, embodiments of a method for manufacturing a semiconductor device including integrally formed non-volatile memory (NVM) transistors and metal-oxide-semiconductor (MOS) transistors according to the present disclosure have been described. For illustrative purposes, a limited number of possible embodiments of the present disclosure have been given above. Although the present disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various modifications and changes can be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

[0141] Although this document contains numerous details, these details should not be construed as limiting the scope of this disclosure or any potentially claimed protection, but rather as descriptions of features that may be specific to a particular implementation. Some features described herein in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, and even initially stated so, in some cases one or more features may be removed from the claimed combination, and the claimed combination may involve sub-combinations or variations thereof.

Claims

1. A method for manufacturing a semiconductor device, in, The semiconductor device includes a first region in which a plurality of flash memory cells are formed and a second region in which metal-oxide-semiconductor (MOS) transistors are formed, wherein each flash memory cell includes two storage transistors and a gate transistor disposed between the two storage transistors. The method includes: Provide a semiconductor substrate and form an isolation structure therein; The storage gate dielectric stack and the first gate electrode layer are formed for the storage transistor; Remove the portion in the first region corresponding to the gate structure of the gate transistor, as well as the storage gate dielectric stack and the first gate electrode layer in the second region; The gate dielectric layer and the second gate electrode layer of the gating transistor and the MOS transistor are formed concurrently; The gate structure of the selected transistor is formed and hard mask blocking portions are formed on both sides thereof; and The gate structure is formed for the storage transistor in the first region and the MOS transistor in the second region.

2. The method according to claim 1, wherein, The gate structure of the storage transistor, from bottom to top in the vertical direction, includes a channel region, the storage gate dielectric stack, the first gate electrode layer, and the hard mask blocking portion. The gate structure of the selected transistor includes a channel region, a gate dielectric layer, and a second gate electrode layer arranged sequentially along the vertical direction.

3. The method according to claim 1, wherein, The upper surface of the second gate electrode layer is higher than the upper surface of the first gate electrode layer.

4. The method according to claim 1, wherein, The MOS transistors disposed in the second region include one or more of low-voltage MOS transistors, interface MOS transistors, or high-voltage MOS transistors.

5. The method according to claim 4, wherein, The thickness of the gate dielectric layer of the selector transistor is the same as the thickness of the gate dielectric layer of any one of the low-voltage MOS transistor, the interface MOS transistor, and the high-voltage MOS transistor.

6. The method according to claim 1, wherein, The flash memory cells in the first region are isolated by a first isolation structure, the MOS transistors in the second region are isolated by a second isolation structure, and the first region and the second region are isolated by the first isolation structure and / or the second isolation structure. The first isolation structure may be the same as or different from the second isolation structure.

7. The method according to claim 1, further comprising: Perform a first injection process to form the well region of the flash memory cell and the channel region of the storage transistor, and to adjust the threshold voltage of the storage transistor; A second injection process is performed to form the well region and channel region of the MOS transistor, and to adjust the threshold voltage of the MOS transistor; as well as A third injection process is performed to form the channel region of the gate transistor and to adjust the threshold voltage of the gate transistor. The first implantation process and the third implantation process may have the same or different ion types, doses and / or energies.

8. The method according to claim 7, wherein, The second implantation process is performed before forming the storage gate dielectric stack and the first gate electrode layer of the storage transistor, or after removing the portion in the first region corresponding to the gate structure of the gate transistor and the storage gate dielectric stack and the first gate electrode layer in the second region.

9. The method according to claim 7, wherein, The first implantation process and the third implantation process are performed such that the doping concentration of the channel region of the storage transistor is lower than the doping concentration of the channel region of the gate transistor.

10. The method according to claim 1, wherein, The storage gate dielectric stack comprises, from bottom to top, a first oxide layer, a storage dielectric layer, and a second oxide layer in the vertical direction. The storage medium layer, from bottom to top in the vertical direction, includes first to third storage medium sublayers formed of silicon nitride, and The second storage medium sublayer has a higher silicon content than the first and third storage medium sublayers.

11. The method according to claim 10, wherein, The storage medium layer also includes a fourth storage medium sublayer above the third storage medium sublayer, and The fourth storage medium sublayer has a higher silicon content than the third storage medium sublayer.

12. The method according to claim 1, further comprising: A high work function metal interface layer is formed between the storage gate dielectric stack and the first gate electrode layer.

13. The method according to claim 1, further comprising: An isolation layer is formed to isolate the gate transistor and the storage transistor.

14. The method according to claim 1, further comprising: Metal silicides are formed on the surface of the gate electrodes of the gating transistor and the MOS transistor.

15. The method of claim 14, further comprising: Metal silicide is formed on all or part of the surface of the gate electrode of the storage transistor.

16. The method according to claim 1, wherein, The gate structures of the storage transistor in the first region and the MOS transistor in the second region are formed concurrently or sequentially.

Images