Bidirectional anti-static film layer structure of quick detection block, array substrate and display device

Abstract

The invention discloses a bidirectional anti-static film layer structure of a fast detection block, an array substrate and a display device. The bidirectional anti-static film layer structure comprises a first static end, a second static end and a static release module, the gate layer and the drain layer of the first thin film transistor in the plurality of thin film transistors are stacked together and electrically connected to form a first laminated structure, and the gate layer and the drain layer of the last thin film transistor in the plurality of thin film transistors are stacked together and electrically connected to form a second laminated structure; the first electrostatic end and the second electrostatic end are led out from the first laminated structure and the second laminated structure respectively. The first laminated structure and the second laminated structure are utilized, and the first electrostatic end and the second electrostatic end are respectively led out from the first laminated structure and the second laminated structure, so that metal layer exchange through a common electrode layer (ITO layer) is avoided, and the problems that the overlapping design of an ESD circuit film layer is unreasonable and the cost is low are solved. Products are easy to fail or false detection is caused by wrong lap joint of the probes during electrical performance detection.

Description

Technical Field

[0001] This invention relates to the field of display panel performance testing technology, and in particular to a bidirectional antistatic film structure for a fast testing block, an array substrate, and a display device. Background Technology

[0002] With the rapid development of display technology, the bezels of displays are evolving towards extremely narrow bezels. However, this narrow bezel design compresses the physical space within the product bezel. The existing circuitry within the bezel has not been simplified, especially the ESD circuitry, which is essential and primarily functions to prevent the fast test block from being damaged by electrostatic discharge during electrical performance testing of the product.

[0003] Therefore, to reduce the risk of electrostatic discharge (ESD) damage to the fast test blocks, display products incorporate an ESD circuit between the two fast test blocks to connect them. The fast test blocks are also connected to a common electrode via this ESD circuit, allowing the signal lines of subsequent fast test blocks to dissipate and release static electricity generated during production and testing to the common electrode. However, due to the imperfect design of existing ESD circuit layers, different metal layers in the ESD circuit are connected using ITO layers for layer swapping. Excessive circuit current or moisture exposure to the ITO layer can cause corrosion, leading to product failure. Therefore, it is best to reduce the number of ITO swapping blocks. Furthermore, because current display products have narrow bezels, small fast test blocks, and small spacing, the operable range of the probes is reduced, and the positioning error tolerance drops sharply. During rapid electrical performance testing of the display at the end of the production line, the ITO layer can easily cause the probes to be incorrectly connected to the wrong fast test blocks, increasing production costs. Summary of the Invention

[0004] Existing ESD circuit film layer overlap designs can easily lead to product failure or false detections due to probe misalignment during electrical performance testing.

[0005] To address the aforementioned issues, a bidirectional anti-static film structure, array substrate, and display device for a fast detection block are proposed. This involves stacking and electrically connecting the gate and drain layers of the first of multiple thin-film transistors to form a first stacked structure, and stacking and electrically connecting the gate and drain layers of the last of the multiple thin-film transistors to form a second stacked structure. A first electrostatic terminal and a second electrostatic terminal are led out from the first and second stacked structures, respectively. This avoids metal layer replacement through the common electrode layer (ITO layer), solving the problem of unreasonable ESD circuit film layer overlap design, which can easily lead to product failure or false detection due to probe misalignment during electrical performance testing.

[0006] In a first aspect, a bidirectional antistatic film structure for a fast detection block includes: First electrostatic terminal; Second electrostatic terminal; Electrostatic discharge module; The first electrostatic terminal and the second electrostatic terminal are electrically connected to the two ends of the electrostatic discharge module, respectively. The electrostatic discharge module is fabricated in the GIP region of the array substrate of the display device, and includes: SD metal layer, used to form SD metal trace patterns for multiple thin-film transistors; A gate metal layer is used to form the gate metal wiring pattern of the plurality of thin-film transistors; An active material layer is located between the SD metal layer and the gate metal layer to form the plurality of thin-film transistors; In this configuration, the gate layer and drain layer of the first of the plurality of thin-film transistors are stacked together and electrically connected to form a first stacked structure, and the gate layer and drain layer of the last of the plurality of thin-film transistors are stacked together and electrically connected to form a second stacked structure. The first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure and the second stacked structure.

[0007] In conjunction with the bidirectional antistatic film structure of the fast detection block described in the first aspect of the present invention, in a first possible embodiment, the electrostatic discharge module includes: The first transistor, the second transistor, and the third transistor; The drain layer of the first transistor is electrically connected to the source layer of the second transistor to form a series structure in the first direction; The source layer of the third transistor is electrically connected to the drain layer of the second transistor, forming a second-direction series structure.

[0008] In conjunction with the first possible embodiment of the first aspect of the present invention, in the second possible embodiment, the first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor and the second stacked structure of the third transistor.

[0009] In conjunction with the second possible implementation of the first aspect of the present invention, in the third possible implementation, the drain layer and gate layer of the first transistor are stacked and connected together by discharge to form the first stacked structure; the drain layer and gate layer of the third transistor are stacked and connected together by discharge to form the second stacked structure.

[0010] In conjunction with the third possible embodiment of the first aspect of the present invention, in the fourth possible embodiment, the electrostatic discharge module further includes: First layer-changing block, second layer-changing block, and third layer-changing block; The source layer of the first transistor is electrically connected to the common electrode through the first layer-swapping block; The gate layer of the second transistor is electrically connected to the common electrode through the second layer-swapping block; The source layer of the third transistor is electrically connected to the common electrode through the third layer-swapping block.

[0011] In conjunction with the bidirectional antistatic film structure of the fast detection block described in the first aspect of the present invention, in a fifth possible embodiment, the electrostatic discharge module includes: First transistor, second transistor, third transistor, fourth transistor, and fifth transistor; The drain layer of the first transistor is connected to the source layer of the second transistor, and the drain layer of the second transistor is connected to the source layer of the third transistor, forming a first-direction series structure. The source layer of the fifth transistor overlaps with the drain layer of the fourth transistor, and the source layer of the fourth transistor overlaps with the drain layer of the third transistor, forming a second-direction series structure.

[0012] In conjunction with the fifth possible implementation of the first aspect of the present invention, in the sixth possible implementation, the first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor and the second stacked structure of the fifth transistor.

[0013] In conjunction with the sixth and seventh possible embodiments of the first aspect of the present invention, the drain layer and gate layer of the first transistor are stacked and connected together by discharge to form the first stacked structure; the drain layer and gate layer of the fifth transistor are stacked and connected together by discharge to form the second stacked structure.

[0014] In a second aspect, an array substrate includes a bidirectional antistatic film structure of the fast detection block described in the first aspect.

[0015] Thirdly, a display device comprising the array substrate described in the second aspect.

[0016] The bidirectional antistatic film structure, array substrate, and display device of the fast detection block described in this invention are formed by stacking and electrically connecting the gate layer and drain layer of the first of a plurality of thin-film transistors together to form a first stacked structure, and stacking and electrically connecting the gate layer and drain layer of the last of the plurality of thin-film transistors together to form a second stacked structure. The first electrostatic terminal and the second electrostatic terminal are led out from the first stacked structure and the second stacked structure, respectively, thereby avoiding metal layer replacement through the common electrode layer (ITO layer). This solves the problem that unreasonable ESD circuit film layer overlap design can easily lead to product failure or false detection due to probe overlap error during electrical performance testing. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is an overall schematic diagram of the display device in this application; Figure 2 This is a schematic diagram of the overall structure of the antistatic film layer in this application; Figure 3 This is a schematic diagram of the first-direction series structure of a specific embodiment of the antistatic film layer structure in this application; Figure 4 This is a schematic diagram of the second-direction series structure of a specific embodiment of the antistatic film layer structure in this application; Figure 5 This is a schematic diagram of the first-direction series structure of another specific embodiment of the antistatic film layer structure in this application; Figure 6 This is a schematic diagram of the second-direction series structure of another specific embodiment of the antistatic film layer structure in this application. Detailed Implementation

[0019] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0023] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0024] In existing technologies, unreasonable ESD circuit film layer overlap design can easily lead to product failure or false detection due to probe overlap errors during electrical performance testing.

[0025] To address the aforementioned issues, a bidirectional antistatic film structure for a fast detection block, an array substrate, and a display device are proposed.

[0026] Firstly, a bidirectional antistatic film structure for a fast detection block, such as... Figure 1 and Figure 2 , Figure 1 This is an overall schematic diagram of the display device in this application. Figure 2This is a schematic diagram of the overall structure of the antistatic film layer in this application; it includes a first electrostatic terminal, a second electrostatic terminal, and an electrostatic discharge module; the first electrostatic terminal and the second electrostatic terminal are electrically connected to the two ends of the electrostatic discharge module respectively; the electrostatic discharge module is fabricated in the GIP region of the array substrate of the display device, and includes: an SD metal layer for forming SD metal trace patterns of multiple thin-film transistors; a gate metal layer for forming gate metal trace patterns of multiple thin-film transistors; an active material layer located between the SD metal layer and the gate metal layer to form multiple thin-film transistors; wherein, the gate layer and drain layer of the first of the multiple thin-film transistors are stacked together and electrically connected to form a first stacked structure, and the gate layer and drain layer of the last of the multiple thin-film transistors are stacked together and electrically connected to form a second stacked structure; the first electrostatic terminal and the second electrostatic terminal are led out from the first stacked structure and the second stacked structure respectively. By stacking and electrically connecting the gate and drain layers of the first of multiple thin-film transistors together to form a first stacked structure, and stacking and electrically connecting the gate and drain layers of the last of the multiple thin-film transistors together to form a second stacked structure, and leading out the first electrostatic terminal and the second electrostatic terminal from the first stacked structure and the second stacked structure respectively, the metal layer replacement through the common electrode layer (ITO layer) is avoided. This solves the problem that unreasonable film layer overlap design in ESD circuits can easily lead to product failure or false detection due to probe overlap errors during electrical performance testing.

[0027] In this embodiment, the array substrate includes a glass substrate 100, a buffer layer 200, an isolation layer 300, an insulating layer 400, a planarization layer 500, a passivation layer 600, a pixel electrode layer 700, and a common electrode layer 800. Each transistor also includes a gate layer, an SD metal layer, and an active layer.

[0028] First Embodiment In this embodiment, such as Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of a first-direction series structure of a specific embodiment of the antistatic film layer structure in this application. Figure 4 This is a schematic diagram of a second-direction series structure of a specific embodiment of the antistatic film layer structure in this application; the electrostatic discharge module includes a first transistor 110, a second transistor 120 and a third transistor 130; the drain layer of the first transistor 110 is electrically connected to the source layer of the second transistor 120 to form a first-direction series structure; the source layer of the third transistor 130 is electrically connected to the drain layer of the second transistor 120 to form a second-direction series structure.

[0029] In this embodiment, the first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor 110 and the second stacked structure of the third transistor 130.

[0030] In this embodiment, the drain layer and gate layer of the first transistor 110 are stacked and connected together to form a first stacked structure; the drain layer and gate layer of the third transistor 130 are stacked and connected together to form a second stacked structure.

[0031] In this embodiment, the electrostatic discharge module further includes a first layer-switching block 101, a second layer-switching block 102, and a third layer-switching block 103; the source layer 113 of the first transistor 110 is electrically connected to the common electrode layer through the first layer-switching block 101; the gate layer 121 of the second transistor 120 is electrically connected to the common electrode layer 800 through the second layer-switching block 102; and the source layer 133 of the third transistor 130 is electrically connected to the common electrode layer 800 through the third layer-switching block 103.

[0032] In this embodiment, the first transistor 110 includes a first gate layer 111, a first active layer 112, a first source layer 113, and a first drain layer 114; the second transistor 120 includes a second gate layer 121, a second active layer 122, a second source layer 123, and a second drain layer 124; and the third transistor 130 includes a third gate layer 131, a third active layer 132, a third source layer 133, and a third drain layer 134.

[0033] In this embodiment, the electrostatic discharge module includes three transistors. The first transistor 110 is the first transistor, and its gate layer 111 and drain layer 114 form a first stacked structure. Similarly, the third transistor 130 is the last transistor, and its gate layer 131 and drain layer 134 form a second stacked structure. This stacked structure avoids the metal layer transition between the gate layer and the drain layer. Because there is also a common electrode layer in all fast detection blocks, they are on the same layer, which can easily cause misconnection and thus false detection. In this embodiment, the metal layer replacement through the common electrode layer (ITO layer) is avoided, which solves the problem that unreasonable ESD circuit film layer overlap design can easily lead to product failure or false detection due to probe overlap error during electrical performance testing.

[0034] Second Embodiment In this embodiment, as Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the first-direction series structure of another specific embodiment of the antistatic film layer structure in this application; Figure 6This is a schematic diagram of a second-direction series structure of another specific embodiment of the antistatic film layer structure in this application. The electrostatic discharge module includes a first transistor 110, a second transistor 120, a third transistor 130, a fourth transistor 140, and a fifth transistor 150; the drain layer of the first transistor 110 overlaps with the source layer of the second transistor 120, and the drain layer of the second transistor 120 overlaps with the source layer of the third transistor 130, forming a first-direction series structure; the source layer of the fifth transistor 150 overlaps with the drain layer of the fourth transistor 140, and the source layer of the fourth transistor 140 overlaps with the drain layer of the third transistor 130, forming a second-direction series structure.

[0035] In this embodiment, the first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor 110 and the second stacked structure of the fifth transistor 150.

[0036] In this embodiment, the drain layer and gate layer of the first transistor 110 are stacked and connected together to form a first stacked structure; the drain layer and gate layer of the fifth transistor 150 are stacked and connected together to form a second stacked structure.

[0037] In this embodiment, the first transistor 110 includes a first gate layer 111, a first active layer 112, a first source layer 113, and a first drain layer 114; the second transistor 120 includes a second gate layer 121, a second active layer 122, a second source layer 123, and a second drain layer 124; the third transistor 130 includes a third gate layer 131, a third active layer 132, a third source layer 133, and a third drain layer 134; the fourth transistor 140 includes a fourth gate layer 141, a fourth active layer 142, a fourth source layer 143, and a fourth drain layer 144; and the fifth transistor 150 includes a fifth gate layer 151, a fifth active layer 152, a fifth source layer 153, and a fifth drain layer 154.

[0038] In this embodiment, the electrostatic discharge module includes five transistors. The first transistor 110 is the first transistor, and its gate layer 111 and drain layer 114 form a first stacked structure. Similarly, the fifth transistor 150 is the last transistor, and its gate layer 151 and drain layer 154 form a second stacked structure. This stacked structure avoids the metal layer transition between the gate layer and the drain layer. Because there is also a common electrode layer in all fast detection blocks, they are on the same layer, which can easily cause misconnection and thus false detection. In this embodiment, the metal layer replacement through the common electrode layer (ITO layer) is avoided, which solves the problem that unreasonable ESD circuit film layer overlap design can easily lead to product failure or false detection due to probe overlap error during electrical performance testing.

[0039] In this embodiment, a first stacked structure is formed by stacking and electrically connecting the gate layer and drain layer of the first of the multiple thin-film transistors, and a second stacked structure is formed by stacking and electrically connecting the gate layer and drain layer of the last of the multiple thin-film transistors. The first electrostatic terminal and the second electrostatic terminal are led out from the first stacked structure and the second stacked structure, respectively. This avoids the need to replace the metal layer through the common electrode layer (ITO layer), and solves the problem that unreasonable film layer overlap design of ESD circuits can easily lead to product failure or false detection due to probe overlap error during electrical performance testing.

[0040] In this embodiment, nine layer-swapping blocks are included, which respectively connect the gate layer and source layer metal to the common electrode layer 800, thereby allowing the charge on it to be better dispersed.

[0041] In a second aspect, an array substrate includes a bidirectional antistatic film structure for the fast detection block of the first aspect.

[0042] Thirdly, a display device includes an array substrate as described in the second aspect.

[0043] The bidirectional antistatic film structure, array substrate, and display device of the fast detection block of the present invention form a first stacked structure by stacking and electrically connecting the gate layer and drain layer of the first of a plurality of thin film transistors together, and stacking and electrically connecting the gate layer and drain layer of the last of the plurality of thin film transistors together to form a second stacked structure. The first electrostatic terminal and the second electrostatic terminal are led out from the first stacked structure and the second stacked structure, respectively, thereby avoiding metal layer replacement through the common electrode layer (ITO layer). This solves the problem that unreasonable ESD circuit film layer overlap design can easily lead to product failure or false detection due to probe overlap error during electrical performance testing.

[0044] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A bidirectional antistatic film structure for a fast detection block, characterized in that, include: First electrostatic terminal; Second electrostatic terminal; Electrostatic discharge module; The first electrostatic terminal and the second electrostatic terminal are electrically connected to the two ends of the electrostatic discharge module, respectively. The electrostatic discharge module is fabricated in the GIP region of the array substrate of the display device, and includes: SD metal layer, used to form SD metal trace patterns for multiple thin-film transistors; A gate metal layer is used to form the gate metal wiring pattern of the plurality of thin-film transistors; An active material layer is located between the SD metal layer and the gate metal layer to form the plurality of thin-film transistors; In this configuration, the gate layer and drain layer of the first of the plurality of thin-film transistors are stacked together and electrically connected to form a first stacked structure, and the gate layer and drain layer of the last of the plurality of thin-film transistors are stacked together and electrically connected to form a second stacked structure. The first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure and the second stacked structure.

2. The bidirectional antistatic film structure of the fast detection block according to claim 1, characterized in that, The electrostatic discharge module includes: The first transistor, the second transistor, and the third transistor; The drain layer of the first transistor is electrically connected to the source layer of the second transistor to form a series structure in the first direction; The source layer of the third transistor is electrically connected to the drain layer of the second transistor, forming a second-direction series structure.

3. The bidirectional antistatic film structure of the fast detection block according to claim 2, characterized in that, The first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor and the second stacked structure of the third transistor.

4. The bidirectional antistatic film structure of the fast detection block according to claim 3, characterized in that, The drain layer and gate layer of the first transistor are stacked and connected together to form the first stacked structure; the drain layer and gate layer of the third transistor are stacked and connected together to form the second stacked structure.

5. The bidirectional antistatic film structure of the fast detection block according to claim 4, characterized in that, The electrostatic discharge module also includes: First layer-changing block, second layer-changing block, and third layer-changing block; The source layer of the first transistor is electrically connected to the common electrode through the first layer-swapping block; The gate layer of the second transistor is electrically connected to the common electrode through the second layer-swapping block; The source layer of the third transistor is electrically connected to the common electrode through the third layer-swapping block.

6. The bidirectional antistatic film structure of the fast detection block according to claim 1, characterized in that, The electrostatic discharge module includes: First transistor, second transistor, third transistor, fourth transistor, and fifth transistor; The drain layer of the first transistor is connected to the source layer of the second transistor, and the drain layer of the second transistor is connected to the source layer of the third transistor, forming a first-direction series structure. The source layer of the fifth transistor overlaps with the drain layer of the fourth transistor, and the source layer of the fourth transistor overlaps with the drain layer of the third transistor, forming a second-direction series structure.

7. The bidirectional antistatic film structure of the fast detection block according to claim 6, characterized in that, The first electrostatic terminal and the second electrostatic terminal are respectively led out from the first stacked structure of the first transistor and the second stacked structure of the fifth transistor.

8. The bidirectional antistatic film structure of the fast detection block according to claim 7, characterized in that, The drain layer and gate layer of the first transistor are stacked and connected together to form the first stacked structure; the drain layer and gate layer of the fifth transistor are stacked and connected together to form the second stacked structure.

9. An array substrate, characterized in that, The bidirectional antistatic film structure of the fast detection block as described in any one of claims 1-8.

10. A display device, characterized in that, Includes the array substrate as described in claim 9.

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