Semiconductor structure and manufacturing method thereof
By employing a structure consisting of a bulk silicon substrate, an oxide layer, a polysilicon layer, and an epitaxial layer in the photoelectric conversion element, the high cost and complex isolation issues of SOI wafers are solved, enabling low-cost and high-efficiency manufacturing of photoelectric conversion elements and improving the reliability and performance of the elements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2026-04-07
AI Technical Summary
Existing technologies for manufacturing optoelectronic conversion components use high-cost SOI wafers, resulting in high manufacturing costs. Furthermore, the isolation process between different components is complex, making it difficult to achieve low-cost and efficient electrical isolation and component miniaturization.
The structure employs a bulk silicon substrate, an oxide layer, a patterned polysilicon layer, and a patterned epitaxial layer. The polysilicon layer is formed by chemical vapor deposition to alleviate lattice mismatch, and spatially isolated optoelectronic components and control circuits are fabricated on the same silicon wafer through a patterning process, reducing packaging costs and component interference.
This achieves the goals of reducing costs, shrinking component size, improving component reliability and efficiency, reducing interference between different components, and lowering production costs.
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Figure CN121815862A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure for growing a photoelectric conversion element on a bulk silicon substrate. BACKGROUND
[0002] Photoelectric conversion elements are devices that use light signals to control current or voltage, and are widely used. Common photoelectric conversion elements include, for example, photo voltage generation (PVG) elements, photo relays, photo couplers, photo MOS transistors, and photo triacs. These elements have in common that they use light signals to isolate, control, or convert electrical signals, and are used in the fields of electrical isolation, control switches, and circuit protection.
[0003] In the manufacture of the above-mentioned conventional photoelectric conversion elements, in order to improve the performance of the elements, a bulk silicon substrate is not generally used, but a silicon on insulator (SOI) wafer is used. The SOI wafer has a thin silicon layer and an insulating layer on the surface, which provides better electrical isolation characteristics for the production of photoelectric components, transistors, and control circuits. However, the high cost of SOI wafers makes it difficult to obtain sufficient profits from the cost structure of manufacturing such elements. Therefore, how to develop an innovative semiconductor structure to produce the above-mentioned photoelectric components at a lower cost is a problem that needs to be solved. SUMMARY
[0004] The main purpose of the present invention is to provide an innovative semiconductor structure and its manufacturing method to reduce the cost of manufacturing photoelectric conversion elements, and to reduce the size of the elements, improve the reliability and performance of the elements.
[0005] To achieve the above-mentioned purpose, the present invention provides a semiconductor structure, which includes a bulk silicon substrate, an oxide layer, a patterned polysilicon layer, and a patterned epitaxial layer. The oxide layer is disposed above the bulk silicon substrate, the patterned polysilicon layer is disposed above the oxide layer, and the patterned epitaxial layer is disposed above the patterned polysilicon layer. The patterned epitaxial layer has a photoelectric component and a control circuit, and the photoelectric component and the control circuit are spatially isolated from each other due to the patterned polysilicon layer.
[0006] In an embodiment of the semiconductor structure of the present invention, the oxide layer is a silicon dioxide layer.
[0007] In an embodiment of the semiconductor structure of the present invention, the photoelectric component includes a light emitting diode or a photodiode.
[0008] In one embodiment of the semiconductor structure of the present application, the control circuit comprises a transistor.
[0009] To achieve the above object, the present application provides a semiconductor structure, comprising a bulk silicon substrate, a patterned oxide layer, a patterned polysilicon layer, a patterned epitaxial layer, and a control circuit. The patterned oxide layer is disposed above the bulk silicon substrate, the patterned polysilicon layer is disposed above the patterned oxide layer, the patterned epitaxial layer is disposed above the patterned polysilicon layer, and the patterned epitaxial layer has a photoelectric component. The control circuit is disposed above the exposed portion of the bulk silicon substrate. The photoelectric component and the control circuit are spatially separated from each other by the patterned oxide layer.
[0010] To achieve the above object, the present application provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a bulk silicon substrate; providing an oxide layer disposed above the bulk silicon substrate; providing a patterned polysilicon layer disposed above the oxide layer; and providing a patterned epitaxial layer disposed above the patterned polysilicon layer. The patterned epitaxial layer has a photoelectric component and a control circuit, and the photoelectric component and the control circuit are spatially separated from each other by the patterned polysilicon layer.
[0011] To achieve the above object, the present application provides a method for manufacturing a semiconductor structure, comprising the following steps: providing a bulk silicon substrate; providing a patterned oxide layer disposed above the bulk silicon substrate to expose a portion of the bulk silicon substrate; providing a patterned polysilicon layer disposed above the patterned oxide layer; providing a patterned epitaxial layer disposed above the patterned polysilicon layer, the patterned epitaxial layer having a photoelectric component; and providing a control circuit disposed above the exposed portion of the bulk silicon substrate. The photoelectric component and the control circuit are spatially separated from each other by the patterned oxide layer.
[0012] Other objects, features, and advantages of the present application will become apparent to those skilled in the art from the following description, taken in conjunction with the accompanying drawings and the appended claims. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 A schematic diagram of a conventional photovoltaic device fabricated using an SOI wafer;
[0014] Figures 2 to 3 A schematic diagram of a semiconductor structure fabricated in one embodiment of the present application;
[0015] Figure 4 A schematic diagram of a circuit using a bidirectional optical thyristor fabricated using the semiconductor structure of the present application;
[0016] Figures 5 to 6 A schematic diagram of a semiconductor structure fabricated in another embodiment of the present application;
[0017] Figure 7 Schematic diagram of an application of the photovoltaic voltage generating element of the semiconductor structure of the present application to a circuit;
[0018] Figure 8 Schematic diagram of a process step for the semiconductor structure of an embodiment of the present application; and
[0019] Figure 9 Schematic diagram of a process step for the semiconductor structure of another embodiment of the present application.
[0020] BRIEF DESCRIPTION OF DRAWINGS
[0021] 10 SOI wafer
[0022] 12 silicon substrate
[0023] 14 insulating layer
[0024] 16 silicon thin film layer
[0025] 18 isolation
[0026] 100 bulk silicon substrate
[0027] 110 oxide layer
[0028] 120 polysilicon layer
[0029] 130 epitaxial layer
[0030] 200 bidirectional optical shutter
[0031] 300 photovoltaic voltage generating element
[0032] O photovoltaic member
[0033] C control circuit DETAILED DESCRIPTION
[0034] The present application will be explained below by way of examples, which are not intended to limit the present application to any particular environment, application or special way of implementation as described in the examples. Therefore, the description of the examples is only for the purpose of illustrating the present application and is not intended to limit the present application. It should be noted that elements not directly related to the present application have been omitted from the following examples and the drawings, and the dimensional relationship between the elements in the drawings is only for easy understanding and is not intended to limit the actual proportions.
[0035] As mentioned above, in order to improve the performance of the photoelectric conversion element, the conventional manufacturing process usually uses SOI wafer, however, the manufacturing process of SOI wafer is more complicated than the conventional bulk silicon wafer, and usually needs additional process to place a thin silicon layer on the insulating layer, which involves ion implantation and high-precision cutting and bonding technology, so that the price of SOI wafer is usually several times of the conventional bulk silicon wafer. In addition, please refer to Figure 1 As shown, the inventors found that when manufacturing photoelectric conversion elements using SOI wafers, in order to simultaneously manufacture at least two different components in the photoelectric conversion element on the same wafer, such as one of a light emitting diode or a bidirectional photothyristor, and the other is a transistor or a control circuit, etc., effective spatial isolation and / or electrical isolation between different components is required to avoid interference with each other. The SOI wafer 10 must be partitioned in the silicon thin film layer 16 above the insulating layer 14 on the surface of the silicon substrate 12, so that an isolation 18 is formed between the predetermined regions of each component. The isolation can be a trench isolation formed by wet etching, or ion implantation of opposite polarity to the silicon thin film layer 16 to form a heavily doped region. After forming an effective isolation on the silicon thin film layer 16, individual process treatment of different components in the photoelectric conversion element can be performed. In this way, such a complex pre-process will make the manufacturing cost high.
[0036] Therefore, the present application discloses an innovative semiconductor structure that can greatly reduce manufacturing costs while maintaining the performance of the original photoelectric conversion element. In the following, bidirectional photothyristor and photo-voltage generation (PVG) elements will be used as examples to illustrate the present application. Those skilled in the art can naturally apply the present application to other photoelectric conversion elements, such as photo relays, photo couplers, photo MOS, etc. after understanding the present application. Please refer to Figure 2 which shows a semiconductor structure and a manufacturing method thereof in an embodiment of the present application, in particular a semiconductor structure and a manufacturing method thereof based on a bulk silicon substrate. First, a bulk silicon substrate 100 is provided. It should be noted that, in order to reduce manufacturing costs, the present application does not use the aforementioned SOI wafer, but uses a conventional bulk silicon wafer based on single crystal silicon as the element growth wafer. Then, an oxide layer 110 is formed on the bulk silicon substrate 100. In specific embodiments, the oxide layer 110 is a silicon dioxide layer.
[0037] Secondly, due to the epitaxial process involved in the photoelectric conversion element, such as gallium arsenide, gallium nitride and other III-V compound semiconductors, the lattice of such III-V materials does not match the silicon, and the difference in the coefficient of thermal expansion between the two is large, resulting in stress and defect misorientation. Therefore, in order to alleviate the lattice misfit, reduce the formation of stress and defects, the present application utilizes chemical vapor deposition (CVD) and other techniques to deposit a polysilicon layer 120 on the oxide layer 110, as a relief III-V materials and bulk silicon substrate 100 between the stress difference, reduce the generation of lattice misorientation. Because the polysilicon itself is a disordered structure, it can better adapt to the lattice misfit between different materials, can promote the transition of different lattice directions, reduce the strain and defect density of III-V materials when directly grown on single crystal silicon, and help improve the quality of subsequent epitaxial growth.
[0038] More particularly, in order to reduce the cost of semiconductor element manufacturing and reduce the volume of semiconductor elements, the present application is aimed at the function and circuit arrangement of the predetermined element, and the polysilicon layer 120 is patterned to form a plurality of patterned polysilicon layers on the oxide layer 110, which are spatially isolated from each other, so that different process steps can be performed on the polysilicon layer 120 in subsequent processes. As shown in Figure 3 A patterned epitaxial layer 130 is formed above the polysilicon layer 120 in response to the patterned polysilicon layer 120. In particular, for example, an epitaxial process of III-V compound semiconductors (such as gallium arsenide, gallium nitride) can be performed on a part of the patterned polysilicon layer, so that the relevant III-V compound semiconductor layer is selectively epitaxially grown on a part of the patterned polysilicon layer, thereby forming an optoelectronic component O, such as a light-emitting diode or a photodiode. On the other hand, a control circuit C, such as a transistor and / or other control component, is formed on other parts of the patterned epitaxial layer 130.
[0039] As shown in Figure 3 The optoelectronic component O and the control circuit C are spatially isolated from each other in response to the patterned polysilicon layer 120. Such a patterned process combined with selective epitaxial growth can achieve the purpose of manufacturing different functional components on the same silicon wafer. This circuit integration effect helps to reduce the size of the element, reduce the packaging cost, and improve the reliability of the element. As shown in Figure 4 The block shown by the dashed line in the figure is a schematic diagram of a bidirectional optical gate 200 using the semiconductor structure of the present application, and the bidirectional optical gate 200 is actually applied to a circuit.
[0040] Another embodiment of the present application will be described below with the PVG element as an example. Unlike the aforementioned embodiment, this embodiment is particularly suitable for the components of silicon-based material in the optoelectronic conversion element, and without the need for the pretreatment of lattice adjustment, the components of silicon-based material can be directly grown on the silicon wafer. Please refer to Figure 5 which shows that a patterned oxide layer 110 is formed on the integrated silicon substrate 100 in a specific predetermined area, and the surface of the bulk silicon substrate 100 not covered by the oxide layer 110 is exposed. Then, a patterned polysilicon layer 120 is formed on the patterned oxide layer 110, so as to facilitate the selective growth of the epitaxial process in the subsequent process.
[0041] Please refer to Figure 6 , and then, as described above, the polysilicon layer 120 is used as a buffer for lattice adjustment, and a patterned epitaxial layer 130 is selectively epitaxially grown on the patterned polysilicon layer 120, so that the patterned epitaxial layer 130 can form appropriate optoelectronic components O, including light-emitting diodes or photo diode arrays (PDA). On the other hand, on the exposed part of the bulk silicon substrate 100, a growth process suitable for silicon-based materials can be performed to form functional components of silicon-based materials, such as a transistor and other control components of the control circuit C, without the need for epitaxial growth of III-V materials on the entire wafer surface, thereby effectively reducing the production cost.
[0042] As shown in Figure 6 , the optoelectronic components O and the control circuit C are spatially isolated from each other due to the patterned oxide layer 110, which can achieve the purpose of manufacturing different functional components on the same silicon wafer, helps to reduce the size of the element, reduce the cost of packaging, and also can reduce the problem of interference between different components, and improve the performance of the element. Please refer to Figure 7 which shows that the block shown by the dashed line in the figure is a schematic diagram of applying the semiconductor structure of the present application to a photovoltaic voltage generating element 300, and actually applying the photovoltaic voltage generating element 300 to a circuit.
[0043] It is noted that in some embodiments, before forming the control circuit C, a portion of the patterned epitaxial layer can also be directly epitaxially grown on the exposed portion of the bulk silicon substrate 100 in the aforementioned selective epitaxial growth process, and the control circuit C including transistors or other control components can be directly formed on the portion of the patterned epitaxial layer. Since the control circuit C is made of general silicon-based material, the growth process can ignore the problems of lattice mismatch, etc., and therefore, even if the epitaxial layer directly grown on the exposed portion of the bulk silicon substrate 100 has more lattice defects or dislocations, it does not affect the related functions of the control circuit C. Therefore, in some embodiments, the control circuit C and the optoelectronic component O can also be completed in the same epitaxial process.
[0044] Reference is made to Figure 8 which shows the process steps of a semiconductor structure in an embodiment of the present application. First, in step S01, a bulk silicon substrate is provided. Next, in step S02, an oxide layer is provided and disposed above the bulk silicon substrate. In step S03, a patterned polysilicon layer is provided and disposed above the oxide layer. In step S04, a patterned epitaxial layer is provided and disposed above the patterned polysilicon layer. The patterned epitaxial layer has an optoelectronic component and a control circuit, and the optoelectronic component and the control circuit are spatially isolated from each other due to the patterned polysilicon layer. The composition and relationship of the elements in each process step can be referred to the foregoing description, and will not be described in detail.
[0045] Reference is made to Figure 9 which shows the process steps of a semiconductor structure in another embodiment of the present application. First, in step S01, a bulk silicon substrate is provided. Next, in step S02, a patterned oxide layer is provided and disposed above the bulk silicon substrate to expose a portion of the bulk silicon substrate. In step S03, a patterned polysilicon layer is provided and disposed above the patterned oxide layer. In step S04, a patterned epitaxial layer is provided and disposed above the patterned polysilicon layer, and the patterned epitaxial layer has an optoelectronic component. In step S05, a control circuit is provided and disposed above the exposed portion of the bulk silicon substrate, and the optoelectronic component and the control circuit are spatially isolated from each other due to the patterned oxide layer. The composition and relationship of the elements in each process step can be referred to the foregoing description, and will not be described in detail.
[0046] The above-described embodiments are only used to illustrate the implementation of the present application and explain the technical features of the present application, and are not used to limit the protection scope of the present application. Any changes or equivalent arrangements made by any person skilled in the art should fall within the protection scope of the present application, and the protection scope of the present application should be subject to the claims.
Claims
1. A semiconductor structure comprising: Integrated silicon substrate; An oxide layer is disposed above the bulk silicon substrate; A patterned polysilicon layer is disposed above the oxide layer; and A patterned epitaxial layer is disposed above the patterned polysilicon layer. in, The patterned epitaxial layer has a photoelectric component and a control circuit, which are spatially isolated from each other due to the patterned polysilicon layer.
2. The semiconductor structure of claim 1, wherein the oxide layer is a silicon dioxide layer.
3. The semiconductor structure of claim 1, wherein the optoelectronic component comprises a light-emitting diode or a photodiode.
4. The semiconductor structure of claim 1, wherein the control circuit comprises a transistor.
5. A semiconductor structure comprising: Integrated silicon substrate; A patterned oxide layer is disposed above the bulk silicon substrate to expose a portion of the bulk silicon substrate; A patterned polysilicon layer is disposed above the patterned oxide layer; A patterned epitaxial layer is disposed above the patterned polysilicon layer, and the patterned epitaxial layer has a photoelectric component; as well as A control circuit is disposed above the exposed portion of the bulk silicon substrate. The photoelectric component and the control circuit are spatially isolated from each other due to the patterned oxide layer.
6. The semiconductor structure of claim 5, wherein the oxide layer is a silicon dioxide layer.
7. The semiconductor structure of claim 5, wherein the optoelectronic component comprises a light-emitting diode or a photodiode.
8. The semiconductor structure of claim 5, wherein the control circuit comprises a transistor.
9. A method for manufacturing a semiconductor structure, comprising: Provides an integrated silicon substrate; An oxide layer is provided and disposed above the bulk silicon substrate; A patterned polysilicon layer is provided, disposed above the oxide layer; and A patterned epitaxial layer is provided above the patterned polysilicon layer. in, The patterned epitaxial layer has a photoelectric component and a control circuit, which are spatially isolated from each other due to the patterned polysilicon layer.
10. The manufacturing method of claim 9, wherein the oxide layer is provided as a silicon dioxide layer.
11. A method for manufacturing a semiconductor structure, comprising: Provides an integrated silicon substrate; A patterned oxide layer is provided above the bulk silicon substrate to expose a portion of the bulk silicon substrate; A patterned polysilicon layer is provided and disposed above the patterned oxide layer; A patterned epitaxial layer is provided above the patterned polysilicon layer, the patterned epitaxial layer having a photoelectric component; and A control circuit is provided, disposed above the exposed portion of the bulk silicon substrate. in, The optoelectronic component and the control circuit should be spatially isolated from each other due to the patterned oxide layer.
12. The manufacturing method of claim 11, wherein providing the patterned oxide layer is providing a patterned silicon dioxide layer.