Display device and manufacturing method thereof

Abstract

The invention relates to a display device and a manufacturing method thereof. A display device according to an embodiment may include: a substrate; a pixel electrode and a common electrode disposed on the substrate and disposed spaced apart from each other on the substrate; a light emitting element structure disposed on the common electrode and including a light emitting column and a plurality of dummy columns surrounding the light emitting column; and a connection electrode connecting the light emitting column and the pixel electrode, in which the light emitting element structure may further include: a reflective layer surrounding an upper surface and a side surface of the dummy column; and a first protective layer surrounding an upper surface and a side surface of the dummy column and an upper surface and a side surface of the light emitting column.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device and a manufacturing method thereof. BACKGROUND

[0002] As the information society develops, the demand for display devices for displaying images increases in various forms. The display device can be a flat panel display device such as a liquid crystal display, a field emission display, a light emitting display, etc.

[0003] The light emitting display device can include an organic light emitting display device including an organic light emitting diode element as a light emitting element and a micro light emitting display device including a micro light emitting diode element (hereinafter referred to as a micro light emitting element) as a light emitting element. The micro light emitting diode element is configured of an inorganic substance, and thus has an advantage of less deterioration problem and long lifespan compared to the organic light emitting diode element. SUMMARY

[0004] The present application relates to a display device and a manufacturing method thereof.

[0005] The technical problems of the present application are not limited to the above-mentioned technical problems, and other technical problems not mentioned herein can be clearly understood by those skilled in the art of the present application based on the following description.

[0006] A display device according to an embodiment for solving the above-mentioned technical problems can include a substrate; a pixel electrode and a common electrode disposed on the substrate and spaced apart from each other on the substrate; a light emitting element structure disposed on the common electrode and including a light emitting pillar and a plurality of dummy pillars surrounding the light emitting pillar; and a connection electrode connecting the light emitting pillar and the pixel electrode, wherein the light emitting element structure can further include a reflection layer surrounding upper surfaces and side surfaces of the dummy pillars, and a first protection layer surrounding upper surfaces and side surfaces of the dummy pillars and upper surfaces and side surfaces of the light emitting pillar.

[0007] The light emitting pillar according to an embodiment can have a first inclination angle constituted by a lower surface and side surfaces of the light emitting pillar, the dummy pillar can have a second inclination angle constituted by a lower surface and side surfaces of the dummy pillar, and the second inclination angle can be different from the first inclination angle.

[0008] The second inclination angle according to an embodiment can be less than the first inclination angle.

[0009] The dummy pillar according to an embodiment can be tapered to be narrower in width toward an upper portion on the substrate, and the upper portion and the lower portion of the light emitting pillar can have the same width.

[0010] The light emitting element structure according to an embodiment can further include an element reflective layer on a lower surface, a plurality of semiconductor layers disposed on the element reflective layer, and a conductive layer disposed on the plurality of semiconductor layers.

[0011] The plurality of semiconductor layers according to an embodiment can include a second semiconductor layer including a first portion having a first height and a second portion having a second height on the first portion, an active layer disposed on the second semiconductor layer, and a first semiconductor layer disposed on the active layer.

[0012] Each of the dummy pillar and the light emitting pillar according to an embodiment can include the second semiconductor layer including the second portion, the active layer, the first semiconductor layer, and the conductive layer.

[0013] The first protective layer according to an embodiment can include an opening portion exposing a portion of the conductive layer of the light emitting pillar, and the connection electrode can be connected with the conductive layer through the opening portion.

[0014] The reflective layer according to an embodiment can include a first layer and a second layer of M (M is an integer of 2 or more) pairs having different refractive indexes from each other or a metal.

[0015] The display device according to an embodiment can further include a planarization layer disposed on the light emitting element structure, and a second protective layer disposed on an upper surface of the planarization layer and a side surface of the light emitting element structure, and having an opening portion overlapping with an opening portion of the first protective layer.

[0016] The display device according to an embodiment can further include a partition wall disposed to surround the light emitting element structure, a third reflective layer disposed on a side surface of the partition wall, and a wavelength conversion layer disposed on a space formed by the partition wall.

[0017] The light emitting element structure according to an embodiment can not overlap with the partition wall.

[0018] The light emitting element structure according to an embodiment can not overlap with the light emitting pillar, and can overlap with a portion of the dummy pillar.

[0019] The dummy column according to an embodiment can be circular or polygonal in plan, and the light emitting column can be circular or polygonal in plan.

[0020] The dummy column according to an embodiment can have the same shape as the light emitting column in plan.

[0021] The dummy column according to an embodiment can have a different shape from the light emitting column in plan.

[0022] The display device manufacturing method according to an embodiment can include forming a second semiconductor substance layer, an active substance layer, a first semiconductor substance layer, and a conductive substance layer on a semiconductor substrate; performing first etching on the second semiconductor substance layer, the active substance layer, the first semiconductor substance layer, and the conductive substance layer to form a plurality of columns each including a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer; forming a reflective layer having an opening portion in a part of the plurality of columns, and performing second etching on the columns in which the reflective layer is not disposed; and forming a first protective layer having an opening portion on the columns in which the reflective layer is not disposed on a front surface of the semiconductor substrate.

[0023] The first etching according to an embodiment can be dry etching, and the second etching can be wet etching.

[0024] In the step of forming a reflective layer having an opening portion in a part of the plurality of columns, and performing second etching on the columns in which the reflective layer is not disposed according to an embodiment, among the plurality of columns, the columns in which the reflective layer surrounds the upper surface and the side surface can be dummy columns, the columns in which the reflective layer is not disposed due to the opening portion on the upper surface and the side surface can be light emitting columns, and the light emitting columns can have different inclined surfaces from the dummy columns by the second etching.

[0025] The display device manufacturing method according to an embodiment can further include separating a light emitting element structure including the light emitting column and the dummy column from the semiconductor substrate, and transferring to a circuit substrate including a pixel electrode and a common electrode; and forming a connection electrode connecting the pixel electrode and the light emitting column.

[0026] Specific matters of other embodiments are included in the detailed description and the drawings.

[0027] By the display device and the manufacturing method thereof according to an embodiment, light extraction efficiency of the display device can be improved.

[0028] Effects according to an embodiment are not limited by the above examples, and include more various effects in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a perspective view showing a display device according to an embodiment.

[0030] Figure 2 is a layout view showing a display device according to an embodiment.

[0031] Figure 3 is a block diagram showing a display device according to an embodiment.

[0032] Figure 4 is an equivalent circuit diagram showing a sub-pixel according to an embodiment.

[0033] Figure 5 is a layout view showing a pixel of a display region according to an embodiment.

[0034] Figure 6 is a cross-sectional view showing an example of a cross section of a display panel corresponding to the I1-I1' line, the I2-I2' line, and the I3-I3' line of Figure 5

[0035] Figure 7 is a cross-sectional view showing an example of a cross section of the A1 region of Figure 6

[0036] Figure 8 is a diagram schematically showing a light-emitting element structure according to an embodiment.

[0037] Figure 9 is a layout view showing a pixel of a display region according to another embodiment.

[0038] Figure 10 is a cross-sectional view showing an example of a part of a cross section of a display panel in a third light-emitting region of Figure 9

[0039] Figure 11 is a flowchart showing a manufacturing method of a display device according to an embodiment.

[0040] Figures 12 to 22 is a diagram for explaining a manufacturing method of a display device according to an embodiment.

[0041] Figures 23 to 26 is a plan view for explaining positions of dummy columns and light-emitting columns in a sub-pixel according to an embodiment.

[0042] Figure 27 and Figure 28 is a plan view for explaining positions of dummy columns and light-emitting columns in a sub-pixel according to another embodiment.

[0043] Figure 29 ​​​is an example view illustrating a smart watch including a display device according to an embodiment.

[0044] Figure 30 and Figure 31 is an example view illustrating a virtual reality device including a display device according to an embodiment.

[0045] Figure 32 is an example view illustrating a virtual reality device including a display device according to still another embodiment.

[0046] Figure 33 is an example view illustrating a car dashboard and a center dashboard including a display device according to an embodiment.

[0047] Figure 34 is an example view illustrating a transparent display device including a display device according to an embodiment.

[0048] REFERENCE NUMERALS DETAILED DESCRIPTION

[0049] Advantages and features of the present application and methods of accomplishing the same can be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. The present application may, however, be embodied in multiple different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art, and no portion of the application should be deemed critical, essential, or required, except those items will be defined by the appended claims.

[0050] Where an element or layer is referred to as being "on" another element or substrate, it can be directly on the element or substrate or intervening layers can also be present. In this specification, like drawing reference numerals indicate like elements. The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments are exemplary and thus the present application is not limited to the illustrated matters.

[0051] The respective features of the various embodiments of the present application can be partially or wholly combined or can be independently implemented, and various embodiments can be implemented in a variety of combinations or drives in the technical field. The respective embodiments can be independently implemented or implemented together in a related relationship.

[0052] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0053] Figure 1 is an example view illustrating a display device according to an embodiment.

[0054] Reference Figure 1The display device 10 can be used not only as a display screen of a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigator, an Ultra Mobile PC (UMPC), and the like, but also as a display screen of various products such as a television, a notebook computer, a monitor, a billboard, an internet of things (IOT) device, and the like.

[0055] The display device 10 can be an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a light emitting display device such as an ultra-small light emitting display device using an ultra-small light emitting diode (micro light emitting diode (micro LED) or nano light emitting diode (nano LED)). Hereinafter, a case in which the display device 10 is an ultra-small light emitting display device will be mainly described, but the present disclosure is not limited thereto. Hereinafter, for convenience of description, the ultra-small light emitting diode will be referred to as a light emitting element.

[0056] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0057] The display panel 100 can be formed in a planar shape of a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. A corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be formed in an arc shape having a predetermined curvature or in a right angle. The planar shape of the display panel 100 is not limited to a quadrangle, and can be formed in other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 can be formed flat, but is not limited thereto. For example, the display panel 100 can include curved portions formed at left and right side ends and having a constant curvature or a varying curvature. In addition, the display panel 100 can be formed to be soft so that the display panel 100 can be bent, folded, bended, folded, or curled.

[0058] The substrate SUB of the display panel 100 (refer toFigure 6 ) can include a main area MA and a sub area SBA.

[0059] The main area MA can include a display area DA in which an image is displayed and a non-display area NDA which is a surrounding area of the display area DA. The display area DA can include a plurality of pixels in which an image is displayed. Each of the pixels can include a plurality of sub-pixels. For example, each of the pixels can include a first sub-pixel which emits light of a first color, a second sub-pixel which emits light of a second color, and a third sub-pixel which emits light of a third color, but embodiments of the present specification are not limited thereto.

[0060] The sub area SBA can protrude from one side of the main area MA in a second direction DR2. Although Figure 1 An example in which the sub area SBA is expanded is exemplarily shown, but the sub area SBA can be curved, in which case the sub area SBA can be disposed on a lower surface of the display panel 100. In the case in which the sub area SBA is curved, the sub area SBA can overlap the main area MA in a third direction DR3 which is a thickness direction of the display panel 100. The display driving circuit 250 can be disposed in the sub area SBA.

[0061] The display driving circuit 250 can generate a signal and a voltage for driving the display panel 100. The display driving circuit 250 can be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 can be attached to the circuit board 300 by a chip on film (COF) method.

[0062] The circuit board 300 can be attached to one end of the sub area SBA of the display panel 100. Accordingly, the circuit board 300 can be electrically connected with the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 can receive digital video data, a timing signal, and a driving voltage through the circuit board 300. The circuit board 300 can be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0063] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power voltage from the outside. The power supply circuit 500 can be formed as an integrated circuit (IC) and attached to the circuit board 300 in a COF manner.

[0064] Figure 2 FIG. 1 is a layout diagram illustrating a display device according to an embodiment. Figure 2 An example illustrates a case in which the sub area SBA is unfolded without being bent.

[0065] Referring to Figure 2 The display panel 100 can include a main area MA and a sub area SBA.

[0066] The main area MA can include a display area DA in which an image is displayed and a non-display area NDA which is a surrounding area of the display area DA. The display area DA can occupy a majority of the main area MA. The display area DA can be disposed at the center of the main area MA.

[0067] The display area DA can include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX can include a plurality of sub-pixels SPX. The pixel PX can be defined as a group of sub-pixels that can express the smallest unit of white gray scale.

[0068] The non-display area NDA can be disposed adjacent to the display area DA. The non-display area NDA can be an outer area of the display area DA. The non-display area NDA can be disposed to surround the display area DA. The non-display area NDA can be an edge area of the display panel 100.

[0069] The first scan driving part SDC1 and the second scan driving part SDC2 can be disposed in the non-display area NDA. The first scan driving part SDC1 can be disposed at one side (e.g., the left side) of the display panel 100, and the second scan driving part SDC2 can be disposed at the other side (e.g., the right side) of the display panel 100, but is not limited thereto. Each of the first scan driving part SDC1 and the second scan driving part SDC2 can be electrically connected to the display driving circuit 250 through a scan fan-out wiring. Each of the first scan driving part SDC1 and the second scan driving part SDC2 can receive a scan control signal from the display driving circuit 250 and output a scan signal to a scan wiring according to the scan control signal.

[0070] The sub-area SBA can protrude from one side of the main area MA in the second direction DR2. The length of the sub-area SBA in the second direction DR2 can be less than the length of the main area MA in the second direction DR2. The length of the sub-area SBA in the first direction DR1 can be less than the length of the main area MA in the first direction DR1, or the length of the sub-area SBA in the first direction DR1 can be substantially the same as the length of the main area MA in the first direction DR1. The sub-area SBA can be curved, and can be disposed at a lower portion of the display panel 100. In this case, the sub-area SBA can overlap the main area MA in the third direction DR3.

[0071] The sub-area SBA can include a connection area CA, a pad area PA, and a bending area BA.

[0072] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA can be contiguous with the non-display area NDA of the main area MA, and the other side of the connection area CA can be contiguous with the bending area BA.

[0073] The pad area PA is an area in which the pads PD and the display driving circuit 250 are disposed. The display driving circuit 250 can be attached to the driving pads of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD in the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA can be contiguous with the bending area BA.

[0074] The bending area BA is a curved area. In the case where the bending area BA is curved, the pad area PA can be disposed at a lower portion of the connection area CA and a lower portion of the main area MA. The bending area BA can be disposed between the connection area CA and the pad area PA. One side of the bending area BA can be contiguous with the connection area CA, and the other side of the bending area BA can be contiguous with the pad area PA.

[0075] Figure 3 FIG. 1 is a block diagram illustrating a display apparatus according to an embodiment.

[0076] Referring to Figure 3 The display area DA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0077] The plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. The plurality of scan lines SL and the plurality of light emission control lines EL can extend along the first direction DR1 and can be arranged along the second direction DR2. The plurality of data lines DL can extend along the second direction DR2 and can be arranged along the first direction DR1. The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0078] Each of the plurality of sub-pixels SPX can be connected to one of the plurality of write scan lines GWL, one of the plurality of control scan lines, one of the plurality of initialization scan lines GIL, one of the plurality of bias scan lines GBL, one of the plurality of light emission control lines EL, and one of the plurality of data lines DL. Each of the plurality of sub-pixels SPX can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and can cause the light emitting element to emit light according to the data voltage.

[0079] The non-display area NDA includes a first scan driving section SDC1 and a second scan driving section SDC2.

[0080] Each of the first scan driving section SDC1 and the second scan driving section SDC2 includes a write scan signal output section 611, an initialization scan signal output section 612, a bias scan signal output section 613, and a light emission control signal output section 614. Each of the write scan signal output section 611, the initialization scan signal output section 612, the bias scan signal output section 613, and the light emission control signal output section 614 can receive a scan timing control signal SCS from the timing control circuit 251.

[0081] The write scan signal output section 611 can generate and sequentially output a write scan signal to the write scan line GWL according to the scan timing control signal SCS of the timing control circuit 251.

[0082] The initialization scan signal output section 612 can generate and sequentially output an initialization scan signal to the initialization scan line GIL according to the scan timing control signal SCS.

[0083] The bias scan signal output section 613 can generate and sequentially output a bias scan signal to the bias scan line GBL according to the scan timing control signal SCS. The light emission control signal output section 614 can generate and sequentially output a light emission control signal to the light emission control line EL according to the scan timing control signal SCS.

[0084] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252.

[0085] The data driving circuit 252 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs it to the data line DL. In this case, a sub-pixel SPX can be selected by a write scan signal of the first scan driving part SDC1 and the second scan driving part SDC2, and a data voltage can be supplied to the selected sub-pixel SPX.

[0086] The timing control circuit 251 can receive digital video data DATA and a timing signal from the outside. The timing control circuit 251 can generate a scan timing control signal SCS and a data timing control signal DCS for controlling the display panel 100 according to the timing signal. The timing control circuit 251 can output the scan timing control signal SCS to the first scan driving part SDC1 and the second scan driving part SDC2. The timing control circuit 251 can output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0087] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 can generate and supply a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VINT, and a fourth power supply voltage VAINT to the display panel 100.

[0088] Figure 4 is an equivalent circuit diagram illustrating a sub-pixel according to an embodiment.

[0089] Referring to Figure 4 A sub-pixel SPX according to an embodiment can be connected to a scan line GWL, GIL, GBL, an emission control line EL, and a data line DL. For example, the sub-pixel SPX can be connected to a write scan line GWL, an initialization scan line GIL, a bias scan line GBL, an emission control line EL, and a data line DL.

[0090] A sub-pixel SPX according to an embodiment includes a driving transistor DT, a switching element, a capacitor C1, and an emission element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0091] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0092] The light-emitting element LE can be a micro light-emitting diode.

[0093] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted by the light-emitting element LE is proportional to the driving current Ids. The anode electrode of the light-emitting element LE can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode can be connected to the second power supply voltage VSS applied. Figure 3 The second power line VSL.

[0094] Capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power supply line VDL to which a first power supply voltage is applied. The first power supply voltage can be a level higher than the second power supply voltage VSS. Figure 3 The voltage level of capacitor C1 is [not specified]. One electrode of capacitor C1 can be connected to the gate electrode of the driving transistor DT, and the other electrode can be connected to the first power supply line VDL.

[0095] like Figure 4 As shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can all be formed using p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed using polysilicon.

[0096] The gate electrode of the first transistor ST1 and the gate electrode of the second transistor ST2 can be connected to a write scan line GWL, the gate electrode of the third transistor ST3 can be connected to an initialization scan line GIL, and the gate electrode of the fourth transistor ST4 can be connected to a bias scan line GBL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are each formed using a p-type MOSFET, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can each be turned on in a case where a gate low voltage scan signal and an emission control signal are applied to the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively. One electrode of the third transistor ST3 is connected to a first initialization voltage line VIL to which a third power supply voltage VINT ( Figure 3 ) is applied, and one electrode of the fourth transistor ST4 can be connected to a second initialization voltage line VAIL to which a fourth power supply voltage VAINT ( Figure 3 ) is applied. The third power supply voltage VINT ( Figure 3 ) and the fourth power supply voltage VAINT ( Figure 3 ) can be voltages different from each other. Further, the third power supply voltage VINT ( Figure 3 ) and the fourth power supply voltage VAINT ( Figure 3 ) can be voltages having a lower level than the first power supply voltage VDD, and can be voltages having a higher level than the second power supply voltage VSS ( Figure 3 ).

[0097] Alternatively, the driver transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be formed using p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 can be formed using n-type MOSFETs. In this case, the active layer of each of the driver transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed using p-type MOSFETs can be formed using polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed using n-type MOSFETs can be formed using an oxide semiconductor. Further, since the first transistor ST1 and the third transistor ST3 are formed using n-type MOSFETs, the first transistor ST1 can be turned on in the case where a scan signal to which a gate high voltage is applied is input, and the third transistor ST3 can be turned on in the case where an initialization scan signal to which a gate high voltage is applied is input. In contrast, since the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed using p-type MOSFETs, they can be turned on in the case where a scan signal to which a gate low voltage is applied and a light-emitting control signal are input.

[0098] Alternatively, in the case where the fourth transistor ST4 is formed using an n-type MOSFET and the driver transistor DT, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fifth transistor ST5, and the sixth transistor ST6 are formed using p-type MOSFETs, the active layer of the fourth transistor ST4 can be formed using an oxide semiconductor, and the active layer of each of the driver transistor DT, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fifth transistor ST5, and the sixth transistor ST6 can be formed using polysilicon. Further, in contrast to the fourth transistor ST4 which is turned on in the case where a scan signal to which a gate high voltage is applied is input, the driver transistor DT, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fifth transistor ST5, and the sixth transistor ST6 can be turned on in the case where a scan signal to which a gate low voltage is applied and a light-emitting control signal are input.

[0099] Alternatively, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driver transistor DT can also be formed using n-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driver transistor DT can be formed using an oxide semiconductor, and they can be turned on in the case where a scan signal to which a gate high voltage is applied and a light-emitting control signal are input.

[0100] Figure 5 FIG. 1 is a layout diagram illustrating pixels of a display area according to an embodiment.

[0101] Referring to Figure 5 Each of the plurality of pixels PX of the display area DA can include three sub-pixels SPX1, SPX2, SPX3, but embodiments of the present specification are not limited thereto and can include four sub-pixels. In the case where each of the plurality of pixels PX includes three sub-pixels SPX1, SPX2, SPX3, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be included.

[0102] The plurality of pixels PX can be arranged in a matrix form. In each of the plurality of pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along a first direction DR1.

[0103] In the case where each of the plurality of pixels PX includes three sub-pixels SPX1, SPX2, SPX3, the first sub-pixel SPX1 can emit light of a first color, the second sub-pixel SPX2 can emit light of a second color, and the third sub-pixel SPX3 can emit light of a third color. Here, the light of the first color can be light of a red wavelength band, the light of the second color can be light of a green wavelength band, and the light of the third color can be light of a blue wavelength band. For example, the blue wavelength band can mean that a main peak wavelength of light is included in a wavelength band of about 370 nm to 460 nm, the green wavelength band means that a main peak wavelength of light is included in a wavelength band of about 480 nm to 560 nm, and the red wavelength band means that a main peak wavelength of light is included in a wavelength band of about 600 nm to 750 nm.

[0104] Alternatively, in the case where each of the plurality of pixels PX includes four sub-pixels, the first sub-pixel can emit light of a first color, the second sub-pixel and the fourth sub-pixel can emit light of a second color, and the third sub-pixel can emit light of a third color. Alternatively, the first sub-pixel can emit light of a first color, the second sub-pixel can emit light of a second color, the third sub-pixel can emit light of a third color, and the fourth sub-pixel can emit light of a fourth color. At this time, the light of the fourth color can be white light.

[0105] The first sub-pixel SPX1 includes a first pixel electrode PXE1, a first common electrode CE1, a plurality of light emitting elements LE, and a first light conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, a second common electrode CE2, a plurality of light emitting elements LE, and a second light conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, a third common electrode CE3, a plurality of light emitting elements LE, and a light transmission layer TPL.

[0106] Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can have a rectangular planar shape with a short side in the first direction DR1 and a long side in the second direction DR2. The area of ​​the first sub-pixel SPX1, the area of ​​the second sub-pixel SPX2, and the area of ​​the third sub-pixel SPX3 can be set based on the light conversion efficiency of the first light conversion layer QDL1 and the second light conversion layer QDL2. That is, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0107] Each of pixel electrodes PXE1, PXE2, and PXE3 can be electrically connected to at least one transistor via pixel connection holes CT1 / CT2 / CT3. For example, each of pixel electrodes PXE1, PXE2, and PXE3 can be connected to the fourth transistor ST4 of the corresponding sub-pixel. Figure 4 The first electrode and the sixth transistor ST6 () Figure 4 The second electrode is electrically connected.

[0108] Each of the pixel electrodes PXE1, PXE2, PXE3 and the common electrodes CE1, CE2, CE3 can have a rectangular planar shape. The area of ​​the first pixel electrode PXE1 can be the same as the area of ​​the first common electrode CE1, the area of ​​the second pixel electrode PXE2 can be the same as the area of ​​the second common electrode CE2, and the area of ​​the third pixel electrode PXE3 can be the same as the area of ​​the third common electrode CE3, but the embodiments in this specification are not limited thereto.

[0109] In the first sub-pixel SPX1, the first pixel electrode PXE1 and the first common electrode CE1 can be arranged separately in the second direction DR2. In the second sub-pixel SPX2, the second pixel electrode PXE2 and the second common electrode CE2 can be arranged separately in the second direction DR2. In the third sub-pixel SPX3, the third pixel electrode PXE3 and the third common electrode CE3 can be arranged separately in the second direction DR2.

[0110] The first common electrode CE1 can be connected to the second power supply voltage VSS through the first common connection hole CT4. Figure 3 The second power line VSL () Figure 4 The second common electrode CE2 can be connected to the second power line VSL through the second common connection hole CT5. The third common electrode CE3 can be connected to the second power line VSL through the third common connection hole CT6. Therefore, the second power supply voltage VSS can be applied to each of the common electrodes CE1, CE2, and CE3.

[0111] Multiple light-emitting element structures (LES) (refer to) Figure 6The light-emitting elements (LES) can be arranged on each of the common electrodes CE1, CE2, and CE3. The common electrodes CE1, CE2, and CE3 may not be exposed by the light-emitting element structures (LES). Multiple light-emitting element structures (LES) can emit light of a third color (i.e., light in the blue wavelength band), but the embodiments in this specification are not limited to this. If the light-emitting element structure (LES) of the first sub-pixel SPX1 emits light of a first color, the light-emitting element structure (LES) of the second sub-pixel SPX2 emits light of a second color, and the light-emitting element structure (LES) of the third sub-pixel SPX3 emits light of a third color, the light conversion layers QDL1 and QDL2 and the light transmission layer TPL can be omitted.

[0112] The first light conversion layer QDL1 can convert or shift the peak wavelength of the incident light into light with another specific peak wavelength and then emit it. For example, the first light conversion layer QDL1 can convert or shift the third light emitted from multiple light-emitting elements LE of the first sub-pixel SPX1 into the first light.

[0113] The second light conversion layer QDL2 can convert or shift the peak wavelength of the incident light into light with another specific peak wavelength and then emit it. For example, the second light conversion layer QDL2 can convert or shift the third light emitted from multiple light-emitting elements LE of the second sub-pixel SPX2 into second light.

[0114] The light transmission layer (TPL) allows incident light to be transmitted directly. For example, the TPL allows third light emitted from multiple light-emitting elements (LEs) of the third sub-pixel SPX3 to be transmitted directly.

[0115] Figure 6 It is shown that... Figure 5 A cross-sectional view of an example of the display panel corresponding to the I1-I1' line, I2-I2' line, and I3-I3' line. Figure 7 It is shown in detail Figure 6 A cross-sectional view of an example of region A1.

[0116] Reference Figure 6 and Figure 7 The substrate SUB can be constructed using insulating materials such as glass or polymer resin. When the substrate SUB is constructed using polymer resin, it can be a stretchable, flexible substrate. The polymer resin can be acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0117] A barrier film (BR) can be disposed on the substrate SUB. The barrier film BR is a film used to protect the transistor and light-emitting element structure (LES) of the thin-film transistor layer (TFTL) from the influence of moisture that permeates through the moisture-permeable substrate SUB. The barrier film BR can be constructed using multiple inorganic films stacked alternately.

[0118] A thin-film transistor (TFT) 1 can be disposed on the barrier film BR. The thin-film transistor TFT 1 can be... Figure 4 One of the fourth transistor ST4 and the sixth transistor ST6 shown. The thin-film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0119] A first active layer ACT1 of a thin-film transistor (TFT) 1 can be disposed on the barrier film BR. The first active layer ACT1 of the TFT 1 may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer ACT1 of the TFT 1 may be constructed using an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0120] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region on the third-direction DR3, which is the thickness direction of the substrate SUB, that overlaps with the first gate electrode G1. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions on the third-direction DR3 that do not overlap with the first gate electrode G1. The first source region S1 and the first drain region D1 may be regions that are doped with ions in the semiconductor material to become conductive.

[0121] A first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1 and the first drain region D1 of the thin film transistor TFT1.

[0122] A first gate metal layer may be disposed on the first gate insulating film 131. The first gate metal layer may include the first gate electrode G1 of the thin-film transistor TFT1 and the first capacitor electrode CAE1. The first gate electrode G1 may overlap with the first active layer ACT1 on the third-direction DR3. Figure 6 The diagram shows a configuration where the first gate electrode G1 and the first capacitor electrode CAE1 are arranged separately from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 can be connected to each other.

[0123] A second gate insulating film 132 may be disposed on the first gate electrode G1 and the first capacitor electrode CAE1 of the thin film transistor TFT1.

[0124] A second gate metal layer may be disposed on the second gate insulating film 132. The second gate metal layer may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap with the first capacitor electrode CAE1 on the third-direction DR3. Since the second gate insulating film 132 has a predetermined dielectric constant, a capacitor C1 can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating film 132 disposed therebetween. Figure 4 ).

[0125] An interlayer insulating film 141 can be arranged on the second capacitor electrode CAE2.

[0126] A first data metal layer may be disposed on the interlayer insulating film 141. The first data metal layer may include a first source connection electrode PCE1. The first source connection electrode PCE1 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that passes through the first gate insulating film 131, the second gate insulating film 132 and the interlayer insulating film 141.

[0127] A first planarization organic film 160 for planarizing the step difference caused by the thin-film transistor TFT1 can be disposed on the first source connection electrode PCE1.

[0128] A second data metal layer may be disposed on the first planarized organic film 160. The second data metal layer may include a second source connection electrode PCE2. The second source connection electrode PCE2 may be connected to the first source connection electrode PCE1 through a second pixel contact hole PCT2 penetrating the first planarized organic film 160.

[0129] A second planarized organic film 180 can be arranged on the second source connection electrode PCE2.

[0130] The barrier film BR, the first gate insulating film 131, the second gate insulating film 132, and the interlayer insulating film 141 can be made of inorganic films (e.g., silicon nitride (SiN)). X ), silicon oxynitride (SiON), silicon oxide (SiO) X Titanium oxide (TiO) X ) or aluminum oxide (AlO) X ))form.

[0131] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer can be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or their alloys.

[0132] The first planarization organic membrane 160 and the second planarization organic membrane 180 can be formed using organic membranes such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0133] A light-emitting element layer may be disposed on the second planarized organic film 180. The light-emitting element layer may include pixel electrodes PXE1, PXE2, PXE3, light-emitting elements LE, and a common electrode CE.

[0134] A pixel electrode layer may be disposed on the second planarized organic film 180. The pixel electrode layer may include pixel electrodes PXE1, PXE2, PXE3 and common electrodes CE1, CE2, CE3.

[0135] The pixel electrode layer can be formed as a single layer or multiple layers of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to reduce the resistance of each of the pixel electrodes PXE1, PXE2, and PXE3, the pixel electrode layer can be made of copper (Cu), which has low sheet resistance.

[0136] A light-emitting element structure (LES) can be arranged thereon. The LES may include a first reflective layer RF1, a plurality of semiconductor layers disposed on the first reflective layer RF1, a conductive layer E1, a second reflective layer RF2 covering at least a portion of the plurality of semiconductor layers, and a first protective layer INS1. In one embodiment, Figures 1 to 5 The light-emitting element LE mentioned in the text can be a light-emitting element structure LES.

[0137] One surface of the light-emitting element structure (LES) can be directly disposed on the common electrode (CE). Conversely, the light-emitting element structure (LES) may not be in direct contact with the pixel electrode.

[0138] The first reflective layer RF1 can be arranged closer to the pixel electrode layer than the multiple semiconductor layers.

[0139] The first reflective layer RF1 can reflect light emitted from the active layer MQW in the downward direction, thereby emitting light onto the upper surface of the light-emitting element LE. Therefore, light loss of the light-emitting element LE can be reduced, thus improving the light efficiency of the light-emitting element LE.

[0140] The first reflective layer RF1 may include a metallic material with high light reflectivity. For example, the first reflective layer RF1 may include aluminum or silver, or an alloy of aluminum or silver.

[0141] Multiple semiconductor layers may include a second semiconductor layer SEM2, an active layer MQW, and a first semiconductor layer SEM1 arranged sequentially on the third-direction DR3.

[0142] The second semiconductor layer SEM2 can be disposed on the first reflective layer RF1. The second semiconductor layer SEM2 can be doped with a second conductivity type dopant such as Si, Ge or Sn. For example, the second semiconductor layer SEM2 can be n-GaN doped with n-type Si.

[0143] The second semiconductor layer SEM2 may include multiple first portions SEM2_1 having a first thickness t1 (refer to...). Figure 8 The first part SEM2_1 and a plurality of second parts SEM2_2 having a second thickness t2 are arranged on the first part SEM2_1. The plurality of second parts SEM2_2 can be arranged alternately on the first part SEM2_1.

[0144] The active layer MQW can be disposed on the second portion SEM2_2 of the second semiconductor layer SEM2. The active layer MQW can emit light by recombination of electron-hole pairs based on the electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0145] The active layer MQW can include materials with single quantum well structures or multiple quantum well structures. When the active layer MQW includes materials with multiple quantum well structures, it can also be a structure in which multiple well layers and barrier layers are stacked alternately. In this case, the well layers can be formed using InGaN, and the barrier layers can be formed using GaN or AlGaN, but are not limited to these. Alternatively, the active layer MQW can have a structure in which semiconductor materials with high band gaps and semiconductor materials with low band gaps are stacked alternately, and can also include different group III to group V semiconductor materials depending on the wavelength band of the emitted light.

[0146] When the active layer MQW includes InGaN, the color of the emitted light can vary depending on the indium (In) content. For example, as the indium (In) content increases, the wavelength band of the light emitted by the active layer MQW can shift towards the red wavelength band, and as the indium (In) content decreases, the wavelength band of the light emitted by the active layer MQW can shift towards the blue wavelength band. For example, the indium (In) content of the active layer MQW in a light-emitting element LE that emits third light (blue wavelength light) can be approximately 10 wt% to 20 wt%.

[0147] The first semiconductor layer SEM1 can be disposed on the active layer MQW. The first semiconductor layer SEM1 can be constructed using GaN doped with a first conductivity type dopant (e.g., a p-type dopant) such as Mg, Zn, Ca, Sr, Ba, etc.

[0148] The first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX. For example, the first semiconductor layer SEM1 can be electrically connected to the pixel electrode PXE of each sub-pixel SPX through the conductive layer E1 and the connection electrode BE.

[0149] The conductive layer E1 can be disposed on the upper surface of the first semiconductor layer SEM1. Figure 7 The illustration shows a scenario where the conductive layer E1 covers the entire lower surface of the first semiconductor layer SEM1, but the embodiments described herein are not limited to this. For example, the conductive layer E1 may be disposed on a portion of the lower surface of the first semiconductor layer SEM1. The conductive layer E1 may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0150] In another embodiment, a third semiconductor layer may be disposed between the second semiconductor layer SEM2 and the first reflective layer RF1. The third semiconductor layer, as a semiconductor material layer with n-type dopant below a predetermined threshold, can be referred to as an undoped semiconductor layer. For example, the third semiconductor layer may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN) with n-type dopant below a predetermined threshold.

[0151] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer used to suppress or prevent excessive electron inflow into the active layer MQW. For example, the electron blocking layer can be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer can be omitted.

[0152] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can serve to alleviate stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be formed using InGaN or GaN. The superlattice layer can also be omitted.

[0153] The light-emitting element structure (LES) may include a light-emitting pillar (LP) and multiple dummy pillars (DP). The dummy pillars (DP) may be arranged around the light-emitting pillar (LP).

[0154] Each of the light-emitting pillar LP and the dummy pillar DP may include a second part of the second semiconductor layer SEM2_2, an active layer MQW, a first semiconductor layer SEM1, and a conductive layer E1.

[0155] Since the dummy pillar DP and the luminous pillar LP are arranged on the same first reflective layer RF1 and second reflective layer RF2, the dummy pillar DP and the luminous pillar LP can be connected to each other.

[0156] The second reflective layer RF2 surrounds the side and top surfaces of the dummy pillar DP. Conversely, the second reflective layer RF2 is not arranged on the side and top surfaces of the luminous pillar LP.

[0157] The second reflective layer RF2 can comprise a metallic material with high light reflectivity. For example, the second reflective layer RF2 can comprise aluminum or silver, or an alloy of aluminum or silver. Furthermore, to function as a distributed Bragg reflector (DBR), the second reflective layer RF2 can comprise a pair of first and second layers with different refractive indices (M is an integer greater than 2). In this case, the M first layers and M second layers can be arranged alternately. Within the same pair, the first layer can be positioned closer to the inner side of the dummy pillar DP than the second layer, and the refractive index of the first layer can be lower than that of the second layer. The difference between the refractive indices of the first and second layers can be greater than 0.55.

[0158] The first and second layers can utilize inorganic materials (e.g., silicon nitride (SiN)). X ), silicon oxynitride (SiON), silicon oxide (SiO) X Titanium oxide (TiO) X ) or aluminum oxide (AlO) X ))form.

[0159] The first protective layer INS1 can be disposed on the front surface of the light-emitting element structure LES. For example, the first protective layer INS1 can be disposed on the upper surface and side surface of the dummy pillar DP and the upper surface and side surface of the light-emitting pillar LP to protect the film of the dummy pillar DP and the light-emitting pillar LP.

[0160] The first protective layer INS1 may include a first opening OP1 on the upper surface of the light-emitting pillar LP that exposes the conductive layer E1. The conductive layer E1 exposed in the first opening OP1 can contact the connection electrode BE (described later) and be connected to the pixel electrode PXE. The first protective layer INS1 may be made of an inorganic material (e.g., silicon nitride (SiN)). X ), silicon oxynitride (SiON), silicon oxide (SiO) X Titanium oxide (TiO) X ) or aluminum oxide (AlO) X The first protective layer INS1 may be formed using a composite film consisting of a zirconium oxide film / alumina film / zirconia film (ZAZ: ZrO2 / Al2O3 / ZrO2). In one embodiment, the first protective layer INS1 may be a composite film consisting of a zirconium oxide film / alumina film / zirconia film (ZAZ: ZrO2 / Al2O3 / ZrO2).

[0161] A planarization layer 190 is arranged on the light-emitting element structure LES. For example, a planarization layer 190 with a predetermined height can be formed on the first protective layer INS1 of the light-emitting element structure LES to planarize the step difference caused by the light-emitting pillar LP and the dummy pillar DP.

[0162] The planarization layer 190 can be formed to cover both the light-emitting pillar LP and the dummy pillar DP. When the planarization layer 190 is formed to cover both the light-emitting pillar LP and the dummy pillar DP, the planarization layer 190 can be formed with an opening in the thickness direction (third direction DR3) that overlaps with the first opening OP1 of the first protective layer INS1 to expose the conductive layer E1.

[0163] The planarization layer 190 can utilize inorganic materials (e.g., silicon nitride (SiN)). X ), silicon oxynitride (SiON), silicon oxide (SiO) X Titanium oxide (TiO) X ) or aluminum oxide (AlO) X The planarization layer 190 can be formed using organic films, but is not limited to this.

[0164] The light-emitting element structure LES may also include a second protective layer INS2 surrounding the upper surface and sides.

[0165] The second protective layer INS2 may surround the upper surface and side surface of the planarization layer 190. The second protective layer INS2 may form an opening in the thickness direction (third direction DR3) that overlaps with the first opening OP1 of the first protective layer INS1 to expose the conductive layer E1.

[0166] The second protective layer INS2 can be made of inorganic materials (e.g., silicon nitride (SiN)). X ), silicon oxynitride (SiON), silicon oxide (SiO) XTitanium oxide (TiO) X ) or aluminum oxide (AlO) X It can be formed, but is not limited to this.

[0167] The connecting electrode BE contacts the conductive layer E1 exposed through the first opening OP1 and extends along the upper surface and side surface of the second protective layer INS2 to contact the pixel electrode PXE. The connecting electrode BE may include one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode BE may also be formed of a transparent conductive material (TCO) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0168] On the second planarized organic film 180, there may also be partition walls BM that divide each sub-pixel SPX1, SPX2, SPX3.

[0169] The separator wall BM can also be called a light-shielding layer because the separator wall BM includes a light-shielding material to prevent the light from the light-emitting element LE of one sub-pixel from traveling to its adjacent sub-pixels.

[0170] The partition wall BM can be formed into a grid pattern throughout the entire display area DA. The partition wall BM can be positioned on the third-direction DR3 without overlapping with multiple light-emitting element structures (LES). The partition wall BM provides space for forming the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. The partition wall BM can be formed using organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0171] In one embodiment, the partition wall BM is formed as a single layer, but is not limited thereto. For example, the partition wall BM can be formed as a double layer. The partition wall BM can be formed as a double layer to ensure sufficient space for forming the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0172] The separator wall (BM) can include the light-blocking material described above. For example, the separator wall (BM) can include inorganic black pigments such as carbon black or organic black pigments.

[0173] A third reflective layer RF3 may be disposed within the space formed by the partition wall BM. The third reflective layer RF3 may be disposed on the side of the partition wall BM. The third reflective layer RF3 may include a metallic material with high light reflectivity. For example, the third reflective layer RF3 may include aluminum or silver, or an alloy of aluminum or silver.

[0174] In the first sub-pixel SPX1, a first light conversion layer QDL1 may be arranged between the partition walls BM and BM; in the second sub-pixel SPX2, a second light conversion layer QDL2 may be arranged between the partition walls BM and BM; and in the third sub-pixel SPX3, a light transmission layer TPL may be arranged between the partition walls BM and BM.

[0175] The first light conversion layer QDL1 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting column LP into first light (light in the red wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic material. The first wavelength conversion particles WCP1 can convert a portion of the third light (light in the blue wavelength band) incident from the light-emitting column LP into first light (light in the red wavelength band).

[0176] The second light conversion layer QDL2 can convert a portion of the third light (light in the blue wavelength band) incident from the luminescent column LP into a second light (light in the green wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic material. The second wavelength conversion particles WCP2 can convert a portion of the third light (light in the blue wavelength band) incident from the luminescent column LP into the second light (light in the green wavelength band).

[0177] The light-transmitting layer (TPL) may include light-transmitting organic materials.

[0178] For example, the first base resin BRS1, the second base resin BRS2, ​​and the light-transmitting layer TPL may include epoxy resins, acrylic resins, Cardo resins, or imide resins, etc. The first wavelength conversion particle WCP1 and the second wavelength conversion particle WCP2 may be quantum dots (QD), quantum rods, fluorescent materials, or phosphorescent materials.

[0179] The first cover layer CAP1 can be arranged on the partition wall BM, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0180] The first capping layer CAP1 can be made of inorganic materials (e.g., silicon nitride (SiN)). X), silicon oxynitride (SiON), silicon oxide (SiO) X Titanium oxide (TiO) X ) or aluminum oxide (AlO) X The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL can be encapsulated by the capping layer CAP.

[0181] A fourth organic membrane 213 may be disposed on the first cover layer CAP1. A plurality of color filters CF1, CF2, and CF3 may be disposed on the fourth organic membrane 213. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0182] A first color filter CF1 disposed on the first sub-pixel SPX1 allows the first light (light in the red wavelength band) to pass through, and can absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter CF1 allows the first light (light in the red wavelength band) emitted from the third light (light in the blue wavelength band) emitted by the light-emitting element LE to pass through, after being converted by the first light conversion layer QDL1, and can absorb or block the third light (light in the blue wavelength band) that has not been converted by the first light conversion layer QDL1. Therefore, the first sub-pixel SPX1 can emit the first light (light in the red wavelength band).

[0183] The second color filter CF2, arranged in the second sub-pixel SPX2, allows the second light (light in the green wavelength band) to pass through, and can absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter CF2 allows the second light (light in the green wavelength band) emitted from the third light (light in the blue wavelength band) emitted by the light-emitting element LE to pass through, after being converted by the second light conversion layer QDL2, and can absorb or block the third light (light in the blue wavelength band) that has not been converted by the second light conversion layer QDL2. Thus, the second sub-pixel SPX2 can emit the second light (light in the green wavelength band).

[0184] The third color filter CF3, arranged in the third sub-pixel SPX3, allows the transmission of third light (light in the blue wavelength band). Therefore, the third color filter CF3 allows the transmission of third light (light in the blue wavelength band) emitted from the light-emitting element LE through the light transmission layer TPL. Thus, the third sub-pixel SPX3 can emit third light (light in the blue wavelength band).

[0185] The first color filter CF1, the second color filter CF2, and the third color filter CF3, which overlap on the third-direction DR3, can overlap with the partition wall BM on the third-direction DR3.

[0186] A fifth organic membrane 214 for planarization can be arranged on multiple color filters CF1, CF2, CF3.

[0187] The fourth organic membrane 213 and the fifth organic membrane 214 can be formed using acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0188] Figure 8 This is a schematic diagram illustrating a light-emitting element structure according to one embodiment. Figure 8 The light-emitting element structure is in Figure 6 and Figure 7 The light-emitting element structure described in the embodiments will not be repeated hereafter.

[0189] Reference Figure 8 The light-emitting element structure LES includes light-emitting pillars LP and multiple dummy pillars DP.

[0190] The light-emitting pillar LP may include a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a conductive layer E1, a second reflective layer RF2, and a first protective layer INS1. The light-emitting pillar LP may include relatively vertical sides. The width of the upper surface of the light-emitting pillar LP may be substantially the same as the width of the lower surface. For example, the light-emitting pillar LP may have a substantially rectangular or square cross-sectional shape. The light-emitting pillar LP has a first tilt angle θ1. The first tilt angle θ1 is the angle between the lower surface of the light-emitting pillar LP and the side surface of the light-emitting pillar LP.

[0191] The dummy pillar DP may include a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a conductive layer E1, a second reflective layer RF2, and a first protective layer INS1. The dummy pillar DP is a conical shape and may have a shape where the width gradually decreases towards the top. In the dummy pillar DP, the width of the active layer MQW is greater than the width of the first semiconductor layer SEM1. The width of the conductive layer E1 of the dummy pillar DP may be the same as the width of the conductive layer E1 of the light-emitting pillar LP. The width of the active layer MQW of the dummy pillar DP may be greater than the width of the active layer MQW of the light-emitting pillar LP. The dummy pillar DP has a second tilt angle θ2. The second tilt angle θ2 may be an angle different from the first tilt angle θ1. The second tilt angle θ2 may be smaller than the first tilt angle θ1. The second tilt angle θ2 is the angle between the lower surface of the dummy pillar DP and the side surface of the dummy pillar DP.

[0192] The second reflective layer RF2 covers the upper surface of the light-emitting element structure LES. The second reflective layer RF2 has a second opening OP2 that exposes the light-emitting pillar LP. For example, the second reflective layer RF2 surrounds the upper surface and side surface of the dummy pillar DP, and the second reflective layer RF2 is not arranged on the upper surface and side surface of the light-emitting pillar LP. The second reflective layer RF2 can also be arranged on the second semiconductor layer SEM2 between the dummy pillar DP and the light-emitting pillar LP.

[0193] In a light-emitting element structure LES according to one embodiment, the light-emitting pillar LP is surrounded by a dummy pillar DP. Therefore, even if a separate reflective layer is not arranged on the side of the light-emitting pillar LP, light emitted from the active layer MQW to the side can be reflected toward the front surface by the second reflective layer RF2 surrounding the dummy pillar DP.

[0194] Therefore, light emitted laterally from the active layer MQW can be separated by the partition wall BM ( Figure 7 Minimize the situation where absorption and disappearance occur.

[0195] Figure 9 This is a layout diagram showing the pixels of a display area according to another embodiment.

[0196] The light-emitting element structure LES and the pixel electrode PXE3 are arranged outside the light-emitting area EA3 of each third sub-pixel SPX3. Figure 5 Different. Figure 9 In the following text, the explanations and references will not be repeated. Figure 5 The described embodiments are repeated, and the main description is consistent with... Figure 5 Differences in the implementation examples.

[0197] Reference Figure 9 Multiple light-emitting element structures (LES) can be arranged on the common electrode CE1, CE2, and CE3 respectively.

[0198] A portion of the multiple light-emitting element structures (LES) and the pixel electrode (PXE3) can be arranged outside the light-emitting region (EA3). For example, the dummy pillar DP of the LES can overlap with the outer side of the light-emitting region (EA3). Conversely, the light-emitting pillar LP must be arranged within the light-emitting region (EA3).

[0199] Figure 10 It is shown Figure 9 A cross-sectional view of a portion of the display panel in the third luminescent region.

[0200] The light-emitting element structure LES and the pixel electrode PXE3 are arranged outside the light-emitting area EA3 of each third sub-pixel SPX3. Figure 8 Different. Figures 6 to 8 In the following text, the explanations and references will not be repeated. Figure 5The described embodiments are repeated, and the main description is consistent with... Figure 11 Differences in the implementation examples.

[0201] Pixel electrodes PXE3 and common electrodes CE3 can be arranged on the second planarized organic film 180, spaced apart from each other.

[0202] The light-emitting element structure LES is arranged on the common electrode CE3, rather than on the pixel electrode PXE3.

[0203] The pixel electrode PXE3 can overlap with the separator walls BM1 and BM2 in the thickness direction DR3.

[0204] Furthermore, a portion of the light-emitting element structure LES can overlap with the partition walls BM1 and BM2 in the thickness direction DR3. For example, a portion of the dummy pillar DP can overlap with the partition walls BM1 and BM2.

[0205] The partition wall may include a first partition wall BM1 and a second partition wall BM2 disposed on the first partition wall BM1. The first partition wall BM1 and the second partition wall BM2 do not overlap with the light-emitting column LP on the third direction DR3.

[0206] The second partition wall BM2 can provide space for forming the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0207] A third reflective layer RF3 may be arranged inside the space formed by the second partition wall BM2. The third reflective layer RF3 may be arranged on the side of the second partition wall BM2.

[0208] The first partition wall BM1 and the second partition wall BM2 may include a light-shielding material to prevent light from the emission pillar LP of one sub-pixel from traveling to its adjacent sub-pixels. For example, the light-shielding material may include inorganic black pigments such as carbon black or organic black pigments.

[0209] The first covering layer CAP1 can be arranged on the second partition wall BM2.

[0210] Figures 12 to 22 This is a flowchart illustrating a method for manufacturing a display device according to an embodiment. Figures 12 to 22 This is a diagram illustrating a method for manufacturing a display device according to an embodiment. Figure 7 Is with Figures 12 to 18 The figure corresponds to one embodiment. Figure 11 The formation of a light-emitting element structure according to one embodiment is highlighted.

[0211] The following will combine Figures 12 to 22 right Figure 12The manufacturing method of the display device shown will be explained.

[0212] First, such as Figure 11 As shown, a second semiconductor material layer SEML2, an active material layer MQWL, a first semiconductor material layer SEML1, and a conductive material layer CML are formed on a semiconductor substrate SSUB. Figure 13 (S110).

[0213] The semiconductor substrate SSUB can be a silicon wafer substrate or a sapphire substrate. A first reflective layer RF1 can be disposed on one surface of the semiconductor substrate SSUB. The first reflective layer RF1 can be disposed on the semiconductor substrate SSUB through an adhesive layer AL.

[0214] The first reflective layer RF1 may include a metallic material with high light reflectivity. For example, the first reflective layer RF1 may include aluminum or silver, or an alloy of aluminum or silver.

[0215] Then, a second semiconductor material layer SEML2 is formed on the first reflective layer RF1. The second semiconductor material layer SEML2 may be a semiconductor material layer doped with a second conductivity type dopant such as silicon (Si), germanium (Ge) or tin (Sn).

[0216] Then, an active material layer MQWL is formed on the second semiconductor material layer SEML2, and a first semiconductor material layer SEML1 is formed on the active material layer MQWL. The active material layer MQWL may include the same semiconductor material layer as the first semiconductor material layer SEML1 and the second semiconductor material layer SEML2. For example, if the first semiconductor material layer SEML1 and the second semiconductor material layer SEML2 include gallium nitride (GaN), the active material layer MQWL may also include gallium nitride (GaN). For example, the active material layer MQWL may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The first semiconductor material layer SEML1 may be a semiconductor material layer doped with a first conductivity type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), or barium (Ba).

[0217] The second semiconductor material layer SEML2, the active material layer MQWL, and the first semiconductor material layer SEML1 can be formed on a semiconductor substrate SSUB using an epitaxial growth process. As an epitaxial growth process, methods for forming the second semiconductor material layer SEML2, the active material layer MQWL, and the first semiconductor material layer SEML1 can utilize electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, and metal-organic chemical vapor deposition (MOCVD), etc. Preferably, metal-organic chemical vapor deposition (MOCVD) can be used, but the embodiments in this specification are not limited to this.

[0218] Then, a conductive material layer CML is formed on the first semiconductor material layer SEML1. The conductive material layer CML can be formed using one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0219] Second, such as Figure 11 As shown, multiple pillar PS are formed by performing a first etching on the second semiconductor material layer SEML2, the active material layer MQWL, the first semiconductor material layer SEML1, and the conductive material layer CML. Figure 11 (S120).

[0220] For example, after forming a mask pattern on the conductive material layer CML, a first etching and patterning is performed on the second semiconductor material layer SEML2, the active material layer MQWL, the first semiconductor material layer SEML1, and the conductive material layer CML according to the mask pattern. The first etching can be dry etching. Multiple pillars PS with a second tilt angle θ2 are formed by the dry etching process. When using the dry etching process, the etching gas can be chlorine (Cl2) or oxygen (O2), but is not limited to these.

[0221] The smaller the second tilt angle θ2 of the dummy column DP, the wider the viewing angle; and the larger the second tilt angle θ2, the higher the light output efficiency.

[0222] Since the second tilt angle θ2 can be controlled by adjusting the process conditions of the first etching process, the second tilt angle θ2 can be determined based on the viewing angle or the light extraction efficiency.

[0223] Patterning can be performed up to at least a portion of the second semiconductor layer SEM2. The first thickness t1 of the unpatterned second semiconductor layer SEM2 can be approximately 400 nm to approximately 900 nm. The second thickness t2 of the patterned semiconductor layers SEM2, MQW, and SEM1 can be approximately 600 nm.

[0224] The mask pattern can be removed after multiple pillar PSs are formed.

[0225] Third, a second reflective layer RF2 is formed, and a second etching process is performed. Figure 14 (S130).

[0226] Reference Figure 15 A reflective material layer RFL is formed on the front surface of a semiconductor substrate SSUB. The reflective material layer RFL can be deposited by processes such as filling, but is not limited to these.

[0227] Then, refer to Figure 16 An opening OP is formed by removing the reflective material layer RFL from a portion of the pillar PS. The portion of the PS with the reflective material layer RFL removed can become a light-emitting pillar LP, and the PS with the second reflective layer RF2 retained can become a dummy pillar DP.

[0228] Reference Figure 16 The light-emitting pillar LP is then subjected to a second etching to form an inclined surface with a first tilt angle θ1. This second etching can be a wet etching process. The light-emitting pillar LP with the first tilt angle θ1 is formed by a wet etching process. When using a wet etching process, tetramethylammonium hydroxide (TMAH) can be used as the etching solution, but it is not limited to this.

[0229] The second reflective layer RF2 can act as a mask. Therefore, as Figure 11 As shown, the dummy pillar DP surrounded by the second reflective layer RF2 may not be etched, while only the emitting pillar LP may be etched. Therefore, the tilt angles of the tilted surfaces of the dummy pillar DP and the emitting pillar LP may be different from each other. For example, the dummy pillar DP may have a second tilt angle θ2, and the tilted surface of the emitting pillar LP may have a first tilt angle θ1.

[0230] Fourth, a first protective layer INS1 with a first opening OP1 and a planarization layer 190 are formed. Figure 17 (S140).

[0231] like Figure 18As shown, the first protective layer INS1 is formed to cover the dummy pillar DP and the light-emitting pillar LP, which are covered by the second reflective layer RF2.

[0232] For example, the first protective layer INS1 can be deposited entirely on one surface of the semiconductor substrate SSUB. The first protective layer INS1 can be formed to cover one surface and side surfaces of the dummy pillar DP and the light-emitting pillar LP. The first protective layer INS1 can be formed on one surface of the semiconductor substrate SSUB exposed between the dummy pillar DP and the light-emitting pillar LP.

[0233] Subsequently, an insulating material layer is formed on one surface of the semiconductor substrate SSUB to planarize it.

[0234] The insulating layer can be formed to completely cover each dummy pillar DP and luminous pillar LP. The insulating layer becomes the planarization layer 190.

[0235] Next, as Figure 11 As shown, the first opening OP1 can be formed by removing the first protective layer INS1 and the planarization layer 190 from the upper surface of the light-emitting column LP. At least a portion of the conductive layer E1 can be exposed through the first opening OP1.

[0236] Fifth, the light-emitting element structure (LES) formed by the processes described in steps S110 to S140 is arranged on the circuit board. Figure 6 (S150).

[0237] The light-emitting element structure LES formed through the above steps S110 to S140 is separated from the semiconductor substrate SSUB.

[0238] Circuit board as reference Figure 19 The circuit substrate described herein can have a thin-film transistor layer (TFTL) and a circuit electrode layer formed on the substrate SUB.

[0239] For example, such as Figure 20 As shown, at least one surface of the first reflective layer RF1 of the light-emitting element structure LES is disposed on the common electrode CE.

[0240] Sixth, a second protective layer INS2 and a connecting electrode BE are formed.

[0241] like Figure 21 As shown, after forming a protective material layer covering the front surface of the circuit board, a portion of it is etched using a photolithography process to form a second protective layer INS2.

[0242] Photolithography is a process in which a photoresist is coated onto a substrate, and light is passed through a mask with a desired pattern to form a desired structure. For example, the photoresist can be formed to surround the light-emitting element structure LES. Therefore, the second protective layer INS2 can be formed to cover both the upper surface and the sides of the light-emitting element structure LES, but should not cover the pixel electrode PXE. Furthermore, by additional etching, an opening is formed in the area of ​​the second protective layer INS2 that overlaps with the first opening OP1 of the light-emitting pillar LP, so that the conductive layer E1 of the light-emitting pillar LP is exposed.

[0243] Then, as Figure 11 As shown, a connection electrode BE can be formed that connects the conductive layer E1 exposed through the first opening OP1 of the light-emitting pillar LP to the pixel electrode PXE.

[0244] For example, to form the connection electrode BE, a conductive material layer can be deposited on the entire circuit substrate, and the connection electrode BE can be formed by partially etching the conductive material layer deposited in unwanted areas. The connection electrode BE can extend along the second protective layer INS2 on the conductive layer E1 of the light-emitting pillar LP, and can be disposed on the upper surface of the pixel electrode PXE.

[0245] Sixth, the separator BM, the third reflective layer RF3, the wavelength conversion layer QDL, and the first cover layer CAP1 can be formed sequentially. Figure 22 (S160).

[0246] Reference Figure 18 A separator wall BM is formed on the second planarized organic film 180. For example, the separator wall BM is formed on the second planarized organic film 180 using a negative photoresist. The portion of the negative photoresist that does not receive light is dissolved, so the separator wall BM can be formed into an inverted cone shape that tends to narrow downwards.

[0247] A reflective material layer is deposited on the front surface of a circuit board with a partition wall BM. Then, a portion of the reflective material layer is partially etched to form a third reflective layer RF3 on the side of the partition wall BM.

[0248] Partial Etching Methods and References Figure 19 and Figures 23 to 26 The descriptions are similar, so detailed explanations are omitted.

[0249] A first light conversion layer QDL1 is formed in each of the first sub-pixels SPX1, a second light conversion layer QDL2 is formed in each of the second sub-pixels SPX2, and a light transmission layer TPL is formed in each of the third sub-pixels SPX3. Then, a first cover layer CAP1 is formed covering the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0250] Subsequently, a color filter layer can be formed as needed.

[0251] Figures 23 to 26 This is a plan view used to illustrate the positions of the dummy pillars and light-emitting pillars in a sub-pixel according to an embodiment.

[0252] Reference Figure 23 The dummy pillars DP can be arranged around the light-emitting pillar LP. For example, when the sub-pixel SPX is quadrilateral, a light-emitting pillar LP can be arranged in the center, and four dummy pillars DP can be arranged at the corners of the quadrilateral shape.

[0253] Reference Figures 24 to 26 The dummy pillar DP and the luminous pillar LP can have the same shape on the plane. For example, the dummy pillar DP and the luminous pillar LP can be circular on the plane, but are not limited to this.

[0254] Reference Figure 24 The dummy column DP can be different from the luminous column LP on the plane.

[0255] For example, such as Figure 25 As shown, the light-emitting pillar LP located at the center of the sub-pixel SPX can be circular on the plane, and the dummy pillars DP located at each corner can be quadrilaterals. Or, as... Figure 26 As shown, the light-emitting pillar LP arranged at the center of the sub-pixel SPX can be circular in the plane, and the dummy pillars DP arranged at each corner can be triangular. As another example, such as... Figure 27 As shown, the light-emitting pillar LP arranged at the center of the sub-pixel SPX can be hexagonal in the plane, and the dummy pillars DP arranged at each corner can be triangles. When the dummy pillar DP is a triangle, the hypotenuse L of the triangle can face the light-emitting pillar LP.

[0256] Figure 28 and Figure 27 This is a plan view used to illustrate the positions of the dummy pillars and light-emitting pillars in a sub-pixel according to another embodiment.

[0257] Reference Figure 28A grid can have four sub-pixels, and a light-emitting pillar LP can be placed at the center of each sub-pixel. The light-emitting pillar LP and the dummy pillar DP can have the same shape on the plane, but are not limited to this, and can have different shapes from each other. The dummy pillar DP can have a larger area than the light-emitting pillar LP.

[0258] A dummy pillar DP can be arranged to overlap multiple sub-pixels at the location where the vertices of adjacent sub-pixels converge. For example, a first dummy pillar DP1 can be arranged at each vertex of the first sub-pixel SPX_1, the second sub-pixel SPX_2, the third sub-pixel SPX_3, and the fourth sub-pixel SPX_4.

[0259] In this configuration, the light-emitting pillar LP is positioned in the center of the sub-pixel SPX, and multiple dummy pillars DP surround the light-emitting pillar LP.

[0260] Reference Figure 27 The dummy pillar DP can be arranged to continuously surround the luminous pillar LP.

[0261] like Figure 28 and Figure 6 As shown, in some embodiments, the dummy pillar DP can be arranged outside the sub-pixel SPX. In this case, at least a portion of the dummy pillar DP can be connected to the partition wall BM of the sub-pixel SPX. Figure 7 and Figure 29 )overlapping.

[0262] Figure 29 This is an example diagram illustrating a smartwatch including a display device according to an embodiment.

[0263] Reference Figure 30 According to one embodiment, the display device 10_1 can be applied to a smartwatch 1000_1, which is one of the smart devices.

[0264] Figure 31 and Figure 30 This is an example diagram illustrating a virtual reality device including a display device according to an embodiment.

[0265] Reference Figure 31 and Figure 1 According to one embodiment, the head-mounted display device 1000_2 includes a first display device 10_2, a second display device 10_3, a display device storage part 1100, a storage part cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0266] The first display device 10_2 provides an image to the user's left eye, and the second display device 10_3 provides an image to the user's right eye. The first display device 10_2 and the second display device 10_3 are respectively connected to... Figure 2 and Figure 30 The display devices 10 described are substantially the same, therefore the description of the first display device 10_2 and the second display device 10_3 is omitted.

[0267] The first optical component 1510 may be disposed between the first display device 10_2 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_3 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0268] The intermediate frame 1400 can be arranged between the first display device 10_2 and the control circuit board 1600, and can also be arranged between the second display device 10_3 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display device 10_2, the second display device 10_3, and the control circuit board 1600.

[0269] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_2 and the second display device 10_3 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_2 and the second display device 10_3 via connectors.

[0270] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_2, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_3. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_2 and the second display device 10_3.

[0271] The display device housing 1100 serves to house the first display device 10_2, the second display device 10_3, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 31 and Figure 32The illustration shows a case where the first eyepiece 1210 and the second eyepiece 1220 are arranged separately, but the embodiments in this specification are not limited to this. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one.

[0272] The first eyepiece 1210 can be aligned with the first display device 10_2 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_3 and the second optical component 1520. Therefore, the user can see the image of the first display device 10_2 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can see the image of the second display device 10_3 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0273] The headband 1300 serves to secure the display device storage unit 1100 to the user's head, ensuring that the first eyepiece 1210 and the second eyepiece 1220 of the storage unit cover 1200 are positioned respectively in the user's left and right eyes. When the display device storage unit 1100 is made lightweight and compact, the head-mounted display device 1000_2 can be equipped with, for example... Figure 32 The eyeglass frame shown is used to replace the headband 1300.

[0274] In addition, the head-mounted display device 1000_2 may also be equipped with a battery for power supply, an external memory slot for storing external memory, an external connection port for receiving image sources, and a wireless communication module. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0275] Figure 32 This is an example diagram illustrating a virtual reality device including a display device according to yet another embodiment. Figure 32 The image shows a virtual reality device 1000_3 using a display device 10_4 according to an embodiment.

[0276] Reference Figure 32 According to one embodiment, the virtual reality device 1000_3 can be a glasses-shaped device. According to one embodiment, the virtual reality device 1000_3 may include a display device 10_4, a left eye lens 10a, a right eye lens 10b, a support frame 20, eyeglass temples 30a and 30b, a reflective component 40, and a display device storage unit 50.

[0277] Figure 32 The example illustrates a virtual reality device 1000_3 as an eyeglass-type display device including temples 30a and 30b. That is, the virtual reality device 1000_3 according to one embodiment is not limited to... Figure 32 In addition to the examples shown, it can be applied to various electronic devices in various forms.

[0278] The display device housing 50 may include a display device 10_4 and a reflective component 40. The image displayed on the display device 10_4 can be reflected by the reflective component 40 and provided to the user's right eye through the right eye lens 10b. Therefore, the user can view the virtual reality image displayed on the display device 10_4 through their right eye.

[0279] Figure 33 The illustration shows the display device housing 50 located at the right end of the support frame 20, but the embodiments described herein are not limited to this. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, the image displayed on the display device 10_4 can be reflected from the reflective member 40 and provided to the user's left eye through the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10_4 through their left eye. Alternatively, the display device housing 50 may be located at both the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10_4 through both their left and right eyes.

[0280] Figure 33 This is an example diagram illustrating a car dashboard and a central dashboard including a display device according to an embodiment. Figure 33 The image shows a car using display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to one embodiment.

[0281] Reference Figure 34 According to one embodiment, display devices 10_a, 10_b, and 10_c can be applied to a car's dashboard, or to a car's center fascia, or to a center information display (CID) arranged on the car's dashboard. Furthermore, according to one embodiment, display devices 10_d and 10_e can be applied to interior mirror displays that replace the side mirrors of a car.

[0282] Figure 34 This is an example diagram illustrating a transparent display device including a display apparatus according to an embodiment.

[0283] Reference ​According to one embodiment, the display device 10_5 can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM. Therefore, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10_5, but also view objects RS or the background located behind the transparent display device. When the display device 10_5 is applied to a transparent display device, the substrate of the display device 10_5 may include a transmissive portion capable of transmitting light, or it may be formed using a light-transmitting material.

[0284] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that the invention can be implemented in other specific forms without changing the technical concept or essential features of the invention. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive.

Claims

1. A display device, comprising: substrate; Pixel electrodes and common electrodes are arranged on the substrate and spaced apart from each other on the substrate; A light-emitting element structure is arranged on the common electrode and includes a light-emitting pillar and a plurality of dummy pillars surrounding the light-emitting pillar; as well as Connect the electrode to the light-emitting column and the pixel electrode. The light-emitting element structure further includes: A reflective layer surrounding the upper surface and sides of the dummy pillar; and The first protective layer surrounds the upper surface and side surface of the dummy pillar and the upper surface and side surface of the luminous pillar.

2. The display device according to claim 1, wherein, The light-emitting column has a first tilt angle formed by the lower surface and the side surface of the light-emitting column. The dummy column has a second tilt angle formed by the lower surface and the side surface of the dummy column, and the second tilt angle is different from the first tilt angle.

3. The display device according to claim 2, wherein, The second tilt angle is smaller than the first tilt angle.

4. The display device according to claim 1, wherein, The dummy pillar tends to narrow in width at the upper part of the substrate. The upper and lower parts of the luminous column have the same width.

5. The display device according to claim 1, wherein, The light-emitting element structure also includes: The component reflective layer is located on the lower surface; Multiple semiconductor layers are arranged on the reflective layer of the element; and A conductive layer is disposed on the plurality of semiconductor layers.

6. The display device according to claim 5, wherein, The plurality of semiconductor layers include: The second semiconductor layer includes a first portion having a first height and a second portion having a second height on the first portion; An active layer is disposed on the second semiconductor layer; and A first semiconductor layer is disposed on the active layer.

7. The display device according to claim 6, wherein, Each of the dummy pillar and the light-emitting pillar includes a second semiconductor layer containing the second portion, the active layer, the first semiconductor layer, and the conductive layer.

8. The display device according to claim 7, wherein, The first protective layer includes an opening that exposes a portion of the conductive layer of the light-emitting column, through which the connecting electrode is connected to the conductive layer.

9. The display device according to claim 7, wherein, The reflective layer comprises a metal and a first and a second layer having M pairs of different refractive indices, where M is an integer greater than 2.

10. The display device according to claim 1, further comprising: A planarization layer is disposed on the light-emitting element structure; as well as The second protective layer is disposed on the upper surface of the planarization layer and the side of the light-emitting element structure, and has an opening that overlaps with the opening of the first protective layer.

11. The display device according to claim 1, further comprising: Partition walls are arranged to surround the light-emitting element structure; A third reflective layer is disposed on the side of the partition wall; as well as A wavelength conversion layer is arranged in the space formed by the partition wall.

12. The display device according to claim 11, wherein, The light-emitting element structure does not overlap with the partition wall.

13. The display device according to claim 11, wherein, The light-emitting element structure does not overlap with the light-emitting pillar, but overlaps with a portion of the dummy pillar.

14. The display device according to claim 1, wherein, The illusory pillar is circular or polygonal in the plane. The luminous pillars are circular or polygonal in planar shape.

15. The display device according to claim 14, wherein, The dummy column has the same shape as the luminous column on the plane.

16. The display device according to claim 14, wherein, The dummy column has a different shape on the plane than the luminous column.

17. A method for manufacturing a display device, comprising the following steps: A second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer are formed on a semiconductor substrate; A first etching is performed on the second semiconductor material layer, the active material layer, the first semiconductor material layer, and the conductive material layer to form a plurality of pillars, each comprising a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer. A reflective layer with an opening is formed in a portion of the plurality of pillars, and a second etching is performed on the pillars where the reflective layer is not disposed; and On the pillar where the reflective layer is not disposed, a first protective layer having an opening is formed on the front surface of the semiconductor substrate.

18. The method for manufacturing a display device according to claim 17, wherein, The first etching is a dry etching, and the second etching is a wet etching.

19. The method for manufacturing a display device according to claim 17, wherein, In the step of forming a reflective layer with an opening in a portion of the plurality of pillars, and performing a second etching on the pillars where the reflective layer is not disposed, Of the plurality of pillars, those pillars with the reflective layer surrounding their upper and side surfaces are considered dummy pillars, while those pillars without the reflective layer on their upper and side surfaces due to the opening are considered light-emitting pillars. By means of the second etching, the light-emitting pillar has a different inclined surface than the dummy pillar.

20. The method for manufacturing a display device according to claim 19, further comprising the following steps: The light-emitting element structure, including the light-emitting pillar and the dummy pillar, is separated from the semiconductor substrate and transferred to a circuit substrate including the pixel electrode and the common electrode; and A connecting electrode is formed to connect the pixel electrode and the light-emitting column.

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