Josephson junction preparation method and device and electronic equipment
By detecting and etching the initial Josephson junctions on the quantum chip, the area uniformity of all Josephson junctions is ensured, thus solving the problem of uneven Josephson junction area on the quantum chip and improving the uniformity of quantum bit frequency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2026-04-07
AI Technical Summary
The Josephson junction area varies at different locations on a quantum chip, resulting in non-uniform qubit frequencies.
By detecting the area information of each initial Josephson junction, the initial Josephson junction with the smallest area is determined as the target Josephson junction. Based on the area information of the target Josephson junction, the non-target Josephson junctions are etched to make their area equal to that of the target Josephson junction.
This improves the uniformity of the Josephson junction area on the quantum chip, thereby enhancing the uniformity of the qubit frequency.
Smart Images
Figure CN121815952A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of chip fabrication technology, and in particular to a method, apparatus and electronic device for fabricating Josephson junctions. Background Technology
[0002] A quantum chip is the core component of a quantum computer. It consists of qubits arranged in an array, and each qubit includes a bit capacitor and a Josephson junction coupled to the bit capacitor.
[0003] The frequency of a qubit is determined by both the bit capacitance and the superconducting critical current of the Josephson junction. The size of the bit capacitance is determined by the geometric pattern defined by ultraviolet lithography, and the manufacturing process is highly controllable. The superconducting critical current of the Josephson junction is affected by the junction area. However, when fabricating Josephson junctions using oblique evaporation, the phenomenon of differences in the junction area of Josephson junctions at different locations on the quantum chip is often encountered, leading to non-uniform qubit frequencies.
[0004] Therefore, improving the uniformity of the Josephson junction area on a quantum chip is an urgent problem to be solved when fabricating Josephson junctions. Summary of the Invention
[0005] The purpose of this invention is to provide a method, apparatus, and electronic device for preparing Josephson junctions to overcome the shortcomings of the prior art, which can improve the uniformity of the Josephson junction area in quantum chips.
[0006] The solution presented in this application is implemented through the following steps.
[0007] In a first aspect, examples of this application present a method for preparing a Josephson junction, the method comprising:
[0008] Multiple initial Josephson junctions are formed on the substrate;
[0009] Obtain the area information of each initial Josephson knot, and designate the initial Josephson knot whose area information satisfies the preset area condition as the target Josephson knot, and designate the initial Josephson knots other than the target Josephson knots as non-target Josephson knots.
[0010] Based on the area information of the target Josephson junction, the non-target Josephson junction is etched so that the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
[0011] According to some examples of this application, forming a plurality of initial Josephson junctions on the substrate includes:
[0012] A first photoresist layer is formed by coating a photoresist layer onto the surface of the substrate.
[0013] The first photoresist layer is exposed and developed to form the plurality of first vias;
[0014] Using an oblique evaporation process, a first superconducting layer, a barrier layer, and a second superconducting layer are stacked in each of the first through-holes to form the initial Josephson junction.
[0015] According to some examples of this application, each of the first vias is the same size, and the first vias are distributed in an array on the first photoresist layer.
[0016] According to some examples of this application, the shape of the first through hole includes a straight line or a cross shape.
[0017] According to some examples of this application, obtaining the area information of each initial Josephson knot and selecting the initial Josephson knot whose area information satisfies a preset area condition as the target Josephson knot includes:
[0018] Each initial Josephson node is detected one by one to obtain the area information corresponding to each initial Josephson node, and the area information includes the area value;
[0019] The area values of each initial Josephson knot are compared, and the initial Josephson knot with the smallest area value is taken as the target Josephson knot.
[0020] According to some examples of this application, the step of detecting each initial Josephson knot one by one to obtain the area information corresponding to each initial Josephson knot includes:
[0021] The initial Josephson junction was image-detected using a microscope to obtain initial image information;
[0022] The area information is determined based on the initial image information.
[0023] According to some examples of this application, the area information includes length, width, and area value, and the etching of the non-target Josephson junction based on the area information of the target Josephson junction includes:
[0024] Based on the area value of the target Josephson junction and the length and width of the non-target Josephson junction, the etching size corresponding to each non-target Josephson junction is determined;
[0025] The area of the non-target Josephson junction is etched according to the etch dimensions.
[0026] According to some examples of this application, etching the area of the non-target Josephson junction according to the etching size includes:
[0027] A second photoresist layer is formed by coating a photoresist layer onto the surface of the substrate.
[0028] The second photoresist layer is exposed and developed according to the etching size to form a second via corresponding to the etching size;
[0029] The non-target Josephson junction is etched using a dry etching process, and the area of the non-target Josephson junction remaining after etching is equal to the area of the target Josephson junction.
[0030] Secondly, examples of this application provide an apparatus for preparing a Josephson junction, the apparatus comprising:
[0031] An initial module for forming multiple initial Josephson junctions on a substrate;
[0032] The acquisition module is used to acquire the area information of each initial Josephson knot, and to designate the initial Josephson knot whose area information meets the preset area conditions as the target Josephson knot, and to designate the initial Josephson knots other than the target Josephson knots as non-target Josephson knots.
[0033] An etching module is used to etch the non-target Josephson junction based on the area information of the target Josephson junction until the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
[0034] According to some examples of this application, the initial module is specifically used for:
[0035] A first photoresist layer is formed by coating a photoresist layer onto the surface of the substrate.
[0036] The first photoresist layer is exposed and developed to form the plurality of first vias;
[0037] Using an oblique evaporation process, a first superconducting layer, a barrier layer, and a second superconducting layer are stacked in each of the first through-holes to form the initial Josephson junction.
[0038] According to some examples of this application, each of the first vias is the same size, and the first vias are distributed in an array on the first photoresist layer.
[0039] According to some examples of this application, the shape of the first through hole includes a straight line or a cross shape.
[0040] According to some examples in this application, the acquisition module is specifically used for:
[0041] Each initial Josephson node is detected one by one to obtain the area information corresponding to each initial Josephson node, and the area information includes the area value;
[0042] The area values of each initial Josephson knot are compared, and the initial Josephson knot with the smallest area value is taken as the target Josephson knot.
[0043] According to some examples in this application, the acquisition module is specifically used for:
[0044] The initial Josephson junction was image-detected using a microscope to obtain initial image information;
[0045] The area information is determined based on the initial image information.
[0046] According to some examples of this application, the area information includes length, width, and area value, and the etching module is specifically used for:
[0047] Based on the area value of the target Josephson junction and the length and width of the non-target Josephson junction, the etching size corresponding to each non-target Josephson junction is determined;
[0048] The area of the non-target Josephson junction is etched according to the etch dimensions.
[0049] According to some examples of this application, the etching module is specifically used for:
[0050] A second photoresist layer is formed by coating a photoresist layer onto the surface of the substrate.
[0051] The second photoresist layer is exposed and developed according to the etching size to form a second via corresponding to the etching size;
[0052] The non-target Josephson junction is etched using a dry etching process, and the area of the non-target Josephson junction remaining after etching is equal to the area of the target Josephson junction.
[0053] Thirdly, examples of this application provide an electronic device, including: a processor;
[0054] Memory used to store processor-executable instructions;
[0055] The processor executes the executable instructions to implement the Josephson junction fabrication method as described in the first aspect above.
[0056] In the Josephson junction fabrication method described in the foregoing example of this application, an initial Josephson junction whose area information meets a preset area condition is designated as the target Josephson junction, and other initial Josephson junctions besides the target Josephson junction are designated as non-target Josephson junctions. Based on the area information of the target Josephson junction, the non-target Josephson junctions are etched to make their area equal to that of the target Josephson junction. This method allows the area of multiple fabricated Josephson junctions to be controlled to be equal to the area of the target Josephson junction, effectively improving the uniformity of the Josephson junction area on the quantum chip. Attached Figure Description
[0057] To illustrate this more clearly, the accompanying drawings used in the description will be briefly introduced below.
[0058] Figure 1 Here is a flowchart illustrating a method for preparing a Josephson junction, as shown in one example of this application.
[0059] Figure 2 Here is a flowchart of a method for preparing a Josephson knot, as shown in another example of this application;
[0060] Figure 3 Here is a flowchart of a method for preparing a Josephson knot, as shown in another example of this application;
[0061] Figure 4 This is a structural diagram of the apparatus for preparing a Josephson junction in one example of this application;
[0062] Figure 5 This is a structural diagram of an electronic device in one example of this application. Detailed Implementation
[0063] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0064] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0066] A quantum chip is the core component of a quantum computer. It consists of arrayed qubits, each comprising a qubit capacitor and a Josephson junction coupled to the qubit capacitor. The frequency of a qubit is determined by both the qubit capacitor and the superconducting critical current of the Josephson junction. The size of the qubit capacitor is determined by the geometric pattern defined by ultraviolet lithography, offering relatively high controllability in the manufacturing process. The superconducting critical current of the Josephson junction is affected by the junction area; however, when fabricating Josephson junctions using oblique evaporation, the problem of varying junction areas at different locations on the quantum chip is often encountered.
[0067] Based on this, such as Figure 1 As shown in the illustration, one embodiment of the present invention provides a method for preparing a Josephson junction. The method includes, for example, the following steps:
[0068] Step S110: Form a plurality of initial Josephson junctions on the substrate;
[0069] Step S120: Obtain the area information of each initial Josephson knot, take the initial Josephson knot whose area information meets the preset area conditions as the target Josephson knot, and take the initial Josephson knots other than the target Josephson knots as non-target Josephson knots.
[0070] Step S130: Based on the area information of the target Josephson junction, etch the non-target Josephson junction so that the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
[0071] The number of initial Josephson junctions is at least two. Multiple initial Josephson junctions are fabricated on the substrate using the same process step (i.e., oblique evaporation), and these multiple initial Josephson junctions are located at different positions on the substrate. Because multiple initial Josephson junctions are fabricated at different positions on the substrate using oblique evaporation, there is an area non-uniformity among the initial Josephson junctions on the substrate. The area information may include the area value, length, width, and position of the initial Josephson junction on the substrate. The preset area condition is that the area value of the initial Josephson junction is the minimum value.
[0072] Specifically, the length, width, and center coordinates of each initial Josephson junction on the substrate are measured and recorded using high-resolution imaging equipment. Based on the length and width of the initial Josephson junctions, their area values are determined, generating a mapping table between initial Josephson junctions and their area information. This table is then reordered in ascending order of area value, and the initial Josephson junction with the smallest area value is identified as the target Josephson junction. All other initial Josephson junctions are considered non-target Josephson junctions, with the area value of the non-target junctions being greater than that of the target Josephson junction. Using the area value of the target Josephson junction as the target value, the non-target Josephson junctions are etched to make their areas equal to the area of the target Josephson junction.
[0073] This application proposes a method for fabricating Josephson junctions. An initial Josephson junction whose area information meets a preset area condition is designated as the target Josephson junction, and other initial Josephson junctions besides the target Josephson junction are designated as non-target Josephson junctions. Based on the area information of the target Josephson junction, the non-target Josephson junctions are etched to make their area equal to that of the target Josephson junction. This method can control the area of multiple fabricated Josephson junctions to be equal to the area of the target Josephson junction, effectively improving the uniformity of the Josephson junction area on the quantum chip and also contributing to improving the uniformity of the qubit frequency on the quantum chip.
[0074] In one embodiment of this application, step S110, which involves forming a plurality of initial Josephson junctions on a substrate, includes:
[0075] A photoresist layer is formed by coating a photoresist layer onto the surface of a substrate.
[0076] The first photoresist layer is exposed and developed to form multiple first vias;
[0077] Using an oblique evaporation process, a first superconducting layer, a barrier layer, and a second superconducting layer are stacked in each first through-hole to form an initial Josephson junction.
[0078] Each of the first vias has the same size and is arranged in an array on the first photoresist layer. The number of first vias is equal to the number of the initial Josephson junctions. It should be noted that the shape of the first vias can be set according to the actual shape of the fabricated Josephson junction, and the shape of the first vias includes, but is not limited to, a straight line or a cross shape.
[0079] Specifically, a substrate is obtained and cleaned; photoresist is coated on the surface of the substrate to form a first photoresist layer; the first photoresist layer is exposed using a photolithography machine. During the exposure process, a mask with a pattern corresponding to the first vias is used. The transparent areas on the mask allow light to pass through and illuminate the photoresist, while the light-blocking areas prevent light from passing through; after exposure, the photoresist is developed using a developer to remove the exposed (or unexposed, depending on the type of photoresist) portions, thereby forming multiple first vias in the first photoresist layer corresponding to the mask pattern; the developed substrate is placed in a deposition chamber, and the evaporation source (i.e., the source of the superconducting material and the barrier material) is placed on the substrate at a certain tilt angle, so that the superconducting material and the barrier material are deposited into the first vias at an tilt angle, thereby sequentially forming a stacked first superconducting layer, a barrier layer, and a second superconducting layer in the first vias, constituting an initial Josephson junction.
[0080] like Figure 2 As shown, in one embodiment of this application, step S120, obtaining the area information of each initial Josephson knot and using the initial Josephson knot whose area information satisfies a preset area condition as the target Josephson knot, includes:
[0081] Step S210: Detect each initial Josephson knot one by one to obtain the area information corresponding to each initial Josephson knot. The area information includes the area value.
[0082] Step S220: Compare the area values of each initial Josephson knot and select the initial Josephson knot with the smallest area value as the target Josephson knot.
[0083] Specifically, using scanning equipment technology, each initial Josephson node is scanned one by one, and the area of each initial Josephson node is measured and recorded. The area values of all the measured initial Josephson nodes are compared, and a sorting algorithm is used to arrange the initial Josephson nodes in ascending order of area value. The initial Josephson node with the smallest area value is identified and marked as the target Josephson node.
[0084] In one embodiment of this application, step S210, which involves detecting each initial Josephson knot one by one to obtain the area information corresponding to each initial Josephson knot, includes:
[0085] The initial Josephson junction was image detected using a microscope to obtain initial image information;
[0086] Based on the initial image information, the area information is determined.
[0087] Specifically, using a microscope (including optical microscopes, scanning electron microscopes (SEM), and atomic force microscopes (AFM), the magnification, focal length, illumination intensity, and other parameters of the microscope are adjusted to obtain a clear initial image of the initial Josephson junction. This initial image can have a one-to-one correspondence with the initial Josephson junctions, or it can be a single image containing all the initial Josephson junctions on the substrate. Preprocessing operations such as denoising and edge detection are performed on the acquired initial image to extract the edge features of the initial Josephson junctions, obtaining the length and width of each initial Josephson junction, and thus determining the area value of each initial Josephson junction.
[0088] In one embodiment of this application, the area information includes length, width, and area value, such as... Figure 3 As shown, step S130 above, based on the area information of the target Josephson junction, etches the non-target Josephson junction, including:
[0089] Step S310: Based on the area value of the target Josephson junction and the length and width of the non-target Josephson junction, determine the corresponding etching size for each non-target Josephson junction;
[0090] Step S320: Etch the area of the non-target Josephson junction according to the etching size.
[0091] Specifically, for each non-target Josephson junction, the area of the target Josephson junction is used as the target area. Based on the (initial) length and (initial) width of the non-target Josephson junction, the length etching amount, length non-etching amount, width etching amount, and width non-etching amount are determined. The length etching amount and width etching amount are the etching length and etching width, respectively. The product of the length non-etching amount and the width non-etching amount equals the target area. The length etching amount and width etching amount together serve as the etching dimension. Based on the length etching amount and width etching amount, the etching region of the non-target Josephson junction is determined. Then, the non-target Josephson junction is etched according to the etching region. The etching depth is equal to the sum of the thicknesses of the first superconducting layer, the barrier layer, and the second superconducting layer.
[0092] It should be noted that, in addition to the target Josephson junction and non-target Josephson junction, if there is a second superconducting layer on the substrate that is not stacked with the first superconducting layer, and a first superconducting layer with a barrier layer formed on its surface that is not stacked with the second superconducting layer, the second superconducting layer and the first superconducting layer with a barrier layer formed on its surface must be etched simultaneously during the etching process of the etched area. The etching depth is equal to the sum of the thicknesses of the first superconducting layer, the barrier layer, and the second superconducting layer.
[0093] In one embodiment of this application, step S320, which involves etching the area of the non-target Josephson junction according to the etching size, includes:
[0094] A second photoresist layer is formed by coating a photoresist layer onto the surface of a substrate.
[0095] The second photoresist layer is exposed and developed according to the etching size to form a second via corresponding to the etching size;
[0096] Using a dry etching process, non-target Josephson junctions are etched, and the area of the retained non-target Josephson junctions after etching is equal to the area of the target Josephson junction.
[0097] Specifically, photoresist is coated onto the surface of the substrate containing the non-target Josephson junction to form a second photoresist layer. The second photoresist layer is then exposed using a photolithography machine. During exposure, a mask with a pattern corresponding to the etching dimensions (i.e., length etching amount and width etching amount) is used. Transparent areas on the mask allow light to pass through and illuminate the photoresist, while light-blocking areas prevent light from passing through. After exposure, the photoresist is developed using a developer to remove the exposed (or unexposed, depending on the photoresist type) portions, thereby forming multiple second vias in the first photoresist layer corresponding to the mask pattern. Dry etching (such as ion beam etching) is then used to etch the areas through the second vias, ensuring that the area of the un-etched non-target Josephson junction is equal to the area of the target Josephson junction.
[0098] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0099] Based on the same inventive concept, this application also provides an apparatus for preparing the Josephson junction as described above. The solution provided by this apparatus is similar to the solution described in the above method; therefore, the specific limitations of one or more Josephson junction preparation apparatus embodiments provided below can be found in the limitations of the Josephson junction preparation method described above, and will not be repeated here.
[0100] like Figure 4 As shown, this application also provides a Josephson junction preparation apparatus 400, which includes:
[0101] Initial module 410 is used to form multiple initial Josephson junctions on the substrate;
[0102] The acquisition module 420 is used to acquire the area information of each initial Josephson knot, and to designate the initial Josephson knot whose area information meets the preset area conditions as the target Josephson knot, and to designate the initial Josephson knots other than the target Josephson knots as non-target Josephson knots.
[0103] Etching module 430 is used to etch non-target Josephson junctions based on the area information of the target Josephson junction until the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
[0104] In one embodiment of this application, the initial module 410 is specifically used for:
[0105] A photoresist layer is formed by coating a photoresist layer onto the surface of a substrate.
[0106] The first photoresist layer is exposed and developed to form multiple first vias;
[0107] Using an oblique evaporation process, a first superconducting layer, a barrier layer, and a second superconducting layer are stacked in each first through-hole to form an initial Josephson junction.
[0108] In one embodiment of this application, each first via is the same size, and the first vias are distributed in an array on the first photoresist layer.
[0109] In one embodiment of this application, the shape of the first through hole includes a straight line or a cross shape.
[0110] In one embodiment of this application, the acquisition module 420 is specifically used for:
[0111] Each initial Josephson knot is examined one by one to obtain the area information corresponding to each initial Josephson knot, including the area value.
[0112] Compare the area values of each initial Josephson knot and select the initial Josephson knot with the smallest area value as the target Josephson knot.
[0113] In one embodiment of this application, the acquisition module 420 is specifically used for:
[0114] The initial Josephson junction was image detected using a microscope to obtain initial image information;
[0115] Based on the initial image information, the area information is determined.
[0116] In one embodiment of this application, the area information includes length, width, and area value, and the etching module 430 is specifically used for:
[0117] Based on the area of the target Josephson junction and the length and width of the non-target Josephson junctions, the corresponding etching size for each non-target Josephson junction is determined;
[0118] Based on the etching dimensions, the area of the non-target Josephson junction is etched.
[0119] In one embodiment of this application, the etching module 430 is specifically used for:
[0120] A second photoresist layer is formed by coating a photoresist layer onto the surface of a substrate.
[0121] The second photoresist layer is exposed and developed according to the etching size to form a second via corresponding to the etching size;
[0122] Using a dry etching process, non-target Josephson junctions are etched, and the area of the retained non-target Josephson junctions after etching is equal to the area of the target Josephson junction.
[0123] Based on the same inventive concept, such as Figure 5 As shown, an embodiment of the present invention also proposes an electronic device, comprising:
[0124] Processor; memory used to store processor-executable instructions.
[0125] The processor executes executable instructions to implement the Josephson junction fabrication method described above.
[0126] In the description of this specification, references to terms such as "some embodiments" or "example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0127] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for preparing a Josephson knot, characterized in that, The method includes: Multiple initial Josephson junctions are formed on the substrate; Obtain the area information of each initial Josephson knot, and designate the initial Josephson knot whose area information satisfies the preset area condition as the target Josephson knot, and designate the initial Josephson knots other than the target Josephson knots as non-target Josephson knots. Based on the area information of the target Josephson junction, the non-target Josephson junction is etched so that the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
2. The method for preparing a Josephson knot according to claim 1, characterized in that, The formation of multiple initial Josephson junctions on the substrate includes: A first photoresist layer is formed by coating a photoresist layer onto the surface of the substrate. The first photoresist layer is exposed and developed to form the plurality of first vias; Using an oblique evaporation process, a first superconducting layer, a barrier layer, and a second superconducting layer are stacked in each of the first through-holes to form the initial Josephson junction.
3. The method for preparing a Josephson knot according to claim 2, characterized in that, Each of the first vias has the same size, and the first vias are arranged in an array on the first photoresist layer.
4. The method for preparing a Josephson knot according to claim 2, characterized in that, The shape of the first through hole may be either straight or cross-shaped.
5. The method for preparing a Josephson knot according to claim 1, characterized in that, The step of obtaining the area information of each initial Josephson knot and selecting the initial Josephson knot whose area information satisfies a preset area condition as the target Josephson knot includes: Each initial Josephson node is detected one by one to obtain the area information corresponding to each initial Josephson node, and the area information includes the area value; The area values of each initial Josephson knot are compared, and the initial Josephson knot with the smallest area value is taken as the target Josephson knot.
6. The method for preparing a Josephson knot according to claim 5, characterized in that, The step of detecting each initial Josephson knot one by one to obtain the area information corresponding to each initial Josephson knot includes: The initial Josephson junction was image-detected using a microscope to obtain initial image information; The area information is determined based on the initial image information.
7. The method for preparing a Josephson knot according to claim 1, characterized in that, The area information includes length, width, and area value. Etching the non-target Josephson junction based on the area information of the target Josephson junction includes: Based on the area value of the target Josephson junction and the length and width of the non-target Josephson junction, the etching size corresponding to each non-target Josephson junction is determined; The area of the non-target Josephson junction is etched according to the etch dimensions.
8. The method for preparing a Josephson knot according to claim 7, characterized in that, The etching of the area of the non-target Josephson junction according to the etching size includes: A second photoresist layer is formed by coating a photoresist layer onto the surface of the substrate. The second photoresist layer is exposed and developed according to the etching size to form a second via corresponding to the etching size; The non-target Josephson junction is etched using a dry etching process, and the area of the non-target Josephson junction remaining after etching is equal to the area of the target Josephson junction.
9. An apparatus for preparing a Josephson junction, characterized in that, The device includes: An initial module for forming multiple initial Josephson junctions on a substrate; The acquisition module is used to acquire the area information of each initial Josephson knot, and to designate the initial Josephson knot whose area information meets the preset area conditions as the target Josephson knot, and to designate the initial Josephson knots other than the target Josephson knots as non-target Josephson knots. An etching module is used to etch the non-target Josephson junction based on the area information of the target Josephson junction until the area of the non-target Josephson junction is equal to the area of the target Josephson junction.
10. An electronic device, comprising: processor; Memory used to store processor-executable instructions; The processor executes the executable instructions to implement the method for preparing a Josephson junction as described in any one of claims 1-8.