Preparation method of metal contact layer, metal contact layer structure and semiconductor device

Abstract

The embodiment of the invention relates to the technical field of semiconductor devices, and discloses a preparation method of a metal contact layer, a metal contact layer structure and a semiconductor device. The preparation method comprises the following steps: providing a silicon carbide substrate, and at least sequentially depositing a first metal layer and a second metal layer on the back surface of the silicon carbide substrate once; carrying out heat treatment on the silicon carbide substrate deposited with the first metal layer and the second metal layer by adopting a nanosecond ultraviolet pulse laser annealing process, and forming a metal contact layer on the back surface of the silicon carbide substrate; the metal contact layer is formed by compositely distributing a low-resistance silicide and a carbide, the low-resistance silicide is generated by reacting the first metal layer, the second metal layer and a silicon element in the silicon carbide substrate, and the carbide is generated by reacting the second metal layer and a carbon element in the silicon carbide substrate; and the carbide is distributed in the low-resistance silicide. According to the technical scheme provided by the invention, the specific contact resistance of the metal contact layer can be greatly reduced, and the holes are filled with carbides, so that the on resistance of the semiconductor device is synchronously improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor devices, and in particular to a preparation method of a metal contact layer, a metal contact layer structure and a semiconductor device. BACKGROUND

[0002] Silicon carbide (SiC) as the third generation of wide bandgap semiconductor material, has the characteristics of large bandgap, high saturated electron drift velocity, excellent thermal conductivity, strong radiation resistance, etc., is the core material for manufacturing high-frequency, high-temperature and high-power semiconductor devices, and is widely used in new energy vehicles, smart grids, aerospace and other fields.

[0003] In the preparation of semiconductor devices, the quality of the back metal contact layer directly determines the electrical performance and reliability of the device. In the traditional preparation method of SiC devices, a single nickel (Ni) layer is usually used to react with the silicon carbide substrate through rapid thermal annealing (RTA) or furnace tube annealing to form a nickel silicide as an ohmic contact layer. However, when SiC reacts with Ni, the free carbon produced by the decomposition of SiC is easy to form graphite, and the longitudinal resistivity (perpendicular to the chip surface) of graphite is 10³ times that of the transverse resistivity, so the graphite layer will significantly increase the series resistance, hindering the reduction of the on-resistance of the device; the diffusion rates of Ni, Si and C are quite different, and the atomic diffusion imbalance in the traditional annealing process is easy to form Kirkendall voids at the metal / SiC interface, which weakens the mechanical strength and electrical uniformity of the alloy layer. Therefore, there is an urgent need for a back metal contact layer preparation method that can precisely control the interface reaction, suppress defect generation, and balance low resistance and high reliability. SUMMARY

[0004] The purpose of the embodiments of the present application is to at least provide a preparation method of a metal contact layer, a metal contact layer structure and a semiconductor device, which can at least greatly reduce the specific contact resistance of the metal contact layer, fill the carbide holes, reduce the interface holes, reduce the resistance dispersion, and improve the on-resistance of the semiconductor device.

[0005] To solve the above technical problems, at least one embodiment of the present application provides a preparation method of a metal contact layer applied to a semiconductor device, which comprises: providing a silicon carbide substrate; performing at least one deposition process: sequentially depositing a first metal layer and a second metal layer on the back surface of the silicon carbide substrate; The laser annealing process is performed: a nanosecond ultraviolet pulse laser annealing process is used to heat treat the silicon carbide substrate on which the first metal layer and the second metal layer are deposited, to form a metal contact layer on the back surface of the silicon carbide substrate; the metal contact layer is composed of a low-resistance silicide and a carbide, the low-resistance silicide is generated by the reaction of the first metal layer, the second metal layer and the silicon element in the silicon carbide substrate, and the carbide is generated by the reaction of the second metal layer and the carbon element in the silicon carbide substrate; the carbide is distributed in the low-resistance silicide.

[0006] In some optional embodiments, the specific contact resistance of the metal contact layer ranges from 1×10 -5 Ω cm 2 -3×10 -5 Ω cm².

[0007] In some optional embodiments, the deposition process is a magnetron sputtering process; the first metal layer comprises a nickel metal layer, and the thickness of the nickel metal layer is 100-175 nm; the second metal layer comprises a titanium metal layer, and the thickness of the titanium metal layer is 25-100 nm.

[0008] In some optional embodiments, the deposition process is an atomic layer deposition process, and the first metal layer and the second metal layer are alternately deposited multiple times by the atomic layer deposition process to form a multilayer structure; the number of cycles of the alternate deposition is 10-40 times.

[0009] In some optional embodiments, in the laser annealing process, the scanning mode of the nanosecond ultraviolet pulse laser is linear scanning, the laser spot is in a Gaussian distribution, and the overlap degree of adjacent scanning tracks is 70%-90%.

[0010] In some optional embodiments, the laser annealing process only has one nanosecond constant temperature section, the temperature range of the nanosecond constant temperature section is 1200°C-1500°C, and the duration is tens to hundreds of nanoseconds.

[0011] In some optional embodiments, a silicon carbide substrate is provided, comprising: The back surface of the silicon carbide substrate is subjected to a thinning process and a cleaning process.

[0012] At least one embodiment of the present application also provides a metal contact layer structure prepared by the preparation method of the metal contact layer as described above, and the metal contact layer structure is applied to a semiconductor device, and the metal contact layer structure comprises: a silicon carbide substrate; a metal contact layer located on the back surface of the silicon carbide substrate; the metal contact layer is composed of a low-resistance silicide and a carbide.

[0013] In some optional embodiments, the initial structure of the metal contact layer comprises at least one time of alternately stacking the first metal layer and the second metal layer.

[0014] At least one embodiment of the present application also provides a semiconductor device comprising the metal contact layer structure as described above.

[0015] The embodiments of the present application provide a preparation method of a metal contact layer, a metal contact layer structure and a semiconductor device. The preparation method comprises the following steps: providing a silicon carbide substrate; performing at least one deposition process to deposit a first metal layer and a second metal layer on the back surface of the silicon carbide substrate in sequence; and performing a nanosecond ultraviolet pulse laser annealing process to heat treat the silicon carbide substrate on which the first metal layer and the second metal layer are deposited. The first metal layer reacts with silicon elements in the silicon carbide substrate to form a low-resistance silicide, so as to provide an efficient conductive channel. The second metal layer reacts with C to generate a stable carbide, so as to inhibit the generation of graphite. The carbide and the low-resistance silicide form a dense composite structure to constitute the metal contact layer, thereby greatly reducing the specific contact resistance of the metal contact layer, and the carbide fills the holes, reduces the interface holes, reduces the resistance dispersion, and simultaneously improves the on-resistance of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate like elements, and in which: the drawings are not necessarily to scale, except as otherwise noted.

[0017] Figure 1 is a flowchart of a preparation method of a metal contact layer according to an embodiment of the present application; Figures 2-7 is a process structure diagram involved in a process step of the preparation method of the metal contact layer according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be realized even without these technical details and various changes and modifications based on the following embodiments.

[0019] In order to facilitate the understanding of the embodiments of the present application, the related content about the defects existing in the conventional annealing process is introduced first.

[0020] In the conventional technology, a single nickel (Ni) layer is usually used to react with a silicon carbide substrate through rapid thermal annealing (RTA) or furnace tube annealing to form a nickel silicide (Ni2Si, NiSi) as an ohmic contact layer. However, this scheme has the following key defects: (1) Graphite enrichment leads to increased resistance: When SiC reacts with Ni, the free carbon produced by the decomposition of SiC tends to form a graphite layer (about 150 layers of carbon atoms stacked), and the longitudinal resistivity (perpendicular to the chip surface) of graphite is 10³ times that of the transverse resistivity. Since the carrier transport of a vertical SiC device is mainly longitudinal, the graphite layer will significantly increase the series resistance and hinder the reduction of the on-resistance (Rdson) of the device; (2) Kirkendall void defects: The diffusion rates of Ni, Si, and C are quite different, and the atomic diffusion imbalance in the conventional annealing process tends to form Kirkendall voids at the metal / SiC interface. Kirkendall voids are the "products" of atomic diffusion imbalance and are the core hidden defects that threaten the long-term reliability of semiconductor devices and electronic packages. The existence of Kirkendall voids weakens the mechanical strength and electrical conductivity uniformity of the alloy layer, resulting in a large dispersion of electrical parameters within the chip, such as a contact resistance deviation of more than 30%; (3) Poor process controllability: The heating / cooling rate of RTA or furnace tube annealing is slow (usually seconds), making it difficult to precisely control the amount and morphology of Ni2Si, which tends to result in problems such as large silicide grains, excessive interface reaction, and insufficient long-term high-temperature stability.

[0021] Therefore, there is an urgent need for a SiC back metal contact layer preparation method that can precisely control the interface reaction, suppress defect formation, and balance low resistance and high reliability.

[0022] Embodiment one: The embodiment of the present application relates to a metal contact layer preparation method, which provides a silicon carbide substrate, performs at least one deposition process on the back surface of the silicon carbide substrate to sequentially deposit a first metal layer and a second metal layer, and uses a nanosecond ultraviolet pulse laser annealing process to heat treat the silicon carbide substrate with the deposited first metal layer and second metal layer. The first metal layer reacts with silicon elements in the silicon carbide substrate to form a low-resistance silicide, providing an efficient conductive channel. The second metal layer reacts with C to form a stable carbide, suppressing the formation of graphite. The carbide and the low-resistance silicide form a dense composite structure to form a metal contact layer, thereby significantly reducing the specific contact resistance of the metal contact layer, and the carbide fills the pores, reducing resistance dispersion, and improving the on-resistance of the semiconductor device.

[0023] The implementation details of the metal contact layer preparation method of the present embodiment will be described in detail below. The following content is only provided for the implementation details for easy understanding, and is not essential for implementing the present scheme.

[0024] This application provides a method for preparing a metal contact layer, applicable to semiconductor devices, such as... Figure 1 As shown, the method for preparing the metal contact layer includes: Step 110: Provide a silicon carbide substrate.

[0025] like Figure 2 As shown, the silicon carbide substrate 100 is exemplarily selected as a 4H-SiC single crystal substrate, and the silicon carbide substrate 100 is n-type or p-type.

[0026] During this process, such as Figure 2 As shown, the back side of the silicon carbide substrate 100 is thinned first. Depending on the semiconductor device design requirements, the back side of the silicon carbide substrate 100 may be thinned to a target thickness, such as 100μm-150μm, using mechanical grinding or chemical mechanical polishing (CMP). Thicknesses of 100μm, 120μm, or 150μm can be retained as needed. Simultaneously, the thickness uniformity of the silicon carbide substrate 100 must be ensured, such as a thickness deviation ≤3%, to avoid temperature field imbalance during subsequent annealing due to uneven thickness. Then, the thinned silicon carbide substrate is cleaned. A multi-step cleaning process can be used to thoroughly remove oil, natural oxide layer, and residual impurities from the back side of the silicon carbide substrate. After cleaning, the surface roughness Ra ≤ 0.5nm to ensure the bonding quality of the metal layer and silicon carbide substrate interface in subsequent steps.

[0027] Step 120: Perform at least one deposition process: deposit a first metal layer and a second metal layer sequentially on the back side of the silicon carbide substrate.

[0028] like Figure 2 As shown, in this step, the first metal layer 200 and the second metal layer 300 are metals that can react with the silicon carbide substrate 100 to form low-resistivity silicides. That is, the first metal layer 200 and the second metal layer 300 are metals that have the ability to form low-resistivity phases when reacting with the silicon carbide substrate 100. The second metal layer 300 is a metal that can form stable carbides with carbon elements, playing a role in suppressing graphite and filling voids to a certain extent. Therefore, the first metal layer 200 and the second metal layer 300 are determined based on the physicochemical properties of the metals, their reaction compatibility with silicon carbide (SiC), and functional complementarity, combined with the device performance requirements, namely low resistance, high density, and high stability. Furthermore, it is necessary to ensure that the first metal layer 200 and the second metal layer 300 can form good adhesion.

[0029] For example, the first metal layer 200 is, for example, Co (cobalt), Pt (platinum), or Ni (nickel). The second metal layer 300 is, for example, aluminum (Al), tantalum (Ta), tungsten (W), or molybdenum (Mo).

[0030] For example, the first metal layer 200 is a nickel (Ni) layer, and the second metal layer 300 is a titanium (Ti) layer. Specifically, the core reason for selecting Ni for the first metal layer 200 and Ti for the second metal layer 300 is to meet the basic requirements of low contact resistance and interfacial bonding. Ni has moderate chemical reactivity, good compatibility with Ti, and easily forms a stable phase, while Ti has a strong affinity for carbon. Therefore, in this step, when the first metal layer 200 is a nickel (Ni) layer and the second metal layer 300 is a titanium (Ti) layer, Ni can react with SiC to form low-resistivity silicides to ensure conductive channels, and can also form good adhesion with the Ti layer, avoiding the problem of detachment caused by poor interfacial bonding of traditional single metal layers. At the same time, it provides a structural basis for the Ni layer to perform the "carbon capture" function. Therefore, the selection of Ni for the first metal layer 200 and Ti for the second metal layer 300 is to ensure low contact resistance and good interfacial bonding. The selection of Ti for the second metal layer 300 is to suppress defects and improve stability. The complementary functions and process compatibility of the two layers make them the optimal metal combination for the SiC back-side metal contact layer 500. Thus, the combination of Ni and Ti layers is a choice made considering the synergistic design of low-resistance core and defect suppression, simultaneously achieving the three core requirements of low resistance, high density, and high stability—something that cannot be replaced by a single metal layer in existing technologies.

[0031] For example, two structures are available for depositing a first metal layer 200 and a second metal layer 300 on the back side of a silicon carbide substrate 100: one is a Ni / Ti bilayer structure, and the other is a multi-layer structure. Specifically, when the initial structure of the Ni / Ti bilayer structure is formed on the back side of the silicon carbide substrate 100, a magnetron sputtering device can be started, the cleaned substrate can be fixed on the sample stage, a vacuum can be drawn, sputtering gas can be introduced, and the first metal layer 200 can be deposited first using the magnetron sputtering process. The sputtering rate is controlled so that the thickness of the first metal layer 200 is 100-175 nm, ensuring that the first metal layer 200 completely covers the back side of the silicon carbide substrate 100; then the second metal layer 300 is deposited, and the thickness of the second metal layer 300 is controlled to be 25-100 nm to avoid the second metal layer 300 from prematurely contacting the silicon carbide substrate 100.

[0032] like Figure 4As shown, when an initial multi-layered structure is formed on the back side of a silicon carbide substrate 100, an atomic layer deposition process can be used to alternately deposit a first metal layer 200 and a second metal layer 300 multiple times to form a multi-layered structure, i.e., a composite structure after nanoscale alternating multi-cycle stacking reaction. During this process, the thicknesses of the first metal layer 200 and the second metal layer 300 can both be controlled within 1-10 nm, and the number of alternating deposition cycles is 1-70. The first metal layer 200 is a nickel (Ni) layer, and the second metal layer 300 includes a titanium (Ti) layer. Due to the relationship between the number of stacking cycles and performance, under the premise of a fixed single-layer thickness, as the number of Ni / Ti stacking cycles increases from 5 to approximately 30-40, the average specific contact resistance of the subsequently formed metal contact layer 500 gradually decreases, and the on-chip standard deviation also decreases simultaneously. When the number of cycles continues to increase to more than 50, the improvement in contact resistance tends to saturate, and even slight degradation may occur due to process complexity and stress accumulation. Therefore, it is optimal to control the number of alternating deposition cycles between 10 and 40 to avoid uneven Ti distribution due to too few cycles, while too many cycles increase process complexity and stress accumulation.

[0033] Among them, such as Figure 3 and Figure 4 As shown, the initial structures of the metal contact layers obtained by the above two methods before laser processing have basically the same total film thickness.

[0034] In one embodiment, the second metal layer 200 may also be an aluminum (Al) layer, a tantalum (Ta) layer, a tungsten (W) layer, or a molybdenum (Mo) layer.

[0035] Step 130: Perform laser annealing process: The silicon carbide substrate with the first metal layer and the second metal layer deposited is heat-treated using a nanosecond ultraviolet pulsed laser annealing process to form a metal contact layer on the back side of the silicon carbide substrate; the metal contact layer is composed of a composite distribution of low-resistivity silicide and carbide, the low-resistivity silicide is generated by the reaction of the first metal layer, the second metal layer and silicon element in the silicon carbide substrate, and the carbide is generated by the reaction of the second metal layer and carbon element in the silicon carbide substrate; the carbide is distributed in the low-resistivity silicide.

[0036] In this step, such as Figure 3 and Figure 4As shown, due to the high temperature during laser annealing, and because Ni and Ti are easily oxidized metals, direct exposure to air will rapidly form high-resistivity impurity phases such as nickel oxide (NiO) and titanium oxide (TiO2), which will damage the ohmic contact performance formed subsequently. Therefore, to make the ohmic contact layer (metal contact layer 500) after laser annealing more stable, a protective layer 400 can be formed on the side of the second metal layer 300 facing away from the silicon carbide substrate 100. This protective layer 400 can isolate air or control the oxygen content, preventing excessive oxidation of the Ni / Ti layer and ensuring the formation of the target phase, such as TiC or Ni2Si, during the alloying process. Figure 5 and Figure 6 As shown, then a laser annealing process is performed.

[0037] by Figure 6 The example of a Ni / Ti bilayer structure deposited on the back side of a silicon carbide substrate 100 is illustrated. In the laser annealing process, a nanosecond ultraviolet pulsed laser annealing device can be used. The silicon carbide substrate 100 with the first metal layer 200 and the second metal layer 300 deposited is heat-treated using nanosecond ultraviolet pulsed laser annealing (UV-LA). By precisely controlling the laser parameters and temperature history, the interface reaction and phase transition path can be precisely controlled. Continuing with the example of the first metal layer 200 being a Ni layer and the second metal layer 300 being a Ti layer, the specific process parameters and procedures can be implemented using the following key operations: Regarding the laser parameter settings, the wavelength of the ultraviolet laser should be set to 350-400nm to match the high absorption rate of 4H-SiC. A nanosecond ultraviolet pulsed laser with a wavelength of 355nm can be selected, with a pulse width of 10-100ns, a scanning speed of 100-300mm / s, a linear scanning mode, a Gaussian laser spot distribution, a spot diameter of 30-100μm, a single-pass energy density of 4.2-5.0J / cm², an average power of 5-30W, 1-3 scan passes, and an overlap of 70%-90% between adjacent scan trajectories, preferably set to 80%.

[0038] Among them, the pulse width / average power determines the transient peak temperature T and the duration of high temperature; the spot diameter and scanning speed determine the dwell characteristics of energy distribution. The pulse width / average power can be finely adjusted to optimize morphology and phase selectivity, with a single-pass energy density of 4.2–5.0 J / cm² and an overlap of 80% between adjacent scanning trajectories as a benchmark.

[0039] During this process, the single-pass energy density can be finely adjusted according to the initial total thickness of the metal contact layer. The larger the thickness, the higher the single-pass energy density can be, but it should be avoided to exceed 5.0 J / cm² to prevent damage to the silicon carbide substrate.

[0040] In this process, the optimal overlap between adjacent scanning trajectories in the scanning direction is approximately 80%. If the overlap is too small, for example, below 50%, the energy received in the middle region between the two scanning trajectories will be significantly lower, resulting in insufficient temperature rise and alloying reaction in this region. This can easily lead to "striped" alloy layer thickness fluctuations and localized high contact resistance areas. If the overlap is too high, for example, close to 100%, the same location will be subjected to repeated intense heating, which can easily cause surface erosion, roughening, and stress cracking. Therefore, through multiple process window experiments, it has been found that when the overlap is set in the range of approximately 70%-90%, the intra-chip electrical uniformity is significantly improved. Among these, an overlap of approximately 80% can ensure a smooth and continuous energy field distribution without causing excessive repeated heating, thereby obtaining a flat, dense, and relatively uniform alloy layer structure.

[0041] Regarding the annealing process, a staged annealing approach can be adopted. That is, the heat treatment process of laser annealing can include three stages: rapid heating stage, nanosecond isothermal stage, and rapid cooling stage, thereby simplifying the process window and facilitating stable control on the mass production line.

[0042] In the rapid heating phase, ultraviolet laser irradiation is used, causing electrons on the metal surface to instantly absorb photon energy and transfer it to the crystal lattice, achieving rapid thermal equilibrium in the electron-lattice system. During this process, energy only acts on the metal layer and the SiC interface, while the temperature of the silicon carbide substrate remains essentially unchanged, thus creating a steep temperature gradient between a high-temperature surface and a low-temperature substrate, preventing substrate damage. In the rapid heating phase, the interface temperature quickly reaches the kinetic critical value (e.g., >1200℃) for the reaction between the Ni layer and the silicon carbide substrate, bypassing the high-resistivity Ni3Si phase that is easily formed in the low-temperature region and directly entering the stable formation range of Ni2Si. Therefore, it avoids the premature decomposition of SiC to generate free C (carbon elements) and aggregate to form graphite, which is common in traditional slow heating (e.g., RTA). In this embodiment, the rapid heating phase reduces the diffusion time of C in the low-temperature region, reserving a reaction window for the subsequent Ti layer to capture C.

[0043] During the nanosecond isothermal phase, the temperature range is 1200℃-1500℃, and the duration is tens to hundreds of nanoseconds, ideally maintained at 50-200 ns. The core reactions occurring in this phase are: Ni reacts with Si in SiC to form a low-resistivity Ni₂Si phase; Ti reacts with Si in SiC to form a low-resistivity TiSi₂ phase; Ti reacts with free C from SiC decomposition to form TiC; simultaneously, Ti combines with Si and TiC to form a mixed phase Ti₃SiC₂. These two carbides fill the potential pores in the Ni₂Si layer, thus suppressing voids. Only one nanosecond isothermal phase is used in this process to reduce the accumulation of thermal stress and interfacial re-diffusion introduced by multiple heating cycles, maintain the singularity and controllability of the interfacial reaction, and avoid the regeneration of unfavorable phases (such as excessively thick intermetallic compounds or new pores) during secondary or multiple heating processes.

[0044] The temperature is controlled at 1200-1500℃ in the nanosecond isothermal range because this is the optimal range for the simultaneous formation of Ni2Si and TiC / Ti3SiC2. If the temperature is below 1200℃, the reaction kinetics between Ni and SiC are insufficient, resulting in discontinuous Ni2Si layers and an increase in specific contact resistance, making it greater than 5 × 10⁻⁶. -5 Ω cm²; if the temperature exceeds 1500℃, excessive diffusion of Ni, Si, and C leads to coarse Ni₂Si grains and intensified C segregation, resulting in graphite formation and consequently increased electrical resistance. Therefore, at a constant temperature of 1200-1500℃, the reaction between Ti and C / Si can be completed within nanoseconds, simultaneously forming the TiC / Ti₃SiC₂ phase, which stabilizes the interface and inhibits graphite formation. Furthermore, this temperature range allows for controllable atomic diffusion distances, preventing excessive Ti diffusion from hindering Ni₂Si formation or excessive Ni diffusion from damaging the SiC matrix, ultimately resulting in a dense composite structure filled with Ni₂Si and TiC / Ti₃SiC₂.

[0045] During the rapid cooling phase following the laser pulse, heat conduction dominates the cooling process. The high-temperature metal layer rapidly dissipates heat to the low-temperature silicon carbide substrate and surrounding environment, causing the temperature to drop instantly to well below the reaction temperature. This ultrafast cooling rate prevents the Ni2Si-TiC / Ti3SiC2 composite structure formed at high temperatures from undergoing phase transformation or grain growth; the phase transformation process is essentially "frozen," preventing excessive diffusion and coarse grain growth under prolonged high temperatures, thus maintaining the nanoscale fine structure and density. Therefore, this rapid cooling phase suppresses secondary defects and avoids the problems of coarse grains and graphite regeneration that occur in traditional slow cooling methods (such as the second-level cooling of RTA).

[0046] like Figure 7As shown, after the laser annealing process, the metal contact layer 500 is a composite metal layer composed of low-resistivity silicides and carbides, achieving uniform alloying. The low-resistivity silicides formed include Ni2Si and TiSi2, and the carbides formed include TiC and Ti3SiC2. TiC and Ti3SiC2 are generated by the reaction of the Ti layer with carbon elements in the 4H-silicon carbide substrate, and TiC and Ti3SiC2 fill the potential porosity regions of the low-resistivity silicides, thereby forming a low-defect, low-porosity, and flat and dense Ni2Si and TiC / Ti3SiC2 composite structure on the back side of the silicon carbide substrate, i.e., the metal contact layer 500.

[0047] In one embodiment, the low-resistivity silicide and carbide are distributed in a gradient composite pattern, with a higher proportion of low-resistivity silicide closer to the silicon carbide substrate and a higher proportion of carbide farther from the silicon carbide substrate, in order to balance the interfacial bonding force and surface conductivity.

[0048] The heat treatment of the laser annealing process in this application avoids the defects caused by single temperature or time control by dividing the temperature stages. The resulting metal contact layer 500, which is composed of Ni2Si and TiC / Ti3SiC2, has three major advantages: low resistance, high density, and high stability. It perfectly solves the industry pain points of graphite enrichment, high resistance, and poor reliability of traditional SiC back metal contact layers.

[0049] The method for preparing the metal contact layer provided in this application involves performing at least one deposition process to sequentially deposit a first metal layer and a second metal layer on the back side of a silicon carbide substrate. A nanosecond ultraviolet pulsed laser annealing process is then used to heat-treat the silicon carbide substrate with the deposited first and second metal layers. The first and second metal layers react with Si elements in the silicon carbide substrate to form low-resistivity silicides, providing a highly efficient conductive channel. The second metal layer reacts with C to generate stable carbides, suppressing graphite formation. The carbides and low-resistivity silicides combine to form a dense composite structure constituting the metal contact layer, thereby significantly reducing the specific contact resistance of the metal contact layer. Furthermore, the carbides fill voids, reducing interface voids and resistance dispersion, thus simultaneously improving the on-resistance of the semiconductor device.

[0050] In one embodiment, the specific contact resistance of the metal contact layer is in the range of 1×10⁻⁶. -5 Ω cm 2 -3×10 -5 Ω cm².

[0051] Example 2: The embodiments of this application also provide a metal contact layer structure, such as Figure 7As shown, the metal contact layer structure is prepared using the metal contact layer preparation method provided in any of the above embodiments. The metal contact layer structure is applied to a semiconductor device, and the metal contact layer structure includes: Silicon carbide substrate 100; The metal contact layer 500 is located on the back side of the silicon carbide substrate 100; the metal contact layer 500 is composed of a low-resistivity silicide and a carbide composite distribution.

[0052] Combination Figure 6 As shown, in the metal contact layer 500, the low-resistivity silicide is generated by the reaction of the first metal layer 200 and the second metal layer 300 in the initial structure of the metal contact layer 500 with the silicon element in the silicon carbide substrate 100; the carbide is generated by the reaction of the second metal layer 300 with the carbon element in the silicon carbide substrate 100, and the carbide is distributed in the low-resistivity silicide.

[0053] In one embodiment, the specific contact resistance of the metal contact layer 500 is in the range of 1×10⁻⁶. -5 Ω cm 2 -3×10 -5 Ω cm².

[0054] In one embodiment, the silicon carbide substrate 100 is a 4H-SiC substrate.

[0055] In one embodiment, the low-resistivity silicide layer includes Ni2Si and TiSi2, and the carbide includes TiC and Ti3SiC2. TiC and Ti3SiC2 are generated by the reaction of the Ti layer with carbon elements in the silicon carbide substrate, and TiC and Ti3SiC2 fill the potential porous regions of the low-resistivity silicide to form a dense composite structure.

[0056] In one embodiment, the low-resistivity silicide and carbide are distributed in a gradient composite pattern, with a higher proportion of low-resistivity silicide closer to the silicon carbide substrate and a higher proportion of carbide farther from the silicon carbide substrate, in order to balance the interfacial bonding force and surface conductivity.

[0057] In one embodiment, the surface roughness of the metal contact layer 500 is ≤5nm, the cross-section has no Kirkendall voids, the graphite content is ≤1%, and there is no continuous graphite layer in the longitudinal conductive path.

[0058] In one embodiment, such as Figure 6 As shown, the initial structure of the metal contact layer is a first metal layer 200 and a second metal layer 300 that are stacked alternately at least once.

[0059] In one embodiment, the first metal layer is a nickel (Ni) metal layer, the second metal layer includes a titanium (Ti) metal layer, the thickness of the first metal layer is 100-175 nm, and the thickness of the second metal layer is 25-100 nm.

[0060] In one embodiment, such as Figure 7 As shown, the initial structure of the metal contact layer consists of multiple alternating layers of a first metal layer 200 and a second metal layer 300, with the alternation cycle ranging from 1 to 70 times. Exemplarily, the alternation cycle is 10 to 40 times. Exemplarily, the thickness of both the first metal layer 200 and the second metal layer 300 is 1 to 10 nm.

[0061] For example, the first metal layer 200 is a nickel (Ni) metal layer, and the second metal layer 300 includes a titanium (Ti) metal layer.

[0062] Example 3: The embodiments of this application also provide a semiconductor device including the metal contact layer structure provided in any of the above embodiments.

[0063] In one embodiment, the semiconductor device is a vertical SiC MOSFET or a SiC diode, and the metal contact layer serves as the back ohmic contact layer of the semiconductor device.

[0064] Example 4: According to an exemplary embodiment, this embodiment uses the metal contact layer prepared by the metal contact layer preparation method in the above embodiments, and applies it to a typical vertical SiC MOSFET device structure. Meanwhile, using a traditional single Ni layer as the back contact layer as a control, under the same device layout and epitaxial conditions, the metal contact layers prepared by the metal contact layer preparation method provided in this application have the following comparison data on typical electrical performance under different back metal contact layer structures, showing the contact resistance and chip on-resistance: (Table 1 below). Table 1

[0065] The above data shows that the metal contact layer prepared by the method of this application, when the metal contact layer is formed by a Ni / Ti bilayer structure, has a specific contact resistance that can be reduced by about 30-50% compared to a metal contact layer formed by a Ni monolayer using the RTA annealing process, and the on-resistance of the semiconductor device is reduced by about 15-25% accordingly.

[0066] When the metal contact layer is formed by a multi-layer structure of alternating nanoscale Ni / Ti, the specific contact resistance can be reduced by about 20-30% compared to the metal contact layer formed by RTA annealing of a single Ni layer, and the intra-chip and inter-chip dispersion is significantly reduced.

[0067] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0068] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A method for preparing a metal contact layer, characterized in that, The method for preparing the metal contact layer, which is used in semiconductor devices, includes: Provide silicon carbide substrates; Perform at least one deposition process: sequentially deposit a first metal layer and a second metal layer on the back side of the silicon carbide substrate; Perform laser annealing process: The silicon carbide substrate with the first metal layer and the second metal layer deposited is heat-treated using a nanosecond ultraviolet pulsed laser annealing process to form a metal contact layer on the back side of the silicon carbide substrate; the metal contact layer is composed of a composite distribution of low-resistivity silicide and carbide, the low-resistivity silicide is generated by the reaction of the first metal layer, the second metal layer and silicon element in the silicon carbide substrate, and the carbide is generated by the reaction of the second metal layer and carbon element in the silicon carbide substrate; the carbide is distributed in the low-resistivity silicide.

2. The method for preparing the metal contact layer according to claim 1, characterized in that, The specific contact resistance of the metal contact layer is in the range of 1×10⁻⁶. -5 Ω cm 2 -3×10 -5 Ω cm².

3. The method for preparing the metal contact layer according to claim 1, characterized in that, The deposition process is magnetron sputtering; the first metal layer includes a nickel metal layer with a thickness of 100-175 nm; the second metal layer includes a titanium metal layer with a thickness of 25-100 nm.

4. The method for preparing the metal contact layer according to claim 1, characterized in that, The deposition process is atomic layer deposition, in which the first metal layer and the second metal layer are deposited alternately multiple times to form a multi-layered structure; the number of alternating deposition cycles is 10-40 times.

5. The method for preparing the metal contact layer according to claim 1, characterized in that, In the laser annealing process, the nanosecond ultraviolet pulse laser is scanned linearly, the laser spot is Gaussian distributed, and the overlap of adjacent scanning trajectories is 70%-90%.

6. The method for preparing the metal contact layer according to claim 5, characterized in that, The laser annealing process has only one nanosecond isothermal section, the temperature range of which is 1200℃-1500℃ and the duration is tens to hundreds of nanoseconds.

7. The method for preparing the metal contact layer according to any one of claims 1 to 6, characterized in that, The silicon carbide substrates provided include: The back side of the silicon carbide substrate is thinned and cleaned.

8. A metal contact layer structure, characterized in that, The metal contact layer is prepared by the method described in any one of claims 1-7, and the metal contact layer structure is applied to a semiconductor device. The metal contact layer structure includes: silicon carbide substrate; A metal contact layer is located on the back side of the silicon carbide substrate; the metal contact layer is composed of a low-resistivity silicide and a carbide composite.

9. The metal contact layer structure according to claim 8, characterized in that, The initial structure of the metal contact layer includes at least one alternating stacking of a first metal layer and a second metal layer.

10. A semiconductor device, characterized in that, Includes the metal contact layer structure as described in claim 8 or 9.

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