Basepad structure and QFN (Quad Flat No-lead) multi-core sealed chip

Abstract

The invention relates to a base island structure, and belongs to the technical field of chip manufacturing, the base island structure comprises a base layer, a plurality of chip installation layers are arranged on the base layer, preset intervals are reserved between the chip installation layers, and the preset intervals can reduce electromagnetic coupling between the adjacent chip installation layers; the chip mounting layer comprises a chip mounting part and a lead connecting part, and the chip mounting part is connected with the lead connecting part; the preset distance is at least arranged between the adjacent chip mounting parts, between the chip mounting parts and the wiring parts of the lead connecting parts, and between the adjacent lead connecting parts. The packaging structure has the effects of improving the packaging density, reducing the electromagnetic coupling effect and improving the packaging efficiency.

Description

Technical Field

[0001] This application relates to the field of chip manufacturing technology, and in particular to a base island structure and a QFN multi-core packaged chip. Background Technology

[0002] In existing QFN packaging structures, chip mounting is typically performed as follows: a chip is mounted on a base layer (base island), which is then fixed to the central support area of ​​a connection frame. The chip is electrically connected to the peripheral bonding areas of the connection frame via bonding wires, and finally, the entire package is encapsulated by the package housing. With the continuous development of semiconductor manufacturing processes, chip sizes are constantly shrinking, while the external dimensions of QFN packages cannot be reduced in tandem for certain applications. This results in low effective space utilization within the package housing in traditional single-chip QFN packages, with a significant amount of underutilized cavity space. Consequently, package density and integration are limited, making it difficult to meet the demands for miniaturized and high-performance devices.

[0003] To improve the integration and functional density of QFN packages, the industry has proposed a multi-chip co-packaging solution that integrates multiple chips into the same QFN package. However, multiple chips cannot be simply mounted directly on the same substrate, as this can easily lead to electrical interference, wiring conflicts, and reliability issues between chips. Therefore, corresponding improvements are needed to the substrate structure and chip mounting methods.

[0004] One type of multi-chip QFN technology uses a multi-base island mounting configuration, where multiple independent small-sized base layers are set on the lead frame, with each base layer corresponding to a chip. Each base layer is fixed to a different support position on the connecting frame. For example, publication number CN209896055U discloses a QFN package structure for a multi-base island lead frame and a power conversion module. However, this type of multi-base island solution still has the following drawbacks: First, the substrate customization is difficult, requiring the customization of multiple small-sized base layers according to different chip sizes. The smaller the chip size, the higher the requirement for the precision of the base layer processing, significantly increasing the difficulty and cost of substrate manufacturing. Second, the positioning and fixing of multiple small-sized base layers on the lead frame depends on the assembly process, which is prone to positional deviations and increases assembly difficulty. Moreover, multiple base layers need to be installed and fixed one by one, involving many assembly steps, which is not conducive to improving overall production efficiency.

[0005] The multi-chip single-base island structure can overcome the shortcomings of the aforementioned multi-base island schemes. For example, CN103346129A discloses a ceramic package shell and its fabrication method, as well as a chip packaging method. This scheme divides the metal layer into multiple electrically isolated regions by depositing a metal layer on the same ceramic substrate and etching the metal layer to form multiple isolation trenches. Each region is used to install a chip, thereby realizing a single-base island multi-chip encapsulation structure.

[0006] This technical solution simplifies the base structure and assembly process to some extent, but the following problems still exist in practical applications: First, although isolation trenches can electrically divide a metal layer into multiple isolation regions, the spacing between adjacent isolation regions is usually small, resulting in strong electromagnetic coupling between adjacent conductive areas, which easily leads to large distributed capacitance and distributed inductance. This electromagnetic coupling effect becomes more pronounced, especially as the number of isolation regions and chips increases, thus affecting the high-frequency performance and signal integrity of multi-chip packages.

[0007] Secondly, as the bonding wires extend from the chip bonding area to the surrounding bonding areas, they often need to cross the underlying metal isolation area, resulting in a large overlap between the bonding wires and the metal layer, further increasing the distributed capacitance and inductance. This problem becomes particularly prominent when the number of chips and bonding wires increases.

[0008] Furthermore, when bonding wires are bonded to the metal layer, reliable bonding points are typically formed on the metal surface through thermoforming or ultrasonic methods. Due to the high thermal conductivity of the metal layer, heat easily diffuses along the metal layer during the bonding process, resulting in reduced local heating efficiency at the bonding points. This prolongs the bonding time, affects the bonding efficiency, and further reduces the overall packaging production efficiency. Summary of the Invention

[0009] To address the aforementioned issues, this application provides a base island structure and a QFN multi-core packaged chip.

[0010] The base island structure provided in this application adopts the following technical solution: A base island structure includes a base layer, on which a plurality of chip mounting layers are disposed, and a preset spacing is left between the plurality of chip mounting layers, the preset spacing being able to reduce electromagnetic coupling between adjacent chip mounting layers; The chip mounting layer includes a chip mounting portion and a lead connection portion, wherein the chip mounting portion is connected to the lead connection portion; The preset spacing is at least set to: Between adjacent chip mounting portions, between the connection points of the chip mounting portion and the lead connection portion, and between adjacent lead connection portions.

[0011] By adopting the above technical solution, a preset distance is set between chip mounting portions, which can effectively reduce the electromagnetic coupling between adjacent chip mounting portions. Setting a preset distance between the wiring area of ​​the chip mounting portion and its corresponding lead connection portion not only reduces the electromagnetic coupling between the lead connection portion and its connected chip mounting portion, but also reduces the electromagnetic coupling between the lead connection portion and chip mounting portions in adjacent chip mounting layers.

[0012] In this structure, when a chip on one chip mounting section needs to be connected to another chip mounting layer by a lead wire, the lead wire can be directly connected to the wiring area of ​​the lead connection section of the other chip mounting layer. Since there is a preset distance between the wiring area and the adjacent chip mounting section, the area of ​​the metal layer crossed by the lead wire during the connection process is further reduced, which helps to reduce the overall electromagnetic coupling effect.

[0013] Setting a preset spacing between adjacent lead connections can reduce electromagnetic coupling between them. Although adjacent lead connections are not usually directly connected by leads, the above structural design helps to reduce the metal coverage area on the substrate. In multi-chip packages with a large number of leads, it can further reduce the electromagnetic coupling between the leads and the substrate metal layer.

[0014] Furthermore, during wire bonding on the lead connection portion, due to the existence of the preset spacing, the heat generated during the bonding process is mainly transferred to the chip mounting portion along the extension direction of the lead connection portion, reducing the path of heat diffusion in the metal layer through multiple directions, thereby improving the local heating efficiency of the bonding point, which is conducive to shortening the bonding time and thus improving the overall packaging production efficiency.

[0015] Optionally, the lead connection portion includes a first connection segment and a second connection segment, the first connection segment being connected to the chip mounting layer, the first connection segment being connected to the second connection segment, and the second connection segment being separated from the chip mounting layer by the preset distance.

[0016] By adopting the above technical solution, a specific lead connection structure is provided. A preset distance is left between the second connection segment and the chip mounting layer, so that the bonding position of the lead is far away from the chip mounting portion.

[0017] Without increasing the overall size of the substrate, the effective electrical distance between the lead solder joint and the chip mounting part is increased, which helps to reduce the electromagnetic coupling between the lead and the chip mounting part.

[0018] Furthermore, the zigzag connection structure formed by the first and second connecting segments, such as a T-shape or an L-shape, extends the heat conduction path between the welding area and the chip mounting portion, which helps to improve the local heating efficiency of the bonding point, thereby enhancing the stability of wire bonding and packaging production efficiency.

[0019] The lead connection has a simple structure and flexible layout, making it suitable for placement in the chip mounting layer near the surrounding bonding area, which is beneficial for achieving high-density packaging of multiple chips.

[0020] Optionally, the lead connection portion includes at least two third connection segments, one of which is connected to the chip mounting portion, and adjacent third connection segments are connected by a fourth connection segment. All the third connection segments and all the fourth connection segments together form a meandering structure, and the third connection segments and the fourth connection segments are all separated from the adjacent chip mounting layers by the preset spacing.

[0021] By adopting the above technical solution, another specific structural form of the lead wire connection part is provided.

[0022] This lead connection consists of a meandering structure formed by multiple third and fourth connection segments, such as a stepped or S-shaped type, suitable for use in chip mounting layers far from the surrounding bonding areas. The meandering structure allows the lead connection to bypass multiple chip mounting layers while maintaining a preset distance from adjacent layers. This helps reduce electromagnetic coupling between the lead connection and the chip mounting layers. Simultaneously, the segmented structure formed by multiple third and fourth connection segments breaks down the originally long connection path into multiple shorter metal connection segments, which helps reduce the equivalent distributed inductance of the lead connection.

[0023] Furthermore, by connecting the end of the third connection segment near the peripheral bonding area to the peripheral bonding area via a lead, the inner chip mounting layer can achieve electrical connection with the peripheral bonding area with a shorter lead length, thereby further reducing the equivalent inductance of the lead and improving the stability of signal transmission.

[0024] Optionally, parallel leads are connected to the chip mounting layer to form parallel conductive paths on the chip mounting layer.

[0025] By adopting the above technical solution and setting up parallel conductive paths, the equivalent impedance of the conductive paths can be reduced. Under high-frequency or transient signal transmission conditions, parallel conductive paths help reduce the fluctuations in conductive path impedance caused by frequency changes, thereby improving the impedance characteristics during signal transmission. This structure is particularly suitable for long lead connection sections.

[0026] Optionally, the chip mounting portion has an extension portion on the side away from the lead connection portion to which it is connected, the extension portion is connected to the parallel lead, and the parallel lead connected to the extension portion is located on one side of the chip.

[0027] By adopting the above technical solution, the design of the extension can avoid the parallel lead from crossing the top of the chip, thereby reducing the electromagnetic coupling between the parallel lead and the active area of ​​the chip.

[0028] Optionally, a protrusion is provided at the edge of the side of the base layer facing the chip mounting layer. The top surface of the chip mounting layer is lower than the top surface of the protrusion. The leads connecting the chip mounting layer to the peripheral pins and the leads connecting the chip to the peripheral pins both cross the protrusion. Furthermore, the arched parts of the leads connecting the chip mounting layer to the peripheral pins and the leads connecting the chip to the peripheral pins are both located directly above the protrusion. When the chip is mounted on the chip mounting layer, the top surface of the chip is lower than the top surface of the protrusion.

[0029] By adopting the above technical solution, since the top surface height of the protrusion is higher than the top surface height of the chip mounting layer, the arched part of the lead is located directly above the protrusion, making the distance between the arched part of the lead and the protrusion shorter. Before injection molding to form the encapsulation shell, local application of adhesive can be made to the arched part of the lead wire at the protrusion, so that the adhesive can wrap the arched part of the lead wire and bond with the protrusion. The adhesive is less likely to spread to other areas of the substrate, thereby avoiding the adhesive overflowing to the bottom of the substrate or the bonding area with the connecting frame. This can avoid unnecessary contact between the adhesive and the intermediate layer between the substrate and the connecting frame, thereby reducing the risk of delamination. After the lead wire is fixed to the raised part with adhesive, the deformation and displacement of the lead wire arch can be effectively limited, thereby reducing the drift of electrical parameters caused by changes in the position of the lead wire. At the same time, this structure does not require large-area application of adhesive to the entire base surface; only local application of adhesive to the corresponding position of the raised part is needed to effectively fix the lead wire, which helps to reduce the amount of adhesive used and simplify the process.

[0030] Optionally, the protrusion is made of the same material as the base layer, and the protrusion is arranged along the circumference of the base layer to form a frame structure.

[0031] By adopting the above technical solution, a specific protrusion structure is provided.

[0032] The raised portion and the base layer are made of the same material. The middle groove area can be formed by locally etching the base layer. The groove area is used to set the chip mounting layer, and the raised portion is naturally formed around its periphery. Therefore, there is no need to set or assemble independent components, which helps to simplify the processing technology and improve the structural consistency.

[0033] By forming a border structure along the circumference of the substrate, a confining space for accommodating the fixative can be created on the substrate, preventing the fixative from overflowing during the coating process. Under the constraint of the border structure, the fixative layer can be coated entirely on the chip mounting layer, increasing the thickness of the fixative layer without overflow. This allows for simultaneous coverage of the lead arches between the chip mounting layer and the surrounding bonding area, as well as the lead arches between the chip and adjacent chip mounting layers.

[0034] Although this method increases the amount of adhesive used compared to local dispensing, it can simultaneously fix multiple lead arches with a single coating, reducing the number of dispensing operations and improving the efficiency of the packaging process.

[0035] Optionally, the base layer includes a first layer and a second layer, the first layer being disposed on the second layer, the first layer being an insulating and thermally conductive functional layer, and the second layer being a structural layer for bonding with the encapsulation lead structure.

[0036] By adopting the above technical solution, the material of the second layer can be matched with the material of the packaging lead structure, thereby improving the bonding strength and structural stability between the base layer and the packaging lead structure.

[0037] This application also provides a QFN multi-core co-packaged chip using the following technical solution: A QFN multi-core packaged chip, using the above-mentioned base island structure, includes a lead frame and a package housing. The base island structure is mounted on the base island region of the lead frame, and the base island structure is connected to the external connection terminal of the lead frame via leads. The package housing covers the internal connection area of ​​the base island structure and the lead frame, and exposes the external connection terminal of the lead frame to the outside of the package housing.

[0038] By adopting the above technical solution, the QFN packaged chip using the base island structure of this application can balance packaging density, electromagnetic performance, welding efficiency and structural reliability.

[0039] Optionally, the base island structure is connected to the lead frame via nanosilver.

[0040] By adopting the above technical solution, the high thermal conductivity of nano-silver allows heat from the chip on the base island to be rapidly conducted to the lead frame, which helps to reduce the chip's operating temperature and improve heat dissipation efficiency. Simultaneously, the reliable electrical connection formed by nano-silver also helps maintain a low-impedance electrical path between the chip and the lead frame.

[0041] In summary, this application includes at least one of the following beneficial technical effects: 1. Preset spacing can significantly reduce the electromagnetic coupling effect of the base island structure; 2. When wire bonding is performed on the lead connection, due to the existence of the preset spacing, the heat generated during the bonding process is mainly transferred to the chip mounting part along the extension direction of the lead connection, which reduces the path of heat diffusion in the metal layer in multiple directions, thereby improving the local heating efficiency of the bonding point, which is conducive to shortening the bonding time and thus improving the overall packaging production efficiency. 3. By setting up parallel conductive paths, the equivalent impedance of the conductive path can be reduced. Under the conditions of high-frequency signal or transient signal transmission, parallel conductive paths are beneficial to reduce the fluctuation of the conductive path impedance with frequency change, thereby improving the impedance characteristics during signal transmission. 4. After the lead wire is fixed to the protrusion with adhesive, the deformation and displacement of the lead wire at the arched part can be effectively limited, thereby reducing the drift of electrical parameters caused by changes in the position of the lead wire. At the same time, this structure does not require large-area application of adhesive to the entire base surface. Only local application of adhesive to the corresponding position of the protrusion is needed to effectively fix the lead wire, which helps to reduce the amount of adhesive used and simplify the process. 5. The adhesive can wrap around the arched part of the lead wire and bond with the protrusion. The adhesive is not easy to spread to other areas of the substrate, thus avoiding the adhesive from overflowing to the bottom of the substrate or the bonding area with the connecting frame. It can avoid unnecessary contact between the adhesive and the intermediate layer between the substrate and the connecting frame, thereby reducing the risk of delamination. 6. Due to the high thermal conductivity of silver nanoparticles, heat from the chip on the base island can be rapidly conducted to the lead frame, which helps reduce the chip's operating temperature and improves heat dissipation efficiency. Simultaneously, the reliable electrical connections formed by silver nanoparticles also help maintain a low-impedance electrical path between the chip and the lead frame. Attached Figure Description

[0042] Figure 1 This is a structural schematic diagram illustrating the preset spacing in an embodiment of this application.

[0043] Figure 2 This is a schematic diagram illustrating the structure of the chip mounting section in an embodiment of this application.

[0044] Figure 3 This is a schematic diagram illustrating the structure of the first and second layers in an embodiment of this application.

[0045] Figure 4 This is a schematic diagram illustrating the structure of parallel leads in an embodiment of this application.

[0046] Figure 5 This is a structural schematic diagram illustrating the protrusion in an embodiment of this application.

[0047] Figure 6 This is a schematic diagram of the protrusion used to illustrate the frame structure in an embodiment of this application.

[0048] Figure 7 This is a structural schematic diagram illustrating the first setting method of the protrusion block in the embodiments of this application.

[0049] Figure 8 This is a structural schematic diagram illustrating the second arrangement of the protrusion block in an embodiment of this application.

[0050] Figure 9 This is a structural schematic diagram illustrating one of the wiring methods of the chip, chip mounting part, and connection layer in the embodiments of this application.

[0051] Figure 10 This is a schematic diagram illustrating the structure of the encapsulation shell, lead frame, and nano-silver in an embodiment of this application.

[0052] Figure 11 This is a schematic diagram illustrating the structure of thermally conductive adhesive and nano-silver in an embodiment of this application.

[0053] Explanation of reference numerals in the attached drawings: 1. Base layer; 11. First layer; 12. Second layer; 13. Protrusion; 131. Protrusion block; 2. Chip mounting layer; 21. Chip mounting part; 22. Lead connection part; 221. First connection segment; 222. Second connection segment; 223. Third connection segment; 224. Fourth connection segment; 225. Fifth connection segment; 23. Connection layer; 24. Parallel lead; 25. Extension; 3. Preset spacing; 4. Lead frame; 5. Encapsulation shell; 6. Nano silver; 7. Thermally conductive adhesive. Detailed Implementation

[0054] The following is in conjunction with the appendix Figure 1-11 This application will be described in further detail.

[0055] This application discloses a base island structure.

[0056] like Figure 1 The base island structure includes a base layer 1, on which a plurality of chip mounting layers 2 are disposed, and a preset spacing 3 is left between the plurality of chip mounting layers 2. The preset spacing 3 can reduce the electromagnetic coupling between adjacent chip mounting layers 2. like Figure 2 The chip mounting layer 2 includes a chip mounting portion 21 and a lead connection portion 22, and the chip mounting portion 21 is connected to the lead connection portion 22; The preset spacing 3 should be set at least as follows: Between adjacent chip mounting portions 21, between the connection points of chip mounting portions 21 and lead connection portions 22, and between adjacent lead connection portions 22.

[0057] The base layer 1 can be a single-layer structure, a two-layer structure, or even a multi-layer structure. Specifically, in a single-layer structure, the base layer 1 is made of an insulating and thermally conductive material, and metal can be deposited on its top. That is, the base layer 1 can be a ceramic / glass / glass-ceramic / insulating polymer composite material, where the insulating polymer composite material can be engineering plastics such as PEEK and PPS, or it can be an epoxy resin-based composite material. In a two-layer structure, such as... Figure 3 The base layer 1 includes a first layer 11 and a second layer 12. The first layer 11 is made of an insulating and thermally conductive material, the material of which has been described above. The second layer 12 is used to bond with the package lead structure and is made of a conductive and thermally conductive material. The second layer 12 can be made of metal or metal composite materials, such as copper, copper alloys, silver, silver alloys, nickel, nickel alloys, or a composite metal structure formed by stacking multiple metals. In the multilayer structure, the bottom layer can be a metal layer, while the remaining layers can be ceramic layers and insulating polymer composite material layers. The chip mounting layer 2 is made of a conductive and thermally conductive material, generally copper, but can also be silver, aluminum, or other alloys.

[0058] The preset spacing 3 ranges from 100μm to 500μm. It should be noted that the preset spacing 3 described in this invention is not intended to completely eliminate electromagnetic coupling, but rather to significantly reduce electromagnetic coupling to a level that does not affect the normal operation of the chip by increasing the physical spacing between adjacent conductive structures based on the packaging structure and operating frequency conditions.

[0059] The specific value of the preset spacing 3 can be determined comprehensively based on the chip's operating frequency range, the length and width of adjacent conductive structures, the relative orientation between conductive structures, the dielectric constant of the internal medium of the package, and the allowable crosstalk level.

[0060] The chip mounting portion 21 and the lead connection portion 22 can be made of the same metal or different metals. The chip mounting portion 21 and the lead connection portion 22 can be formed using two processes. The first process involves depositing a metal layer on the base layer 1, and then etching the metal layer according to the required number and position of the chip mounting portions 21 and the lead connection portions 22. The second process involves first etching the base layer 1 according to the required number and position of the chip mounting portions 21 and the lead connection portions 22, and then depositing metal into the etched grooves. This can be done by directly depositing a metal layer of the required thickness, or by first depositing a single metal layer and then polishing it until the chip mounting portion 21 and the lead connection portion 22 are exposed. Compared to the second process mentioned above, the first process has a relatively simple process flow, is compatible with the existing ceramic-coated metal substrate preparation process, and has good versatility and process reproducibility; the second process is conducive to the flexible layout of the chip mounting part 21 and the lead connection part 22 according to the specific packaging structure, and is suitable for application scenarios with special requirements for structural integration or local thickness.

[0061] like Figure 2 The preset spacing 3 is at least set between the chip mounting part 21 and the lead connection part 22 at the connection point, referring to the following two forms: In the same chip mounting layer 2, there is a preset spacing 3 between the connection points of the chip mounting part 21 and the lead connection part 22; In different chip mounting layers 2, there is a preset distance 3 between the wiring point of the lead connection part 22 of one chip mounting layer 2 and the chip mounting part 21 of another chip mounting layer 2.

[0062] The preset spacing 3 can also be used to set other non-functional areas, that is, except for the chip mounting part 21 and the lead connection part 22 where the corresponding metal material needs to be retained, all other metal materials are etched.

[0063] According to actual circuit requirements, a connection layer 23 is usually also required on the base layer 1. The connection layer 23 is made of the same material as the chip mounting layer 2 and is formed together in the same process. The connection layer 23 is usually a cubic structure and is also used to mount chips or connect leads to ground. In this case, the chip mounting part 21 and the lead connection part 22 must also have a preset distance 3 between them and the base layer 1.

[0064] like Figure 2 and Figure 4 The lead wire connector 22 has various structural forms: The first type: The lead connection portion 22 includes a first connection segment 221 and a second connection segment 222. The first connection segment 221 is connected to the chip mounting portion 21, and the first connection segment 221 is connected to the second connection segment 222. A preset distance 3 is left between the second connection segment 222 and the chip mounting portion 21. That is, the specific shape formed by the first connection segment 221 and the second connection segment 222 can be L-shaped, T-shaped, or 7-shaped, etc. This lead connection portion 22 structure is simple in form and flexible in layout, and is suitable for placement in the chip mounting layer 2 near the peripheral bonding area.

[0065] The second type: The lead connection portion 22 includes at least two third connection segments 223. One third connection segment 223 is connected to the chip mounting portion 21, and adjacent third connection segments 223 are connected through a fourth connection segment 224. All the third connection segments 223 and all the fourth connection segments 224 together form a meandering structure. A preset spacing 3 is left between each of the third connection segments 223 and the adjacent chip mounting layer 2. That is, the specific shape formed by all the third connection segments 223 and the fourth connection segments 224 can be S-shaped, Z-shaped, stepped, or wave-shaped. This lead connection portion 22 structure is suitable for use in chip mounting layers 2 far from the surrounding bonding area.

[0066] The third type: The lead wire connection part 22 includes a fifth connection segment 225, which is a thin straight line segment. The width and length of the fifth connection segment 225 are smaller than the width and length of the first connection segment 221, the second connection segment 222, the third connection segment 223, and the fourth connection segment 224.

[0067] Parallel leads 24 are connected to the chip mounting layer 2 to form parallel conductive paths on the chip mounting layer 2. This design takes into account that in the structure of the second lead connection part 22, since the overall length of the lead connection part 22 is relatively long and the impedance is relatively large, the equivalent impedance of the conductive path can be reduced by setting the parallel conductive path.

[0068] like Figure 4 Specifically, the parallel lead 24 can be connected in several ways: A parallel lead 24 is led out from the side of the chip mounting portion 21 away from the lead connection portion 22, and the parallel lead 24 is connected to the side of the chip mounting portion 21 near the lead connection portion 22 / the third connection segment 223 / the fourth connection segment 224. A parallel lead 24 is led out from the chip mounting part 21 near the lead connection part 22, and the parallel lead 24 is connected to the third connection segment 223 / fourth connection segment 224; Parallel leads 24 are drawn out from the third connection segment 223 directly connected to the chip mounting section 21, and the parallel leads 24 are connected to other third connection segments 223 / fourth connection segments 224.

[0069] Furthermore, an extension 25 can be provided on the side of the chip mounting portion 21 away from the lead connection portion 22 to which it is connected. The extension 25 connects to the parallel lead 24, and the parallel lead 24 connected to the extension 25 is located on one side of the chip. This further design takes into account that when the parallel lead 24 is led out from the side of the chip mounting portion 21 away from the lead connection portion 22, the parallel lead 24 can be prevented from crossing over the chip, thereby reducing the electromagnetic coupling between the parallel lead 24 and the active area of ​​the chip.

[0070] In existing technologies, to reduce lead length, leads are typically placed around the perimeter of the base island and connected to the surrounding bonding area. The arched portion of the lead is usually located above the base island, meaning its orthographic projection lies within the base island area. This arched portion is the most prone to deformation, displacement, and parameter drift. However, existing base island structures cannot directly fix the arched portion of the lead with adhesive. This is because the arch height of the lead is subject to requirements; directly covering the entire base island surface with an adhesive layer sufficient to cover the lead height would cause the adhesive to overflow to the bottom of the base island where it meets the connecting frame. Since the base island and connecting frame are usually connected via an intermediate layer, the adhesive may react with this intermediate layer, leading to delamination and wasting adhesive.

[0071] Therefore, in order to solve the above problems, such as Figure 5 A protrusion 13 is provided on the edge of the base layer 1 facing the chip mounting layer 2. The top surface of the chip mounting layer 2 is lower than the top surface of the protrusion 13. The leads connecting the chip mounting layer 2 to the peripheral pins and the leads connecting the chip to the peripheral pins both cross the protrusion 13. Furthermore, the arched parts of the leads connecting the chip mounting layer 2 to the peripheral pins and the leads connecting the chip to the peripheral pins are both located directly above the protrusion 13.

[0072] Since the top surface height of the protrusion 13 is higher than the top surface height of the chip mounting layer 2, the arched part of the lead is located directly above the protrusion 13, making the distance between the arched part of the lead and the protrusion 13 shorter. Before injection molding to form the package shell 5, local dispensing of adhesive can be applied to the arched part of the lead at the protrusion 13, so that the adhesive can wrap the arched part of the lead and bond with the protrusion 13. The adhesive is also less likely to spread to other areas of the base layer 1, thereby avoiding the adhesive overflowing to the bottom of the base layer 1 or the bonding area with the connecting frame. This avoids unnecessary contact between the adhesive and the intermediate layer between the base layer 1 and the connecting frame, thereby reducing the risk of delamination. After the arched part of the lead is fixed to the protrusion 13 by the adhesive, the deformation and displacement of the arched part of the lead can be effectively limited, thereby reducing the drift of electrical parameters caused by changes in the position of the lead.

[0073] The specific structure of the protrusion 13 can be divided into two types, such as... Figure 6The first method involves a protrusion 13 forming a frame structure along the circumference of the base layer 1. This structure creates a confining space on the base layer 1 to accommodate the fixative, preventing overflow during coating. Under the constraint of the frame structure, the fixative layer can be applied uniformly to the chip mounting layer 2, increasing its thickness without overflow. This allows simultaneous coverage of the lead arches between the chip mounting layer 2 and the surrounding bonding area, as well as the lead arches between the chip and adjacent chip mounting layers 2. Although this method increases the amount of fixative used compared to localized application, it enables simultaneous fixation of multiple lead arches in a single application, reducing the number of application passes and improving packaging process efficiency.

[0074] There are two processes for the protrusion 13 to form a frame structure. The first process is to locally etch the base layer 1 to form a central groove area. The groove area is used to set the chip mounting layer 2, and the protrusion 13 is naturally formed around the groove. Under this process, the protrusion 13 is made of the same material as the base layer 1, and there is no need to set or assemble independent components. This helps to simplify the processing technology and improve the structural consistency.

[0075] The second process involves forming a raised frame structure around the top surface of the base layer 1 using a deposition process. In this process, the raised portion 13 can be made of a different material than the base layer 1, allowing the material and height of the raised portion 13 to be independently designed and optimized according to the lead wire fixing requirements. For example, the raised portion 13 can be made of a material with high mechanical strength or good adhesion to the fixing adhesive to enhance the support and fixing effect at the lead wire arch; simultaneously, by controlling the deposition process parameters, the height of the raised portion 13 can be precisely adjusted to better match the height of the lead wire arch.

[0076] like Figure 7 and Figure 8 The second type of protrusion 13 has the following specific structural form: the protrusion 13 includes several protrusions 131, which are disposed at the top edge of the base layer 1. The protrusions 131 can be arranged equidistantly along the circumference of the top surface of the base layer 1, and the protrusions 131 can also be arranged according to the number of leads and the position of the arch. The advantage of this design is that the protrusions 131 are only set at the corresponding positions of the lead arch, so that the fixing adhesive can partially cover the lead arch. This reduces the amount of fixing adhesive used while ensuring the lead fixing effect, and avoids large-area coverage of non-critical areas, which helps to reduce the introduction of encapsulation stress and parasitic parameters.

[0077] There are two processes for forming the protrusion 13 into several protrusions 131. The first process is to locally etch the base layer 1 to form multiple protrusions 131. The second process is to deposit multiple protrusions 131 around the top surface of the base layer 1.

[0078] like Figure 10 This application discloses a QFN multi-core packaged chip, employing the aforementioned base island structure, including a lead frame 4 and a package shell 5. The base island structure is mounted on the base island region of the lead frame 4, i.e., the base layer 1 is connected to the lead frame 4 via nano-silver 6. The base layer 1 can be a multi-layer structure, and the bottom layer is made of the same material as the lead frame 4, thereby enabling better bonding between the base layer 1 and the lead frame 4. Furthermore, the base island structure is connected to the external connection terminals (peripheral pins) of the lead frame 4 via leads. The package shell 5 covers the internal connection areas of the base island structure and the lead frame 4, exposing the external connection terminals of the lead frame 4 to the outside of the package shell 5. Example

[0079] Taking the integration of seven chips as an example, Embodiment 1 of this application specifically discloses a base island structure.

[0080] like Figure 9 and Figure 10 A substrate island structure includes a base layer 1, which is a single-layer structure, specifically a ceramic layer. Six chip mounting layers 2 and two connecting layers 23 are disposed on the base layer 1. Both the chip mounting layers 2 and the connecting layers 23 are copper layers, formed by etching the same copper deposition layer. The base layer 1 is divided into three regions: an upper region, a middle region, and a lower region. The two connecting layers 23 and the six chip mounting layers 2 are arranged within these three regions. Two chip mounting layers 2 are arranged in the upper region of the base layer 1, one chip mounting layer 2 and two connecting layers 23 are arranged in the middle region of the base layer 1, and three chip mounting layers 2 are arranged in the lower region of the base layer 1.

[0081] Each chip mounting layer 2 includes a chip mounting portion 21 and a lead connection portion 22; In the two chip mounting layers 2 on the base layer 1, one chip mounting portion 21 is located at the right corner of the base layer 1, and the other chip mounting portion 21 is located in the middle of the base layer 1. The lead connection portions 22 of both chip mounting portions 21 in this area include a first connecting segment 221 and a second connecting segment 222, which are perpendicular to each other, forming an L-shaped structure. The second connecting segment 222 connected to the chip mounting portion 21 at the right corner of the base layer 1 is located between the two chip mounting portions 21 and is spaced 3 apart from both chip mounting portions 21. The other second connecting segment 222 is closer to the side of the base layer 1 than the chip mounting portion 21 in the middle of the base layer 1, and the two are also spaced 3 apart.

[0082] In the chip mounting layer 2 in the middle region of the base layer 1, the chip mounting part 21 is located on the left side of the middle region of the base layer 1, a connecting layer 23 is located on the right side of the middle region of the base layer 1, and another connecting layer 23 is located in the middle region of the base layer 1. The connecting layer 23 in the middle region of the base layer 1 is positioned closer to the lower region of the base layer 1 than the other connecting layer 23 and the chip mounting part 21. A preset distance 3 is maintained between the chip mounting part 21 and the connecting layer 23 in the middle region of the base layer 1, and a preset distance 3 is maintained between the chip mounting part 21 and the connecting layer 23 in the middle region of the base layer 1 and the chip mounting part 21, the first connecting segment 221, and the second connecting segment 222 in the upper region of the base layer 1.

[0083] The lead connection portion 22 connected to the chip mounting portion 21 in the base layer 1 includes two third connection segments 223 and one fourth connection segment 224. The two third connection segments 223 are arranged horizontally, and the fourth connection segment 224 is arranged vertically, forming a Z-shaped structure. One third connection segment 223 is connected to the chip mounting portion 21, and the end of the third connection segment 223 away from the chip mounting portion 21 is connected to the fourth connection segment 224. The other end of the fourth connection segment 224 is connected to another third connection segment 223, so that the end of the third connection segment 223 away from the chip mounting portion 21 is located near the left side of the area in the base layer 1. Furthermore, the third connection segment 223 and the fourth connection segment 224 are all separated from the connection layer 23, the chip mounting portion 21 in the area of ​​the base layer 1, the first connection segment 221, and the second connection segment 222 by a predetermined distance 3.

[0084] Furthermore, a fifth connecting segment 225 is connected to the lower corner of the chip mounting section 21 in the base layer 1, on the side away from the third connecting segment 223.

[0085] Furthermore, the chip mounting portion 21 in the region of the substrate 1 is connected to an extension portion 25, which extends into the right side of the region on the substrate 1 (the metal layer on the right side of the region on the substrate 1 is completely etched). A parallel lead 24 is connected to the extension portion 25, and the other end of the parallel lead 24 is connected to the side of the chip mounting portion 21 near the third connecting segment 223, and this parallel lead 24 is located on one side of the chip. In addition, another parallel lead 24 is also connected to the side of the chip mounting portion 21 near the third connecting segment 223, and the other end of this other parallel lead 24 is connected to the fourth connecting segment 224.

[0086] Of the three chip mounting portions 21 in the lower region of the substrate 1, the three chip mounting portions 21 are located on the left, middle, and right sides of the lower region of the substrate 1, respectively. The lead connection portions 22 connected to the chip mounting portions 21 located on the left and middle sides of the lower region of the substrate 1 each include a first connecting segment 221 and a second connecting segment 222, which are perpendicular to each other and form an L-shaped structure. The lead connection portion 22 connected to the chip mounting portion 21 located on the right side of the lower region of the substrate 1 also includes a first connecting segment 221 and a second connecting segment 222, which are perpendicular to each other and form a T-shaped structure.

[0087] The second connecting segment 222 and the first connecting segment 221 connected to the chip mounting portion 21 on the left side of the lower region of the substrate 1 are located between the chip mounting portion 21 on the left side of the lower region of the substrate 1 and the chip mounting portion 21 in the middle of the lower region of the substrate 1. The second connecting segment 222 and the first connecting segment 221 connected to the chip mounting portion 21 in the middle of the lower region of the substrate 1 are located between the chip mounting portion 21 in the middle of the lower region of the substrate 1 and the chip mounting portion 21 on the right side of the lower region of the substrate 1. The second connecting segment 222 and the first connecting segment 221 connected to the chip mounting portion 21 on the right side of the lower region of the substrate 1 are located between the chip mounting portion 21 on the right side of the lower region of the substrate 1 and the chip mounting portion 21 on the right side of the middle region of the substrate 1.

[0088] This ensures that the first connecting segment 221 and the second connecting segment in the lower region of the base layer 1 are all separated from the connecting layer 23, the chip mounting part 21 in the middle region of the base layer 1, the third connecting segment 223 in the middle region of the base layer 1, the fourth connecting segment 224 in the middle region of the base layer 1, the fifth connecting segment 225 in the middle region of the base layer 1, and the chip mounting part 21 in the lower region of the base layer 1 by a preset distance 3.

[0089] Seven chips are respectively mounted on the chip mounting part 21 on the right side of the upper region of the base layer 1, the chip mounting part 21 in the middle of the upper region of the base layer 1, the connecting layer 23 in the middle of the middle region of the base layer 1, the connecting layer 23 on the right side of the middle region of the base layer 1, the chip mounting part 21 on the left side of the lower region of the base layer 1, the chip mounting part 21 in the middle of the lower region of the base layer 1, and the chip mounting part 21 on the right side of the lower region of the base layer 1 using thermally conductive adhesive 7.

[0090] Embodiment 1 of this application also specifically discloses a QFN multi-core packaged chip.

[0091] A QFN multi-chip package, employing the base island structure of Embodiment 1 of this application, includes a lead frame 4 and a package shell 5. A base layer 1 is mounted on the base island region of the lead frame 4 using nano-silver 6. The external connection terminals of the lead frame 4 are connected to the corresponding chip, connection layer 23, second connection segment 222, third connection segment 223, and fifth connection segment 225 via gold wires. The package shell 5 covers the base island structure and the internal connection region of the lead frame 4, exposing the external connection terminals of the lead frame 4 to the outside of the package shell 5. The specific connection method of the gold wires between the chip, connection layer 23, second connection segment 222, third connection segment 223, and fifth connection segment 225 can be determined according to the circuit and chip functional module division. Figure 9 A schematic diagram of a connection is disclosed in the document. Example

[0092] Reference Figure 8 and Figure 11 The difference between this embodiment and embodiment 1 is that a protrusion 13 is provided on the edge of the base layer 1 facing the chip mounting layer 2. The protrusion 13 is arranged along the circumference of the base layer 1 to form a frame structure. The protrusion 13 is formed by etching grooves into the base layer 1.

[0093] The top surface of the chip mounting layer 2 and the top surface of the chip are both lower than the top surface of the protrusion 13. The gold wires connecting the chip mounting layer 2 to the external connection end of the lead frame 4 and the gold wires connecting the chip to the peripheral pins all cross the protrusion 13. Furthermore, the arched parts of the leads connecting the chip mounting layer 2 to the peripheral pins and the leads connecting the chip to the peripheral pins are both located directly above the protrusion 13. Thermally conductive adhesive 7 is poured onto the base layer 1, completely covering the chip, the chip mounting portion 21, the parallel leads 24, and the internally connected gold wires. It also covers the arched parts (the raised parts) of the gold wires connecting the base island structure to the external connection section of the lead frame 4.

[0094] The base layer 1 includes a first layer 11 and a second layer 12. The first layer 11 is a ceramic layer, and the second layer 12 is a metal layer of the same material as the lead frame 4. The second layer 12 is connected to the lead frame 4 through nano silver 6.

[0095] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A base island structure, characterized in that: Includes a base layer (1), on which a plurality of chip mounting layers (2) are provided, and a preset spacing (3) is left between the plurality of chip mounting layers (2), the preset spacing (3) can reduce the electromagnetic coupling between adjacent chip mounting layers (2); The chip mounting layer (2) includes a chip mounting portion (21) and a lead connection portion (22), wherein the chip mounting portion (21) is connected to the lead connection portion (22); The preset spacing (3) is at least set to: Between adjacent chip mounting portions (21), between the connection points of the chip mounting portion (21) and the lead connection portion (22), and between adjacent lead connection portions (22).

2. The base island structure according to claim 1, characterized in that: The lead connection part (22) includes a first connection segment (221) and a second connection segment (222). The first connection segment (221) is connected to the chip mounting part (21), and the first connection segment (221) is connected to the second connection segment (222). The second connection segment (222) and the chip mounting part (21) are separated by the preset distance (3).

3. The base island structure according to claim 1, characterized in that: The lead connection portion (22) includes at least two third connection segments (223), one of the third connection segments (223) is connected to the chip mounting portion (21), and adjacent third connection segments (223) are connected by a fourth connection segment (224). All the third connection segments (223) and all the fourth connection segments (224) together form a meandering structure. The third connection segments (223) and the fourth connection segments (224) are all separated from the adjacent chip mounting layer (2) by the preset spacing (3).

4. The base island structure according to claim 3, characterized in that: Parallel leads (24) are connected to the chip mounting layer (2) to form parallel conductive paths on the chip mounting layer (2).

5. The base island structure according to claim 4, characterized in that: The chip mounting portion (21) has an extension portion (25) on the side away from the lead connection portion (22) connected to it. The extension portion (25) is connected to the parallel lead (24), and the parallel lead (24) connected to the extension portion (25) is located on one side of the chip.

6. The base island structure according to claim 1, characterized in that: The base layer (1) has a protrusion (13) on the edge facing the chip mounting layer (2). The top surface of the chip mounting layer (2) is lower than the top surface of the protrusion (13). The leads connecting the chip mounting layer (2) to the peripheral pins and the leads connecting the chip to the peripheral pins both cross the protrusion (13). The arched parts of the leads connecting the chip mounting layer (2) to the peripheral pins and the leads connecting the chip to the peripheral pins are both located directly above the protrusion (13). When the chip is mounted on the chip mounting layer (2), the top surface of the chip is lower than the top surface of the protrusion (13).

7. The base island structure according to claim 6, characterized in that: The protrusion (13) is made of the same material as the base layer (1), and the protrusion (13) is arranged along the circumference of the base layer (1) to form a frame structure.

8. The base island structure according to claim 1, characterized in that: The base layer (1) includes a first layer (11) and a second layer (12). The first layer (11) is disposed on the second layer (12). The first layer (11) is an insulating and thermally conductive functional layer, and the second layer (12) is a structural layer for bonding with the encapsulation lead structure.

9. A QFN multi-core packaged chip, characterized in that: The base island structure according to any one of claims 1-8 includes a lead frame (4) and a package housing (5), the base island structure is mounted on the base island region of the lead frame (4), and the base island structure is connected to the external connection end of the lead frame (4) via leads, the package housing (5) covers the internal connection area of ​​the base island structure and the lead frame (4), and exposes the external connection end of the lead frame (4) to the outside of the package housing (5).

10. The QFN multi-core packaged chip according to claim 9, characterized in that: The base island structure is connected to the lead frame (4) via nanosilver (6).

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