Integrated device package

Abstract

In one embodiment, an integrated device package is disclosed. The integrated device package may include a carrier and a molding compound over a portion of an upper surface of the carrier. The integrated device package may include an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die including active circuitry. The integrated device package may include a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element including a dummy stress compensation element without active circuitry. At least one of the stress compensating element and the integrated device die may be directly bonded to the carrier without an adhesive.

Description

Case Analysis

[0001] This application is a divisional application of Chinese invention patent application No. 202180055333.2, filed on June 23, 2021, entitled "Integrated Device Package". Priority requirements

[0002] This application claims priority to U.S. nonprovisional patent application No. 16 / 917,686, filed June 30, 2020, the entire contents of which are incorporated herein by reference in their entirety and for all purposes. Technical Field

[0003] This field relates to integrated device packages and methods for forming the same. Background Technology

[0004] In various package arrangements, it can be advantageous to arrange multiple integrated device dies within a package, such as a system-in-package (SIP). For example, some packages include different types of active chips or integrated device dies spaced apart from each other along the package substrate. Furthermore, three-dimensional (3D) integration techniques often utilize packages in which two or more integrated device dies are stacked on top of each other and electrically connected. Molding compounds or encapsulations can be applied over the integrated device dies, which can generate stress within the package. Therefore, there remains a continuous need for improved integrated device packages. Attached Figure Description

[0005] These and other aspects will become apparent from the following description of preferred embodiments and accompanying drawings, which are intended to illustrate rather than limit the invention.

[0006] Figures 1A to 1C The illustrations illustrate the use of sacrificial carriers in various direct bonding processes.

[0007] Figure 2 The illustration shows multiple components directly bonded to the carrier.

[0008] Figures 3A to 3C Various examples are shown in which components are directly bonded to a carrier without adhesive.

[0009] Figure 4A It is a schematic side view of multiple elements directly bonded to a carrier, wherein protective material is applied over the elements and in the gaps between the elements.

[0010] Figure 4B It is a schematic side view of multiple elements including one or more dummy elements directly bonded to the carrier.

[0011] Figures 5A to 5C The diagram illustrates a series of processing steps used to form a reconstructed wafer.

[0012] Figure 6 It is a schematic side cross-sectional view of a reconstructed wafer having a bonding layer configured to be directly bonded to another reconstructed wafer or substrate.

[0013] Figure 7A The illustration shows two opposing reconstructed wafers prior to direct bonding.

[0014] Figure 7B The illustration shows two opposite reconstructed wafers after they have been directly bonded together.

[0015] Figures 8A to 8B The illustrations depict methods and structures for stacking two or more reconfigurable wafers according to various embodiments.

[0016] Figures 9A to 9F Various face-up bonding structures according to various embodiments are illustrated.

[0017] Figures 10A to 10E Various face-down bonding structures according to various embodiments are illustrated.

[0018] Figure 11 The illustration shows another embodiment in which additional filler material can be used as a second protective material and can provide conformal protective material over the gap between adjacent elements.

[0019] Figures 12A to 12C The illustrations depict methods for forming a reconstructed wafer according to various embodiments.

[0020] Figures 13A to 13B The illustrations depict methods for forming a reconstructed wafer according to various embodiments.

[0021] Figures 14A to 14C Another embodiment is illustrated in which a molding compound can be provided between adjacent elements directly bonded to the carrier, and a metal can be provided on the molding compound.

[0022] Figures 15A to 15C The illustration shows another embodiment in which a molding compound can be provided between adjacent elements directly bonded to the carrier and metals can be provided on both sides of the molding compound.

[0023] Figures 16A to 16C Another embodiment in which a protective coating or layer can be provided between the molding compound and the carrier is illustrated.

[0024] Figures 17A to 17D The diagram illustrates an additional bonding structure that can be provided using the methods disclosed herein.

[0025] Figure 18AThis is a schematic side cross-sectional view of an integrated device package according to another embodiment.

[0026] Figure 18B yes Figure 18A A schematic top view of the integrated device package, with the molding compound hidden for clarity.

[0027] Figure 18C It is a schematic top plan view of an integrated device package that includes increased lateral overlap between stress-compensating elements.

[0028] Figure 19 This is a schematic diagram of a system comprising one or more bonding structures according to various embodiments. Detailed Implementation

[0029] The various embodiments disclosed herein relate to bonding structures including a first element (e.g., a first integrated device die) having a first side and a second side opposite to the first side. The bonding structure may include a second element (e.g., a second integrated device die) having a first side and a second side opposite to the first side. The first side of the second integrated device die may be directly bonded to the first side of the first integrated device die without an intermediate adhesive along the bonding interface. A protective material may be disposed around the periphery (e.g., corresponding sidewalls) of the first and second integrated device dies. The protective material may extend from the second side of the first integrated device die to the second side of the second integrated device die. In various embodiments, portions of the protective material may be disposed within the gap between adjacent first integrated device dies or elements. In some embodiments, the protective material may include an inorganic dielectric, such as silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon, etc.

[0030] The embodiments disclosed herein may include a wafer-level process in which a wafer or substrate serving as a carrier is provided with multiple integrated device dies and a protective material (which may include one or more protective layers) above the integrated device dies. The dies and protective material may form at least a portion of a reconstructed wafer, which may be bonded (e.g., directly bonded without adhesive) to another reconstructed wafer formed by a similar process. For example, after removing the carrier, the bonded reconstructed wafers may be monolithized to form multiple bonded structures. In some embodiments, the bonded structures may include package structures. Direct bonded interconnects or DBIs, as used herein, are examples. ® It may include a bonding structure in which densely dispersed conductive contacts are bonded to each other without an intermediate binder. In various embodiments, the surrounding dielectric or non-conductive material may also be directly bonded without an intermediate binder. ZiBond ®The process can include direct bonding between non-conductive materials without an intermediate binder. Examples of DBI and ZiBond processes and structures can be found at least in U.S. Patent Nos. 9,391,143; 10,141,218; 10,147,641; 9,431,368; and 7,126,212, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes. Each monolithic die mounted on the carrier can be tested prior to mounting, such that all dies in the reconstructed wafer can be known good dies (KGD).

[0031] Figures 1A to 1C The use of the sacrificial carrier 3 in various direct bonding processes is schematically illustrated. As shown in the figure, in some embodiments, element 2 can be directly bonded to carrier 3 without adhesive. Throughout this application, element 2 (or any other element described herein) can include any suitable type of element, such as semiconductor elements (e.g., integrated device dies), optical elements, etc. Carrier 3 can include any suitable type of carrier, such as a carrier having one or more logic or processing devices, and / or a sacrificial carrier that will be removed at some point during processing (e.g., a carrier without an active processing circuitry system).

[0032] Component 2 may include a front surface 9 and a rear surface 10 opposite to the front surface 9. In various embodiments, the front surface 9 may include the surface closest to the active circuitry or device formed in component 2. A first front bonding layer 4 may be disposed on the front surface 9 of component 2. Although the bonding layer 4 is shown on the front surface 9 of component 2, the bonding layer may also or alternatively be provided on the rear surface 10 for bonding. The bonding layer 4 may include one or more contact pads 6 disposed within or surrounded by a non-conductive field region 5. In some embodiments, the contact pads may include copper, although other conductive materials are also suitable. In some embodiments, the non-conductive field region may include a dielectric, such as silicon oxide, silicon nitride, etc. The rear surface 10 may or may not include active circuitry or devices. In various embodiments, component 2 may include a monolithic component (such as a monolithic device die) having a side surface 8. The side surface 8 may include markings indicating the monolithic process, such as saw marks, etch patterns, etc.

[0033] As stated above, and as Figure 1AAs shown, element 2 (e.g., a bare die) can be directly bonded to carrier 3 without an intermediate binder along bonding interface 12. As described above, pre-bonding layer 4 can prepare for bonding. For example, pre-bonding layer 4 can be polished to a very low surface roughness and treated to enhance direct dielectric-to-dielectric bonding. In some embodiments, the surfaces to be bonded can be terminated with a suitable material and activated prior to bonding. For example, in some embodiments, the surfaces to be bonded can be very lightly etched for activation and exposed to a nitrogen-containing solution and terminated with a nitrogen-containing material. As an example, the surfaces to be bonded can be exposed to ammonia immersion and / or nitrogen-containing plasma (with or without separate etching) after very light etching.

[0034] Once the surfaces are prepared, the non-conductive field region 5 of element 2 can contact the corresponding non-conductive region of carrier 3. The interaction of the activated surfaces can result in direct bonding between the non-conductive region 5 of element 2 and the corresponding non-conductive region of carrier 3 without intermediate adhesive, external pressure, voltage, and at room temperature. In various embodiments, the bonding force of the non-conductive regions can be a covalent bond greater than a van der Waals bond. In some embodiments, only the non-conductive field region of element 2 is directly bonded to the corresponding non-conductive region of carrier 3. However, in other embodiments, the contact pads 6 of element 2 can be directly bonded to the corresponding conductive contacts of carrier 3, and the non-conductive region 5 can also be directly bonded to the non-conductive region of carrier 3. In such embodiments, direct bonding of the contacts can improve the alignment of element 2 relative to carrier 3. In the embodiments disclosed herein, using direct bonding can reduce movement during assembly compared to implementations utilizing intermediate adhesive.

[0035] like Figure 1B As shown, the protective material 7 can be applied over at least a portion of the element 2, including at least the periphery or side surface 8 of the element 2. In some embodiments, the protective material 7 can be deposited along the side surface 8 and deposited on the upper surface of the carrier 3. The protective material 7 can include one or more protective layers, including one or more inorganic layers, such as silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, metal, etc.

[0036] like Figure 1CAs shown, the carrier 3 can be removed from element 2 and protective material 7 in any suitable manner. In the illustrated embodiment, the carrier 3 may comprise a silicon substrate or element having a nano-oxide layer 11, which, as used herein, may comprise at least one of a natural silicon oxide layer and a thermally oxidized silicon oxide layer. Each of the embodiments disclosed herein may utilize such a carrier having a nano-oxide layer 11. In some embodiments, the silicon nano-oxide layer 11 may be used as an etch stop layer to selectively etch the carrier 3 during the carrier removal process. In some embodiments, at least a portion of the nano-oxide layer 11 may be retained after the silicon substrate of the carrier 3 has been removed. In other embodiments, the entire carrier 3 (e.g., silicon substrate and nano-oxide layer 11) may be removed. In embodiments utilizing the nano-oxide layer 11, element 2 may be planarized for bonding, but carrier 3 may not be planarized prior to direct bonding. In other embodiments, both element 2 and carrier 3 may be planarized for direct bonding. Direct bonding and subsequent removal of carrier 3 as described herein can advantageously leave a flat surface for reconstructed wafers for further desired processing, including for additional direct bonding processes. In contrast, reconstructed wafers formed on sacrificial or temporary adhesive layers (e.g., tape or film) cannot reliably provide a flat surface, thus leading to subsequent alignment problems, such as direct bonding of dies subsequently used for stacking. Such stacks with direct bonding can be achieved by directly bonding individual second dies to the first reconstructed wafer, or by simultaneously bonding multiple second dies to the second reconstructed wafer.

[0037] Advantageously, Figures 1A to 1C Examples of this approach can enable the reconstruction of wafers used for direct bonding with improved alignment accuracy. For example, although in Figures 1A to 1C Only one element 2 or die is shown, but it should be understood that an array of multiple dies can be provided, as shown below. In other applications where an adhesive is used to bond element 2 (e.g., a die) to a carrier 3, element 2 or the die may become misaligned relative to the carrier 3 due to adhesive movement or migration, for example, during or after heating, or during placement for bonding. Such misalignment can lead to misalignment in subsequent bonded structures and negatively impact the performance of the bonded structures. The embodiments disclosed herein can advantageously reduce misalignment by providing a direct bonded interconnection with the carrier 3, which can be used to effectively secure element 2 or the die relative to the carrier 3 for subsequent processing, such as providing a protective material 7 (inorganic or organic) over element 2, or any other suitable processing.

[0038] Figure 2 The illustration shows multiple elements 2 directly bonded to a carrier 3 (such as a wafer). Unless otherwise stated, Figure 2 The reference numerals in the figures can indicate the same as those in the figures below. Figures 1A to 1CComponents with the same number are identical or substantially similar. Figure 2 In this context, each component 2 may include one or more conductive vias 13 connected to the back of the corresponding contact pad 6. For example... Figure 2 As shown, conductive vias can initially extend upwards from the contact pads and terminate within the body of component 2. After direct bonding, the die or component 2 can be diced or monolithized into multiple diced or monolithized components 2. As explained herein, removing the silicon substrate using the nano-oxide layer 11 leaves a substantially smooth surface for subsequent direct bonding.

[0039] Figures 3A to 3C Various examples are shown in which element 2 (e.g., integrated device die) is directly bonded to carrier 3 (e.g., silicon substrate with nano-oxide layer 11) without intermediate binder. Figure 3A The diagram illustrates the relatively wide spacing or gap G between elements 2, while Figure 3B The diagram illustrates the relatively narrow spacing or gap G between elements 2. Figure 3C The illustration shows an additional dummy element 2' or die disposed between the active element 2 or die, with a relatively narrow gap G between them. Provided as... Figure 3B and Figure 3C The narrow gap G shown can advantageously reduce the amount of protective material 7 used to fill the gap G in subsequent steps and enable conformal filling of the gap G. Furthermore, as Figure 3A and Figure 3B As shown, one or more alignment features 14 may be provided on the upper surface of the carrier 3. The alignment features 14 may be selectively positioned on the carrier 3 to assist in the precise placement of the element 2.

[0040] Figure 4A This is a schematic side view of multiple elements 2 directly bonded to the carrier 3, with protective material 7 applied over the elements 2 and within the gap G between the elements 2. Figure 4A In the diagram, element 2 is shown entirely as an active integrated device die. Figure 4B In this context, some components include dummy components 2', such as passive blocks of semiconductor materials (e.g., silicon). Figure 4A and Figure 4B In this process, a protective layer 7 (such as an inorganic protective layer) may be disposed on a portion of the element 2, including a portion of the periphery surrounding the gap G (such as the side surface 8) and the upper surface of the element 2 (in the... Figures 4A to 4B The middle section is above the section 10). Seams 15, such as gaps or breaks, may exist in the protective material 7.

[0041] The protective layer 7 may include one or more protective layers, including, for example, inorganic or organic protective layers. In the illustrated embodiments, for example, the protective layer 7 may include one or more inorganic layers, such as silicon oxide, silicon nitride, polycrystalline silicon, amorphous silicon, or metal. In other embodiments, at least a portion of the protective material 7 may include an organic material, such as a molding compound or epoxy resin. In some embodiments, the protective material 7 includes both a conformal layer and a gap-filling layer. Advantageously, the protective material 7 may assist in securing the element 2 to the carrier 3 so that the element 2 does not shift during subsequent direct bonding. The protective material 7 may also assist in protecting the element 2 during polishing and other processing techniques to prevent damage to the die (e.g., breakage). Examples of structures and processes for providing a protective material 7 on and between adjacent directly bonded dies on a carrier are disclosed in U.S. Patent No. 10,204,893, which is incorporated herein by reference in its entirety.

[0042] Figures 5A to 5C The illustration depicts a series of processing steps for forming the reconstructed wafer 20. In subsequent steps, the reconstructed wafer 20 can be bonded (e.g., directly bonded) to another reconstructed wafer 20 or other substrates. Figure 5A In this process, the upper surface of the conformal protective material 7 can be removed, for example, by etching, grinding, polishing, etc. In some embodiments, removing the protective material 7 may also remove a portion of the rear end 10 of the element 2. In other embodiments, the removal step may be performed by sealing the rear end 10 of the element 2.

[0043] Go to Figure 5B A portion of element 2 can be removed from the rear 10' by etching, grinding, chemical mechanical polishing (CMP), or any other suitable method to form a thinned rear 10' of element 2. For example... Figure 5A As shown, this removal step can expose the conductive substrate via (TSV) 13 or other electrical interconnects formed within the device. The removal step can also form a cavity 16 at least partially defined by the thinned rear end 10' of the device 2 and the sidewalls of the protective material 7. Figure 5C In this embodiment, a non-conductive layer 18 (e.g., a second oxide layer) may be disposed (e.g., deposited) around the thinned rear 10' of element 2 and the exposed via 13. In some embodiments, the provided non-conductive layer 18 (e.g., silicon oxide) may be ground or polished to create a flat surface and ensure that the non-conductive layer 18 is substantially flat relative to the exposed end of the via 13 and the protective material.

[0044] exist Figure 5C In this configuration, the reconstructed wafer 20 may include a front surface 22 configured to bond (e.g., directly bond) to another reconstructed wafer or other type of substrate. The reconstructed wafer 20 may also include a rear surface 23. Figure 5C In the reconstructed wafer 20, the protective material 7 can be disposed between adjacent elements 2 and can extend from the front surface 22 of the reconstructed wafer 20 to the upper surface of the carrier 3. A vertical interface 19 can be defined between the non-conductive layer 18 above the element 2 and the protective material 7. Similarly, a vertical interface 21 can be defined between the bonding layer 4 and the protective material 7.

[0045] Figure 6 This is a schematic side cross-sectional view of a reconstructed wafer having a second bonding layer 4b configured to be directly bonded to another reconstructed wafer or substrate. Figure 6 middle, Figure 1A The first bonding layer 4, contact 6, and non-conductive field region 5 in Figure 5 have been correspondingly renumbered as reference numerals 4a, 6a, and 5a. For example... Figure 6 As shown, in some embodiments, a second bonding layer 4b may be provided over the non-conductive layer 18 (e.g., a second oxide layer), such as a DBI layer having alternating conductive contacts 6b and non-conductive bonding portions (e.g., field regions 5b), to facilitate additional bonding connections, and, if necessary, to provide bonding pads for easy DBI alignment. Therefore, in Figure 6 In this configuration, the second bonding layer 4b may extend across multiple (e.g., all) elements 2 of the reconfigured wafer 20. Horizontal interfaces 19 may be formed between the second bonding layer 4b and the non-conductive layer 18, and between the second bonding layer 4b and the underlying protective material 7.

[0046] exist Figures 7A to 7B In this configuration, two opposing reconstructed wafers 20a and 20b can be provided and directly bonded to form a bonded reconstructed wafer 1'. Reference numerals "a" or "b" have been added to indicate their corresponding association with reconstructed wafers 20a or 20b. Figure 7A The illustration shows two opposing reconstructed wafers 20a and 20b prior to direct bonding. Figure 7B The illustration shows two opposing reconstructed wafers 20a and 20b after being directly bonded to each other. Direct bonding of the die to the conductive and non-conductive surfaces on the carriers 3a and 3b provides the desired flatness at the die bonding surfaces. However, in other embodiments, carriers may not be used, and alternatively, the reconstructed wafer may include elements (e.g., dies) that are at least partially embedded in a molding compound or encapsulation without the use of a carrier. Figure 7BIn this configuration, non-conductive protective layers can be directly bonded to each other along bonding interface 12 without adhesive. Other non-conductive field regions of the reconstructed wafers 20a and 20b (such as non-conductive field regions 5a and 5b of bonding layers 4a and 4b, and one or more non-conductive layers 8, etc.) can also be bonded to each other using adhesive. Furthermore, conductive contacts 6a and 6b can be directly bonded without adhesive. In some embodiments, some or all of the conductive contacts 6a and 6b may initially be recessed relative to the bonding surface. The bonded wafers 20a and 20b can be heated to cause the contacts 6a and 6b to expand and form electrical contacts. After heating, the interface between contacts 6a and 6b may not be in the same plane as bonding interface 12.

[0047] like Figures 8A to 8B As shown, additional reconstructed wafers 20a, 20b can be provided to provide any number of stacked reconstructed wafers 1'. The stacked reconstructed wafers 1' can be monolithized along the monolithization track S to provide multiple bond structures 1. Any suitable number of reconstructed wafers 20a, 20b can be provided to form the stacked reconstructed wafers 1', or the stacked reconstructed wafers can be monolithized to form any suitable number of bond structures 1. Monolithization can occur before (if sacrificed) the removal of the carrier 3 as shown in the figure, or after monolithization. In some embodiments, as Figure 8A As shown, carriers 3a and 3b may not be removed before monolithization. In some embodiments, such as Figure 8B As shown, one carrier 3a can be removed before monolithization. In other embodiments, both carriers 3a and 3b can be removed before monolithization. As explained herein, removing carriers 3a and / or 3b using, for example, an etching process can leave a nano-oxide layer 11 to facilitate further direct bonding.

[0048] Figures 9A to 9F and Figures 10A to 10E The illustration shows various face-up or face-down bonding structures that can be obtained by the methods described herein. Figures 9A to 9F and Figures 10A to 10E The bonding structure 1 shown may include a monolithic reconfigurable element 24, such as a monolithic reconfigurable integrated device die. According to various embodiments, for illustrative purposes, in Figure 9A , Figure 9E and Figure 9F The diagram illustrates the monolithic reconfigurable element 24 to show what structures can be produced by the monolithic reconfigurable wafer 20. For example... Figures 9A to 9F and 10A to Figure 10EAs shown, the surface closest to the active circuit system or device can be the front surface 22 of the bonding structure 1, while the surface opposite to the front surface 22 can be the rear surface 23. Unlike individually picked-up and placed dies or components, the directly bonded reconstructed element 24 of the illustrated embodiment can have coplanar side surfaces and a direct bonding interface 12 between the conductive (e.g., metallic) and non-conductive (e.g., inorganic dielectrics such as oxides, including nitrogen and / or fluorine content to aid direct bonding) surfaces of the reconstructed element 24 without an intermediate adhesive.

[0049] Figures 9A to 9F The illustration shows an example of a face-down bonding structure. Go to... Figure 9A The monolithic reconfigurable element 24 may include element 2, a non-conductive layer 18 disposed on the thinned rear surface 10' of element 2, and bonding layers 4a and 4b respectively at the front surface 22 and the rear surface 23. Figure 9A As shown, the protective material 7 can extend from the rear 23 to the front 22 of the reconfigurable element 24. Therefore, in Figure 9A In some embodiments, the monolithic reconfigurable element 24 may have sidewalls 25 defined by the external exposed surface of the protective material. A vertical interface 26 may be defined between the protective material 7 and element 2, the non-conductive layer 8, and the first bonding layer 4a and the second bonding layer 4b. Figure 9A In this arrangement, the protective material 7 is correspondingly adjacent to the bonding layers 4a and 4b, which can be applied prior to the provision of the protective material 7. In other embodiments, such as bonding... Figure 6 As explained, one or more of the bonding layers 4a, 4b may extend over the protective material 7, such that the sidewall 25 includes the protective material 7 and the side edges of the bonding layers 4a and / or 4b.

[0050] Figure 9B The illustration shows that the front surface 22a of the reconfigurable element 24a is directly bonded to the rear surface 23b of the reconfigurable element 24b without intermediate adhesive to form a front-to-back bonding arrangement of the bonding structure 1. Figure 9B In this process, the first portion 7a of the protective material can extend from the rear surface 23a of the reconstructed element 24a to the bonding interface 12. The second portion 7b of the protective material can extend from the bonding interface 12 to the front surface 22b of the reconstructed element 24b.

[0051] Figure 9C The illustration shows that the front surface 22a of the reconfigurable element 24a is directly bonded to the rear surface 23a of the reconfigurable element 24b without intermediate adhesive to form a front-to-front bonding arrangement of the bonding structure 1. Figure 9CIn this process, the first portion 7a of the protective material can extend from the rear surface 23a of the reconstructed element 24a to the bonding interface 12. The second portion 7b of the protective material can extend from the bonding interface 12 to the rear surface 23b of the reconstructed element 24b.

[0052] Figure 9D The illustration shows that the rear surface 23a of the reconfigurable element 24a is directly bonded to the rear surface 23b of the reconfigurable element 24b without intermediate adhesive to form a rear-to-rear bonded arrangement of the bonding structure 1. Figure 9D In this process, the first portion 7a of the protective material can extend from the front surface 22a of the reconstructed element 24a to the bonding interface 12. The second portion 7b of the protective material can extend from the bonding interface 12 to the front surface 22b of the reconstructed element 24b.

[0053] Figure 9E and Figure 9F The illustration shows another example of a monolithic reconfigurable element 24 utilizing the second protective layer 40. This can be achieved, for example... Figures 11 to 12C Find information about formation Figure 9E and Figure 9F Further details regarding the method for reconstructing element 24. For example, in Figure 9E In one embodiment, the second protective material 40 may be applied over the protective material 7. Figure 9E In this configuration, the second protective material 40 may be exposed at the rear surface 23 of the reconfigurable element 24 adjacent to the bonding layer 4b. Furthermore, the protective material 7 may be exposed at the front surface 22 adjacent to the bonding layer 4a and below the second protective layer 40. Therefore, in... Figure 9E In the middle, the sidewall 25 may include a horizontal interface 42 between the first protective material 7 and the second protective material 25. In addition, at the rear surface 23, a vertical interface 41 may be provided between the first protective material 7 and the second protective material 25.

[0054] exist Figure 9F In some embodiments, the second protective material 40 may also be applied over the protective material 7. However, compared with... Figure 9E The implementation methods differ, in Figure 9F In this process, a third protective layer 43 can be provided on top of the second protective material 40. The third protective layer 43 can be exposed at the rear surface 23 of the reconfigurable element 24. Therefore, in Figure 9F A vertical interface 45 may be provided between the protective material 7 and the third protective material 43. A horizontal interface 46 may be provided between the second protective material 40 and the third protective material 43.

[0055] Figures 10a to 10a Figure 10E An example of an upward-facing bonding structure 1 is illustrated. Unless otherwise stated, Figures 10a to 10b are... Figure 10E The reference numerals in the attached figures can refer to... Figures 9A to 9F The reference numerals in the figures are the same or substantially similar for the components. Turning to Figure 10a, a monolithic reconstructed element 24 with its face upward oriented is shown. In Figures 10b to... Figure 10D In this process, the corresponding reconfigurable elements 24a and 24b are directly bonded to each other to form a bonded structure.

[0056] and Figure 9B Similarly, the diagram illustrates a front-to-back bonding arrangement where the front surface 22a of reconfigurable element 24a is directly bonded to the rear surface 23b of reconfigurable element 24b without intermediate adhesive, forming the front-to-back bonding arrangement of bonding structure 1. Figure 10B In this process, the first portion 7a of the protective material can extend from the rear surface 23a of the reconstructed element 24a to the bonding interface 12. The second portion 7b of the protective material can extend from the bonding interface 12 to the front surface 22b of the reconstructed element 24b.

[0057] Figure 10C The illustration shows that the rear surface 23a of the reconfigurable element 24a is directly bonded to the rear surface 23b of the reconfigurable element 24b without intermediate adhesive to form a rear-to-rear bonded arrangement of the bonding structure 1. Figure 10C In this process, the first portion 7a of the protective material can extend from the front surface 22a of the reconstructed element 24a to the bonding interface 12. The second portion 7b of the protective material can extend from the bonding interface 12 to the front surface 22b of the reconstructed element 24b.

[0058] Figure 10D The illustration shows that the front surface 22a of the reconfigurable element 24a is directly bonded to the rear surface 22b of the reconfigurable element 24b without intermediate adhesive to form a front-to-front bonding arrangement of the bonding structure 1. Figure 10D In this configuration, a first portion 7a of the protective material extends from the rear surface 23a of the reconstructed element 24a to the bonding interface 12. A second portion 7b of the protective material extends from the bonding interface 12 to the rear surface 23b of the reconstructed element 24b. Figure 10D In this context, the bonding layer 4a can extend over the protective materials 7a and 7b and can be exposed over the sidewall 25. (As described above...) Figure 6 As explained, in some embodiments, a bonding layer 4a may be provided over the protective material 7 across the wafer such that when the reconstructed wafer is monolithized, the bonding layer 4a is exposed at the sidewalls and flush with the protective material 7 at the sidewalls 25.

[0059] Figure 10E The illustration shows a monolithic reconfigurable element 24, which has a second protective material 40 disposed on the side and top surfaces of the protective material 7. Figure 9E and Figure 9F The implementation methods differ, in Figure 10EIn this configuration, the first front bonding layer 4a may be coplanar or flush with the second protective material 40. The second rear bonding layer 4b may be coplanar or flush with the protective material 7.

[0060] Figure 11 Another embodiment similar to the one described above is illustrated, except that an additional filler material can be used as a second protective material 40 and can be provided on top of a conformal protective material 7 in the gap G between adjacent elements 2. The protective material 7 can be conformally deposited on the rear 10 and side surfaces 8 of the elements 2 and on the upper surface of the carrier 3. The conformal protective material 7 can have gaps G between portions of the protective material 7 disposed on the side surfaces 8 of the elements 2. The second protective material 40 can be used to fill the gaps G. The second filler protective material 40 can include any suitable material, including organic or inorganic materials.

[0061] Figures 12A to 12C The illustration shows a method for forming a reconfigured wafer 20 according to various embodiments. Figure 12A Generally similar to Figure 11 The remainder, except for the second protective material 40, is disposed on the end of the outer element 2. Figure 12B In this process, a portion of the protective material 7 and a portion of the second filler protective material 40 can be removed to provide a generally flat surface. In various embodiments, for example, the corresponding portions of the filler and conformal protective materials 40, 7 can be removed by etching, grinding, abrasion, chemical mechanical polishing (CMP), etc. Figure 12C In this process, a portion of the bulk semiconductor material (e.g., silicon) of element 2 or the die can be removed via, for example, etching, polishing, CMP, etc., to form a cavity 16 to expose the conductive via 13. The coefficient of thermal expansion of conformal and / or gap-filling protective material(s) can be within 5 ppm / °C of the coefficient of thermal expansion of element 2 (e.g., integrated device die).

[0062] exist Figure 13A From the middle, one can Figure 12C In the structure shown, the second filler protective material 40 is removed, and additional protective material 48 can be provided over element 2 and the exposed via 13. Figure 13B In this process, a portion of the additional protective material 48 and protective material 7 provided can be removed or planarized to form a bonding surface 49 with a via exposed on the upper surface.

[0063] Figures 14A to 14C Another embodiment is illustrated, in which molding compound 50 can be disposed between adjacent elements 2 directly bonded to carrier 3 without an adhesive. Figure 14A In this embodiment, via 13 is shown exposed at the rear, but in other embodiments, via 13 may be buried as illustrated above. Figure 14BAs shown, it can be done as follows Figure 14B A metal 51 (such as copper) is provided on top of the molding compound 51 shown. For example, in various embodiments, the metal 51 may be provided using a chemical plating process, a sputtering process, or any other suitable method. Figure 14C As shown, metal 51 can be planarized by, for example, chemical mechanical polishing (CMP) or any other suitable method. In some embodiments, the use of organic materials in the structure of the molding compound may make it difficult to planarize to a sufficient smoothness (e.g., less than 5 nm, etc.) using CMP. By providing metal 51 (such as copper) on top of the molding compound, CMP or other planarization processes can be used to planarize to a sufficient smoothness for direct bonding.

[0064] Figures 15A to 15C Generally similar to Figures 14A to 14C In addition to Figures 15A to 15C In this process, a second metal 52 can be provided on the carrier 3 between the carrier 3 and the molding compound 50. Figures 16A to 16C Another embodiment is illustrated in which a protective coating 53 or layer (e.g., silicon oxide) can be provided between the molding compound 50 and the carrier 3. In various embodiments, the protective coating can also be provided after wafer placement and before metal deposition. Figure 16A In this process, the protective coating 53 can conformally coat the upper surface of the carrier 3 and the upper and side surfaces of the element 3. The molding compound 50 can be disposed on the protective coating 53 and between the element 2. Figure 16B As described above, metal 51 can be provided on top of molding compound 50. Figure 16C In this process, polishing, grinding, or buffing processes can be used to remove a portion of the protective coating 53 covering the component 2 to expose the via 13. The metal 51 and the component 2 can be planarized to form a smooth surface for bonding.

[0065] Figures 17A to 17D The illustration shows another bonding structure 1 that can be provided using the methods disclosed herein. Figure 17A In this configuration, the bonding structure 1 may include a plurality of elements 2, which may include a combination of an integrated device die and an interposer. Therefore, the method disclosed herein can be used in active and / or passive devices. Furthermore, as... Figure 17A As shown, insulating pillars 55 can be provided to separate adjacent elements 2 in the upper reconstructed element. Figure 17B In this configuration, the bonding structure 1 may include one or more redistribution layers (RDLs) 57, which may include lateral conductive routing traces to transmit signals laterally inward or outward. The RDLs 57 may enable fan-in or fan-out arrangements for connection to an external package substrate. Figure 17CIn this process, conductive vias 56 can be provided in the insulating pillar 56 to transmit signals from the lower element 2 to the upper surface of the bonding structure 1. Figure 17D In this configuration, the bonding structure 1 may include both a via 56 in the insulating pillar 56 and one or more RDLs 57. Those skilled in the art will understand that other combinations may be suitable. Other examples of integrated device packages

[0066] Integrated device packages may include one or more integrated device dies (e.g., chips) with active circuitry, such as transistors and other types of active devices. The integrated device dies may be mounted to a carrier, such as a semiconductor interposer, a semiconductor or dielectric (e.g., glass) substrate, another integrated device die, a reconfigured wafer, or an element. In various arrangements, a molding compound or encapsulation may be provided over the exposed surfaces of the integrated device die and the package substrate. The molding compound may include polymeric materials, such as epoxy resins or potting compounds. The material of the molding compound may have a coefficient of thermal expansion (CTE) different from that of the carrier and / or the integrated device die. During high-temperature process steps, CTE mismatch between the molding compound and the carrier (and / or the integrated device die) may induce stress in the carrier and / or the integrated device die. For example, stress caused by CTE mismatch can lead to cracking and / or warping of the carrier and / or the integrated device die, which can reduce package yield and / or affect system performance. Therefore, there remains a continued demand for improved packages that reduce stress caused by CTE mismatch between the molding compound and the carrier (and / or the integrated device die).

[0067] Figure 18A This is a schematic side cross-sectional view of an integrated device package 82 according to various embodiments. Figure 18B yes Figure 18A A schematic top plan view of the integrated device package 82. (See attached image.) Figures 18A to 18B As shown, package 82 may include carrier 103 and a plurality of integrated device dies 102 mounted to the upper surface of carrier 103. The integrated device dies 102 may include active circuitry. For example, integrated device dies 102 may include processor dies, memory dies, sensor dies, microelectromechanical systems (MEMS) dies, or any other suitable device (such as transistors or other active devices) that includes active circuitry. Figure 18B The top view shows three integrated device dies 102, but it should be understood that any suitable number of device dies 102 can be provided. For example, one or two integrated device dies 102 can be mounted to the carrier 103, or more than three integrated device dies 102 can be mounted to the carrier. Furthermore, in Figures 18A to 18BIn this configuration, the integrated device dies 102 are spaced laterally along the carrier 103. Alternatively or additionally, the integrated device dies 102 may be stacked vertically to reduce the package coverage area.

[0068] The carrier 103 may include any suitable support structure for the integrated device die 102. For example, in some embodiments, the carrier 103 may include an interposer (such as a semiconductor interposer), a semiconductor or dielectric (such as a glass) substrate, another integrated device die (such as an active chip with an active electronic circuitry system), a reconfigured wafer or component, etc. The carrier 103 may include a material having a first CTE (e.g., a semiconductor material, a dielectric material, etc.). In various embodiments, the integrated device die 102 may have a CTE substantially similar to the first CTE of the carrier 103. In some embodiments, the bulk material of one or more dies 102 may be the same material as the corresponding bulk material of the carrier 103. In various embodiments, the carrier 103 may include silicon, glass, or any other suitable material. In some embodiments, the carrier 103 may include an integrated device die (such as a processor die) having a larger lateral coverage area than the die 102. The integrated device die 102 may be mounted to the carrier 103 in any suitable manner. For example, the die 102 may be directly mixed and bonded to the carrier 103 without adhesive, as explained herein. In such embodiments, the non-conductive field regions of the die 102 can be directly bonded to the corresponding non-conductive field regions of the carrier 103 without adhesive. Furthermore, the conductive contacts of the die 102 can be directly bonded to the corresponding conductive contacts of the carrier 103 without adhesive. However, in other embodiments, the die 102 can be mounted to the carrier 103 using adhesive. In some embodiments, the carrier 103 can remain coupled to the die 102, such that the carrier 103 remains present in the larger electronic system. In other embodiments, the carrier 103 may include temporary structures (such as mounting tapes or sacrificial substrates) that are removed (e.g., stripped or etched away) and are not present in the final electronic package or system.

[0069] like Figure 18A As shown, molding compound 108 can be provided on the integrated device die 102 and on the exposed upper surface of the carrier 103. For ease of illustration, molding compound 108 is concealed within... Figure 18BIn the top view, the integrated device die 102 may be at least partially embedded (e.g., fully embedded or buried) within the molding compound 108. As described above, the molding compound 108 may comprise a polymeric material (such as epoxy resin or potting compound) having a second CTE different from the first CTE of the carrier 103 (and / or die 102). For example, the second CTE of the molding compound 108 may differ from the first CTE of the carrier 103 (and / or die 102) by a sufficiently large amount to cause CTE-induced stress on the carrier 103 and / or die 102 (e.g., CTE mismatch can be as high as about 12 ppm in some cases). As described above, the CTE mismatch between the molding compound 108 and the carrier 103 (and / or die 102) during high-temperature process steps can lead to stress that causes warping, cracking, or other types of damage to components of the package 82.

[0070] To reduce the effects of CTE mismatch between the molding compound 108 and the carrier 103 (and / or die 102), the package 82 may include one or more stress compensation elements 104a-104d mounted to the upper surface of the carrier 103. As shown in the figure, the stress compensation elements 104a-104d may be disposed around the integrated device die 102, such that the integrated device die 102 is disposed within an internal region of the package 82 surrounded by the stress compensation elements 104a-104d. The molding compound 108 may also be provided or applied over the stress compensation elements 104a-104d, such that the stress compensation elements 104a-104d are at least partially embedded in the molding compound 108. The stress compensation elements 104a-104d may be spaced apart from each other by intermediate portions of the molding compound 108 and spaced apart from the die 102. Stress compensation elements 104a-104d may comprise semiconductor materials (e.g., silicon), insulating materials (e.g., glass), or any other suitable material type having a CTE substantially matching (or close to) the second CTE of the carrier 103 and / or die 102. In some embodiments, stress compensation elements 104a-104d may comprise the same material as the carrier 103 and / or die 102. In other embodiments, stress compensation elements 104a-104d may comprise materials different from those of the carrier 103 and / or die 102. Each stress compensation element 104a-104d may comprise the same material, or some (or all) may comprise different materials. In various embodiments, the CTE of the stress compensation elements 104a-104d may be within 10% of the second CTE of the carrier 103 and / or integrated device die 102, within 5% of the second CTE, or within 1% of the second CTE. In various embodiments, the CTE of stress compensation elements 104a-104d can be less than 10 ppm, less than 8 ppm, or less than 7 ppm. For example, the CTE of stress compensation elements 104a-104d can be in the range of 3 ppm to 7 ppm.

[0071] Advantageously, stress compensation elements 104a-104d can reduce the stress applied to the carrier 103 and / or die 102 because the material composition of the stress compensation elements 104a-104d is selected to have a CTE substantially matched with that of the carrier 103 and / or die 102. The CTE-matched stress compensation elements 104a-104d can be disposed over a large area of ​​the carrier 103 to act as a stress-matching filler that compensates for or reduces any stress caused by CTE mismatch between the molding compound 108 and the carrier 103 and / or die 102. For example, in some embodiments, stress compensation elements 104a-104d can be mounted to cover a large portion of the unoccupied area of ​​the carrier 103 (e.g., areas of the carrier 103 that do not support the die 102 or other electronic components or devices), for example, at least 20%, at least 50%, at least 75%, at least 85%, or at least 90% of the unoccupied area of ​​the carrier 103. In some embodiments, stress compensation elements 104a-104d can be installed to cover 20% to 90% of the unoccupied area of ​​the carrier 103, 35% to 90% of the unoccupied area of ​​the carrier 103, or 50% to 90% of the unoccupied area of ​​the carrier 103. In some embodiments, such as Figure 18B As shown in the top view, stress compensation elements 104a-104d can overlap laterally such that all lines perpendicular to the opposite side edges 105a, 105b can pass through or intersect at least one stress compensation element 104a-104d. In this arrangement, stress compensation elements 104a-104d can be used to prevent or inhibit crack propagation through the carrier 103.

[0072] In addition, such as Figure 18B As shown in the top plan view, stress compensation elements 104a-104d can be disposed between the outer edges 105a-105d of the package 82 and the integrated device die 102, such that at least one lateral side edge 109 of each integrated device die 102 lies in a corresponding plane intersecting with at least one stress compensation element 104a-104d. In some embodiments, a majority (or all) of the side edges 109 of the die 102 may lie in a corresponding plane intersecting with at least one stress compensation element 104a-104d.

[0073] Figure 18C This is a schematic top plan view of the integrated device package 82, including the laterally overlapping stress compensation elements 104a-104d. Unless otherwise stated, Figure 18C The components can be with Figures 18A to 18B Components with the same serial number are identical or substantially similar. Figure 18C In, with Figure 18BIn contrast, stress compensation element 104b is vertically shortened (as shown in the top view), and stress compensation element 104d is horizontally extended (as shown in the top view). Therefore, in Figure 18C In this configuration, the stress compensation element 104d can extend to and be exposed along the side edge 105b. Figure 18C In this configuration, all lines perpendicular to each side edge 105a-105d may pass through or intersect with at least one stress compensation element 104a-104d, which can prevent or stop crack propagation.

[0074] In some embodiments, stress compensation elements 104a-104d may comprise dummy stress compensation elements without active circuitry, for example, without active devices in the dummy stress compensation elements. In such embodiments, dummy stress compensation elements may comprise dummy sheets or blocks of semiconductor materials (such as silicon) or dielectric materials (such as glass) without any active circuitry. The use of dummy elements can provide further benefits because it eliminates the need to pattern or form circuitry or devices in the elements 104a-104d, which can reduce processing costs and complexity. However, in other embodiments, one or more of the stress compensation elements 104a-104d may comprise active integrated device dies with active circuitry or devices. The use of multiple stress compensation elements 104a-104d can advantageously enable package assemblers to pick up and place the elements 104a-104d at desired locations, such as in locations highly sensitive to breakage and / or in target spaces above the carrier 103.

[0075] Similar to the integrated device die 102, stress compensation elements 104a-104d can be mounted to the carrier 103 in any suitable manner. For example, stress compensation elements 104a-104d can be directly bonded to the carrier 103 without adhesive. As mentioned above, stress compensation elements 104a-104d may include dummy stress compensation elements without an active circuit system. In such embodiments, stress compensation elements 104a-104d may include non-conductive field regions that are directly bonded to corresponding non-conductive field regions of the carrier 103 along the bonding interface without adhesive. Furthermore, in some embodiments, stress compensation elements 104a-104d can be directly bonded such that the bonding interface between elements 104a-104d and the carrier 103 consists only of non-conductive to non-conductive direct bonding (e.g., the bonding interface does not have conductor to conductor or metal to metal direct bonding). For example, in embodiments utilizing dummy stress compensation elements without active circuitry and / or contact pads, stress compensation elements 104a-104d can be directly bonded to the carrier 103 using only non-conductive-to-non-conductive direct bonding. For instance, the non-conductive or dielectric bonding layers of elements 104a-104d can be directly bonded to the corresponding non-conductive or dielectric bonding layers of the carrier 103 without adhesive. In such embodiments, non-conductive-to-non-conductive direct bonding can include one or more different types of non-conductive materials along the bonding interface. Therefore, in the various embodiments disclosed herein, one or more elements (such as die 102) can be directly bonded to the carrier 103 along the bonding interface without adhesive, such that the non-conductive field regions and conductive contact pads of one or more elements (e.g., die 102) are directly bonded to the corresponding non-conductive field regions and conductive contacts of the carrier 103. One or more other elements (such as stress compensation elements 104a-104d) may be directly bonded to the carrier 103 along the bonding interface without adhesive, such that the bonding interface between the stress compensation elements 104a-104d and the carrier 103 comprises only non-conductive-non-conductive direct bonds (e.g., dielectric bonding layers of direct bonds between elements 104a-104d and the carrier 103). For example, some elements 104a-104d may not include any conductive contacts directly bonded to the carrier 103. Non-conductive field regions of the die 102, stress compensation elements 104a-104d, and / or carrier 103 may comprise inorganic dielectric materials (e.g., silicon oxide). Non-conductive field regions may comprise unpatterned portions of the die 102, stress compensation elements 104a-104d, and / or carrier 103. The bonding interface may include features that indicate direct non-conductive bonding, such as one or more fluorine peaks at the nitrogen-sealed end surface, at the bonding interface, and at the upper and / or lower interface of the dielectric bonding layer of the element.

[0076] In other embodiments, such as those in which stress compensation elements 104a-104d include circuitry and contact pads, both the non-conductive field regions of the stress compensation elements 104a-104d and the contact pads can be directly bonded to the corresponding non-conductive field regions and contact pads of the carrier 103. In other embodiments, the stress compensation elements 104a-104d can be bonded to the carrier 103 using an adhesive. In some embodiments, the carrier 103 can be mounted to an external device, such as a system motherboard, or to another structure. In other embodiments, the carrier 103 may include a temporary support structure that can be removed after the molding compound 108 is applied. Figure 18B Four stress compensation elements 104a-104d are shown, but it should be understood that four or more stress compensation elements 104a-104d may be provided.

[0077] like Figures 18A to 18B As shown, package 82 may include outer edges 105a-105d. Package 82 may be formed by a monolithization process, through which a larger wafer or reconstructed wafer is monolithized along the monolithization path S to produce multiple monolithized packages 82. In some embodiments, monolithization may include a sawing process, an etching process, or any other suitable process by which package 82 can be formed from a larger wafer or reconstructed wafer. After monolithization, the outer edges 105a-105d (including, for example, the outer edges of stress compensation elements 104a, 104c, carrier 103, and / or molding compound 108, such as...) Figure 18B (As shown) may include monolithic markings indicating the monolithic process. For example, for a sawing monolithic process, the monolithic markings may include sawing marks, such as stripes in the monolithic surface. For an etching monolithic process, the monolithic markings may include markings or microstructures indicating the etching path. Figure 18C In some embodiments, the outer edge 105b may include the outer edge of the stress compensation element 104d, the edge of the carrier 103, and the molding compound, each of which may include a marking indicating a monolithic process. It should be understood that the stress compensation elements 104a-104d can be positioned anywhere along the carrier 103. For example, in other embodiments, some or all of the stress compensation elements 104a-104d may be laterally inset relative to the outer edges 105a-105d of the package 82, such that the stress compensation elements 104a-104d are embedded in the molding compound 108.

[0078] In various embodiments, the monolithic channel S can pass through one or more stress compensation elements 104a-104d, such that during monolithization, the molding compound 108 and one or more stress compensation elements 104a-104d can be exposed along one or more outer edges 105a-105d of the package 82. For example, as Figures 18A to 18B As shown, stress compensation elements 104a, 104c may include side edges 106a, 106c exposed at corresponding outer edges 105a, 105c of the package 82. Furthermore, side edges 107 of the molding compound 108 may be exposed along the outer edges 105a-105d of the package 82. As shown, the exposed side edges 106a, 106c of the stress compensation elements 104a, 104c may be flush with the side edges 107 of the molding compound 108 (including the portion of the molding compound 108 above the stress compensation elements 104a, 104c and the portion of the molding compound 108 laterally adjacent to the stress compensation elements 104a, 104c). In various embodiments, some stress compensation elements 104b, 104d may be laterally inserted relative to the outer edges 105b, 105d of the package 82, such that elements 104b, 104d can be completely embedded in the molding compound 108. In some embodiments, all stress compensation elements 104a-104d may be inserted laterally relative to the outer edges 105a-105d.

[0079] Figure 19 This is a schematic diagram of a system 80 comprising one or more integrated device packages 82 according to various embodiments. System 80 may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, tablet computing device, laptop computer, etc.), a desktop computer, an automobile or a component thereof, a stereo system, a medical device, a camera, or any other suitable type of system. In some embodiments, the electronic device may include a microprocessor, a graphics processor, an electronic recording device, or a digital memory. System 80 may include one or more device packages 82 that are mechanically and electrically connected to system 80, for example, via one or more motherboards. Each package 82 may include one or more integrated device dies and / or bonding structures 1. The integrated device die and / or bonding structure may include the above-mentioned bonding... Figures 1A to 18B Any integrated device package and / or bonding structure shown and described.

[0080] In one embodiment, an integrated device package is disclosed. The integrated device package may include a carrier and a molding compound on a portion of the upper surface of the carrier. The integrated device package may include an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die including an active circuit system. The integrated device package may include a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element being spaced apart from the integrated device die, the stress compensation element including a dummy stress compensation element without an active circuit system. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without adhesive.

[0081] In another embodiment, an integrated device package is disclosed. The integrated device package may include a molding compound and an integrated device die, the die being at least partially embedded in the molding compound, the die including an active circuit system. The integrated device package may also include a plurality of dummy stress compensation elements, each dummy stress compensation element having no active circuit system, and the dummy stress compensation elements being spaced apart from each other by the molding compound.

[0082] In another embodiment, a method for forming an integrated device package is disclosed. The method may include providing a molding compound over an integrated device die and a plurality of dummy stress compensation elements spaced apart from each other by the molding compound. The integrated device die may include an active circuit system. The plurality of dummy stress compensation elements may not have an active circuit system.

[0083] In another embodiment, an integrated device package is disclosed. The integrated device package may include a molding compound and an integrated device die, the die being at least partially embedded in the molding compound, the die including an active circuit system. The integrated device package may include a stress compensation element, which is at least partially embedded in the molding compound and spaced apart from the die. The molding compound and the stress compensation element may be exposed at an outer edge of the integrated device package.

[0084] In another embodiment, an electronic component is disclosed. The electronic component may include a carrier having a first non-conductive field region and a first conductive contact. The electronic component may include a first element that is directly bonded to the carrier without adhesive, a second non-conductive field region of the first element being directly bonded to the first non-conductive field region of the carrier without adhesive, and a second conductive contact of the first element being directly bonded to a first conductive contact of the carrier. The electronic component may include a second element that is directly bonded to the carrier without adhesive, such that only a third non-conductive field region of the second element is directly bonded to the first non-conductive field region of the carrier.

[0085] In another embodiment, an electronic component is disclosed. The electronic component may include a carrier having a first non-conductive field region and a first conductive contact. The electronic component may include a first element that is directly bonded to the carrier without adhesive, a second non-conductive field region of the first element being directly bonded to the first non-conductive field region of the carrier without adhesive, and a second conductive contact of the first element being directly bonded to a first conductive contact of the carrier. The electronic component may include a second element that is directly bonded to the carrier without adhesive, wherein the second element does not include any conductive contacts directly bonded to the carrier.

[0086] In one embodiment, a bonding structure is disclosed. The bonding structure may include a first reconfiguration element comprising a first element and having a first side including a first bonding surface and a second side opposite to the first side. The first reconfiguration element may include a first protective material disposed around the first sidewall surface of the first element. The bonding structure may include a second reconfiguration element comprising a second element and having a first side including a second bonding surface and a second side opposite to the first side. The first reconfiguration element may include a second protective material disposed around the second sidewall surface of the second element. The second bonding surface of the first side of the second reconfiguration element may be directly bonded to the first bonding surface of the first side of the first reconfiguration element without an intermediate adhesive along the bonding interface. The first protective material may be flush with the first bonding surface and the second protective material may be flush with the second bonding surface.

[0087] In another embodiment, a bonding structure is disclosed. The bonding structure may include a first reconfigurable element comprising a first element and having a first side and a second side opposite to the first side. The bonding structure may include a second reconfigurable element comprising a second element and having a first side and a second side opposite to the first side, the first side of the second reconfigurable element being directly bonded to the first side of the first reconfigurable element without an intermediate adhesive along the bonding interface. The bonding structure may include a protective material disposed around respective first and second side surfaces of the first and second elements. The bonding structure may include a non-conductive layer disposed between the first and second elements, the non-conductive layer being flush with at least one of the first and second side surfaces of the first and second elements, such that an interface is provided between the protective material and the non-conductive layer.

[0088] In another embodiment, a bonding structure is disclosed. The bonding structure may include a first reconstructed wafer comprising a plurality of first elements. The bonding structure may also include a second reconstructed wafer comprising a plurality of second elements. The first and second reconstructed wafers may be directly bonded to each other without adhesive.

[0089] In another embodiment, a bonding method is disclosed. The bonding method may include applying a first protective material over a plurality of first elements to form a first reconstructed wafer. The bonding method may include applying a second protective material over a plurality of second elements to form a second reconstructed wafer. The bonding method may include directly bonding the first reconstructed wafer to the second reconstructed wafer without an adhesive.

[0090] In another embodiment, a bonding method is disclosed. This bonding method may include directly bonding a first element to a carrier without an adhesive. The carrier may include a silicon carrier, with a silicon oxide layer directly disposed on the surface of the silicon carrier. The silicon oxide layer may be directly bonded to the first element. The silicon oxide layer may include a native oxide layer or a thermal oxide layer.

[0091] All these embodiments are intended to fall within the scope of this disclosure. These and other embodiments will become apparent to those skilled in the art from the following detailed description of the embodiments with reference to the accompanying drawings, and the claims are not limited to any particular embodiment(s) disclosed. Although certain embodiments and examples have been disclosed herein, those skilled in the art will understand that the disclosed implementations extend beyond the specifically disclosed embodiments to other alternative embodiments and / or uses, as well as their obvious modifications and equivalents. Furthermore, although several variations have been shown and described in detail, other modifications will be apparent to those skilled in the art based on this disclosure. It is also conceivable that various combinations or sub-combinations of specific features and aspects of the embodiments may be made and still fall within the scope of the invention. It should be understood that various features and aspects of the disclosed embodiments can be used to combine or substitute for each other to form different modes of the disclosed implementations. Therefore, it is intended that the scope of the subject matter disclosed herein should not be limited to the specific disclosed embodiments described above, but should be determined only by a fair reading of the appended claims.

Claims

1. An integrated electronic component package, comprising: A substrate having a surface including a first non-conductive field region; An integrated device die is directly bonded to the surface of the substrate without an intermediate binder. The integrated device die has a second non-conductive field region that directly contacts and is directly bonded to the first non-conductive field region without an intermediate binder. A stress compensation element is directly bonded to the surface of the substrate without an intermediate adhesive, wherein the stress compensation element has no active circuitry, wherein the stress compensation element comprises a block of semiconductor material, wherein the stress compensation element is disposed between the outer edge of the electronic component and the integrated device die, and wherein the stress compensation element is laterally inserted from the outer edge. as well as An insulating material is provided on the substrate, wherein the integrated device die and the stress compensation element are spaced apart from each other by the insulating material, wherein the stress compensation element is spaced apart from the outer edge by the insulating material, and wherein the insulating material extends between the outer edge and the stress compensation element.

2. The electronic component according to claim 1, wherein the substrate comprises a semiconductor substrate.

3. The electronic component of claim 1, wherein the integrated device die comprises a first integrated device die, and the substrate comprises a second integrated device die.

4. The electronic component of claim 3, wherein the first integrated device die includes a first active circuit device, the second integrated device die includes a second active circuit device, and wherein the first active circuit is electrically connected to the second active circuit device.

5. The electronic component of claim 4, wherein the first integrated device die is mixed-bonded to a bonding layer on the second integrated device die.

6. The electronic component of claim 1, wherein the stress compensation element comprises a dummy die.

7. The electronic component of claim 1, wherein the semiconductor material comprises silicon.

8. The electronic component of claim 1, wherein the integrated device die comprises a memory die.

9. The electronic component of claim 1, wherein the integrated device die and the stress compensation element are spaced apart from each other by a gap, and wherein the insulating material at least partially fills the gap.

10. The electronic component of claim 5, wherein the second integrated device die includes opposing front and rear surfaces, wherein the second active circuit is closer to the front surface than the rear surface, and wherein the front surface of the second integrated device die is opposite to the first integrated device die.

11. The electronic component according to claim 1, further comprising: One or more integrated device dies are directly bonded to the surface of the substrate without intermediate adhesive, wherein the one or more integrated device dies comprise the integrated device dies, and wherein the one or more integrated device dies occupy a first portion of the surface of the substrate but not a second portion of the surface; as well as One or more stress compensation elements are directly bonded to the surface of the substrate without intermediate adhesive, wherein the one or more stress compensation elements include the stress compensation element, and wherein the one or more stress compensation elements occupy at least 50% of the second portion of the surface.

12. The electronic component of claim 1, wherein the stress compensation element includes a third non-conductive field region, wherein the first non-conductive field region and the third non-conductive field region are in direct contact with each other and are directly bonded together without an intermediate adhesive, and wherein at least one of the first non-conductive field region and the third non-conductive field region includes an activated surface with nitrogen end capping.

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