High voltage wake-up signaling input / output for 10base-t1s system base chip

Abstract

A method may include receiving signaling at a system base chip of a transceiver implementing a 10SPE PHY; changing, at the system base chip, the signaling from a first voltage level that is incompatible with a voltage domain of a microcontroller (MCU) implementing a controller of the 10SPE PHY to a second voltage level that is compatible with the voltage domain of the MCU; and communicating the changed signaling to the MCU.

Description

Priority Statement

[0001] This application claims the benefit of International Patent Application Serial No. PCT / CN2023 / 107647, filed on July 17, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.

[0002] The example systems involve the 10SPE physical layer (PHY). Some example systems involve a system base chip for implementing a transceiver of the 10SPE PHY and a microcontroller for implementing a controller of the 10SPE PHY. Some example systems involve a system base chip that processes high-voltage signaling destined for the PHY and interfaces the high-voltage signaling with the low-voltage domain of the microcontroller. Background Technology

[0003] A system base chip (SBC) is an integrated circuit (IC) that combines multiple functions required for the operation of an electronic system. ICs and SBCs are utilized in a variety of operating environments. Attached Figure Description

[0004] To facilitate the identification of any particular element or action in the discussion, the most important number in the figure labels refers to the figure number of the element when it was first introduced.

[0005] Figure 1 It is a block diagram depicting a system of 10SPE PHY implementations (among others) based on one or more examples.

[0006] Figure 2 It describes a system base chip (SBC) based on one or more examples (such as...). Figure 1 The circuit diagram of the high-voltage input / output of the SBC.

[0007] Figure 3 This is a schematic diagram of a system for driving high-voltage GPIOs of an SBC, based on one or more examples.

[0008] Figure 4 It is a description based on one or more examples via Figure 2 A schematic diagram of a system that generates internal signals using a high-voltage I / O circuit.

[0009] Figure 5 It is a state diagram depicting the behavior of an SBC that manages high-voltage GPIOs according to one or more examples.

[0010] Figure 6 It is a flowchart depicting, according to one or more examples, the process of processing a high-voltage signal and interfacing it with a low-voltage MCU.

[0011] Figure 7It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes or methods disclosed herein. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples of practices in which this disclosure may be practiced are shown by way of illustration in the drawings. These examples are described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0013] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of this disclosure. The accompanying drawings are not necessarily drawn to scale. For the reader's convenience, similar structures or components in the drawings may retain the same or similar numbering; however, similarity in numbering does not imply that the structure or component must be identical in size, composition, configuration, or any other property.

[0014] The following description may include examples to help enable those skilled in the art to practice the disclosed examples. The use of the terms “exemplary,” “for example,” and “e.g.” means that the description is illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of this disclosure to the specified components, steps, features, functions, etc.

[0015] It should be readily understood that the components of the examples described herein and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following description of numerous examples is not intended to limit the scope of this disclosure, but rather to represent numerous examples only. While many aspects of the examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0016] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, where such details do not require a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0017] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0018] The various exemplary logic blocks, modules, and circuits described in conjunction with the examples disclosed herein can be implemented or executed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) can be a microprocessor, but in alternative embodiments, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor executes computational instructions (e.g., software code) related to the examples of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0019] Examples can be described based on processes depicted as flowcharts, schematic diagrams, structural diagrams, or block diagrams. While a flowchart may describe operable actions as a continuous process, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. A process may correspond to a method, thread, function, procedure, subroutine, or subroutine, but is not limited thereto. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another.

[0020] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise stated, a group of elements may include one or more elements.

[0021] As used herein, the term "substantially" refers to and includes the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. For example, depending on whether a particular parameter, attribute, or condition is substantially satisfied, it may be satisfied with at least 90%, at least 95%, or even at least 99%.

[0022] As used herein, any relational terms (such as "above", "below", "on", "under", "upper", "lower", etc., but not limited thereto) are used for clarity and convenience in understanding this disclosure and the accompanying drawings, and such relational terms do not imply or depend on any particular preference, orientation or order unless the context clearly indicates otherwise.

[0023] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as "coupled" to another element, then the element may be in direct physical or electrical contact, or there may be an intermediary element or layer. In contrast, when an element is described as "directly coupled" to another element, then there is no intermediary element or layer. The term "connection" is used interchangeably with the term "coupled" in this specification and has the same meaning unless otherwise expressly indicated or the context will otherwise indicate to a person skilled in the art.

[0024] As used herein, the terms “assert,” “deassert,” and their derivatives used with respect to the pin and the component are referred to respectively to assert or deassert the signal associated with the pin (e.g., a signal specifically assigned to or to the pin, but not limited thereto).

[0025] A system base chip (SBC) is an integrated circuit (IC) that combines multiple functions used to operate an electronic system. SBCs typically integrate a variety of different functions into a single chip. These functions, as non-limiting examples, include: power management functions for managing the power supply to the system, such as, but not limited to, voltage regulators, power switches, or protection circuitry; communication interfaces, such as, but not limited to, CAN (Controller Area Network), LIN (Local Interconnect Network), SPI (Serial Peripheral Interface), or I2C (Internal Integrated Circuit); embedded systems that control and coordinate tasks, such as, but not limited to, state machines or microprocessors; analog functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), temperature sensors, and other signal conditioning circuitry; and diagnostic and safety functions, such as, but not limited to, monitoring and reporting voltage levels, temperature, or fault conditions.

[0026] SBCs exist in a variety of operating environments, including automotive and industrial applications. A non-limiting example of an automotive application of SBCs is in 10SPE (i.e., 10 Mbps single-pair Ethernet) networks (also known as "10BASE-T1S networks"). 10SPE is a network technology specified in IEEE 802.3 clauses 147 and 148. 10SPE can be used to provide collision-free deterministic transmission over multipoint networks.

[0027] In some cases, as a non-limiting example, the transceiver (xcvr) and controller of a 10SPE physical layer device (PHY) may reside on different dies, thus subjecting the dies to different process conditions. This architecture is referred to herein as a “split PHY” architecture. The digital block of the PHY controller, which is susceptible to damage during high-voltage temperature processes, may reside on a first die that does not undergo high-voltage temperature processes. The analog and digital blocks of the PHY transceiver (which are not susceptible to damage during high-voltage temperature processes or require such processes) may reside on a second die that does undergo such high-voltage temperature processes.

[0028] The 10SPE transceiver interface standard, currently being developed by Open Consortium Technical Committee 14 (hereinafter referred to as "TC14"), defines a hardware interface (specifically a 3-pin hardware interface) for communication between the PHY transceiver and the PHY controller in a discrete PHY architecture.

[0029] In 10SPE, the microcontroller (MCU) implements the PHY controller function, and the SBC implements the PHY transceiver function. In 10SPE, the SBC's non-transceiver responsibilities include regulated power delivery (e.g., low-voltage power delivery), observability / control of the high-voltage domain (e.g., handling high-voltage signals), and functional safety mechanisms for the MCU to reach a safe state. Therefore, in addition to transceiver functions, the SBC can also implement electronic system functions such as power management, watchdog circuits, monitors, and general-purpose input / output (GPIO), but is not limited to these.

[0030] TC14 describes the low-power (sleep-wake) behavior of PHY transceivers for partial networking. Partial networking refers to the feature of enabling selective power management and communication capabilities within a network. Partial networking allows certain network nodes or devices to enter a low-power state or sleep state while still maintaining basic communication functionality. In Ethernet networks, partial networking is used to optimize power consumption, particularly in automotive or industrial applications. Allowing selected devices to enter a low-power state or sleep state can reduce overall power consumption, extend battery life, or improve energy efficiency, but is not limited to these.

[0031] Modern MCUs typically operate at lower voltages (such as 3.3V), making them incompatible with the high-voltage DC signals commonly found in automotive, industrial, and other high-voltage applications. For example, in automotive applications, the battery voltage (Vbat) may be nominally 12V, but can vary significantly under different conditions, such as those specified by the LV124 standard, but not limited to these. Similarly, other applications, like fire alarm systems, can operate at a nominal voltage of 24V.

[0032] One or more examples as a whole involve a system base chip (SBC) capable of handling both power supply voltage signals and high voltage signals. The SBC integrates high-voltage (HV) GPIO capabilities, allowing the SBC to process high-voltage signals and interface with low-voltage devices, such as low-voltage MCUs.

[0033] In one or more examples, the SBC is able to shift high-voltage system signal levels to MCU-compatible levels (e.g., from 12V to 3.3V, but not limited to this).

[0034] Additionally or alternatively, in one or more examples, changes in the high-voltage input can be detected and determined by the SBC and then communicated to the MCU via an interrupt. This allows the MCU to be notified of high-voltage changes without being directly exposed to the high voltage.

[0035] Additionally or alternatively, in one or more examples, when the MCU writes to a register, the SBC can use an open-drain driver to signal the event as a high voltage or ground (GND) output.

[0036] Additionally or alternatively, in one or more examples, the MCU may control the high-voltage domain module via GPIO outputs to enable functionality such as wake-up signaling, but is not limited thereto.

[0037] Additionally or alternatively, in one or more examples, a high-voltage GPIO can be used for a wake-up signal (e.g., WAKEIN, but not limited to) in the always-on domain (uninterrupted voltage domain (VDDU)). This allows the SBC to detect wake-up based on a high-voltage input and wake the system from a low-power or sleep state (change the power state).

[0038] Figure 1 It is a block diagram depicting a system 100 of a 10SPE PHY based on one or more examples (among others).

[0039] System 100 includes MCU 102 and SBC 108. MCU 102 includes PHY controller 104 and I2C bus controller 106. PHY controller 104 and PHY transceiver 110 form a 10SPE PHY. PHY controller 104 and PHY transceiver 110 communicate via hardware interface 112, which includes connections for carrying signals associated with transmit signaling (TX connection), energy detection signaling (ED connection), and receive signaling (RX connection). MCU 102 and SBC 108 communicate via I2C bus and optionally via command, control, and management connections (in... Figure 1 The MCU communicates via connections INTn and RSTn (which are specific, non-limiting examples of command, control, and management connections), which specifically instruct the MCU on the actions required by the MCU. Non-limiting examples of communication via command, control, and management connections include interrupt (IRQ) signaling.

[0040] PHY controller 104 manages the digital aspects of 10BASE-T1S PHY communication. This PHY controller handles tasks such as encoding, decoding, and managing the link layer protocol. I2C bus controller 106 manages communication on the I2C bus, facilitating command, control, and data exchange between MCU 102 and SBC 108. Figure 1 In the specific example depicted, optional logic for communication between management commands, control, and management connections (e.g., INTn and RSTn, but not limited to) is represented by the same block representing the I2C bus controller 106, but may be different logical partitions.

[0041] SBC 108 implements or manages the functions of PHY transceiver 110, MCU 102, and its own internal functions (SBC functions, which are non-transceiver functions). SBC 108 may also optionally implement sensor functions (sensors are not depicted but should be considered optional). Vuc is the power supply voltage managed by and supplied from SBC 108 to MCU 102. SBC 108 may also optionally supply power voltages to other devices such as sensors as needed (e.g., providing Vsen, but not limited to). Vsup is the power supply voltage supplied to SBC 108 and can be used to generate Vuc, for example, directly or as a regulated version of Vsup. Vbat is the battery voltage and represents the high-voltage power supply voltage supplied to system 100 and more specifically to SBC 108 (e.g., an unregulated voltage source that generates a voltage higher than the power supply voltage VSup). GPIO is a general purpose input / output connection. The transmit / receive connection, common-mode choke (CMC), and connector are, but not limited to, the physical circuitry that connects the SBC 108 to a physical transmit medium (such as twisted pair). WAKEIN is an input connection specifically for receiving external power management signals (e.g., wake-up or sleep, but not limited to) from an external source (e.g., outside of system 100, but not limited to). WAKEOUT is an output connection specifically for transmitting power management signals to sources outside of system 100.

[0042] SBC 108 is capable of high-voltage I / O processing, as discussed below. In one or more examples, SBC 108 includes one or both of level shifter 116 and IRQ signaler 118 to facilitate high-voltage I / O processing.

[0043] Level shifter 116 converts the signal from a high voltage level to a lower MCU-compatible voltage level. This allows MCU 102 to safely read the high voltage input of high voltage I / O 114 without being directly exposed to the high voltage.

[0044] IRQ signaler 118 detects and determines a change in the high-voltage input of high-voltage I / O 114. IRQ signaler 118 transmits the determined signal to MCU 102 via an interrupt (e.g., generating an interrupt, but not limited to this), enabling MCU 102 to respond to a high-voltage event without directly processing the high-voltage signal. System 100 may include one or more interrupt and control lines connecting SBC 108 and MCU 102 to facilitate IRQ and control signaling that transmits the determined signal to MCU 102 to notify MCU 102 of a high-voltage event.

[0045] SBC 108 may also include GPIO control 120 in an always-on domain to facilitate power management functions, such as wake-up detection and signaling, in cooperation with one or more of level shifters 116 or IRQ signalers 118. In one or more examples, GPIO control 120 may detect specific conditions, such as a high-voltage wake-up signal on the HV GPIO, and trigger an appropriate system response.

[0046] High-voltage GPIO (HV GPIO) can handle voltage levels higher than GPIO. In this case, HV GPIO handles signals represented by voltage level Vbat, while GPIO handles signals represented by level Vsup, where Vsup is lower than Vbat.

[0047] Through a hypothetical wake-up process, a high-voltage GPIO pin can be configured to detect a wake-up signal represented by a voltage change that meets specific conditions.

[0048] The IRQ signaler 118 of SBC 108 determines the detected signal to ensure that it is a valid wake-up event. After determination, the IRQ signaler 118 generates an interrupt to notify the MCU 102 of the wake-up event. Upon receiving the interrupt, the MCU 102 initiates a process to transition the system from a low-power or sleep state to an active state.

[0049] Figure 2 This is a circuit diagram depicting an HV I / O 200 for an SBC (such as SBC 108) according to one or more examples. The HV I / O 200 connects the WAKEIN and WAKEOUT connections of the SBC (e.g., SBC 108) to pads. The pads are used for high-voltage connections. The pads operate under Vbat, and the SBC connections operate under Vsup, where Vsup... <Vbat。

[0050] HV I / O 200 is Figure 1 A non-limiting example of a level shifter 116.

[0051] In one or more examples, HV I / O 200 may be internal circuitry of SBC 108 that couples internal connections of SBC 108 to connections for connecting external to SBC (e.g., pads), or HV I / O 200 may be external to SBC 108, acting as an interface between the SBC's connections for connecting to external sources and such external sources.

[0052] The high-voltage input stage includes a comparator with hysteresis (here, a Schmitt trigger). The comparator's output is coupled to the SBC's internal wake-up signaling connection, `dind`. This output is switchably coupled to ground via a transistor switch. This output of the comparator can be connected in series or parallel to `dind` depending on the state of the transistor switch. When the switch is on, the comparator's output is coupled in parallel to `dind`; when the switch is off, the comparator's output is coupled in series to `dind`. The gate of the switch and the comparator's reference input are coupled to receive the signal `en-ind`.

[0053] The comparator's input is coupled in parallel to an input node, which is also coupled to ground via a capacitor. The input node is switchably coupled to a high-value resistor (here, a 500K ohm resistor) via another transistor switch. The gate of this transistor switch is coupled to Vsup (here, 3.3V). This transistor is an n-channel MOSFET, coupled in series with the high-value resistor. The other end of the high-value resistor is coupled to a node in parallel with multiple series-coupled Zener diodes and pads.

[0054] In one or more examples, a wake-up event can be indicated by a specific voltage change at the pad. Signal detector ( Figure 2 (Not depicted) An internal bit (e.g., a flag, but not limited to) may be set in response to the detection of an effective voltage change at the pad. The effective voltage change at the pad can be used to infer the effective voltage change at the pad. The effective voltage change at the pad indicates a wake-up signal at the pad. When the pad is at a voltage potential Vbat, this causes Vbat (3.3V) to appear at the comparator input. When the pad is at a ground voltage potential, this causes the ground voltage to appear at the comparator input.

[0055] The section of the HV I / O 200 circuit above the high-voltage input stage is the high-voltage output stage. Doutd and Endb are internal signals used to control the output state of the pads. Connections to Doutd and Endb are made to the inputs of a NOR gate. When Doutd and Endb are set to 0, the gate output (GATE_out) is set to 1. When either or both of Doutd and Endb are set to 1, the gate output (GATE_out) is set to 0. With an N-channel MOSFET as the transistor switch, when Doutd and Endb are 0 (grounded), the transistor switch is on and current flows, thus grounding the pads. When either or both of Doutd and Endb are at logic level 1, the transistor switch is off and current flows are not allowed, thus the pads are at VBAT.

[0056] Figure 3This is a schematic diagram of a system 300 for driving a high-voltage GPIO for an SBC, based on one or more examples. System 300 includes a CSR 302, a MUX 304, and an inverter 306.

[0057] CSR 302 is a command status register that includes at least the following bits: EXT flag, flag 1, flag 2, and flag select. Flag 1, flag 2, and flag select can be used as needed based on specific operating conditions.

[0058] MUX 304 provides MUX selection between flag 1 and flag 2 based at least in part on flag selection. The output of MUX 304 is coupled to a high-voltage I / O via inverter 306. The EXT flag is a bit that can be set by GPIO (e.g., an external wake-up signal, but not limited to) via HV I / O 200 (as a non-limiting example).

[0059] Figure 4 It is a description based on one or more examples via Figure 2 A schematic diagram of a system 400 for generating internal signals using high-voltage I / O. System 400 includes a high-voltage input / output 402, a signal detector 404, and a CSR 406.

[0060] System 300 receives an input signal (voltage signal) with a voltage range from Vbat to ground (i.e., in the high voltage domain). High voltage input / output 402 (which can be...) Figure 2 The HV I / O 200 converts the voltage signal into a signal at a range voltage level, and the converted signal is fed to the signal detector 404. The signal detector determines the portion of the signal present at the pad as a valid input signal based on the output of the high voltage input / output 402, and indicates the valid signal at its output. The EXT_Flag of the CSR is set based on the output of the signal detector 404.

[0061] Figure 5 This is a state diagram depicting the behavior of the SBC (System-Bridge Control) managing high-voltage GPIOs according to one or more examples. Vertices represent states (specifically, operating modes): SBC_sleep, SBC_reset, LPwake, LP, SBC_operative, normal, and config. Directed edges between vertices represent transitions from one state to another. The conditions or events that trigger the transitions indicated by the directed edges are also depicted.

[0062] The SBC off state (SBC_off) is the initial state in which the SBC is completely powered off. The SBC can transition from SBC_off to SBC_reset in response to a Vuc power-on reset (POR).

[0063] The SBC reset state (SBC_reset) is the state in which the SBC initializes its components and is ready for operation. The SBC can transition from the SBC_off state (SBC_oper) in response to the reset signal (RSTn) being "complete" (indicating that the reset process is complete).

[0064] The SBC operating state (SBC_oper) is the state in which the SBC is fully operational and capable of performing its tasks. The SBC can transition from the SBC operating state (SBC_oper) to the SBC sleep state (SBC_sleep) in response to an SBC sleep command and the PHY transceiver being in low-power (LP) mode. The SBC can transition from the SB operating state (SBC_oper) to the low-power (LP) wake-up state in response to an interrupt timeout. The SBC can transition from the SB operating state (SBC_oper) to the SBC_reset state in response to a reset signal (RSTn) indicating "completion".

[0065] The SBC sleep state (SBC_sleep) is a low-power sleep state in which the SBC minimizes its power consumption. The SBC can transition from the SBC_sleep state to the SBC_wake state in response to over-temperature shutdown (OTSD) and over-voltage shutdown (OVSD). The SBC can transition from the SBC_sleep state to the SBC_operate state in response to an SBC wake-up command and the PHY transceiver being in LP mode.

[0066] The SBC wake state (SBC_wake) is the transition state of the SBC from the SBC sleep state to the SBC operating state.

[0067] Low Power Wake (LPwake) is a state that indicates the PHY transceiver is waking up from a low power state. The LPwake state is triggered by a wake-up signal.

[0068] Low Power State (LP) is a state that indicates the PHY transceiver is in a low-power state, in which the PHY transceiver consumes minimal power. The LP state is triggered by a wake-up signal.

[0069] The normal state is the normal operating state in which the PHY transceiver performs its standard functions. The PHY transceiver can transition from the normal state to the transmit state, the config state, or the low-power state. Transitions to the transmit state are triggered by the need to transmit data. Transitions to the config state are triggered by configuration commands. Transitions to the low-power (LP) state are triggered by sleep commands.

[0070] The transmit state is the state in which the PHY transceiver is ready to receive and send data. The PHY transceiver can transition from the transmit state to the xmiting state, which is triggered by the start of transmission.

[0071] The "xmitting" state indicates that the PHY transceiver is in the process of transmitting data. The PHY transceiver can transition from the "xmitting" state to the normal state when the data transmission is completed.

[0072] The configuration state (config) is the state in which the PHY transceiver is being configured. The PHY transceiver can transition from the configuration state to the normal state when the configuration is completed.

[0073] Figure 6 This is a flowchart depicting a process 600, according to one or more examples, for processing a high-voltage signal and interfacing it with a low-voltage MCU. Although the example process 600 depicts a specific sequence of operations, this sequence can be changed without departing from the scope of this disclosure. For example, some of the depicted operations may be performed in parallel or in a different order that does not substantially affect the functionality of process 600. In other examples, different components of the example device or system implementing process 600 may perform their functions substantially simultaneously or in a specific order.

[0074] According to some examples, the method includes receiving signaling at block 602 at the system base chip of a transceiver implementing a 10SPE PHY.

[0075] According to some examples, the method includes: at block 604, at the system base chip, changing the signaling from a first voltage level that is incompatible with the voltage domain of the microcontroller (MCU) implementing the 10SPE PHY to a second voltage level that is compatible with the voltage domain of the MCU.

[0076] According to some examples, the method includes: at block 606, communicating the changed signaling to the MCU.

[0077] Those skilled in the art will understand that the functional elements (e.g., functions, operations, actions, processes, or methods) of the examples disclosed herein can be implemented in any suitable hardware, software, firmware, or a combination thereof. Figure 7 Non-limiting examples of specific implementations of the functional elements disclosed herein are illustrated. In some examples, some or all portions of the functional elements disclosed herein may be executed by hardware capable of performing the functional elements.

[0078] Figure 7This is a block diagram of circuitry 700 that, in some examples, can be used to implement the various functions, operations, actions, processes, or methods disclosed herein. Circuitry 700 includes one or more processors 702 (sometimes referred to herein as "processor 702") operatively coupled to one or more data storage devices 704 (sometimes referred to herein as "storage device 704"). Storage device 704 includes machine-executable code 706 stored thereon, and processor 702 includes logic circuitry 708. Machine-executable code 706 describes functional elements that can be implemented (e.g., executed) by logic circuitry 708. Logic circuitry 708 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 706. When executing the functional elements described by machine-executable code 706, circuitry 700 should be considered as dedicated hardware for executing the functional elements disclosed herein. In some examples, processor 702 may execute the functional elements described by machine-executable code 706 sequentially, simultaneously (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0079] When implemented by the logic circuitry 708 of processor 702, machine-executable code 706 adapts processor 702 to perform the operations of the examples disclosed herein. As a non-limiting example, machine-executable code 706 may adapt processor 702 to perform some or all of the operations to facilitate high-voltage I / O processing discussed herein, such as high-voltage wake-up signaling input / output for a 10BASE-T1S system base chip, but is not limited thereto. As a non-limiting example, processor machine-executable code 706 may adapt processor 702 to perform some or all of the operations in state diagram 500 or process 600.

[0080] Similarly, as a non-limiting example, machine-executable code 706 may adapt processor 702 to perform some or all of the features, functions, or operations disclosed herein, including system 100, HV I / O 200, system 300, system 400, or a finite state machine (FSM) implementing state diagram 500. More specifically, the features, functions, or operations disclosed herein for coordinating power state changes.

[0081] Processor 702 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer when it executes functional elements corresponding to machine-executable code 706 (e.g., software code, firmware code, hardware description) associated with the examples of this disclosure. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but in alternatives, processor 702 may include any conventional processor, controller, microcontroller, or state machine. Processor 702 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0082] In some examples, storage device 704 includes volatile data storage devices (e.g., random access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as a single device (e.g., semiconductor device product, system-on-a-chip (SoC), but not limited thereto). In some examples, processor 702 and storage device 704 may be implemented as separate devices.

[0083] In some examples, the machine-executable code 706 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored in storage device 704, directly accessed by processor 702, and executed by processor 702 using at least logic circuitry 708. Also by a non-limiting example, the computer-readable instructions may be stored on storage device 704, passed to a memory device (not shown) for execution, and executed by processor 702 using at least logic circuitry 708. Therefore, in some examples, the logic circuitry 708 includes electrically configurable logic circuitry 708.

[0084] In some examples, machine-executable code 706 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 708 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstractions, hardware description languages ​​(HDLs), such as the IEEE Standard Hardware Description Language (HDL), can be used. With the aid of non-limiting examples, Verilog, SystemVerilog, or VLSI Hardware Description Language (VHDL) can be used.

[0085] HDL descriptions can be converted into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be converted into a logic-level description, such as Register Transfer Language (RTL), Gate-level (GL) description, Placement-level description, or Mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 708 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL, then converted into a GL description by a synthesis tool, and the GL description can be converted into a placement-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or combinations thereof. Therefore, in some examples, machine-executable code 706 may include HDL, RTL, GL descriptions, Mask-level descriptions, other hardware descriptions, or any combination thereof.

[0086] In an example where machine-executable code 706 includes a hardware description (at any level of abstraction), the system (not shown, but including storage device 704) implements the hardware description described by machine-executable code 706. As a non-limiting example, processor 702 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 708 may be electrically controlled to implement circuitry corresponding to the hardware description into logic circuitry 708. Also as a non-limiting example, logic circuitry 708 may include hardwired logic components manufactured by a manufacturing system (not shown, but including storage device 704) according to the hardware description of machine-executable code 706.

[0087] Regardless of whether the machine-executable code 706 includes computer-readable instructions or a hardware description, the logic circuit 708 is adapted to execute the functional elements described by the machine-executable code 706 when implementing the functional elements of the machine-executable code 706. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0088] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation that performs actions of a module or component and / or software object or software routine that can be stored on and / or executed by general-purpose hardware (e.g., computer-readable media, processing devices, but not limited thereto) of a computing system. In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes (e.g., as separate threads) that execute on a computing system. While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0089] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0090] The terminology used in this disclosure, and particularly in the appended claims (e.g., in the body of the appended claims, but not limited thereto), is generally intended to be “open-ended” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, and the term “having” should be interpreted as “at least having, but not limited to”). As used herein, the term “each” means “some or all”. As used herein, the term “each and every” means “all”.

[0091] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”, but is not limited thereto); the same applies to the use of definite articles to introduce claim statements.

[0092] Furthermore, even when a specific number of the introduced claim statements are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means, in the absence of other modifying elements, at least two statements, or two or more statements, but not limited thereto). Additionally, in instances where conventions such as "at least one of A, B, and C, but not limited thereto" or "one or more of A, B, and C, but not limited thereto" are used, such constructions are generally intended to include, but are not limited to, a single A, a single B, a single C, A and B together, A and C together, B and C together, or A, B, and C together.

[0093] Furthermore, any separate word or phrase presenting two or more alternative terms in the specification, claims, or drawings should be understood to contemplate the possibility of including one term, any one term, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0094] Additional non-limiting embodiments include:

[0095] Example 1: An apparatus comprising: a pad associated with a high-voltage signaling, the high-voltage signaling being represented by a voltage change between first voltage levels; a system base chip including: circuitry for changing a voltage signal between the first voltage level and a corresponding second voltage level, the second voltage level being lower than the first voltage level, the first voltage level being utilized at the pad, and the second voltage level being utilized by the system base chip; and a signal detector for detecting an effective voltage change at the pad in response to the changed voltage signal.

[0096] Example 2: According to the apparatus of Example 1, wherein: the voltage range of the first voltage level is limited between the ground voltage potential and the first voltage level; and the voltage range of the second voltage level is limited between the ground voltage potential and a second voltage level lower than the battery voltage.

[0097] Example 3: An apparatus according to any one of Examples 1 and 2, the apparatus comprising: a register of a system base chip (SBC) for storing the output of the signal detector; and an input path of the circuit extending from the pad to the register, wherein the pad is powered by a first power supply voltage providing the first voltage level, and the input path of the circuit is powered by a second power supply voltage providing the second voltage level.

[0098] Example 4: The apparatus according to any one of Examples 1 to 3, wherein the input path includes a high-value series resistor to limit the current flowing through the circuit when a high voltage is applied to the pad.

[0099] Example 5: An apparatus according to any one of Examples 1 to 4, the apparatus comprising: an interrupt signaler for communicating an event based at least in part on information stored in the register of the SBC.

[0100] Example 6: The apparatus according to any one of Examples 1 to 5, wherein the system base chip implements a 10SPE PHY transceiver.

[0101] Example 7: An apparatus according to any one of Examples 1 to 6, the apparatus comprising: a register for storing an output signal; and an output path of the circuit extending from the register to the pad, wherein the pad is powered by a first power supply voltage providing the first voltage level, and the output path of the circuit is powered by a second power supply voltage providing the second voltage level.

[0102] Example 8: An apparatus comprising: a microcontroller that implements a controller for a 10SPE physical layer (PHY); and a system base chip that implements a transceiver for the 10SPE PHY, wherein the system base chip is configured to receive and process high-voltage external signals and interface the high-voltage external signals with the low-voltage domain of the microcontroller (MCU).

[0103] Example 9: According to the apparatus of Example 8, wherein the high-voltage external signal includes an external wake-up signaling, and the system base chip is configured to: generate an internal wake-up signaling representing the external wake-up signaling, wherein the voltage range of the high-voltage external signaling is limited between a ground voltage level and a first voltage level, and the voltage range of the internal wake-up signaling is limited between a ground voltage and a second voltage level lower than the first voltage level.

[0104] Example 10: The apparatus according to any one of Examples 8 and 9, wherein the system base chip is used to communicate a wake-up event to the MCU at least in part based on the internal wake-up signaling.

[0105] Example 11: The apparatus according to any one of Examples 8 to 10, wherein the system base chip is used to provide the internal wake-up signaling to the MCU.

[0106] Example 12: A method comprising: receiving signaling at a system base chip implementing a transceiver of a 10SPE PHY; at the system base chip, changing the signaling from a first voltage level incompatible with the voltage domain of a microcontroller (MCU) implementing the 10SPE PHY to a second voltage level compatible with the voltage domain of the MCU; and transmitting the changed signaling to the MCU.

[0107] While this disclosure has been described with respect to certain exemplary embodiments, those skilled in the art will recognize and understand that the invention is not limited thereto. Rather, many additions, deletions, and modifications may be made to the exemplary and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. An apparatus, the apparatus comprising: Pads associated with high-voltage signaling, which is represented by voltage changes between first voltage levels; The system base chip includes: A circuit for changing a voltage signal between a first voltage level and a corresponding second voltage level, the second voltage level being lower than the first voltage level, the first voltage level being utilized at the pads, and the second voltage level being utilized by the system base chip; and A signal detector is used to detect changes in the effective voltage at the pad in response to a changed voltage signal.

2. The apparatus according to claim 1, wherein: The voltage range of the first voltage level is limited to between the ground voltage potential and the first voltage level; and The voltage range of the second voltage level is limited to between the ground voltage potential and a second voltage level lower than the battery voltage.

3. The apparatus according to claim 2, wherein the apparatus comprises: The system base chip (SBC) registers are used to store the output of the signal detector; and The input path of the circuit extends from the pad to the register. The pads are powered by a first power supply voltage providing the first voltage level, and the input path of the circuit is powered by a second power supply voltage providing the second voltage level.

4. The apparatus of claim 3, wherein the input path includes a high-value series resistor to limit the current flowing through the circuit when a high voltage is applied to the pad.

5. The apparatus according to claim 3, wherein the apparatus comprises: An interrupt signaler is used to communicate an event based at least in part on information stored in the register of the SBC.

6. The apparatus of claim 1, wherein the system base chip implements an 10SPE PHY transceiver.

7. The apparatus according to claim 1, wherein the apparatus comprises: A register, which is used to store the output signal; and The output path of the circuit extends from the register to the pad. The pads are powered by a first power supply voltage providing the first voltage level, and the output path of the circuit is powered by a second power supply voltage providing the second voltage level.

8. An apparatus comprising: A microcontroller that implements a controller for the 10SPE physical layer (PHY); and The system base chip, which implements the transceiver of the 10SPE PHY, The system base chip is used to receive and process high-voltage external signals and to interface the high-voltage external signals with the low-voltage domain of the microcontroller (MCU).

9. The apparatus of claim 8, wherein the high-voltage external signal includes an external wake-up signaling, and the system base chip is used for: An internal wake-up signaling is generated to represent the external wake-up signaling, wherein the voltage range of the high-voltage external signaling is limited between a ground voltage level and a first voltage level, and the voltage range of the internal wake-up signaling is limited between a ground voltage and a second voltage level lower than the first voltage level.

10. The apparatus of claim 9, wherein the system base chip is configured to communicate a wake-up event to the MCU based at least in part on the internal wake-up signaling.

11. The apparatus of claim 9, wherein the system base chip is used to provide the internal wake-up signaling to the MCU.

12. A method, the method comprising: Signaling is received at the system base chip that implements the 10SPE PHY transceiver; At the system base chip, the signaling is changed from a first voltage level that is incompatible with the voltage domain of the microcontroller (MCU) implementing the 10SPE PHY to a second voltage level that is compatible with the voltage domain of the MCU; as well as The changed signaling is transmitted to the MCU.

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