Intelligent test method and device for digital chip and electronic equipment
By establishing a chip model, analyzing response data, and generating adaptive test sequences, the problem of insufficient evaluation of the dynamic characteristics of digital chips in existing technologies is solved, and efficient and accurate performance and reliability evaluation is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-10
- Publication Date
- 2026-04-10
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing technologies struggle to fully capture the key behavioral characteristics of digital chips under dynamic operating conditions, especially lacking effective quantitative assessment and in-depth diagnosis of potential performance degradation and marginal failures. The testing process also lacks adaptability and intelligent closed-loop, resulting in low testing efficiency.
A model of the chip under test is established, behavioral parameters are extracted by reading and analyzing response data, a test decision model is constructed, an adaptive test sequence is generated, iterative testing is performed, and a test report is generated.
It enables efficient and accurate evaluation of the dynamic performance and reliability of digital chips, and can adaptively apply stress for in-depth probing, identify functional faults, and improve testing depth and efficiency.
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Figure CN121831471A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip testing, and in particular to an intelligent testing method, device and electronic equipment for digital chips. BACKGROUND
[0002] With the continuous evolution of semiconductor technology, the design complexity and integration of digital chips continue to improve, and higher requirements are put forward for their testing methods. Traditional testing schemes mostly rely on preset fixed test vectors and static criteria, which are difficult to fully capture key behavior characteristics such as timing boundaries, signal integrity and power noise sensitivity of chips in dynamic working state, especially for potential performance degradation and marginal faults lack effective quantitative evaluation and deep diagnosis ability. Therefore, it is urgent to develop a method that can simulate real working conditions, intelligently analyze the dynamic characteristics of chips and adaptively generate targeted test sequences to realize efficient and accurate evaluation of the performance, reliability and robustness of digital chips.
[0003] The existing digital chip testing method mainly has the following deficiencies: first, it mostly relies on pre-prepared fixed test vector sets, the testing scene is single, and it is difficult to cover all behavior characteristics of the chip under actual complex dynamic working conditions, especially it is not sensitive to marginal failure modes; second, the testing criteria are mostly simple function correctness checks, lacking quantitative extraction and analysis capabilities of deep performance parameters such as signal quality and timing margin; third, the testing process lacks adaptability and intelligent closed loop, and cannot dynamically adjust the testing strategy according to the real-time response of the chip, resulting in low detection efficiency of potential defects, limited amount of testing report information, and difficulty in supporting deep performance evaluation and reliability analysis. SUMMARY
[0004] The present application relates to the technical field of chip testing, and in particular to an intelligent testing method, device and electronic equipment for digital chips.
[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:
[0006] An intelligent testing method for digital chips, comprising:
[0007] establishing a model of the chip under test and performing a baseline test;
[0008] reading and analyzing the response data to extract behavior parameters;
[0009] constructing a test decision model based on the behavior parameters to generate a test sequence;
[0010] iterative testing based on the test sequence and generating a test report.
[0011] Further, when performing the initial benchmark test, the system calls the primitive operations in the benchmark primitive operation knowledge base to generate a benchmark sequence B0.
[0012] Further, the complete analog waveform W(t) of the target data line is captured at a sampling frequency Fs at least 5 times the clock frequency, 2 clock cycles before and after the clock active edge, the number of times the voltage crosses the threshold voltage is counted as the oscillation number, the time from when the voltage first deviates from the original steady state level by 10% to when the voltage enters and remains within the voltage tolerance band centered on the target steady state level with a tolerance of ±5% is measured as the settling time, the absolute value of the difference between the waveform peak value and the nominal high level is measured as the overshoot amplitude, and the logic state transition abnormality index is determined based on the oscillation number, the settling time and the overshoot amplitude, the expression of the logic state transition abnormality index is: LS = w1 x (OC / Nr) + w2 x (Ts / Tr) + w3 x (Vo / vo), where LS represents the logic state transition abnormality index, OC represents the oscillation number, Ts represents the settling time, Vo represents the overshoot amplitude, w1, w2, w3 represent the parameter weights, Nr represents the reference oscillation number, Tr represents the reference settling time, and vo represents the design allowed overshoot tolerance.
[0013] Further, after the benchmark test, a timing probe test sub-process is initiated, starting from (0.7 x nominal working frequency) and ending at min(1.3 x nominal working frequency, maximum clock frequency), with a frequency scanning step of (0.05 x nominal working frequency), a pseudo-random sequence containing 1000 bytes is sent as a test vector at each test frequency point fi, and the error rate BERi of the read-back data is recorded, a scatter plot of (fi, BERi) is drawn, and a piecewise linear fitting is used to obtain the BER(f) function, and the test frequency point corresponding to the first time the error rate rises from 0 or the noise floor to 0.001 is estimated as the timing tolerance decay gradient on the first derivative of the BER(f) function.
[0014] Further, two decision rules are set based on the behavior parameters, including a decision rule for signal integrity vulnerability and a decision rule for insufficient timing margin.
[0015] Further, the decision rule for signal integrity vulnerability is that when LS>ls, it is determined that the chip has a signal integrity problem or is sensitive to switching noise, the generation strategy is turned to power integrity stress testing, and a test sequence is generated as a square wave data stream with dense 0xFF and 0x00 alternation, lasting 10ms, and a short voltage disturbance of (nominal IO level voltage ± 0.1) is inserted in the sequence.
[0016] Further, the decision rule for the insufficient timing margin is that when TG>tg and fth<the nominal operating frequency, it is determined that the chip timing margin is tight or there is a critical path defect, the strategy is turned to the timing boundary stress and abnormal protocol test, and a test sequence is generated as a pseudo-random data communication test running at a frequency of (0.95xfth) for 1 second, and a gap with a length of (0.3xstandard minimum idle time) is inserted between continuous data transmissions.
[0017] Further, the test sequence is downloaded to the test equipment for execution, new response data is collected, and the process of extracting the behavior parameter is iterated, and the convergence conditions are set as: the variation amplitude of the behavior parameter in three consecutive iterations is less than 5% of the corresponding abnormal index threshold and the decay gradient threshold, in any iteration, the test appears a functional hard error or LS>3 or fth<(0.8xthe nominal operating frequency); the total test time reaches the preset upper limit of time or the iteration number reaches the preset upper limit of iteration, when any of the above convergence conditions is met, it is determined that the test converges, and a test report is generated.
[0018] On the other hand, the present application also provides an intelligent test device for a digital chip, comprising:
[0019] a benchmark test unit for establishing a model of the chip under test and performing a benchmark test;
[0020] a parameter extraction unit for reading and analyzing the response data to extract the behavior parameter;
[0021] a test analysis unit for constructing a test decision model based on the behavior parameter to generate a test sequence;
[0022] an iterative test unit for iterative testing based on the test sequence and generating a test report.
[0023] On the other hand, the present application also provides an electronic device, comprising:
[0024] one or more processors;
[0025] a storage device for storing one or more programs;
[0026] when the one or more programs are executed by the one or more processors, the one or more processors implement the intelligent test method for a digital chip as described above.
[0027] The beneficial effects of the present application are as follows: a complete intelligent test framework from automatic reference establishment, intelligent behavior parameter extraction, data-driven decision to closed-loop iterative verification is provided, which breaks through the staticity and limitation of the traditional test method, can dynamically perceive and quantify the key characteristics of the chip in real work, such as signal integrity, timing margin, etc., and adaptively applies the most relevant stress for deep detection, realizes efficient identification of functional faults, and can more comprehensively evaluate the dynamic performance boundary and potential reliability risk of the chip, provides a powerful intelligent tool for chip design verification, quality screening and fault analysis, and improves the depth, efficiency and value of the test. BRIEF DESCRIPTION OF DRAWINGS
[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0029] Figure 1 The flowchart of the intelligent test method for digital chips in the present embodiment.
[0030] Figure 2 The flowchart of the behavior parameter extraction method in the present embodiment.
[0031] Figure 3 The structural schematic diagram of the intelligent test device for digital chips in the present embodiment.
[0032] Figure 4 The structural schematic diagram of the electronic device in the present embodiment. DETAILED DESCRIPTION
[0033] The intelligent test method, device and electronic device for digital chips disclosed by the present application will be further described in detail in combination with the drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered in isolation, and they can be combined with each other to achieve better technical effects. In the drawings of the following embodiments, the same reference numerals in different drawings represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0034] It should be noted that the structure, proportion, size, etc. shown in the drawings attached to the present specification are only used to cooperate with the content disclosed in the specification, so that those skilled in the art can understand and read, and are not used to limit the conditions for implementing the application. Any modification of structure, change of proportion relationship or adjustment of size, which does not affect the effect and purpose of the application, should be within the scope of the disclosed technology. The scope of the preferred embodiments of the present application includes additional implementations, in which the functions can be performed in a substantially simultaneous manner or in reverse order according to the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.
[0035] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered part of the specification when appropriate. In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Thus, other examples of the exemplary embodiments can have different values.
[0036] In the description of the embodiments of the present application, " / " represents the meaning of or, and "and / or" is used to describe the association relationship of the associated objects, which means that there can be three relationships, such as "A and / or B", which means that A and B exist alone, B exists alone, and A and B exist simultaneously. In the description of the embodiments of the present application, "multiple" means two or more embodiments.
[0037] Please refer to Figure 1 As shown in the figure, the intelligent test method for digital chips of the present embodiment comprises:
[0038] Please continue to refer to Figure 1 As shown in the figure, the intelligent test method for digital chips further comprises:
[0039] Step S1, establishing a model of the chip to be tested and performing a reference test.
[0040] Specifically, in step S1, a test file is established for the digital chip under test, and key interface specification parameters are entered to form a structured chip under test model. The key interface specification parameters include interface type to be tested, interface mode configuration, nominal operating frequency, nominal IO level voltage, data bit width, etc. The interface type to be tested includes SPI, I2C, and UART. The interface mode configuration includes CPOL and CPHA of SPI. Meanwhile, a preset reference test primitive operation knowledge base is loaded. The reference test primitive operation knowledge base contains a series of combinable and atomized test stimulus generation functions. The test stimulus generation functions are instruction functions for testing, such as configuring test equipment master clock output frequency, configuring test equipment output channel high / low level voltage value, sending a specific data sequence, reading data from a specified acquisition channel, and adding a specified timing jitter on the clock or data line.
[0041] Specifically, in step S1, when performing initial reference testing, the system calls the primitives in the reference test primitive operation knowledge base to generate a reference test sequence B0. For example, for an SPI interface chip, the frequency is set to 0.8 times the nominal operating frequency, the voltage is set to the nominal IO level voltage, a preset verification data mode array [0x55, 0xAA, 0xF0, 0x0F, 0x00, 0xFF] is continuously sent, and the response data R0 of the chip under standard working conditions is obtained through the read-back function. Based on the above, the test stimulus generation function for this function is called from the reference test primitive operation knowledge base to combine into a reference test sequence.
[0042] Specifically, in step S1, by establishing a structured model for the chip under test and calling the combinable reference test primitive operation knowledge base, the automation and standardization of test initialization are achieved. This method not only quickly adapts to chips of different interface types and working modes, but also provides stable and repeatable reference working conditions for subsequent testing, ensuring the consistency and comparability of the testing process and laying a reliable data foundation for intelligent analysis.
[0043] In step S2, the response data is read and analyzed to extract behavior parameters, including a logic state transition abnormality index and a timing tolerance degradation gradient.
[0044] Referring to Figure 2 As shown in the figure, the behavior parameter extraction method includes:
[0045] In step S21, the logic state transition abnormality index is extracted.
[0046] Specifically, in step S21, the complete analog waveform W(t) of the target data line is captured 2 clock periods before and after the clock active edge at a sampling frequency Fs of at least 5 times the clock frequency, the number of times of crossing the threshold voltage is counted as the oscillation number, the time from the voltage first deviating from the original steady state level by 10% to the voltage finally entering and remaining within the voltage tolerance band centered on the target steady state level ±5% is measured as the settling time, the absolute value of the difference between the waveform peak value and the rated high level is measured as the overshoot amplitude, and the logic state transition abnormality index is determined based on the oscillation number, the settling time and the overshoot amplitude, the expression of the logic state transition abnormality index being: LS = w1 x (OC / Nr) + w2 x (Ts / Tr) + w3 x (Vo / vo), wherein LS represents the logic state transition abnormality index, OC represents the oscillation number, Ts represents the settling time, Vo represents the overshoot amplitude, w1, w2 and w3 represent parameter weights, Nr represents the reference oscillation number, Tr represents the reference settling time, and vo represents the design-allowed overshoot tolerance. The threshold voltage is set as (voltage maximum value + voltage minimum value) / 2, the process amplitude can also measure the absolute value of the difference between the waveform valley value and the rated low level, and the reference oscillation number and the reference settling time are the mean values of each data counted from historical good chip data, w1 is set as 0.4, w2 is set as 0.4, and w3 is set as 0.2 in this embodiment, and w1, w2 and w3 are weights set according to the degree of influence of each factor on the function.
[0047] Please continue to refer to Figure 2 As shown, the behavior parameter extraction method further includes:
[0048] Step S22, calculate the timing tolerance degradation gradient.
[0049] Specifically, in step S22, after the baseline test, a timing probe test sub-process is initiated, starting from (0.7x nominal operating frequency) and ending at min(1.3x nominal operating frequency, maximum clock frequency), with a frequency scan step of (0.05x nominal operating frequency), a pseudo-random sequence of 1000 bytes is sent as a test vector at each test frequency point fi, and the error rate BERi of the read-back data is recorded, a scatter plot of (fi, BERi) is drawn, and a piecewise linear fitting is used to obtain the BER(f) function. The test frequency point corresponding to the first time the error rate rises from 0 or the noise floor to 0.001 on the first derivative estimate of the BER(f) function is taken as the timing margin decay gradient. The simplified expression of the timing margin decay gradient is: TG = (BER(fth+Δf)-BER(fth)) / Δf, where TG represents the timing margin decay gradient, fth represents the test frequency point when the error rate is 0.001, and Δf represents the change in test frequency point when the error rate first rises from 0 or the noise floor to 0.001. The pseudo-random sequence uses PRBS7.
[0050] Specifically, in step S2, through high-precision waveform analysis of the read-back data and systematic frequency scan testing, two parameters beyond simple "pass / fail" judgment are extracted: the logic state transition abnormality index and the timing margin decay gradient. They accurately characterize the dynamic behavior and robustness boundary of the chip from two dimensions: microscopic changes in signal quality and macroscopic decay in system performance, providing quantifiable and high-discrimination input features for subsequent intelligent decision-making.
[0051] Step S3, constructing a test decision-making model based on the behavior parameters to generate a test sequence.
[0052] Specifically, in step S3, a strategy decision matrix is preset, which maps the behavior parameters to specific test reinforcement directions and sequence generation strategies.
[0053] Specifically, in step S3, two decision rules are set based on the behavior parameters, including a decision rule for signal integrity vulnerability and a decision rule for timing margin deficiency.
[0054] The decision rule for signal integrity vulnerability is that when LS>ls, it is determined that the chip has a signal integrity problem or is sensitive to switching noise, the generation strategy is turned to power integrity stress testing, and a test sequence is generated as a dense square wave data stream alternating between 0xFF and 0x00 for 10ms, and a short voltage disturbance of (nominal IO level voltage ± 0.1) is inserted in the sequence.
[0055] The decision rule for insufficient timing margin is that when TG > tg and fth < nominal operating frequency, it is determined that the chip timing margin is tight or there is a critical path defect, the strategy is turned to the timing boundary stress and abnormal protocol test, and the test sequence is generated as a pseudo-random data communication test running at a frequency of (0.95 x fth) for 1 second, and a gap with a length of (0.3 x standard minimum idle time) is inserted between continuous data transmissions. ls represents the abnormal index threshold, which can be obtained by testing a batch of known qualified chips to obtain their logic state transition abnormal index, taking (the mean value of the logic state transition abnormal index of the batch of qualified chips + 2 times the standard deviation of the logic state transition abnormal index of the batch of qualified chips) as the initial threshold, and can be fine-tuned according to the false positive rate in subsequent use; Tg represents the decay gradient threshold, which is obtained based on the regression analysis of the test data of multiple chips on the pass / fail edge, and the standard minimum idle time is from the public protocol specification of chip or interface standards.
[0056] Specifically, in the step S3, for the test sequence generated by the decision rule for signal integrity vulnerability, the purpose is to maximize the simultaneous flip current on the data bus, and to observe the change of the logic state transition abnormal index and the bit error rate under slight undervoltage or overvoltage conditions; for the test sequence of the decision rule for insufficient timing margin, the purpose is to check whether there are occasional errors.
[0057] Specifically, in the step S3 of the embodiment, the system does not rely on fixed test scripts, but uses the behavior parameters obtained by real-time analysis as the basis for decision, and dynamically selects the test direction that is most likely to expose the current weakness through the built-in strategy rule library. The thresholds involved in the decision rule are derived from statistical analysis of historical test data or public standards, ensuring the scientificity of the decision. This step realizes the fundamental change of the test content from "preset" to "response-driven generation".
[0058] Step S4, iterative testing based on the test sequence and generating a test report.
[0059] Specifically, in step S4 of this embodiment, the test sequence is downloaded to the test device for execution, new response data is collected, and the process of extracting behavioral parameters is iterated. The convergence conditions are set as follows: the change amplitude of the behavioral parameters in three consecutive iterations is less than 5% of their corresponding anomaly index threshold and decay gradient threshold; in any iteration, a functional hard error occurs, or LS > 3, or fth < (0.8 × nominal operating frequency); the total test time reaches a preset time limit or the number of iterations reaches a preset iteration limit. When any of the above convergence conditions are met, the test is determined to be converged, and a test report is generated. The functional hard error includes permanent and structural faults such as continuous bit errors and timing violations. In this embodiment, the preset time limit is set to 60 seconds, and the preset iteration limit is set to 10 times.
[0060] Specifically, in step S4 of this embodiment, the test report includes basic function verification conclusions, dynamic characteristic parameter profiles, limit capability assessments, potential weakness diagnosis, and test path tracing. The basic function verification conclusions refer to whether the chip passes the standard benchmark test B0. The dynamic characteristic parameter profiles record the evolution curves and final values of the logic state transition anomaly index and timing tolerance decay gradient throughout the entire iteration process. The limit capability assessments are the measured upper limit of the stable operating frequency and the tolerance range for voltage fluctuations. The potential weakness diagnosis, based on the triggered decision rules, clearly indicates whether the chip is more sensitive to "switching noise" or "timing disturbances." The test path tracing records all test sequence numbers automatically generated and executed by the system, the decision rules that triggered the sequence, and the parameter states at that time.
[0061] Specifically, in step S4 of this embodiment, by introducing closed-loop iteration and explicit convergence conditions, the testing process can autonomously and purposefully conduct multiple rounds of "flaw detection" and "verification" of potential chip defects until a stable understanding of the chip characteristics is formed or a clear fault is discovered. The final generated report goes beyond the traditional "Pass / Fail" label, providing in-depth insights into the chip's dynamic performance, robustness boundaries, and potential risks.
[0062] Please see Figure 3 As shown, this is an intelligent testing device for digital chips in this embodiment, comprising:
[0063] The benchmark unit is used to build a model of the chip under test and perform benchmark tests.
[0064] The parameter extraction unit is used to read and analyze response data to extract behavioral parameters;
[0065] The test analysis unit is used to build a test decision model based on behavioral parameters to generate test sequences;
[0066] The iterative test unit is used to perform iterative tests based on a test sequence and generate a test report.
[0067] Please see Figure 4 As shown, it is a structural schematic diagram of an electronic device in this embodiment. The electronic device 60 in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.
[0068] like Figure 4 As shown, the electronic device 60 may include a processing unit 61, which can perform various appropriate actions and processes to implement the methods of the embodiments described herein, based on a program stored in ROM 62 or a program loaded from storage device 68 into RAM 63. RAM 63 also stores various programs and data required for the operation of the electronic device 60. The processing unit 61, ROM 62, and RAM 63 are interconnected via bus 64. I / O interface 65 is also connected to bus 64. Typically, the following devices can be connected to I / O interface 65: input devices 66 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 67 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 68 including, for example, magnetic tapes, hard disks, etc.; and communication devices 69. Communication device 69 allows the electronic device 60 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 4 An electronic device 60 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.
[0069] Specifically, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts, thereby implementing the methods as described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 69, or installed from a storage device 68, or installed from a ROM 62. When the computer program is executed by the processing device 61, it performs the functions defined in the methods of the embodiments of the present invention.
[0070] Specifically, the computer-readable medium described in this embodiment may be included in the aforementioned electronic device; or it may exist independently and not be assembled into the electronic device.
[0071] Specifically, in this embodiment, the computer-readable medium carries one or more programs. When the electronic device executes one or more of these programs, the electronic device causes the electronic device to: establish a model of the chip under test and perform benchmark tests; read and analyze response data to extract behavioral parameters; construct a test decision model based on the behavioral parameters to generate a test sequence; perform iterative tests based on the test sequence and generate a test report.
[0072] In the above description, the disclosure of this invention is not intended to limit itself to these aspects. Rather, within the scope of the objectives of this disclosure, components can be selectively and operationally combined in any number. Furthermore, terms such as “comprising,” “encompassing,” and “having” should be interpreted by default as inclusive or open-ended, rather than exclusive or closed, unless explicitly defined as such. All technical, scientific, or other terms are to be understood by those skilled in the art, unless defined as such. Public terms found in dictionaries should not be interpreted in the context of the relevant technical documents in an overly idealistic or impractical manner, unless explicitly defined as such in this disclosure. Any modifications or alterations made by those skilled in the art based on the foregoing disclosure are within the scope of the claims.
Claims
1. An intelligent testing method for digital chips, characterized in that, include: Establish a model of the chip under test and perform benchmark tests; Read and analyze the response data to extract behavioral parameters; A test decision model is built based on behavioral parameters to generate test sequences; Iterative testing is performed based on the test sequence, and a test report is generated.
2. The intelligent testing method for digital chips according to claim 1, characterized in that, When executing the initial benchmark test, the system calls the meta-operations in the benchmark meta-operation knowledge base to combine and generate a benchmark sequence B0.
3. The intelligent testing method for digital chips according to claim 2, characterized in that, The complete analog waveform W(t) of the target data line is captured at a sampling frequency Fs at least 5 times the clock frequency for 2 clock cycles before and after the effective edge of the clock. The number of times it crosses the threshold voltage is counted as the number of oscillations. The time taken from the initial 10% deviation of the voltage from the original steady-state level to the final entry and maintenance of the voltage within a ±5% voltage tolerance band centered on the target steady-state level is measured and taken as the settling time. The absolute value of the difference between the peak value of the waveform and the rated high level is measured as the overshoot amplitude. Based on the number of oscillations, the settling time, and the overshoot amplitude, the logic state transition anomaly index is determined. The expression for the logic state transition anomaly index is: LS = w1 × (OC / Nr) + w2 × (Ts / Tr) + w3 × (Vo / vo), where LS represents the logic state transition anomaly index, OC represents the number of oscillations, Ts represents the settling time, Vo represents the overshoot amplitude, w1, w2, and w3 represent parameter weights, Nr represents the reference number of oscillations, Tr represents the reference settling time, and vo represents the design-allowed overshoot tolerance.
4. The intelligent testing method for digital chips according to claim 3, characterized in that, After benchmark testing, a timing probe test subprocess is initiated, starting at (0.7 × nominal operating frequency) and ending at min(1.3 × nominal operating frequency, maximum clock frequency). The frequency scan step is set to (0.05 × nominal operating frequency). At each test frequency point fi, a pseudo-random sequence containing 1000 bytes is sent as a test vector, and the bit error rate BERi of the readback data is recorded. A scatter plot of (fi,BERi) is plotted, and the BER(f) function is obtained by piecewise linear fitting. The first derivative estimate of the BER(f) function at the test frequency point corresponding to the first rise of the bit error rate from 0 or the noise floor to 0.001 is used as the timing tolerance fading gradient.
5. The intelligent testing method for digital chips according to claim 4, characterized in that, Two decision rules are set based on behavioral parameters, namely a decision rule for signal integrity fragility and a decision rule for insufficient timing margin.
6. The intelligent testing method for digital chips according to claim 5, characterized in that, The decision rule for signal integrity vulnerability is as follows: when LS > ls, it is determined that the chip has a signal integrity problem or is sensitive to switching noise. The generation strategy is then switched to power integrity stress test, and the test sequence is generated as a dense transmission of square wave data streams alternating between 0xFF and 0x00, lasting for 10ms, with short voltage disturbances (nominal IO level voltage ±0.1) inserted into the sequence.
7. The intelligent testing method for digital chips according to claim 4, characterized in that, The decision rule for insufficient timing margin is as follows: when TG > tg and fth < nominal operating frequency, it is determined that the chip timing margin is tight or there is a critical path defect. The generation strategy is then shifted to timing boundary pressure and abnormal protocol testing, and a test sequence is generated as a pseudo-random data communication test running at a frequency of (0.95 × fth) for 1 second, with an interval of (0.3 × the minimum idle time specified by the standard) inserted between continuous data transmissions.
8. The intelligent testing method for digital chips according to claim 7, characterized in that, The test sequence is downloaded to the test device for execution, new response data is collected, and the process of extracting behavioral parameters is iterated. The convergence conditions are set as follows: the change amplitude of the behavioral parameters in three consecutive iterations is less than 5% of their corresponding anomaly index threshold and decay gradient threshold; in any iteration, a functional hard error occurs or LS > 3 or fth < (0.8 × nominal operating frequency); the total test time reaches the preset time limit or the number of iterations reaches the preset iteration limit. When any of the above convergence conditions are met, the test is determined to be converged, and a test report is generated.
9. An intelligent testing device for digital chips, applied to the intelligent testing method for digital chips as described in any one of claims 1-8, characterized in that, include: The benchmark unit is used to build a model of the chip under test and perform benchmark tests. The parameter extraction unit is used to read and analyze response data to extract behavioral parameters; The test analysis unit is used to build a test decision model based on behavioral parameters to generate test sequences; The iterative test unit is used to perform iterative tests based on a test sequence and generate a test report.
10. An electronic device, characterized in that, The electronic device includes: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the intelligent testing method for digital chips as described in any one of claims 1-8.