Mask marking and generating method, photolithography method, and measurement method of overlay error

Abstract

The application provides a mask mark and a generation method, a photolithography method and a measurement method of overlay error. A first pattern in the mask mark can be used to realize position alignment between different mask plates, so as to avoid the influence of placement error on the detection accuracy of overlay error and avoid systematic overlay error. In addition, by obtaining the deviation between the first patterns at the same position in different mask plates, the placement error of the mask plate can be accurately monitored. Furthermore, on the basis of the alignment of the first pattern, the second pattern can be used to accurately detect the overlay error between each film layer and the reference film layer, which is beneficial to optimizing the photolithography process effect and improving the performance and yield of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication technology, and in particular to a mask marking and generation method, a photolithography method, and a method for measuring overlay error. Background Technology

[0002] In photolithography design, it's assumed that the patterns on photomasks for different layers of the same product are aligned. However, in actual processes, deviations inevitably exist between these patterns, known as placement errors. These placement errors directly affect the measurement of overlay errors between different layers on the wafer. Ideally, the placement positions of modified, backup, and replacement photomasks for the same layer should remain strictly consistent. However, in reality, due to fluctuations in photomask materials and technology, these modified, backup, and replacement photomasks also inevitably have placement errors. This leads to fluctuations in process stability and a reduction in the overlay error window.

[0003] Because photomasks cannot directly monitor interlayer alignment using layer-to-layer overlay marks like wafers, the current industry standard is to use registration marks in the fiducial marks of the photomask's non-functional areas to measure their offset relative to the design coordinates, thereby assessing the photomask's own placement error. However, due to hardware limitations, the pattern design, number, and position of registration marks differ between different lithography machines, making it difficult to calculate the placement error between photomasks. Furthermore, the registration marks in non-functional areas are far from the main pattern in functional areas, so the calculated offset cannot accurately reflect the overlay error of the main pattern. Additionally, in the photomask frame area, because the functional priority of registration marks is lower than that of alignment marks, overlay marks (OVL marks), and linewidth measurement bars (CD bars), the placement and number of registration marks are extremely limited, thus affecting the assessment of the photomask's own overlay accuracy. Furthermore, as technology nodes continue to shrink, lithography processes need to evolve towards higher-order overlay, requiring a corresponding increase in the number of overlay marks and registration marks, which the limited border area cannot meet.

[0004] Therefore, a new method for monitoring mask placement errors is urgently needed to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide a mask marking and generation method, a photolithography method, and a method for measuring overlay error, so as to solve at least one of the following problems: how to monitor the placement error between mask templates, how to improve the accuracy of overlay error measurement, and how to improve the photolithography process effect.

[0006] To address the aforementioned technical problems, this invention provides a mask mark, which is applied to multiple mask templates on the same chip, and the mask mark includes registration marks and overlay marks; wherein,

[0007] The registration mark includes a first pattern; the overlay mark includes a plurality of second patterns; and the plurality of second patterns are spaced apart around the first pattern; and,

[0008] In the same placement position, all the first patterns in the plurality of photomasks can overlap and be aligned, and all the second patterns in the plurality of photomasks are interspersed and spaced apart from each other.

[0009] Optionally, in the mask markings, at least one mask marking is formed in each of the mask templates, and the distribution of the mask markings corresponds to the virtual graphic area of ​​the functional area of ​​the chip.

[0010] Optionally, in the mask markings, among the plurality of mask templates, the size of the first pattern is the same in all the mask markings, and the size of the second pattern is the same in all the mask markings; wherein the size of the second pattern is smaller than the size of the first pattern.

[0011] Optionally, in the mask markings, the mask template may also include a modified version, a backup version, and a replacement version of the mask template corresponding to each film layer of the chip.

[0012] Optionally, in the mask marking, the first pattern is cross-shaped, and the length of the first pattern is greater than or equal to 3.8 micrometers, and the width of the first pattern is greater than or equal to 0.3 micrometers and less than or equal to 15 micrometers.

[0013] Optionally, in the mask marking, the shape of the second pattern includes a cross or a star shape, and the length of the second pattern is greater than or equal to 4.5 micrometers, and the width of the second pattern is greater than or equal to 4.5 micrometers.

[0014] Optionally, in the mask mark, the mask mark is square, and the first pattern is located at the center of the mask mark.

[0015] Based on the same inventive concept, the present invention also provides a method for generating mask marks, for generating the mask marks, and the method for generating mask marks includes:

[0016] Based on mask rule checks and chip design rules, determine the allowable size of the mask marks within the functional areas of all film layers in the chip;

[0017] Add the size and shape of the mask mark to the generation rules of the virtual graphics area within the functional area;

[0018] At least according to the generation rules of the virtual graphic region, the mask mark corresponding to the virtual graphic region of each of the film layers is automatically generated, so that the first patterns of all the mask marks at the same position in all the film layers can overlap and be aligned, and all the second patterns are intersected and spaced apart from each other.

[0019] Based on the same inventive concept, the present invention also provides a method for monitoring mask placement error, comprising:

[0020] Provide at least two mask templates, and the at least two mask templates have the mask markings described above;

[0021] Select a gold mask from the at least two mask templates;

[0022] Using the first pattern in the gold photomask as a reference pattern, the deviation between the first pattern in the other photomasks and the reference pattern is obtained as the placement error of the photomask.

[0023] Based on the same inventive concept, the present invention also provides a mask group, which is applied to the same chip and includes multiple mask templates, the multiple mask templates having the mask markings described above.

[0024] Based on the same inventive concept, the present invention also provides a photolithography method, comprising:

[0025] Provide the aforementioned mask set;

[0026] Select a gold mask from the mask group;

[0027] The gold mask is used to form a first pattern and a plurality of second patterns on a chip as reference marks;

[0028] Before performing the photolithography process on any of the remaining photomasks in the photomask group, the first pattern in the selected photomask is aligned with the first pattern in the reference mark using an optical inspection device before the photolithography process is performed.

[0029] Based on the same inventive concept, the present invention also provides a method for measuring overlay error, comprising:

[0030] The aforementioned photolithography method is used to perform a photolithography process on a chip;

[0031] Measure the first error between the first pattern on the current film of the chip and the first pattern in the reference mark; and,

[0032] The second error between the plurality of second patterns on the current layer film of the chip and the plurality of second patterns in the reference mark is measured;

[0033] The overlay error between the current layer film and the film layer containing the reference mark is obtained based on the first error and the second error.

[0034] In summary, this invention provides a mask marking and generation method, a photolithography method, and a method for measuring overlay error. Compared to existing technologies, the first pattern in the mask marking can be used to achieve positional alignment between different masks, thereby avoiding placement errors from affecting the accuracy of overlay error detection and preventing systematic overlay errors. Furthermore, by obtaining the deviation between the first patterns at the same position in different masks, precise monitoring of mask placement errors can be achieved. Additionally, based on the alignment of the first pattern, the second pattern can be used to accurately detect the overlay error between each film layer and the reference film layer, which is beneficial for optimizing photolithography process effects and improving device performance and yield. Attached Figure Description

[0035] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.

[0036] Figure 1 This is a schematic diagram of a combination of various mask markings in an embodiment of the present invention.

[0037] Figure 2 This is a schematic diagram of the first pattern in an embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram of the pattern of the first mask mark in an embodiment of the present invention.

[0039] Figure 4 This is a schematic diagram of the pattern of the second mask mark in an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of the combined pattern of the first mask mark and the second mask mark in an embodiment of the present invention.

[0041] Figure 6 This is a schematic diagram of the pattern of the third mask mark in an embodiment of the present invention.

[0042] Figure 7 This is a schematic diagram of the pattern of the fourth mask mark in an embodiment of the present invention.

[0043] Figure 8This is a schematic diagram of the combined pattern of the third mask mark and the fourth mask mark in an embodiment of the present invention.

[0044] Figure 9 This is a schematic diagram showing the positions of the functional area and the virtual graphics area in an embodiment of the present invention.

[0045] Figure 10 This is a flowchart of the mask mark generation method in an embodiment of the present invention.

[0046] Figure 11 This is a flowchart of a method for monitoring mask placement error in an embodiment of the present invention.

[0047] Figure 12 This is a flowchart of the photolithography method in an embodiment of the present invention.

[0048] Figure 13 This is a flowchart of the method for measuring overlay error in an embodiment of the present invention.

[0049] And, in the attached image:

[0050] 100 - First pattern; 101 - Second pattern; D - Function area; M - Virtual graphic area. Detailed Implementation

[0051] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clearly illustrate the objectives of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0052] Please see Figure 1 This embodiment provides a mask mark, which is applied to multiple mask templates of the same chip, and the mask mark includes a registration mark and an overlay mark; wherein, the registration mark includes a first pattern 100; the overlay mark includes multiple second patterns 101; and the multiple second patterns 101 are distributed at intervals around the first pattern 100; and, in the same placement position, all the first patterns 100 in the multiple mask templates can overlap and be aligned, and all the second patterns 101 in the multiple mask templates are intersected and spaced apart from each other.

[0053] Based on this, the first pattern 100 in the mask markings provided in this embodiment can be used to achieve positional alignment between different masks, so as to avoid placement errors affecting the detection accuracy of overlay errors and avoid systematic overlay errors. Furthermore, by obtaining the deviation between the first patterns 100 at the same position in different masks, precise monitoring of mask placement errors can also be achieved. Moreover, based on the alignment of the first pattern 100, the second pattern 101 can be used to accurately detect the overlay errors between each film layer and the reference film layer, which is beneficial for optimizing the photolithography process and improving device performance and yield.

[0054] The mask markings provided in this embodiment are described in detail below with reference to the accompanying drawings.

[0055] It should be noted that each chip has multiple film layers, and different masks are required to fabricate different film layers. Therefore, multiple masks are needed for the same chip, and the placement error between the masks will affect the overlay error between film layers, ultimately affecting device performance and yield.

[0056] Therefore, the mask markings provided in this embodiment are applied to multiple masks on the same chip, aiming to strictly control placement errors between masks and to help improve lithography accuracy. Specifically, each mask has at least one mask marking, and the mask marking includes a registration mark and an overlay mark. That is, the mask marking is composed of the registration mark and the overlay mark. The registration mark is used to monitor placement errors between masks and to achieve alignment between masks. The overlay mark is used to monitor overlay errors between different film layers of the chip.

[0057] Please see Figure 1 and Figure 2 The registration mark includes a first pattern 100. Preferably, the first pattern 100 is cross-shaped, and the length of the first pattern 100 is greater than or equal to 3.8 micrometers, and the width of the first pattern 100 is greater than or equal to 0.3 micrometers and less than or equal to 15 micrometers. In this embodiment, the length and width refer to the horizontal and vertical dimensions, respectively.

[0058] Furthermore, in all the photomasks corresponding to the chip, the first pattern 100 in the mask markings has the same size and shape, and when the photomasks are located in the same position, for example, when they are stacked, the first pattern 100 in each mask marking can overlap and align. Therefore, the first pattern 100 provided in this embodiment is used to achieve positional alignment between photomasks and to monitor placement errors.

[0059] Please see Figure 1 and Figures 3 to 8The overlay markings include a plurality of second patterns 101. The plurality of second patterns 101 are spaced apart around the first pattern 100. Preferably, the size of the second pattern 101 is smaller than the size of the first pattern 100, so the plurality of second patterns 101 can be scattered around the first pattern 100. It should be noted that the distribution of the second patterns 101 in different photomasks for the same chip is different, and when the photomasks are located in the same position, for example, stacked, all the second patterns 101 in the plurality of photomasks are intersected on the same projection plane and spaced apart from each other. In other words, assuming that the photolithography process is performed using each photomask one by one, and each photomask is placed in the same photolithography position, any two second patterns 101 formed on the chip are non-overlapping and spaced apart; while all the first patterns 100 overlap.

[0060] For example, Figure 3 The image shows the first mask mark in the first mask template. Figure 4 The image shows the second mask mark in the second mask template. For the same chip, under the same placement, photolithography processes can be performed using both the first and second masks, respectively, to form... Figure 5 The pattern shown. Wherein, Figure 5 In the illustrated pattern, the pattern formed by the first pattern 100 in the first mask mark and the first pattern 100 in the second mask mark overlaps, and the patterns formed by the second pattern 101 in the first mask mark and the second pattern 101 in the second mask mark are spaced apart and do not overlap. Similarly, Figure 6 The image shows the third mask mark in the third mask template. Figure 7 The image shows the fourth mask mark in the fourth mask template. For the same chip, under the same placement, photolithography processes can be performed using both the third and fourth masks, respectively, to form... Figure 8 The pattern shown. Wherein, in Figure 8 In the illustrated pattern, the pattern formed by the first pattern 100 in the third mask mark and the first pattern 100 in the fourth mask mark overlaps, and the patterns formed by the second pattern 101 in the third mask mark and the second pattern 101 in the fourth mask mark are spaced apart and do not overlap. Based on this, for the same chip, under the same placement position, photolithography processes can be performed using the first mask, the second mask, the third mask, and the fourth mask respectively, to form... Figure 1 The pattern shown. In Figure 1 In the pattern shown, all the first patterns 100 overlap, and all the second patterns 101 do not overlap.

[0061] Therefore, during the photolithography process, the various photomasks can be aligned using the first pattern 100, thereby avoiding the impact of placement errors between the photomasks on the accuracy of overlay error measurement. Simultaneously, the non-overlapping second pattern 101 also ensures accurate measurement of the overlay error between each film layer and the reference film layer.

[0062] To facilitate the identification and measurement of overlay errors, preferably, the second pattern 101 is a 180° rotationally symmetrical graphic, such as a cross or a star shape. Furthermore, the length of the second pattern 101 is greater than or equal to 4.5 micrometers, and the width of the second pattern 101 is greater than or equal to 4.5 micrometers. Preferably, the second pattern 101 is star-shaped, which is beneficial for stress dispersion of the photomask, resisting deformation interference during the process, and enhancing the durability of the photomask.

[0063] like Figure 9 As shown, since the second pattern 101 is used to measure overlay error, the first pattern 100 and all the second patterns 101; that is, the mask marks, correspond to the distribution within the virtual graphic area (dummy) M in the functional area D of the chip. In other words, based on the distribution of the mask marks, when using a mask template with the mask marks, the mask marks on the mask template will be transferred into the virtual graphic area M of the chip. The virtual graphic area M refers to the area within the functional area D used to add auxiliary graphics without electrical function and compatible with the process. Its core function is to balance pattern density and optimize manufacturing process consistency, ensuring yield and performance, without affecting the chip's logic and electrical functions. Therefore, setting the mask mark corresponding to the virtual graphic area M has several advantages. First, it eliminates the spatial limitations of the border area, and the number and position of the second pattern 101 in the virtual graphic area M are not limited, which is beneficial for stacking more mask templates, has a wide range of applications, and meets the needs of high-order overlay development. Second, compared with the border area, the mask mark is closer to the device structure, which can reduce the distance error with the device structure and improve the detection accuracy.

[0064] It should be added that, such as Figure 9 As shown, each film layer of the chip has multiple virtual pattern regions M, and each virtual pattern region M can correspond to one or more mask marks. However, in order to monitor the placement error of the mask template and measure the overlay error, the mask marks distributed in the virtual pattern regions M of each film layer of the chip are in the same position to ensure that the mask marks of different film layers correspond to each other.

[0065] Preferred, such as Figure 1 and Figures 3-8The dashed box shown indicates that the mask mark is square, and the first pattern 100 is located at the exact center of the mask mark. The purpose of this is to allow for the stacking of more mask templates to meet the needs of advanced processes.

[0066] Furthermore, in this embodiment, the photomask also includes a modified version, a backup version, and a replacement version corresponding to each film layer of the chip. Each modified version, backup version, and replacement version uses the photomask used for the first time as the gold photomask and the first pattern 100 in the gold photomask as the alignment reference. This ensures that the positions of each modified version, backup version, and replacement version are aligned, avoiding placement errors and thus eliminating fluctuations at the wafer end caused by placement errors. This maintains the stability of the process system and greatly saves unnecessary consumption of manpower and resources caused by process fluctuations.

[0067] As described above, the first pattern 100 in the mask markings provided in this embodiment can be used to achieve positional alignment between different mask templates, thereby avoiding placement errors from affecting the accuracy of overlay error detection and preventing systematic overlay errors. Furthermore, the first pattern 100 can also be used in conjunction with other marking patterns to detect wafer-level errors, avoiding wafer placement errors. Additionally, the second pattern 101 in the mask markings can accurately detect overlay errors between each film layer and the reference film layer based on the alignment of the first pattern 100, avoiding measurement errors caused by different focal planes in different layers, which is beneficial for improving the photolithography process effect and ensuring better device performance and yield.

[0068] Based on the same concept, this embodiment also provides a method for generating mask marks, used to generate the aforementioned mask marks. Please refer to... Figures 1 to 10 The method for generating the mask markers includes:

[0069] Step 1 S10: Based on the mask rule check and chip design rules, determine the allowable size of the mask mark within the functional area of ​​all film layers in the chip.

[0070] Mask Rule Check (MRC) is used to verify the mask layout based on process constraints, identify manufacturing defects such as dimensions and spacing, ensure accurate pattern transfer, avoid mask failure risks, and thus guarantee chip yield. Chip design rules, on the other hand, are used to verify parameters such as layout pattern dimensions and spacing based on process node constraints, avoid manufacturing defects, and ensure the design is suitable for mass production. Therefore, based on the mask rule check and chip design rules, the acceptable size of the mask marks within the functional areas of all the film layers can be determined, and the size of the mask marks can be determined accordingly.

[0071] Step 2 S11: Add the size and shape of the mask mark to the generation rules of the virtual graphics area within the functional area.

[0072] Since this embodiment limits the generation of the mask mark to the virtual graphic area within the functional area, the virtual graphic area generation rules should be followed, and the already determined size and shape of the mask mark should be added to it to facilitate subsequent automatic generation.

[0073] Step 3 S12: At least according to the generation rules of the virtual graphic region, automatically generate the mask mark corresponding to the virtual graphic region of each film layer, so that the first pattern 100 of all the mask marks at the same position in all the film layers can overlap and be aligned, and all the second patterns 101 are intersected and spaced apart from each other.

[0074] Based on the design requirements of the first pattern 100 and the second pattern 101 in the mask markings, the size, shape, and positional distribution of the first pattern 100 at the same location in different film layers are the same, while the second pattern 101, apart from having the same size and shape, has a different positional distribution. Therefore, in step three S12, it is also necessary to determine the positional distribution of the second pattern 101 according to the stacking order of each film layer and the usable area within the virtual graphic region, in order to ensure the non-overlapping design of each of the second patterns 101.

[0075] Based on the same concept, please refer to Figures 1 to 9 and Figure 11 This embodiment also provides a method for monitoring mask placement error, including:

[0076] Step 1 S20: Provide at least two mask templates, and the at least two mask templates have the mask markings.

[0077] Step 2 S21: Select a gold mask from the at least two mask templates.

[0078] The gold mask is used as a reference substrate for marking, and the mask corresponding to the key layer in the chip can be selected as the gold mask.

[0079] Step 3 S22: Using the first pattern 100 in the gold photomask as a reference pattern, obtain the deviation between the first pattern 100 in other photomasks and the reference pattern, as the placement error of the photomask.

[0080] It should be noted that step three, S22, can be performed either during the mask production stage or during the photolithography process after mask fabrication. For example, during mask production, using the first pattern 100 in the gold mask as a reference pattern, the deviation between the first patterns 100 of different masks can be measured using optical inspection equipment. This allows for monitoring of mask fabrication errors and avoids impacting wafer fabrication due to insufficient monitoring of mask manufacturing errors. Furthermore, during the photolithography process, by acquiring the deviation between the first pattern 100 in the current mask and the reference pattern, the placement error of the current mask can be monitored. Position adjustments can control the placement error within preset specifications, improving mask alignment accuracy and preventing interference with the measurement of overlay errors.

[0081] Based on the same concept, this embodiment also provides a mask assembly. Please refer to [link / reference]. Figures 1 to 9 The mask group is applied to the same chip and includes multiple mask templates, the multiple mask templates having the mask markings.

[0082] Based on the same concept, this embodiment also provides a photolithography method. Please refer to [link / reference]. Figures 1 to 9 and Figure 12 The engraving method includes:

[0083] Step 1 S30: Provide the mask set.

[0084] The mask group includes multiple mask templates, each corresponding to the same chip. Each mask template has a mask mark; that is, at least one mask mark is formed in each mask template. Furthermore, in the same placement position, all the first patterns 100 in the multiple masks can overlap and be aligned, and all the second patterns 101 in the multiple masks are interleaved and spaced apart from each other.

[0085] Step 2 S31: Select a gold mask from the mask group.

[0086] It should be noted that the gold mask corresponds to the reference film layer in the chip, and this film layer is the key layer most sensitive to overlay accuracy, serving as the comparison benchmark for other film layers.

[0087] Step 3 S32: Use the gold mask to form a first pattern 100 and a plurality of second patterns 101 on a chip as reference marks.

[0088] For example, with Figure 3The mask marking shown is located on a gold mask, and a photolithography process is performed on it to form a first pattern 100 and multiple second patterns 101 on the reference film layer of the chip. The first pattern 100 is the alignment pattern for each mask in subsequent photolithography processes; the multiple second patterns 101 are the overlay error measurement references for each mask layer relative to the reference film layer in subsequent photolithography processes.

[0089] Step 4 S33: Before performing the photolithography process on any of the remaining photomasks in the photomask group, the first pattern 100 in the selected photomask is overlapped and aligned with the first pattern 100 in the reference mark using an optical inspection device, and then the photolithography process is performed.

[0090] That is, in order to avoid the measurement accuracy of overlay error being affected by the placement error of the photomask, before each photolithography process, an optical inspection device is required to align the first pattern 100 in the photomask to be used with the first pattern 100 on the reference film layer, thereby avoiding the influence of the placement error of the photomask on the photolithography effect and improving the photolithography accuracy.

[0091] Based on the same concept, this embodiment also provides a method for measuring overlay error. Please refer to [link / reference]. Figures 1 to 9 and Figure 13 The method for measuring the overlay error includes:

[0092] Step 1 S40: Perform a photolithography process on a chip using the aforementioned photolithography method.

[0093] Based on the above photolithography method, the reference mark is formed at least on the reference film layer of the chip, and the mask mark is formed by photolithography on the current film layer.

[0094] Step 2 S41: Measure and obtain a first error between the first pattern 100 on the current film of the chip and the first pattern 100 in the reference mark; and measure and obtain a second error between the plurality of second patterns 101 on the current film of the chip and the plurality of second patterns 101 in the reference mark.

[0095] It should be noted that although the photolithography method described above sets the first pattern 100 in the photomask to overlap and align with the first pattern 100 in the reference mark, a certain deviation will still exist between them in actual processing. Therefore, a measurement device is needed to obtain the first error between the first pattern 100 on the current film and the first pattern 100 in the reference mark; that is, the placement error between the photomasks. Furthermore, the second pattern 101 is used to obtain the overlay error; therefore, the obtained second error characterizes the overlay error between the current film and the reference film layer as measured by the measurement device.

[0096] Step 3 S42: Obtain the overlay error between the current layer film and the film layer where the reference mark is located based on the first error and the second error.

[0097] Due to the existence of the first error, the accuracy of the second error measured in step S42 is limited. Therefore, it is necessary to correct the second error based on the first error to effectively eliminate the interference of placement errors between photomasks, thereby obtaining a more accurate overlay error, which is beneficial to improving the device fabrication accuracy and yield.

[0098] In summary, this embodiment provides a mask marking and generation method, a photolithography method, and a method for measuring overlay error. The first pattern 100 in the mask marking can be used to achieve positional alignment between different masks, avoiding placement errors from affecting the accuracy of overlay error detection and preventing systematic overlay errors. Furthermore, by obtaining the deviation between the first patterns 100 at the same position in different masks, precise monitoring of mask placement errors can be achieved. And, based on the alignment of the first pattern 100, the second pattern 101 can be used to accurately detect the overlay error between each film layer and the reference film layer, which is beneficial for optimizing the photolithography process and improving device performance and yield.

[0099] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.

Claims

1. A mask mark, characterized in that, The mask markings are applied to multiple mask templates on the same chip, and the mask markings include registration markings and overlay markings; wherein, The registration mark includes a first pattern; the overlay mark includes a plurality of second patterns; and the plurality of second patterns are spaced apart and scattered around the first pattern; and, In the same placement position, all the first patterns in the plurality of photomasks can overlap and be aligned, and all the second patterns in the plurality of photomasks are distributed in a cross pattern and spaced apart from each other; Each of the mask templates has at least one mask mark formed therein, and the distribution of the mask marks corresponds to the virtual graphic area of ​​the functional area of ​​the chip.

2. The mask marking according to claim 1, characterized in that, In the plurality of mask templates, the size of the first pattern in all the mask marks is the same, and the size of the second pattern in all the mask marks is the same; wherein the size of the second pattern is smaller than the size of the first pattern.

3. The mask marking according to claim 1, characterized in that, The photomask also includes modified, backup, and replacement versions of the photomask corresponding to each film layer of the chip.

4. The mask marking according to claim 1, characterized in that, The first pattern is cross-shaped, and the length of the first pattern is greater than or equal to 3.8 micrometers, and the width of the first pattern is greater than or equal to 0.3 micrometers and less than or equal to 15 micrometers.

5. The mask marking according to claim 1, characterized in that, The second pattern has a cross-shaped or star-shaped morphology, and the length of the second pattern is greater than or equal to 4.5 micrometers, and the width of the second pattern is greater than or equal to 4.5 micrometers.

6. The mask marking according to claim 1, characterized in that, The mask mark is square, and the first pattern is located at the center of the mask mark.

7. A method for generating mask markers, characterized in that, A method for generating a mask mark as described in any one of claims 1 to 6, wherein the method for generating the mask mark comprises: Based on mask rule checks and chip design rules, determine the allowable size of the mask marks within the functional areas of all film layers in the chip; Add the size and shape of the mask mark to the generation rules of the virtual graphics area within the functional area; At least according to the generation rules of the virtual graphic region, the mask mark corresponding to the virtual graphic region of each of the film layers is automatically generated, so that the first patterns of all the mask marks at the same position in all the film layers can overlap and be aligned, and all the second patterns are intersected and spaced apart from each other.

8. A method for monitoring mask placement error, characterized in that, include: Provide at least two mask templates, wherein the at least two mask templates have mask markings as described in any one of claims 1 to 6; Select a gold mask from the at least two mask templates; Using the first pattern in the gold photomask as a reference pattern, the deviation between the first pattern in the other photomasks and the reference pattern is obtained as the placement error of the photomask.

9. A mask assembly, characterized in that, The mask group is applied to the same chip and includes multiple mask templates, the multiple mask templates having mask markings as described in any one of claims 1 to 6.

10. A photolithography method, characterized in that, include: Provide the mask assembly as described in claim 9; Select a gold mask from the mask group; The gold mask is used to form a first pattern and a plurality of second patterns on a chip as reference marks; Before performing the photolithography process on any of the remaining photomasks in the photomask group, the first pattern in the selected photomask is aligned with the first pattern in the reference mark using an optical inspection device before the photolithography process is performed.

11. A method for measuring overlay error, characterized in that, include: A photolithography process is performed on a chip using the photolithography method as described in claim 10; The first error between the first pattern on the current film of the chip and the first pattern in the reference mark is measured; as well as, The second error between the plurality of second patterns on the current layer film of the chip and the plurality of second patterns in the reference mark is measured; The overlay error between the current layer film and the film layer containing the reference mark is obtained based on the first error and the second error.

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