Computing system for adjusting supply voltage

Abstract

The invention relates to a computing system for adjusting a supply voltage. A computing system includes a power source, a main voltage regulator, a processor, and a memory module. The power supply is configured to generate a first input voltage and a second input voltage. The main voltage regulator is configured to generate a processor supply voltage from a first input voltage. The memory module includes a power management integrated circuit that generates a memory power supply voltage from a second input voltage. The power management integrated circuit is configured to adjust a voltage level of the memory supply voltage based on the processor supply voltage and the memory supply voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0137813, filed with the Korean Intellectual Property Office on October 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments relate to a computing system, and more particularly to a computing system capable of adjusting the voltage level of a power supply voltage. Background Technology

[0004] Electronic devices comprise many electronic components. Among these components, a computing system may include numerous semiconductor devices, including semiconductors. These semiconductor devices constituting a computing system can communicate with each other by transmitting and receiving system clock signals and data. The computing system can receive power from a power source and provide operating voltages to the semiconductor devices that constitute the system. A typical computing system may include a motherboard, a processor, and a memory module. The processor and memory module may be mounted on the motherboard. A voltage regulator may be formed within the motherboard. The voltage regulator receives power from the power source and converts the power to generate the power supply voltages provided to the memory module and the processor.

[0005] With advancements in semiconductor technology, the operating voltage of semiconductor devices is continuously decreasing. Memory modules may include power management integrated circuits (ICs) that provide stable operating voltages to multiple memory devices mounted on the memory module. The power management IC can generate the memory power supply voltage supplied from the power source and can provide this voltage to multiple memory devices. Memory devices can use multiple memory power supply voltages. Processors can also use multiple processor power supply voltages. The multiple memory power supply voltages and multiple processor power supply voltages can have independent voltage levels. However, the memory power supply voltage and processor power supply voltage used to drive signals such as data signals in bidirectional communication can have the same voltage level. However, since the memory power supply voltage is generated by the power management IC while the processor power supply voltage is generated by a voltage regulator, a voltage level difference may exist between the memory power supply voltage and the processor power supply voltage. This voltage level difference can degrade the operating performance of the computing system. Summary of the Invention

[0006] In an embodiment, a computing system can include a power supply, a main voltage regulator, a processor, and a memory module. The power supply can be configured to generate a first input voltage and a second input voltage. The main voltage regulator can be configured to generate a processor supply voltage based on the first input voltage. The processor can be configured to receive the processor supply voltage. The memory module can be configured to communicate with the processor. The memory module can include at least one memory device and a power management integrated circuit. The power management integrated circuit can be configured to receive the second input voltage and the processor supply voltage, generate a memory supply voltage based on the second input voltage and memory supply voltage setting information, provide the memory supply voltage to the at least one memory device, and change the memory supply voltage setting information based on a comparison of the memory supply voltage to the processor supply voltage.

[0007] In an embodiment, a computing system can include a power supply, a main voltage regulator, a processor, and a memory module. The power supply can be configured to generate a first input voltage and a second input voltage. The main voltage regulator can be configured to generate a processor supply voltage based on the first input voltage. The processor can be configured to receive the processor supply voltage. The memory module can be configured to communicate with the processor. The memory module can include at least one memory device and a power management integrated circuit. The power management integrated circuit can be configured to generate a memory supply voltage based on the second input voltage and memory supply voltage setting information, provide the memory supply voltage to the at least one memory device, and change the memory supply voltage setting information based on a voltage adjustment signal. The processor can be configured to generate the voltage adjustment signal based on the processor supply voltage and the memory supply voltage.

[0008] In an embodiment, a computing system can include a power supply, a main voltage regulator, a processor, and a memory module. The power supply can be configured to generate a first input voltage and a second input voltage. The main voltage regulator can be configured to generate a processor supply voltage based on the first input voltage. The processor can be configured to receive the processor supply voltage. The memory module can be configured to communicate with the processor. The memory module can include at least one memory device and a power management integrated circuit. The power management integrated circuit can be configured to generate a memory supply voltage based on the second input voltage and memory supply voltage setting information, provide the memory supply voltage to the at least one memory device, and change the memory supply voltage setting information based on a voltage adjustment signal. The processor can be configured to generate the voltage adjustment signal based on the processor supply voltage and the memory supply voltage. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram illustrating a configuration of a computing system according to an embodiment.

[0010] Figure 2 This is a diagram illustrating the configuration of a computing system according to an embodiment.

[0011] Figure 3 This is a diagram illustrating the configuration of a computing system according to an embodiment.

[0012] Figure 4 It is shown Figure 3 A diagram showing the configuration of an embodiment of the power management integrated circuit.

[0013] Figure 5 This is a diagram illustrating the configuration of a computing system according to an embodiment.

[0014] Figure 6 This is a diagram illustrating the configuration of a computing system according to an embodiment.

[0015] Figure 7 This is a diagram illustrating the configuration of a computing system according to an embodiment.

[0016] Figure 8 This is a diagram illustrating the configuration of a computing system according to an embodiment. Detailed Implementation

[0017] Figure 1 This is a diagram illustrating the configuration of a computing system 100 according to an embodiment. (Refer to...) Figure 1 The computing system 100 may include a power supply 110, a main voltage regulator 120, a processor 130, and a first memory module 140. Components of the computing system 100 may be coupled to or mounted on a motherboard or motherboard. Some components of the computing system 100 may be embedded in the motherboard or motherboard. Components of the computing system 100 may be coupled via signal paths and / or interface circuitry formed in the motherboard or motherboard. The power supply 110 may be the power source for the computing system 100. The power supply 110 may receive power from an external source and may generate multiple supply voltages by converting the power into voltages and currents suitable for use in the components of the computing system 100. For example, the power supply 110 may generate an input voltage BV and may provide the input voltage BV to the main voltage regulator 120. The computing system 100 may be used as at least one of a desktop computer, a laptop computer, a server, a workstation, a mobile device, and a graphics device. The input voltage BV may have multiple voltage levels depending on the application of the computing system 100. For example, the voltage level of the input voltage BV can be any of 3.3V, 5V, and 12V; however, this disclosure is not limited thereto.

[0018] The main voltage regulator 120 can receive an input voltage BV from the power supply 110. The main voltage regulator 120 can use the input voltage BV as its operating power supply and can generate multiple system power supply voltages. For example, the main voltage regulator 120 can generate a system power supply voltage VDD_S by adjusting the input voltage BV. The system power supply voltage VDD_S can be a voltage shared by the processor 130 and the first memory module 140. For example, the system power supply voltage VDD_S can be the voltage used by the processor 130 and the first memory module 140 for data communication. The main voltage regulator 120 can provide the system power supply voltage VDD_S to the processor 130 and the first memory module 140. The main voltage regulator 120 can be coupled to the processor 130 and the first memory module 140 via the system power line 101 and can provide the system power supply voltage VDD_S to the processor 130 and the first memory module 140 via the system power line 101. In one embodiment, by adjusting the input voltage BV, the main voltage regulator 120 can generate a system supply voltage used only in the processor 130 and a system supply voltage used only in the first memory module 140. For example, each of the plurality of system supply voltages can have at least one voltage level selected from the voltage levels of 0.7V, 0.85V, 1.0V, 1.1V, 1.125V, 1.25V, 1.8V, 1.83V, and 3.3V; however, this disclosure is not limited thereto. For example, the system power supply voltage VDD_S can have a voltage level of 1.0V or 1.1V.

[0019] Processor 130 can communicate with first memory module 140. Processor 130 can receive system power voltage VDD_S from main voltage regulator 120 via system power line 101 and can operate using system power voltage VDD_S. Processor 130 can be a host device capable of accessing first memory module 140 to perform various computational operations. For example, processor 130 may include at least one or a combination of two or more of a central processing unit (CPU), graphics processing unit (GPU), multimedia processor (MMP), digital signal processor, application processor (AP), data processing unit (DPU), neural processing unit (NPU), system-on-a-chip (SoC), and memory controller. Processor 130 can be coupled to first memory module 140 via data bus 103, can transmit data DQ to first memory module 140 via data bus 103, and can receive data DQ transmitted by first memory module 140 via data bus 103. Processor 130 can transmit data DQ to first memory module 140 by driving data bus 103 to system power voltage VDD_S. Although not shown, processor 130 may be coupled to first memory module 140 via clock bus, command bus, address bus or command address bus to access first memory module 140.

[0020] The first memory module 140 can communicate with the processor 130. The first memory module 140 receives the system power voltage VDD_S from the main voltage regulator 120 via the system power line 101 and can operate using the system power voltage VDD_S. The processor 130 can control the first memory module 140 to perform data input and data output operations. A data input operation can be a write operation where data DQ is transferred from the processor 130 to the first memory module 140 and stored in the first memory module 140. A data output operation can be a read operation where data already stored in the first memory module 140 is output as data DQ to the processor 130. The first memory module 140 can be coupled to the processor 130 via the data bus 103, and can transmit data DQ to and receive data DQ transmitted by the processor 130 via the data bus 103. The first memory module 140 can transmit data DQ to the processor 130 by driving the data bus 103 to the system power voltage VDD_S. Although not shown, the first memory module 140 may be coupled to the processor 130 via a clock bus, command bus, address bus, or command-address bus. The computing system 100 may include one or more memory modules. In one embodiment, the computing system 100 may also include a second memory module 150. The second memory module 150 may have substantially the same configuration as the first memory module 140, and may be coupled to components of the computing system 100 in substantially the same manner as the first memory module 140. In one embodiment, the computing system 100 may include three or more memory modules.

[0021] The first memory module 140 may include at least one memory. For example, the first memory module 140 may include four memory devices. The memory devices may be packaged memory devices and may be configured by mounting them on a memory module substrate 141. The memory devices may provide the memory capacity and / or memory density of the first memory module 140. The memory devices included in the first memory module 140 may include volatile memory and non-volatile memory. At least one of the memory devices may be a different type of memory, while the remaining memory devices may be the same type of memory. The memory devices may be coupled to the main voltage regulator 120 via the system power line 101 and may receive the system power supply voltage VDD_S from the main voltage regulator 120. The system power line 101 may be coupled to the memory power line 142. The system power supply voltage VDD_S may be transmitted from the main voltage regulator 120 to the first memory module 140 via the system power line 101 and may be distributed to the memory devices via the memory power line 142 within the first memory module 140. Data DQ transferred from processor 130 to first memory module 140 via data bus 103 can be input to a memory device. The memory device can store data DQ. Data output from the memory device can be transferred to processor 130 as data DQ via data bus 103. The memory device can use the system power supply voltage VDD_S to drive data bus 103 to transfer data DQ.

[0022] The first memory module 140 may further include a serial presence detection (SPD) 145. The SPD 145 may be a register or a small memory device that stores information related to the memory module. The SPD 145 may store information such as the memory capacity, clock speed, operating voltage and driver strength of the first memory module 140, manufacturing information of the memory module and the manufacturing information of the memory device, and may provide the stored information to the processor 130.

[0023] The system power supply voltage VDD_S can be the voltage used to drive the data DQ transmitted via the data bus 103. Preferably, to ensure the performance of the computing system 100, the voltage level of the data bus 103 driven by the first memory module 140 is the same as or at least within tolerance of the voltage level of the data bus 103 driven by the processor 130. However, due to the physical distance difference from the main voltage regulator 120 to the processor 130 and the first memory module 140, a difference inevitably occurs between the actual voltage level of the system power supply voltage VDD_S received by the processor 130 and the actual voltage level of the system power supply voltage VDD_S received by the first memory module 140. When the difference between the actual voltage levels of the system power supply voltage VDD_S used by the processor 130 and the first memory module 140 exceeds the tolerance range, a communication error will occur because the swing range of the data DQ transmitted via the data bus 103 changes.

[0024] Figure 2 This is a diagram illustrating the configuration of a computing system 200 according to an embodiment. (Refer to...) Figure 2 The computing system 200 may include a power supply 210, a main voltage regulator 220, a processor 230, and a first memory module 240. In the following text, the components mentioned above may be omitted. Figure 1 The descriptions of the components of the computing system 100 shown are identical or redundant to the descriptions of the components of the computing system 200. Power supply 210 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. Power supply 210 can provide the first input voltage BV1 to the main voltage regulator 220. Power supply 210 can provide the second input voltage BV2 to the first memory module 240. The second input voltage BV2 can have the same voltage level as the first input voltage BV1, or it can have a different voltage level than the first input voltage BV1. The main voltage regulator 220 can receive the first input voltage BV1 and generate a processor power supply voltage VDD_P by adjusting the first input voltage BV1. The processor power supply voltage VDD_P can be a voltage that can be dedicated to the processor 230. The processor power supply voltage VDD_P can have the same voltage level as the first input voltage BV1. Figure 1 The system power supply voltage VDD_S shown has the same characteristics. The main voltage regulator 220 can be coupled to the processor 230 via the processor power line 201, and can provide the processor power supply voltage VDD_P to the processor 230 via the processor power line 201.

[0025] Processor 230 can communicate with the first memory module 240. Processor 230 receives processor power supply voltage VDD_P from main voltage regulator 220 via processor power line 201 and can operate using processor power supply voltage VDD_P. Processor 230 is coupled to the first memory module 240 via data bus 203, and can transmit data DQ to and receive data DQ transmitted by the first memory module 240 via data bus 203. Processor 230 can transmit data DQ to the first memory module 240 by driving data bus 203 using processor power supply voltage VDD_P.

[0026] The first memory module 240 can communicate with the processor 230. The first memory module 240 can receive a second input voltage BV2 and generate a memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 240 can operate using the memory power supply voltage VDD_M. The target voltage level of the memory power supply voltage VDD_M can be the same as the target voltage level of the processor power supply voltage VDD_P. The first memory module 240 can be coupled to the processor 230 via a data bus 203, and can transmit data DQ to and receive data DQ transmitted by the processor 230 via the data bus 203. The first memory module 240 can transmit data DQ to the processor 230 by driving the data bus 203 to the memory power supply voltage VDD_M. The computing system 200 may include one or more memory modules. In one embodiment, the computing system 200 may further include a second memory module 250. The second memory module 250 may have a substantially the same configuration as the first memory module 240 and may be coupled to components of the computing system 200 in substantially the same manner as the first memory module 240. In one embodiment, the computing system 200 may include three or more memory modules.

[0027] The first memory module 240 may include a power management integrated circuit (PMIC) 243 and at least one memory device. The PMIC 243 may receive a second input voltage BV2 from a power supply 210. The PMIC 243 may generate a memory power supply voltage VDD_M from the second input voltage BV2. The PMIC 243 may store memory power supply voltage setting information related to a target voltage level of the memory power supply voltage VDD_M. The memory power supply voltage setting information may be stored in a register of the PMIC 243. The PMIC 243 may generate the memory power supply voltage VDD_M from the second input voltage BV2 based on the memory power supply voltage setting information. The PMIC 243 may provide and / or distribute the memory power supply voltage VDD_M to at least one memory device included in the first memory module 240. For example, the PMIC 243 may provide the memory power supply voltage VDD_M to at least one memory device via a memory power line 242.

[0028] For example, the first memory module 240 may include four memory devices. The memory devices can be coupled to the PMIC 243 via memory power line 242 and can receive the memory power supply voltage VDD_M from the PMIC 243 via the memory power supply line 242. The memory devices can operate using the memory power supply voltage VDD_M. Data DQ transferred from the processor 230 to the first memory module 240 via the data bus 203 can be input to the memory devices. The memory devices can store data DQ. Data output from the memory devices can be transferred to the processor 230 as data DQ via the data bus 203. The memory devices can use the memory power supply voltage VDD_M to drive the data bus 203 to transfer data DQ. The first memory module 240 may also include a serial presence detection (SPD) 245.

[0029] The first memory module 240 may include a PMIC 243 and can generate a memory power supply voltage VDD_M independently of the processor power supply voltage VDD_P. The first memory module 240 can reduce... Figure 2 The voltage level difference shown is the difference between the power supply voltages that can actually be received by the processor 230 and the first memory module 240 due to the difference in physical distance from the main voltage regulator 220 to the processor 230 and the first memory module 240. However, since the PMIC 243 of the first memory module 240 is manufactured using different processes than the main voltage regulator 220, and the processor power supply voltage VDD_P and the memory power supply voltage VDD_M are not correlated, the processor power supply voltage VDD_P and the memory power supply voltage VDD_M may have an error greater than a threshold range due to process variations.

[0030] Figure 3This is a diagram illustrating the configuration of a computing system 300 according to an embodiment. (Refer to...) Figure 3 The computing system 300 may include a power supply 310, a main voltage regulator 320, a processor 330, and a first memory module 340. The power supply 310 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. The power supply 310 can provide the first input voltage BV1 to the main voltage regulator 320 and the second input voltage BV2 to the first memory module 340. The main voltage regulator 320 can receive the first input voltage BV1 and generate a processor power supply voltage VDD_P from it. The main voltage regulator 320 can be coupled to the processor 330 via a processor power line 301 and can provide the processor power supply voltage VDD_P to the processor 330 via the processor power line 301.

[0031] Processor 330 can communicate with first memory module 340. Processor 330 receives processor power supply voltage VDD_P from main voltage regulator 320 via processor power line 301 and can operate using processor power supply voltage VDD_P. Processor 330 is coupled to first memory module 340 via data bus 303, and can transmit data DQ to and receive data DQ transmitted by first memory module 340 via data bus 303. Processor 330 can transmit data DQ to first memory module 340 by driving data bus 303 using processor power supply voltage VDD_P.

[0032] The first memory module 340 can communicate with the processor 330. The first memory module 340 can receive a second input voltage BV2 and generate a memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 340 can operate using the memory power supply voltage VDD_M. The target voltage level of the memory power supply voltage VDD_M can be the same as the target voltage level of the processor power supply voltage VDD_P. The first memory module 340 can be coupled to the processor 330 via a data bus 303, and can transmit data DQ to and receive data DQ from the processor 330 via the data bus 303. The first memory module 340 can transmit data DQ to the processor 330 by driving the data bus 303 to the memory power supply voltage VDD_M. The computing system 300 may include one or more memory modules. In one embodiment, the computing system 300 may further include a second memory module 350. The second memory module 350 may have a substantially the same configuration as the first memory module 340 and may be coupled to components of the computing system 300 in substantially the same manner as the first memory module 340. In one embodiment, the computing system 300 may include three or more memory modules.

[0033] To adjust the error between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M, the first memory module 340 can be additionally coupled to the processor power line 301 and can receive the processor power supply voltage VDD_P through the processor power line 301. The first memory module 340 can compare the voltage level of the processor power supply voltage VDD_P with the voltage level of the memory power supply voltage VDD_M and can reduce the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M. For example, when the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M exceeds a threshold range, the first memory module 340 can adjust the voltage level of the memory power supply voltage VDD_M so that the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P is within the threshold range. For example, the threshold range can be approximately half of the tolerance range. However, this disclosure is not limited to this, and the tolerance range and the threshold range can be varied. For example, the tolerance range can correspond to approximately 10% of the target voltage level, while the threshold range can correspond to approximately 5% of the target voltage level. When the target voltage level of each of the processor power supply voltage VDD_P and the memory power supply voltage VDD_M is 1.1V, the tolerance range of the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M can be approximately 0.11V. In this case, the threshold range can be approximately 0.055V.

[0034] The first memory module 340 may include a power management integrated circuit (PMIC) 343 and at least one memory. The PMIC 343 may receive a second input voltage BV2 from a power supply 310. The PMIC 343 may generate a memory power supply voltage VDD_M from the second input voltage BV2. The PMIC 343 may store memory power supply voltage setting information regarding a target voltage level for the memory power supply voltage VDD_M. The memory power supply voltage setting information may be stored in a register of the PMIC 343. The PMIC 343 may generate the memory power supply voltage VDD_M from the second input voltage BV2 based on the memory power supply voltage setting information. The PMIC 343 may provide and / or distribute the memory power supply voltage VDD_M to the memories included in the first memory module 340. The PMIC 343 may provide the memory power supply voltage VDD_M to at least one memory via a memory power line 342. The PMIC 343 may also be coupled to a processor power line 301 and may receive a processor power supply voltage VDD_P via the processor power line 301. PMIC 343 can compare the voltage level of the processor power supply voltage VDD_P with the voltage level of the memory power supply voltage VDD_M. When the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M is within a threshold range, PMIC 343 can maintain the memory power supply voltage setting information and can continue to generate the memory power supply voltage VDD_M based on the memory power supply voltage setting information. When the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M exceeds the threshold range, PMIC 343 can modify the memory power supply voltage setting information. For example, when the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M exceeds the threshold range and the processor power supply voltage VDD_P has a higher voltage level than the memory power supply voltage VDD_M, PMIC 343 can modify the memory power supply voltage setting information to increase the voltage level of the memory power supply voltage VDD_M. Conversely, when the processor power supply voltage VDD_P has a lower voltage level than the memory power supply voltage VDD_M, PMIC 343 can modify the memory power supply voltage setting information to lower the voltage level of the memory power supply voltage VDD_M. PMIC 343 can compare the voltage level of the memory power supply voltage VDD_M with the voltage level of the processor power supply voltage VDD_P generated by an independent voltage generator, and can maintain the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P within a threshold range. Therefore, the performance of the computing system 300 can be improved by reducing the variation in the swing range of the data DQ transmitted through the data bus 303 and by improving the communication reliability between the first memory module 340 and the processor 330.

[0035] For example, the first memory module 340 may include four memory devices. The memory devices can be coupled to the PMIC 343 via memory power lines 342 and can receive a memory power supply voltage VDD_M from the PMIC 343 via memory power lines 342. The memory devices can operate using the memory power supply voltage VDD_M. Data DQ transferred from the processor 330 to the first memory module 340 via the data bus 303 can be input to the memory devices. The memory devices can store data DQ. Data output from the memory devices can be transferred to the processor 330 as data DQ via the data bus 303. The memory devices can use the memory power supply voltage VDD_M to drive the data bus 303 to transfer data DQ. The first memory module 340 may also include a serial presence detection (SPD) 345.

[0036] The computing system 300 may further include a system controller 360. The system controller 360 may be a component mounted on or embedded in a motherboard or motherboard. Generally, the system controller 360 may perform functions such as identifying the physical number of memory modules mounted on or coupled to the motherboard or motherboard and setting system information. The system controller 360 may be coupled to and can communicate with the processor 330 and the first memory module 340. The system controller 360 may be coupled to the processor 330 and the first memory module 340 using standard protocols. For example, the system controller 360 may be coupled to the processor 330 and the first memory module 340 via the Serial Peripheral Interface (SPI) protocol, the Inter-Integrated Circuit (I2C) protocol, or a modified Inter-Integrated Circuit (I3C) protocol. In one embodiment, the system controller 360 may communicate with the processor 330 synchronously with the rising edge of a clock signal and with the first memory module 340 synchronously with the falling edge of a clock signal. System controller 360 can be coupled to processor 330 via first signal transmission line 305 and to first memory module 340 via second signal transmission line 307. System controller 360 can be coupled to SPD 345 of first memory module 340 via second signal transmission line 307. PMIC 343 can be coupled to system controller 360 together with SPD 345 via second signal transmission line 307. If PMIC 343 is coupled to system controller 360 together with SPD 345 via second signal transmission line 307, then a separate module pin that enables PMIC 343 to be coupled to system controller 360 among the module pins included in first memory module 340 may not be assigned to PMIC 343. In other words, since PMIC 343 can be coupled to system controller 360 via a module pin already assigned to SPD 345, the number of available module pins may not be reduced. In one embodiment, a separate module pin can be assigned to the PMIC 343, and the PMIC 343 can be coupled to the system controller 360 independently of the SPD345.

[0037] Figure 4 It is shown Figure 3 The diagram shows the configuration of the PMIC 343. (Refer to...) Figure 4The PMIC 343 may include a setting register 410, a reference voltage generator 420, a voltage regulator 430, and monitoring circuitry 440. The setting register 410 may store memory power supply voltage setting information VRI. The memory power supply voltage setting information VRI may be a code signal comprising multiple bits. The setting register 410 may store the code value of the memory power supply voltage setting information VRI. During the manufacturing process of the PMIC 343, the setting register 410 may store the memory power supply voltage setting information VRI. After the first memory module 340 is installed on the computing system 100, the setting register 410 may receive and store the memory power supply voltage setting information VRI from the processor 330 or the system controller 360. The setting register 410 may also receive a voltage adjustment signal MVS. The setting register 410 may modify the memory power supply voltage setting information VRI based on the voltage adjustment signal MVS. For example, the voltage adjustment signal MVS may be a digital signal comprising multiple bits. The setting register 410 may change the code value of the memory power supply voltage setting information VRI based on the logical value of the voltage adjustment signal MVS. For example, when a voltage adjustment signal MVS is received to increase the voltage level of the memory power supply voltage VDD_M, the setting register 410 can increase the code value of the memory power supply voltage setting information VRI. When a voltage adjustment signal MVS is received to decrease the voltage level of the memory power supply voltage VDD_M, the setting register 410 can decrease the code value of the memory power supply voltage setting information VRI.

[0038] Reference voltage generator 420 can receive memory power supply voltage setting information VRI from setting register 410. Reference voltage generator 420 can receive a second input voltage BV2. Reference voltage generator 420 can generate a reference voltage VREF based on the memory power supply voltage setting information VRI and the second input voltage BV2. For example, reference voltage generator 420 can divide the second input voltage BV2 into multiple voltage dividers, select one of the multiple voltage dividers based on the memory power supply voltage setting information VRI, and output the reference voltage VREF. Reference voltage generator 420 can be any voltage generator capable of generating voltage signals with multiple voltage levels based on digital code signals.

[0039] Voltage regulator 430 can receive a reference voltage VREF from reference voltage generator 420 and can operate by receiving a second input voltage BV2. Voltage regulator 430 can generate a memory power supply voltage VDD_M based on the second input voltage BV2 and the reference voltage VREF. Voltage regulator 430 can compare the voltage level of the reference voltage VREF with the voltage level of the memory power supply voltage VDD_M and can raise or lower the voltage level of the memory power supply voltage VDD_M based on the comparison result. When the voltage level of the memory power supply voltage VDD_M is lower than the voltage level of the reference voltage VREF, voltage regulator 430 can raise the voltage level of the memory power supply voltage VDD_M by driving the memory power supply voltage VDD_M to the second input voltage BV2. When the voltage level of the memory power supply voltage VDD_M is higher than the voltage level of the reference voltage VREF, voltage regulator 430 can lower the voltage level of the memory power supply voltage VDD_M, for example, by discharging a node from which it outputs the memory power supply voltage, without driving the memory power supply voltage VDD_M to the second input voltage BV2. The voltage regulator 430 can maintain the memory power supply voltage VDD_M at approximately the same level as the reference voltage VREF. The memory power supply voltage VDD_M generated by the voltage regulator 430 can be adjusted as follows: Figure 3 The memory power line 342 shown provides and / or supplies power to the memory.

[0040] The monitoring circuit 440 can receive the memory power supply voltage VDD_M from the voltage regulator 430 and the processor power supply voltage VDD_P from the main voltage regulator 320 via the processor power line 301. The monitoring circuit 440 can monitor the voltage levels of the memory power supply voltage VDD_M and the processor power supply voltage VDD_P. The monitoring circuit 440 can generate a voltage adjustment signal MVS by comparing the voltage levels of the memory power supply voltage VDD_M and the processor power supply voltage VDD_P. The monitoring circuit 440 can include information about a threshold range. For example, the monitoring circuit 440 can store the information about the threshold range as a digital code. The code value of the digital code including the information about the threshold range can be a threshold value. Furthermore, the monitoring circuit 440 can generate a first voltage level signal based on the memory power supply voltage VDD_M and a second voltage level signal based on the processor power supply voltage VDD_P. Both the first and second voltage level signals can be digital code signals. The first voltage level signal can have a code value that changes based on the voltage level of the memory power supply voltage VDD_M. The second voltage level signal may have a code value that changes based on the voltage level of the processor power supply voltage VDD_P. The monitoring circuit 440 may include an analog-to-digital converter (ADC) that converts the analog voltage into a digital code signal. The monitoring circuit 440 can calculate the first voltage level signal and the second voltage level signal, and can determine whether the difference between the code value of the first voltage level signal and the code value of the second voltage level signal is greater than a threshold. When the difference between the code value of the first voltage level signal and the code value of the second voltage level signal is less than the threshold, the monitoring circuit 440 can determine that the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P is within the threshold range, and may not generate a voltage adjustment signal MVS. When the difference between the code value of the first voltage level signal and the code value of the second voltage level signal is greater than the threshold, the monitoring circuit 440 can determine that the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P exceeds the threshold range, and may generate a voltage adjustment signal MVS. In this case, when the code value of the second voltage level signal is greater than the code value of the first voltage level signal, the monitoring circuit 440 can generate a voltage adjustment signal MVS that can increase the voltage level of the memory power supply voltage VDD_M. When the code value of the second voltage level signal is less than the code value of the first voltage level signal, the monitoring circuit 440 can generate a voltage adjustment signal MVS that can decrease the voltage level of the memory power supply voltage VDD_M.

[0041] Figure 5 This is a diagram illustrating the configuration of a computing system 500 according to an embodiment. (Refer to...) Figure 5The computing system 500 may include a power supply 510, a main voltage regulator 520, a processor 530, and a first memory module 540. In the following text, the components may be omitted. Figure 3 The descriptions of the components of the computing system 300 shown are identical or redundant to the descriptions of the components of the computing system 500. Power supply 510 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. Power supply 510 can provide the first input voltage BV1 to main voltage regulator 520 and can provide the second input voltage BV2 to first memory module 540. Main voltage regulator 520 can receive the first input voltage BV1 and can generate a processor power supply voltage VDD_P from the first input voltage BV1. Main voltage regulator 520 can be coupled to processor 530 via processor power line 501 and can provide processor power supply voltage VDD_P to processor 530 via processor power line 501.

[0042] Processor 530 can communicate with first memory module 540. Processor 530 can receive processor power supply voltage VDD_P from main voltage regulator 520 via processor power line 501 and can operate using processor power supply voltage VDD_P. Processor 530 can be coupled to first memory module 540 via data bus 503, and can transmit data DQ to and receive data DQ transmitted by first memory module 540 via data bus 503. Processor 530 can transmit data DQ to first memory module 540 by driving data bus 503 using processor power supply voltage VDD_P.

[0043] The first memory module 540 can communicate with the processor 530. The first memory module 540 can receive a second input voltage BV2 and generate a memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 540 can operate using the memory power supply voltage VDD_M. The target voltage level of the memory power supply voltage VDD_M can be the same as the target voltage level of the processor power supply voltage VDD_P. The first memory module 540 can be coupled to the processor 530 via a data bus 503, and can transmit data DQ to and receive data DQ transmitted by the processor 530 via the data bus 503. The first memory module 540 can transmit data DQ to the processor 530 by driving the data bus 503 to the memory power supply voltage VDD_M. The computing system 500 may include one or more memory modules. In one embodiment, the computing system 500 may further include a second memory module 550. The second memory module 550 may have a substantially the same configuration as the first memory module 540 and may be coupled to components of the computing system 500 in substantially the same manner as the first memory module 540. In one embodiment, the computing system 500 may include three or more memory modules.

[0044] Processor 530 can monitor the voltage level of processor power supply voltage VDD_P and memory power supply voltage VDD_M. Processor 530 can compare the voltage levels of processor power supply voltage VDD_P and memory power supply voltage VDD_M and determine whether the voltage level difference between them is within a threshold range. When the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M is within the threshold range, processor 530 may not perform the function of changing the voltage level of memory power supply voltage VDD_M. When the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M exceeds the threshold range, processor 530 can generate a voltage adjustment signal MVS, causing the voltage level of memory power supply voltage VDD_M to be adjusted. Processor 530 can provide the voltage adjustment signal MVS to the first memory module 540. The first memory module 540 can change the target voltage level of memory power supply voltage VDD_M based on the voltage adjustment signal MVS.

[0045] The first memory module 540 can generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. The first memory module 540 can generate a first voltage level signal VDDMC that includes information about the voltage level of the memory power supply voltage VDD_M. The processor 530 can generate the first voltage level signal VDDMC from the first memory module 540. The processor 530 can generate a second voltage level signal VDDPC based on the processor power supply voltage VDD_P. The second voltage level signal VDDPC can include information about the voltage level of the processor power supply voltage VDD_P. The processor 530 can include an ADC 531 capable of generating the second voltage level signal VDDPC from the processor power supply voltage VDD_P. The processor 530 can compare the first voltage level signal VDDMC with the second voltage level signal VDDPC, and can generate a voltage adjustment signal MVS based on the comparison result of the first voltage level signal VDDMC and the second voltage level signal VDDPC. The processor 530 may also include a monitoring circuit 532 that generates the voltage adjustment signal MVS by comparing the first voltage level signal VDDMC and the second voltage level signal VDDPC. The monitoring circuit 532 can be used with Figure 4 The monitoring circuit 440 shown has some of the same function.

[0046] The computing system 500 may further include a system controller 560. The system controller 560 may be coupled to a first memory module 540 and a processor 530. The first memory module 540 may transmit a first voltage level signal VDDMC to the system controller 560. The system controller 560 may transmit the first voltage level signal VDDMC received from the first memory module 540 to the processor 530. The processor 530 may transmit a voltage adjustment signal MVS to the system controller 560. The system controller 560 may transmit the voltage adjustment signal MVS received from the processor 530 to the first memory module 540. The processor 530 may be coupled to the system controller 560 via a first signal transmission line 505. The first memory module 540 may be coupled to the system controller 560 via a second signal transmission line 507. The first signal transmission line 505 and the second signal transmission line 507 may use the same communication protocol. The system controller 560 may communicate with the processor 530 and the first memory module 540 via the same communication protocol. The communication protocol may include at least one of the SPI protocol, the I2C protocol, and the I3C protocol. Processor 530, first memory module 540, and system controller 560 can operate without additional signal transmission lines because each of them can perform the operation of reducing the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P using the communication protocol already included in computing system 500. Furthermore, computing system 500 offers greater design flexibility because the monitoring circuitry for detecting the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M can be selectively located in any component of computing system 500.

[0047] The first memory module 540 may include a power management integrated circuit (PMIC) 543 and at least one memory. The PMIC 543 may receive a second input voltage BV2 from a power supply 510. The PMIC 543 may generate a memory power supply voltage VDD_M from the second input voltage BV2. The PMIC 543 may store memory power supply voltage setting information regarding a target voltage level for the memory power supply voltage VDD_M, for example... Figure 4The PMIC 543 can generate a memory power supply voltage VDD_M from the second input voltage BV2 based on memory power supply voltage setting information. The PMIC 543 can supply the memory power supply voltage VDD_M to the memory devices included in the first memory module 540. The PMIC 543 can provide the memory power supply voltage VDD_M to at least one memory device via memory power line 542. The PMIC 543 can generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. The PMIC 543 may include an ADC capable of generating the first voltage level signal VDDMC from the memory power supply voltage VDD_M. The PMIC 543 can be coupled to the system controller 560 via a second signal transmission line 507. The PMIC 543 can transmit the first voltage level signal VDDMC to the system controller 560 via the second signal transmission line 507.

[0048] For example, the first memory module 540 may include four memory devices. The memory devices can be coupled to the PMIC 543 via memory power line 542 and can receive the memory power supply voltage VDD_M from the PMIC 543 via memory power line 542. The memory devices can operate using the memory power supply voltage VDD_M. Data DQ transferred from the processor 530 to the first memory module 540 via data bus 503 can be input to the memory devices. The memory devices can store data DQ. Data output from the memory can be transferred to the processor 530 as data DQ via data bus 503. The memory devices can drive the data bus 503 using the memory power supply voltage VDD_M to transfer data DQ. The first memory module 540 may also include a serial presence detection (SPD) 545. The SPD 545 can be coupled to the system controller 560 via a second signal transmission line 507.

[0049] Figure 6 This is a diagram illustrating the configuration of a computing system 600 according to an embodiment. (Refer to...) Figure 6 The computing system 600 may include a power supply 610, a main voltage regulator 620, a processor 630, a first memory module 640, a system controller 660, and a power switch 670. In the following text, the components mentioned above may be omitted. Figure 5 The descriptions of the components of the computing system 500 shown are identical or redundant to the descriptions of the components of the computing system 600. The power supply 610 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. The main voltage regulator 620 can generate the processor power supply voltage VDD_P by receiving the first input voltage BV1. The main voltage regulator 620 can provide the processor power supply voltage VDD_P to the processor 630 and the power switch 670 via the processor power line 601.

[0050] Processor 630 can communicate with first memory module 640. Processor 630 receives processor power supply voltage VDD_P from main voltage regulator 620 via processor power line 601 and can operate using processor power supply voltage VDD_P. Processor 630 is coupled to first memory module 640 via data bus 603, and can transmit data DQ to and receive data DQ transmitted by first memory module 640 via data bus 603. Processor 630 can transmit data DQ to first memory module 640 by driving data bus 603 using processor power supply voltage VDD_P.

[0051] The first memory module 640 can communicate with the processor 630. The first memory module 640 can receive a second input voltage BV2 and generate a memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 640 can operate using the memory power supply voltage VDD_M. The target voltage level of the memory power supply voltage VDD_M can be the same as the target voltage level of the processor power supply voltage VDD_P. The first memory module 640 can be coupled to the processor 630 via a data bus 603, and can transmit data DQ to and receive data DQ transmitted by the processor 630 via the data bus 603. The first memory module 640 can transmit data DQ to the processor 630 by driving the data bus 603 to the memory power supply voltage VDD_M. The computing system 600 may include one or more memory modules. In one embodiment, the computing system 600 may further include a second memory module 650. The second memory module 650 may have a configuration substantially the same as the first memory module 640 and may be coupled to a component of the computing system 600 in a substantially the same manner as the first memory module 640.

[0052] Processor 630 can monitor the processor power supply voltage VDD_P and the memory power supply voltage VDD_M. Processor 630 can compare the voltage level of processor power supply voltage VDD_P with the voltage level of memory power supply voltage VDD_M, and can generate a voltage adjustment signal MVS by determining whether the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M is within a threshold range. Processor 630 can also generate a switching signal SWS by detecting the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M. Processor 630 can provide the switching signal SWS to power switch 670. When the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M is within the threshold range, processor 630 can enable the switching signal SWS. When the voltage level difference between processor power supply voltage VDD_P and memory power supply voltage VDD_M is outside the threshold range, processor 630 can disable the switching signal SWS.

[0053] The first memory module 640 can generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. The processor 630 can generate a second voltage level signal VDDPC based on the processor power supply voltage VDD_P. The processor 630 may include an ADC 631, which is capable of generating the second voltage level signal VDDPC from the processor power supply voltage VDD_P. The processor 630 may also include a monitoring circuit 632, which generates a voltage adjustment signal MVS by comparing the first voltage level signal VDDMC with the second voltage level signal VDDPC. The processor 630 may also include a switch control circuit 633, which generates a switch signal SWS by comparing the first voltage level signal VDDMC with the second voltage level signal VDDPC. In one embodiment, the switch control circuit 633 may be integrated into the monitoring circuit 632. For example, the monitoring circuit including the functionality of the switch control circuit 633 can enable the switch signal SWS when the voltage adjustment signal MVS is not generated, and can disable the switch signal SWS when the voltage adjustment signal MVS is generated.

[0054] System controller 660 can be coupled to first memory module 640 and processor 630. System controller 660 can be coupled to processor 630 via first signal transmission line 605 and to first memory module 640 via second signal transmission line 607. First memory module 640 can transmit a first voltage level signal VDDMC to system controller 660 via second signal transmission line 607. System controller 660 can transmit the first voltage level signal VDDMC received from first memory module 640 to processor 630 via first signal transmission line 605. Processor 630 can transmit a voltage adjustment signal MVS to system controller 660 via first signal transmission line 605. System controller 660 can transmit the voltage adjustment signal MVS received from processor 630 to first memory module 640 via second signal transmission line 607.

[0055] The first memory module 640 may include a power management integrated circuit (PMIC) 643 and at least one memory. PMIC 643 may receive a second input voltage BV2 from a power supply 610. PMIC 643 may generate a memory power supply voltage VDD_M from the second input voltage BV2. PMIC 643 may store memory power supply voltage setting information regarding a target voltage level for the memory power supply voltage VDD_M. PMIC 643 may generate the memory power supply voltage VDD_M from the second input voltage BV2 based on the memory power supply voltage setting information. PMIC 643 may provide the memory power supply voltage VDD_M to the memory included in the first memory module 640. PMIC 643 may provide the memory power supply voltage VDD_M to at least one memory via a memory power line 642. PMIC 643 may provide the memory power supply voltage VDD_M to a power switch 670 via the memory power line 642. One of the module pins included in the first memory module 640 may be assigned to PMIC 643, and PMIC 643 may be coupled to the power switch 670 via the memory power line 642 and the assigned module pin. PMIC 643 can generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. PMIC 643 may include an ADC that generates the first voltage level signal VDDMC from the memory power supply voltage VDD_M. PMIC 643 may be coupled to system controller 660. PMIC 643 can transmit the first voltage level signal VDDMC to system controller 660 via a second signal transmission line 607.

[0056] For example, the first memory module 640 may include four memory devices. The memory devices can be coupled to the PMIC 643 via memory power line 642 and can receive the memory power supply voltage VDD_M from the PMIC 643 via memory power line 642. The memory devices can operate using the memory power supply voltage VDD_M. Data DQ transferred from the processor 630 to the first memory module 640 via data bus 603 can be input to the memory devices. The memory devices can store data DQ. Data output from the memory devices can be transmitted to the processor 630 as data DQ via data bus 603. The memory devices can drive the data bus 603 using the memory power supply voltage VDD_M to transmit data DQ. The first memory module 640 may also include a serial presence detection (SPD) 645. The SPD 645 can be coupled to the system controller 660 via a second signal transmission line 607.

[0057] Power switch 670 can receive a switch signal SWS and can selectively connect processor power line 601 to memory power line 642 based on the switch signal SWS. When the switch signal SWS is enabled, power switch 670 can be turned on and can connect processor power line 601 to memory power line 642. When the switch signal SWS is disabled, power switch 670 can be turned off and can electrically disconnect processor power line 601 from memory power line 642. When the voltage level difference between memory power supply voltage VDD_M and processor power supply voltage VDD_P is within a threshold range, the switch signal SWS can be enabled, and power switch 670 can connect processor power line 601 to memory power line 642. Since processor power line 601 and memory power line 642 are coupled to each other through power switch 670, the voltage level of memory power supply voltage VDD_M and the voltage level of processor power supply voltage VDD_P can be balanced. For example, when the processor power supply voltage VDD_P has a higher voltage level than the memory power supply voltage VDD_M, the power switch 670 can reduce the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M by lowering the processor power supply voltage VDD_P and raising the memory power supply voltage VDD_M. Conversely, when the processor power supply voltage VDD_P has a lower voltage level than the memory power supply voltage VDD_M, the power switch 670 can reduce the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M by raising the processor power supply voltage VDD_P and lowering the memory power supply voltage VDD_M. When the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P exceeds a threshold range, the switch signal SWS is disabled, and the power switch 670 can electrically disconnect the processor power line 601 from the memory power line 642. The voltage level of the memory power supply voltage VDD_M can be adjusted based on the voltage adjustment signal MVS and PMIC 643, independent of the voltage level of the processor power supply voltage VDD_P. After PMIC 643 adjusts the voltage level of the memory power supply voltage VDD_M based on the voltage adjustment signal MVS, when the processor 630 again determines that the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P is within the threshold range, the processor 630 can re-enable the switch signal SWS. When the switch signal SWS is enabled, the power switch 670 can reduce or minimize the voltage level difference between the processor power supply voltage VDD_P and the memory power supply voltage VDD_M by balancing the voltage levels of the processor power supply voltage VDD_P and the memory power supply voltage VDD_M.

[0058] The power switch 670 may include a resistor 671 and a transistor 672. One end of the resistor 671 may be coupled to the processor power line 601. The switching signal SWS may be an enable signal to a logic high level. The transistor 672 may be an N-channel MOS transistor. In one embodiment, the switching signal SWS may be modified to an enable signal to a logic low level. The transistor 672 may be implemented using a P-channel MOS transistor. The gate of the transistor 672 may be coupled to the other end of the resistor 671 and may receive the switching signal SWS from the processor 630. One of the sources and drains of the transistor 672 may be coupled to the processor power line 601, and the other of the sources and drains of the transistor 672 may be coupled to the memory power line 642.

[0059] Figure 7 This is a diagram illustrating the configuration of a computing system 700 according to an embodiment. (Refer to...) Figure 7 The computing system 700 may include a power supply 710, a main voltage regulator 720, a processor 730, a first memory module 740, a system controller 760, and a power switch 770. In the following text, the components mentioned above may be omitted. Figure 6The descriptions of the components of the computing system 600 shown are identical or redundant to the descriptions of the components of the computing system 700. Power supply 710 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. Main voltage regulator 720 can generate a processor power supply voltage VDD_P from the first input voltage BV1. Main voltage regulator 720 can provide processor power supply voltage VDD_P to processor 730 via processor power line 701. Processor 730 can operate by receiving processor power supply voltage VDD_P. Processor 730 can be coupled to first memory module 740 via data bus 703 and can transmit data DQ to first memory module 740 by driving data bus 703 using processor power supply voltage VDD_P. Processor 730 can generate voltage adjustment signal MVS and switching signal SWS by monitoring memory power supply voltage VDD_M and processor power supply voltage VDD_P. First memory module 740 can receive a second input voltage BV2 and can generate memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 740 can be coupled to the processor 730 via a data bus 703, and can transmit data DQ to the processor 730 by driving the data bus 703 to the memory power supply voltage VDD_M. The first memory module 740 can adjust the target voltage level of the memory power supply voltage VDD_M based on the voltage adjustment signal MVS. The computing system 700 may also include a second memory module 750 having a structure substantially the same as the first memory module 740. The processor 730 can be coupled to the system controller 760 via a first signal transmission line 705. The first memory module 740 can be coupled to the system controller 760 via a second signal transmission line 707.

[0060] The first memory module 740 may include a power management integrated circuit (PMIC) 743 and at least one memory device. For example, the first memory module 740 may include four memory devices. The PMIC 743 may receive a second input voltage BV2, generate a memory power supply voltage VDD_M from the second input voltage BV2, and provide the memory power supply voltage VDD_M to the memory devices through a memory power line 742. The PMIC 743 may generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. The first memory module 740 may also include a serial presence detection (SPD) 745 coupled to the system controller 760 via a second signal transmission line 707.

[0061] PMIC 743 can transmit the first voltage level signal VDDMC to system controller 760 via the second signal transmission line 707. System controller 760 can transmit the first voltage level signal VDDMC to processor 730 via the first signal transmission line 705. Processor 730 can transmit the voltage adjustment signal MVS to system controller 760 via the first signal transmission line 705. System controller 760 can transmit the voltage adjustment signal MVS to the first memory module 740 and PMIC 743 via the second signal transmission line 707. Processor 730 can transmit the switch signal SWS to system controller 760 via the first signal transmission line 705.

[0062] Power switch 770 can receive a switch drive signal SWSD and can selectively connect processor power line 701 to memory power line 742 based on the switch drive signal SWSD. Power switch 770 can receive the switch drive signal SWSD from system controller 760 without requiring... Figure 6 The diagram shows the processor 630 directly receiving the switch signal SWS. The computing system 700 can provide the switch signal SWS as a switch drive signal SWSD to the power switch 770 via the system controller 760, instead of directly providing the switch signal SWS from the processor 730 to the power switch 770. The processor 730 can transmit the switch signal SWS to the system controller 760. The system controller 760 can generate the switch drive signal SWSD by driving the switch signal SWS. The system controller 760 can provide the switch drive signal SWSD to the power switch 770. If... Figure 6 As shown, if the processor 630 directly provides the switching signal SWS to the power switch 670, then an additional signal transmission line is needed to couple the processor 630 and the power switch 670, and the design of the processor 630 may need to be modified. For example... Figure 7 As shown, if the processor 730 provides a switch signal SWS to the system controller 760, and the system controller 760 provides a switch drive signal SWSD to the power switch 770, the power switch 770 can be effectively controlled without changing the design of the processor 730.

[0063] PMIC 743 may include an ADC that generates a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. Processor 730 may include an ADC 731 that generates a second voltage level signal VDDPC based on the processor power supply voltage VDD_P. Processor 730 may include monitoring circuitry 732 that generates a voltage adjustment signal MVS by comparing the first voltage level signal VDDMC and the second voltage level signal VDDPC. Processor 730 may include switch control circuitry 733 that generates a switch signal SWS by comparing the first voltage level signal VDDMC and the second voltage level signal VDDPC. System controller 760 may include a switch driver 761. Switch driver 761 can receive the switch signal SWS from processor 730 and can generate a switch drive signal SWSD by driving the switch signal SWS. Switch driver 761 can provide the switch drive signal SWSD to power switch 770.

[0064] Figure 8 This is a diagram illustrating the configuration of a computing system 800 according to an embodiment. (Refer to...) Figure 8 The computing system 800 may include a power supply 810, a main voltage regulator 820, a processor 830, a first memory module 840, a system controller 860, and a power switch 870. (The following text may omit the references to these components.) Figure 6The descriptions of the components of the computing system 600 shown are identical or redundant to the descriptions of the components of the computing system 800. Power supply 810 can generate a first input voltage BV1 and a second input voltage BV2 by receiving power from an external source. Main voltage regulator 820 can generate a processor power supply voltage VDD_P from the first input voltage BV1. Main voltage regulator 820 can provide the processor power supply voltage VDD_P to processor 830 via processor power line 801. Processor 830 can operate by receiving processor power supply voltage VDD_P. Processor 830 can be coupled to a first memory module 840 via data bus 803 and can transmit data DQ to the first memory module 840 by driving data bus 803 using processor power supply voltage VDD_P. First memory module 840 can receive a second input voltage BV2 and can generate a memory power supply voltage VDD_M from the second input voltage BV2. The first memory module 840 can be coupled to the processor 830 via a data bus 803, and data DQ can be transferred to the processor 830 by driving the data bus 803 to the memory power supply voltage VDD_M. The computing system 800 may also include a second memory module 850 having a structure substantially the same as the first memory module 840. The processor 830 can be coupled to the system controller 860 via a first signal transmission line 805. The first memory module 840 can be coupled to the system controller 860 via a second signal transmission line 807.

[0065] The first memory module 840 may include a power management integrated circuit (PMIC) 843 and at least one memory. For example, the first memory module 840 may include four memory devices. The PMIC 843 may receive a second input voltage BV2, generate a memory power supply voltage VDD_M from the second input voltage BV2, and supply the memory power supply voltage VDD_M to the memory devices via a memory power line 842. The first memory module 840 may also include a serial presence detection (SPD) 845 coupled to the system controller 860 via a second signal transmission line 807.

[0066] System controller 860 can generate a voltage adjustment signal MVS and a switching signal SWS based on the memory power supply voltage VDD_M and the processor power supply voltage VDD_P. When the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P is within a threshold range, system controller 860 can enable the switching signal SWS without generating the voltage adjustment signal MVS. When the voltage level difference between the memory power supply voltage VDD_M and the processor power supply voltage VDD_P exceeds the threshold range, system controller 860 can generate the voltage adjustment signal MVS to change the voltage level of the memory power supply voltage VDD_M and can disable the switching signal SWS. If... Figure 3 orFigure 7 As shown, the PMIC 343 or processor 730 generates a voltage adjustment signal MVS or a switching signal SWS by comparing the memory power supply voltage VDD_M with the processor power supply voltage VDD_P, which may incur the burden of modifying the design of the PMIC 343 or processor 730. If the system controller 860 includes the function of monitoring the memory power supply voltage VDD_M and the processor power supply voltage VDD_P, the burden of modifying the PMIC or processor design can be reduced.

[0067] PMIC 843 can generate a first voltage level signal VDDMC based on the memory power supply voltage VDD_M, and provide the first voltage level signal VDDMC to the system controller 860 through the second signal transmission line 807. Processor 830 can generate a second voltage level signal VDDPC based on the processor power supply voltage VDD_P, and provide the second voltage level signal VDDPC to the system controller 860 through the first signal transmission line 805. System controller 860 can generate a voltage adjustment signal MVS and a switching signal SWS by comparing the first voltage level signal VDDMC with the second voltage level signal VDDPC. System controller 860 can provide the voltage adjustment signal MVS to PMIC 843 of the first memory module 840 through the second signal transmission line 807. PMIC 843 can adjust the target voltage level of the memory power supply voltage VDD_M based on the voltage adjustment signal MVS. System controller 860 can provide the switching signal SWS to the power switch 870. Power switch 870 can receive the switching signal SWS provided by system controller 860. The power switch 870 can selectively electricalally couple the processor power line 801 to the memory power line 842 based on the switch signal SWS to balance the voltage levels of the processor power supply voltage VDD_P and the memory power supply voltage VDD_M.

[0068] PMIC 843 may include an ADC that generates a first voltage level signal VDDMC based on the memory power supply voltage VDD_M. Processor 830 may include an ADC 831 that generates a second voltage level signal VDDPC based on the processor power supply voltage VDD_P. System controller 860 may include monitoring circuitry 861 that generates a voltage adjustment signal MVS by comparing the first voltage level signal VDDMC with the second voltage level signal and VDDPC. System controller 860 may include switch control circuitry 862 that generates a switch signal SWS by comparing the first voltage level signal VDDMC with the second voltage level signal VDDPC.

[0069] As described above, those skilled in the art will understand that this technology can be implemented in many other forms without departing from its technical spirit or essential characteristics. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. The scope of this technology is defined by the appended claims rather than the detailed description, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of this technology.

Claims

1. A computing system, comprising: A power supply that generates a first input voltage and a second input voltage; A main voltage regulator that generates a processor power supply voltage based on the first input voltage; A processor that receives the processor power supply voltage; as well as The memory module communicates with the processor. The memory module includes: At least one memory device; and A power management integrated circuit that: receives a second input voltage and a processor power supply voltage; generates a memory power supply voltage based on the second input voltage and memory power supply voltage setting information; provides the memory power supply voltage to the at least one memory device; and changes the memory power supply voltage setting information based on a comparison between the memory power supply voltage and the processor power supply voltage.

2. The computing system according to claim 1, wherein, The target voltage level of the memory power supply voltage and the target voltage level of the processor power supply voltage are substantially the same.

3. The computing system according to claim 1, in, The memory module is coupled to the processor via a data bus. The memory module utilizes the memory power supply voltage to drive the data bus, and The processor drives the data bus using its power supply voltage.

4. The computing system according to claim 1, wherein, The power management integrated circuit maintains the memory power supply voltage setting information when the voltage level difference between the memory power supply voltage and the processor power supply voltage is within a threshold range. And when the voltage level difference between the memory power supply voltage and the processor power supply voltage exceeds the threshold range, the memory power supply voltage setting information is modified.

5. The computing system according to claim 1, wherein, The power management integrated circuit includes: The configuration register stores the memory power supply voltage setting information and the code value for changing the memory power supply voltage setting information based on the voltage adjustment signal. A reference voltage generator, which generates a reference voltage based on the second input voltage and the memory power supply voltage setting information; A voltage regulator that: generates the memory power supply voltage based on the second input voltage, the reference voltage, and the memory power supply voltage; and A monitoring circuit that: receives the memory power supply voltage and the processor power supply voltage; and generates the voltage adjustment signal by determining whether the voltage level difference between the memory power supply voltage and the processor power supply voltage is greater than a threshold range.

6. The computing system according to claim 5, wherein, The monitoring circuit generates the voltage adjustment signal when the voltage level difference between the memory power supply voltage and the processor power supply voltage exceeds the threshold range.

7. A computing system, comprising: A power supply that generates a first input voltage and a second input voltage; A main voltage regulator that generates a processor power supply voltage based on the first input voltage; A processor that receives the processor power supply voltage; as well as The memory module communicates with the processor. The memory module includes: At least one memory device; and A power management integrated circuit, comprising: generating a memory power supply voltage based on a second input voltage and memory power supply voltage setting information; providing the memory power supply voltage to the at least one memory device; and changing the memory power supply voltage setting information based on a voltage adjustment signal. The processor generates the voltage adjustment signal based on the processor power supply voltage and the memory power supply voltage.

8. The computing system according to claim 7, wherein, The target voltage level of the memory power supply voltage and the target voltage level of the processor power supply voltage are substantially the same.

9. The computing system according to claim 7, in, The memory module is coupled to the processor via a data bus. The memory module utilizes the memory power supply voltage to drive the data bus, and The processor drives the data bus using its power supply voltage.

10. The computing system according to claim 7, wherein, The processor generates the voltage adjustment signal when the difference between the voltage level of the processor power supply voltage and the voltage level of the memory power supply voltage exceeds a threshold range.

11. The computing system according to claim 7, in, The power management integrated circuit: generates a first voltage level signal corresponding to the voltage level of the memory power supply voltage, and The processor: generates a second voltage level signal corresponding to the voltage level of the processor power supply voltage; and generates the voltage adjustment signal by comparing the first voltage level signal with the second voltage level signal.

12. The computing system according to claim 11, wherein, The processor generates the voltage adjustment signal when the difference between the code value of the first voltage level signal and the code value of the second voltage level signal is greater than a threshold.

13. The computing system of claim 11, further comprising a system controller, the system controller communicating with the processor and the memory module. in, The system controller: provides the memory module with the voltage adjustment signal provided by the processor; And to provide the processor with the first voltage level signal provided by the memory module.

14. The computing system according to claim 13, wherein, The system controller communicates with the memory module and the processor via at least one of the Serial Peripheral Interface (SPI) protocol, the Inter-Integrated Circuit (I2C) protocol, and the modified Inter-Integrated Circuit (I3C) protocol.

15. The computing system of claim 7, further comprising a power switch, said power switch: coupling a power line supplying power voltage to the memory via it to a power line supplying power voltage to the processor via it based on a switching signal. in, The processor generates the switching signal based on the memory power supply voltage and the processor power supply voltage.

16. The computing system according to claim 15, wherein, The processor enables the switch signal when the difference between the voltage level of the memory power supply voltage and the voltage level of the processor power supply voltage is within a threshold range; and disables the switch signal when the difference between the voltage levels of the memory power supply voltage and the processor power supply voltage exceeds the threshold range.

17. The computing system according to claim 7, further comprising: A power switch, wherein: based on a switch drive signal, a power line supplying power voltage to the memory is coupled therethrough to a power line supplying power voltage to the processor; and The system controller communicates with the processor and the memory module. The processor: generates a switching signal based on the memory power supply voltage and the processor power supply voltage; and provides the switching signal to the system controller. The system controller generates the switch drive signal by driving the switch signal.

18. A computing system, comprising: A power supply that generates a first input voltage and a second input voltage; A main voltage regulator that generates a processor power supply voltage based on the first input voltage; A processor that receives the processor power supply voltage; A memory module that communicates with the processor; as well as The system controller communicates with the processor and the memory module. The memory module includes: At least one memory device; and A power management integrated circuit, comprising: generating a memory power supply voltage based on a second input voltage and memory power supply voltage setting information; providing the memory power supply voltage to the at least one memory device; and changing the memory power supply voltage setting information based on a voltage adjustment signal. The system controller generates the voltage adjustment signal based on the processor power supply voltage and the memory power supply voltage.

19. The computing system according to claim 18, wherein, The target voltage level of the memory power supply voltage and the target voltage level of the processor power supply voltage are substantially the same.

20. The computing system according to claim 18, in, The memory module is coupled to the processor via a data bus. The memory module utilizes the memory power supply voltage to drive the data bus, and The processor drives the data bus using its power supply voltage.

21. The computing system according to claim 18, wherein, The system controller communicates with the memory module and the processor via at least one of the Serial Peripheral Interface (SPI) protocol, the Inter-Integrated Circuit (I2C) protocol, and the modified Inter-Integrated Circuit (I3C) protocol.

22. The computing system according to claim 18, wherein, The system controller generates the voltage adjustment signal when the difference between the voltage level of the memory power supply voltage and the voltage level of the processor power supply voltage exceeds the threshold range.

23. The computing system according to claim 18, in, The power management integrated circuit generates a first voltage level signal corresponding to the voltage level of the memory power supply voltage. The processor generates a second voltage level signal corresponding to the voltage level of the processor's power supply voltage, and The system controller generates the voltage adjustment signal by comparing the first voltage level signal with the second voltage level signal.

24. The computing system according to claim 23, wherein, The system controller generates the voltage adjustment signal when the difference between the code value of the first voltage level signal and the code value of the second voltage level signal is greater than a threshold.

25. The computing system of claim 18, further comprising a power switch, the power switch coupling a power line supplying power voltage to the memory via a power line supplying power voltage to the processor via a power line based on a switching signal. in, The system controller generates the switching signal based on the memory power supply voltage and the processor power supply voltage.

26. The computing system according to claim 25, wherein, The system controller enables the switching signal when the difference between the voltage levels of the memory power supply voltage and the processor power supply voltage is within a threshold range; and disables the switching signal when the difference between the voltage levels of the memory power supply voltage and the processor power supply voltage exceeds the threshold range.

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