L2P linked list establishing method in storage controller and storage device

Abstract

The invention discloses a link establishment method for an L2P linked list in a storage controller and storage equipment. The method comprises the following steps: reading a P2L mapping table to be matched; inputting each node in the to-be-matched P2L mapping table into a hardware matching engine; obtaining an L2P page index matching result of each node returned by the hardware matching engine; according to the L2P page index matching result, a plurality of L2P linked lists are constructed, and the L2P linked lists comprise all nodes belonging to the same L2P page; and updating the corresponding L2P page in the L2P mapping table according to each L2P linked list. According to the invention, all nodes belonging to the same L2P page in the to-be-matched P2L mapping table are matched into one L2P linked list, so that each L2P page can be updated in sequence according to each L2P linked list when the L2P mapping table is updated, a low-efficiency mode of multiple traversal is avoided, high-speed matching in a link building process is realized by utilizing a parallel matching mechanism of a hardware matching engine, and the matching efficiency is improved. And the updating efficiency of the L2P mapping table is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage chip testing, in particular to a method for building a L2P chain table in a storage controller and a storage device. BACKGROUND

[0002] In a NAND FLASH (flash chip) based solid state storage device (such as a flash memory, an embedded multimedia card, a universal flash storage or a solid state disk), a L2P (Logical to Physical) mapping table is one of the core data structures for implementing an FTL (Flash Translation Layer) function. Corresponding to the L2P mapping table, there is also a P2L (Physical to Logical) mapping table.

[0003] When performing a write operation on the solid state storage device, the P2L mapping of newly written data is updated reversely to update the corresponding L2P table item, so as to maintain address mapping consistency. At present, the existing scheme for updating the L2P mapping table is usually to traverse each node in a to-be-matched P2L mapping table by a controller (CPU, Central Processing Unit) in the solid state storage device, calculate the L2P page index (L2P Table Index) of the node according to the logical unit address (LUA, Logical Unit Address) recorded in the to-be-matched P2L mapping table, load the corresponding L2P page into the memory cache for modification, and then traverse the remaining nodes in the to-be-matched P2L mapping table that have not been updated through the L2P page index to update them. This process is highly dependent on the processing capability of the controller, and when each node in the to-be-matched P2L mapping table is distributed discretely, the update and back flushing of the current L2P page can be completed only after traversing the entire to-be-matched P2L mapping table multiple times.

[0004] Therefore, the existing scheme for updating the L2P mapping table has the problem of low update efficiency. SUMMARY

[0005] The main purpose of the present application is to provide a method for building a L2P chain table in a storage controller and a storage device, which aims to solve the problem of low update efficiency when updating the L2P mapping table.

[0006] To achieve the above purpose, the present application provides a method for building a L2P chain table in a storage controller, comprising: reading a to-be-matched P2L mapping table; inputting each node in the to-be-matched P2L mapping table into a hardware matching engine; obtaining L2P page index matching results of each node returned by the hardware matching engine; constructing a plurality of L2P linked lists according to the L2P page index matching results, wherein the L2P linked lists include all the nodes belonging to the same L2P page; updating a corresponding L2P page in an L2P mapping table according to each L2P linked list.

[0007] In some embodiments, the method further comprises, before inputting each node in the P2L mapping table to be matched into the hardware matching engine: constructing an L2P page index array, an L2P chain head array and an L2P chain tail array, wherein the L2P page index array is used to store L2P page index values to be matched, and the L2P chain head array and the L2P chain tail array are used to manage linked list nodes by offset address indexing; and initializing all elements of the L2P page index array, the L2P chain head array and the L2P chain tail array to invalid values.

[0008] In some embodiments, the method further comprises, before constructing the L2P page index array, the L2P chain head array and the L2P chain tail array: determining the number of nodes in the P2L mapping table to be matched; based on the number of nodes, creating the L2P page index array, the L2P chain head array and the L2P chain tail array, wherein the number of spaces of the L2P page index array, the L2P chain head array and the L2P chain tail array is greater than or equal to the number of nodes.

[0009] In some embodiments, the method further comprises, inputting each node in the P2L mapping table to be matched into the hardware matching engine: batching one or more nodes to be processed from the P2L mapping table to be matched to form a current processing batch node set; concurrently inputting logical unit addresses of each node in the current processing batch node set into the hardware matching engine for matching.

[0010] In some embodiments, the method further comprises, after obtaining L2P page index matching results of each node returned by the hardware matching engine: determining whether there are still unprocessed nodes in the P2L mapping table to be matched; if there are unprocessed nodes in the P2L mapping table to be matched, returning to the step of batching one or more nodes to be processed from the P2L mapping table to be matched to form a current processing batch node set; if there are no unprocessed nodes in the P2L mapping table to be matched, confirming that L2P page index matching results of all the nodes in the P2L mapping table to be matched are obtained.

[0011] In some embodiments, constructing multiple L2P linked lists based on the L2P page index matching results includes: Iterate through each node in the current batch of nodes; For the current node being processed, determine whether the L2P page index matching result of the current node is a match failure; If the L2P page index matching result is a failure, the first element marked as invalid in the L2P page index array is located as the new offset address, and the L2P page index of the current node is written to the location. The newly added L2P index will be used for matching in the next matching. The current node is used as the head and tail of the new L2P linked list, and the element values ​​at the corresponding index positions in the L2P head array and the L2P tail array are updated to the address of the current node based on the new offset address.

[0012] In some embodiments, after determining whether the L2P page index matching result of the current node is a match failure, the method further includes: If the L2P page index matching result is a successful match, then obtain the matched target offset address; Based on the target offset address, query the L2P chain head array and the L2P chain tail array to determine the target L2P linked list corresponding to the target offset address; The node is appended to the tail of the target L2P linked list, and the element value corresponding to the target offset address in the L2P tail array is updated to the address of the current node based on the target offset address.

[0013] In some embodiments, updating the corresponding L2P page in the L2P mapping table according to each of the L2P linked lists includes: The L2P linked lists are selected sequentially, and the L2P pages corresponding to the L2P linked lists are loaded from the non-volatile storage medium into the cache area; Traverse each node in the L2P linked list and update the physical block address corresponding to the logical unit address in the L2P page in batches; After all nodes in the L2P linked list have been processed, the updated L2P page is written back from the cache to the non-volatile storage medium. Repeat the above steps until all L2P pages corresponding to all L2P linked lists have been updated, then the L2P mapping table update is complete.

[0014] In some embodiments, obtaining the L2P page index matching results of each node returned by the hardware matching engine includes: Receive the L2P page index matching results obtained by the hardware matching engine based on the L2P page index array, matching each item of the L2P page index; The L2P page index of the node is obtained by the hardware matching engine through a shift operation on the logical unit address of the node based on the size of the L2P page.

[0015] In some embodiments, receiving the L2P page index matching result obtained by the hardware matching engine based on the L2P page index array through item-by-item matching includes: Receive the L2P page index matching result that failed to match when the hardware matching engine did not find a matching L2P page index; or, Receive the L2P page index matching result generated when the hardware matching engine matches the same L2P page index.

[0016] This application further proposes a storage device, which includes a storage controller, a hardware matching engine, and a flash memory chip; the storage device is capable of executing the chain-building method of the L2P linked list in the storage controller described above.

[0017] The technical solution of this application reads the P2L mapping table to be matched; inputs each node in the P2L mapping table into a hardware matching engine; obtains the L2P page index matching results of each node returned by the hardware matching engine; constructs multiple L2P linked lists based on the L2P page index matching results, wherein each L2P linked list includes all nodes belonging to the same L2P page; updates the corresponding L2P page in the L2P mapping table according to each L2P linked list; by matching all nodes belonging to the same L2P page in the P2L mapping table to be matched into one L2P linked list, the L2P mapping table can be updated sequentially according to each L2P linked list, avoiding the inefficient mode of multiple traversals, and using the parallel matching mechanism of the hardware matching engine to achieve high-speed matching in the chain building process, thus improving the update efficiency of the L2P mapping table. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating an embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 2 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 3 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 4 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 5This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 6 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 7 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 8 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. Figure 9 This is a schematic diagram of the structure of an embodiment of the storage device of this application. Detailed Implementation

[0019] The solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments in this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] This application proposes a method for establishing an L2P linked list in a storage controller, referring to... Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, the method for establishing an L2P linked list in the storage controller includes: Step S110: Read the P2L mapping table to be matched; Step S120: Input each node in the P2L mapping table to be matched into the hardware matching engine; Step S130: Obtain the L2P page index matching results of each node returned by the hardware matching engine; Step S140: Construct multiple L2P linked lists based on the L2P page index matching results, wherein each L2P linked list includes all nodes belonging to the same L2P page; Step S150: Update the corresponding L2P page in the L2P mapping table according to each L2P linked list.

[0021] In this embodiment, the method for establishing the L2P linked list in the storage controller can be configured as software, a program, or encapsulated as executable test firmware, a driver-level plugin, or a modular test tool; then it is configured to the storage controller so that the storage controller can run the method for establishing the L2P linked list in the storage controller.

[0022] It's important to understand that the storage controller will be referred to simply as a controller below. The controller can be configured into the storage device, which can also be configured with a hardware matching engine and flash memory chips (i.e., the storage device can be a flash memory-based solid-state storage device). The flash memory chips are used to store data. When the storage device is connected to a host computer, the host computer can write data into the storage device.

[0023] However, the host computer is software- and system-oriented, requiring a unified, contiguous, and hardware-independent address space; therefore, it only recognizes logical addresses (e.g., logical cell addresses). Storage devices, on the other hand, are hardware-oriented, and their read / write operations are determined by the hardware structure of physical blocks and pages; therefore, they only recognize physical addresses (e.g., physical block addresses). The address spaces of the host computer and storage devices are independent of each other, requiring address translation via a mapping table by the controller. This mapping table includes a P2L mapping table and an L2P mapping table. The P2L mapping table maps physical block addresses to logical cell addresses; the L2P mapping table maps logical cell addresses to physical block addresses. The P2L mapping table is used by the host computer, while the L2P mapping table is used internally by the storage device; together, they complete the bidirectional translation between logical cell addresses and physical block addresses.

[0024] When the host computer needs to write data to the storage device, it can issue a logical cell address write command to the storage device. The controller can then write the data to the physical block of the flash memory chip according to this command and update the corresponding physical block address and logical cell address mapping relationship in the P2L mapping table. The controller can also collect all updated P2L mapping table nodes during this write process; the resulting set of nodes is the P2L mapping table to be matched. Here, each node represents the mapping relationship from physical block address to logical cell address.

[0025] After reading the P2L mapping table to be matched, the controller can input each node in the P2L mapping table into the Hardware Matching Engine (HME). The controller can input one or more nodes concurrently into the Hardware Matching Engine, and use the parallel matching mechanism of the Hardware Matching Engine to achieve fast matching.

[0026] For example, the hardware matching engine can match all nodes belonging to the same L2P page to the same L2P page index, and match nodes not belonging to the same L2P page to their corresponding L2P page indices, thus obtaining the L2P page index matching results for each node; finally, it returns the L2P page index matching results for each node to the controller. At this point, the controller can obtain the L2P page index matching results for each node returned by the hardware matching engine. By assigning the "L2P page index matching" operation, originally performed by the controller, to a dedicated on-chip hardware matching engine, the parallel matching mechanism of the hardware matching engine enables high-speed lookup during the chain establishment process.

[0027] The controller can construct multiple L2P linked lists based on the L2P page index matching results of each node. Each L2P linked list includes all nodes belonging to the same L2P page. For example, all nodes with the same L2P page index can be combined into one L2P linked list; the number of L2P linked lists is equal to the number of different L2P page indices, resulting in multiple L2P linked lists.

[0028] After obtaining multiple L2P linked lists, the controller can update the corresponding L2P pages in the L2P mapping table based on each L2P linked list. For example, it can update the corresponding L2P pages in the L2P mapping table one by one based on each L2P linked list. After updating all the L2P linked lists, the L2P mapping table can be updated.

[0029] This application embodiment matches all nodes belonging to the same L2P page in the P2L mapping table to be matched into an L2P linked list. Thus, when updating the L2P mapping table, each L2P page can be updated sequentially according to each L2P linked list, avoiding the inefficient mode of multiple traversals. Furthermore, the parallel matching mechanism of the hardware matching engine is used to achieve high-speed matching in the chain building process, thereby improving the update efficiency of the L2P mapping table.

[0030] Reference Figure 2 , Figure 2 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, the process of inputting each node in the P2L mapping table to be matched into the hardware matching engine, as described above, further includes: Step S160: Construct an L2P page index array, an L2P chain head array, and an L2P chain tail array. The L2P page index array is used to store the L2P page index values ​​to be matched, and the L2P chain head array and L2P chain tail array are used to manage the linked list nodes by offset address indexing. Step S161, and initialize all elements of the L2P page index array, L2P chain head array, and L2P chain tail array to invalid values.

[0031] In this embodiment, as Figure 2As shown, before executing step S120, the controller can first construct an L2P page index array, an L2P chain head array, and an L2P chain tail array. The L2P page index array is used to store the L2P page index values ​​to be matched, while the L2P chain head array and L2P chain tail array are used to manage the linked list nodes using offset address indexing.

[0032] After constructing the L2P page index array, L2P chain head array, and L2P chain tail array, the controller also needs to initialize all elements of the L2P page index array, L2P chain head array, and L2P chain tail array to invalid values.

[0033] Reference Figure 3 , Figure 3 This is a flowchart illustrating another embodiment of the method for building an L2P linked list in the storage controller of this application. In some embodiments, the process further includes, before constructing the L2P page index array, the L2P chain head array, and the L2P chain tail array: Step S170: Determine the number of nodes in the P2L mapping table to be matched; Step S171: Based on the number of nodes, create an L2P page index array, an L2P chain head array, and an L2P chain tail array, wherein the space of the L2P page index array, the L2P chain head array, and the L2P chain tail array is greater than or equal to the number of nodes.

[0034] In this embodiment, as Figure 3 As shown, before executing step S150, the controller can first determine the number of nodes in the P2L mapping table to be matched.

[0035] After determining the number of nodes, the controller can create an L2P page index array, an L2P chain head array, and an L2P chain tail array based on the number of nodes. The space allocated to these arrays is greater than or equal to the number of nodes. This ensures that each node, even when it belongs to a different L2P page from other nodes, has its own array space, resulting in each node having its own L2P linked list. Furthermore, the space allocated to these arrays is greater than the number of nodes, reserving sufficient array space for subsequent additions. This avoids the need for array resizing and expansion due to insufficient space caused by new nodes, reducing the overhead and latency of dynamic array expansion and improving the stability and real-time performance of the L2P linked list creation process.

[0036] The preferred space size for the L2P page index array, L2P chain head array, and L2P chain tail array is equal to the number of nodes.

[0037] For example: Assuming the number of nodes is M, then the space required for the L2P page index array, the L2P head array, and the L2P tail array is all M, where M is a positive integer. Invalid values ​​are set to INVALID. Offset 0-Offset m all represent offset addresses, where m = M-1.

[0038] Table 1: .

[0039] As shown in Table 1 above, Table 1 is the initialized L2P page index array.

[0040] Table 2: .

[0041] As shown in Table 2 above, Table 2 contains the initialized L2P chain head array and L2P chain tail array.

[0042] In this embodiment, the space of the three arrays is equal to the number of nodes, so that each node can be allocated its own array space when each node belongs to a different L2P page from other nodes, thus enabling each node to have its own L2P linked list.

[0043] Reference Figure 4 , Figure 4 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, the aforementioned input of each node in the P2L mapping table to be matched into the hardware matching engine includes: Step S180: Obtain one or more nodes to be processed in batches from the P2L mapping table to be matched, forming the current batch of nodes; Step S181: The logical unit addresses of each node in the current batch of nodes are concurrently input into the hardware matching engine for matching.

[0044] In this embodiment, as Figure 4 As shown, when executing step S120, the controller retrieves one or more nodes to be processed in batches from the P2L mapping table to be matched. The controller can retrieve one or more nodes to be processed in batches from the P2L mapping table to be matched, forming the current processing batch node set. That is, it retrieves one or more nodes to be processed in batches from the P2L mapping table to be matched; the one or more nodes to be processed in the current batch constitute the current processing batch node set. The retrieval method used is non-repeated retrieval, meaning each node is retrieved only once.

[0045] After obtaining the current batch of nodes, the controller concurrently inputs the logical unit addresses of each node in the current batch to the hardware matching engine for matching. This allows the hardware matching engine to simultaneously match the logical unit addresses of each node through a parallel matching mechanism, thereby matching the L2P page index matching results of N nodes.

[0046] This embodiment reduces the load on the controller by assigning the "L2P page index matching" operation, which was originally performed by the controller, to a dedicated on-chip hardware matching engine. Furthermore, it utilizes the parallel matching mechanism of the hardware matching engine to achieve high-speed lookup during the chain building process, thereby improving the update efficiency of the L2P mapping table.

[0047] Reference Figure 5 , Figure 5 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, after obtaining the L2P page index matching results of each node returned by the hardware matching engine, the method further includes: Step S190: Determine whether there are any unprocessed nodes in the P2L mapping table to be matched; Step S191: If there are unprocessed nodes in the P2L mapping table to be matched, return to the step of obtaining one or more nodes to be processed in batches from the P2L mapping table to be matched, forming the current batch of nodes. Step S192: If there are no unprocessed nodes in the P2L mapping table to be matched, then confirm that the L2P page index matching results of all nodes in the P2L mapping table to be matched have been obtained.

[0048] In this embodiment, as Figure 5 As shown, after executing step S130, the controller can also determine whether there are any unprocessed nodes in the P2L mapping table to be matched. After obtaining the L2P page index matching results of each node returned by the hardware matching engine, the controller can also determine whether there are any unprocessed nodes in the P2L mapping table to be matched.

[0049] If there are unprocessed nodes in the P2L mapping table to be matched, the controller will return to the step of retrieving one or more nodes from the P2L mapping table in batches to form the current batch of nodes. This process is then used to retrieve the remaining unprocessed nodes.

[0050] If there are no unprocessed nodes in the P2L mapping table to be matched, the controller can confirm that it has obtained the L2P page index matching results for all nodes in the P2L mapping table to be matched.

[0051] Reference Figure 6 , Figure 6This is a flowchart illustrating another embodiment of the method for building an L2P linked list in the storage controller of this application. In some embodiments, the aforementioned construction of multiple L2P linked lists based on the L2P page index matching results includes: Step S200: Traverse each node in the current batch of nodes; Step S201: For the current node being processed, determine whether the L2P page index matching result of the current node is a match failure; Step S202: If the L2P page index matching result is a match failure, locate the first element marked as invalid in the L2P page index array as the new offset address, and write the L2P page index of the current node to the position. The next time the matching is performed, the newly added L2P index will be used for matching. Step S203: Use the current node as the head and tail of the new L2P linked list, and update the element values ​​at the corresponding index positions in the L2P head array and L2P tail array to the address of the current node based on the new offset address.

[0052] In this embodiment, as Figure 6 As shown, when executing step S140, the controller can use the current node as the head and tail of a new L2P linked list if a match fails. The controller can first traverse each node in the current batch of nodes. For the current node being processed, it determines whether the L2P page index matching result of the current node is a match failure. That is, for the current node, the controller can judge the L2P page index matching result of the current node to determine whether the L2P page index matching result of the current node is a successful match or a match failure.

[0053] The L2P page index matching result for the current node includes either a successful match or a failed match. A failed match occurs when the current node's L2P page index is not found in the L2P page index array. When the L2P page index matching result for the current node is a failed match, the controller can locate the first element marked as invalid in the L2P page index array as the new offset address and write the current node's L2P page index to that location (the first element marked as invalid). The next matching will then check this newly added L2P index. This newly added L2P index refers to the current node's L2P page index. In other words, after writing the current node's L2P page index to that location, subsequent matching will check this newly added L2P index.

[0054] The controller can also use the current node as the head and tail of a new L2P linked list, and update the element values ​​at the corresponding index positions in the L2P head array and L2P tail array to the address of the current node based on the new offset address.

[0055] For example, based on Table 1 and Table 2, the scenarios in which matching fails are explained.

[0056] Suppose a node's logical unit address is LUA a01, and its L2P page index is L2P Index a. If L2P Index a is not found in the L2P page index array, the position of the first element marked as invalid in the L2P page index array can be used as a new offset address, which can be Offset 0. In this way, L2P Index a can be stored at Offset 0 of Table 1, thus obtaining Table 3 based on Table 1.

[0057] Use LUA a01 as the new L2P linked list; LUA a01 is both the head and tail of the list. Then, update the element value corresponding to Offset 0 in the L2P head array and L2P tail array in Table 2 to the address of LUA a01 (for simplicity, the address of LUA a01 is directly represented by LUA a01 in Table 4), thus obtaining Table 4 based on Table 2.

[0058] Table 3: .

[0059] Table 4: .

[0060] In this embodiment, for the sake of simplicity, the logical unit address of the node is used to represent the node; that is, the logical unit address of the node is used to represent the node, thereby constructing the L2P linked list; in fact, the nodes in the L2P linked list include the mapping relationship from physical block address to logical unit address.

[0061] Reference Figure 7 , Figure 7 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, after determining whether the L2P page index matching result of the current node is a failed match, the method further includes: Step S210: If the L2P page index matching result is a successful match, then obtain the matched target offset address; Step S211: Query the L2P chain head array and L2P chain tail array according to the target offset address to determine the target L2P linked list corresponding to the target offset address; Step S212: Append the node to the tail of the target L2P linked list, and update the element value corresponding to the target offset address in the L2P tail array to the address of the current node based on the target offset address.

[0062] In this embodiment, as Figure 7As shown, after executing step S191, the controller can append the current node to the tail of the target L2P linked list when a match is successful. The successful L2P page index matching result includes the target offset address of the current node. The target offset address of the current node refers to the offset address of the L2P page index that is the same as the current node's L2P page index within the L2P page index array. When the L2P page index matching result of the current node is successful, the controller can obtain the matched target offset address.

[0063] After obtaining the matched target offset address, the controller can query the L2P chain head array and L2P chain tail array based on the target offset address to determine the target L2P chain corresponding to the target offset address.

[0064] After determining the target L2P linked list, the controller can append the node to the tail of the target L2P linked list, and then update the element value corresponding to the target offset address in the L2P tail array to the address of the current node based on the target offset address.

[0065] For example, based on Tables 3 and 4, the scenarios where a match was successfully established are explained.

[0066] Suppose a node's logical unit address is LUA a09, and the node's L2P page index is also L2P Index a; if the target offset address of L2P Index a in the L2P page index array is Offset 0; then we can query the L2P chain head array and L2P chain tail array based on Offset 0 to determine that the target L2P linked list corresponding to the target offset address is LUA a01.

[0067] At this point, LUA a09 can be appended to the end of the LUA a01 chain, thus obtaining LUA a01→LUA a09. Then, the element value corresponding to Offset 0 in the L2P chain tail array in Table 4 is updated to the address of LUA a09 (wherein, as explained above, LUA a09 is directly used to represent the address of LUA a09 in Table 5), thus obtaining Table 5 based on Table 4.

[0068] Table 5: .

[0069] In addition, based on Tables 3 and 5, explanations are provided for both matching failures and successful matches.

[0070] Assuming the logical unit addresses of the two nodes are LUA a03 and LUA b03 respectively, then the L2P page index of LUA a03 is L2P Index a, and the L2P page index of LUA b03 is L2P Index b.

[0071] If L2P Index b is not found in the L2P page index array, a new offset address can be allocated to L2P Index b, which can be Offset 1. In this way, L2P Index b can be stored at Offset 1 in Table 3, thereby obtaining Table 6 based on Table 3.

[0072] If the target offset address of L2P Index a in the L2P page index array is Offset 0, then the L2P chain head array and L2P chain tail array can be queried based on Offset 0 to determine that the target L2P linked list corresponding to the target offset address is LUA a01→LUA a09.

[0073] Use LUA b03 as the new L2P linked list; LUA b03 is both the head and tail of the list. Then update the element value corresponding to Offset 1 in the L2P head array and L2P tail array in Table 5 to the address of LUA b03 (wherein, as explained above, LUA b03 is directly used to represent the address of LUA b03 in Table 7). Append LUA a03 to the end of the LUA a01→LUA a09 chain to obtain LUA a01→LUA a09→LUAa03. Update the element value corresponding to Offset 0 in the L2P chain tail array in Table 5 to the address of LUA a03 (wherein, as explained above, LUA a03 is directly used to represent the address of LUA a03 in Table 7), thus obtaining Table 7 based on Table 5.

[0074] Table 6: .

[0075] Table 7: .

[0076] Thus, after matching all nodes in the P2L mapping table and constructing L2P linked lists, multiple L2P linked lists can be obtained. Each L2P linked list includes all nodes belonging to the same L2P page. The L2P page index of a node is calculated based on its logical unit address; logical unit addresses belonging to the same L2P page will result in the same calculated L2P page index.

[0077] Reference Figure 8 , Figure 8 This is a flowchart illustrating another embodiment of the method for establishing an L2P linked list in the storage controller of this application. In some embodiments, the aforementioned updating of the corresponding L2P page in the L2P mapping table according to each L2P linked list includes: Step S220: Select L2P linked lists in sequence and load the L2P pages corresponding to the L2P linked lists from the non-volatile storage medium into the cache area; Step S221: Traverse each node in the L2P linked list and update the physical block address corresponding to the logical unit address in the L2P page in batches. Step S222: After all nodes in the L2P linked list have been processed, the updated L2P page is written back from the cache to the non-volatile storage medium. Step S223: Repeat the above steps until all L2P pages corresponding to all L2P linked lists have been updated, then the L2P mapping table update is complete.

[0078] In this embodiment, as Figure 7 As shown, when executing step S150, the controller can first load the L2P pages corresponding to the L2P linked list from the non-volatile storage medium into the cache. The controller can sequentially select one L2P linked list from multiple L2P linked lists and load the corresponding L2P pages from the non-volatile storage medium into the cache. That is, for any L2P linked list, the controller can first load the corresponding L2P pages from the non-volatile storage medium into the cache. For example, suppose an L2P linked list is LUA a01→LUA a09→LUA a03. In this way, the corresponding L2P page can be determined based on LUA a01, and thus the L2P page can be loaded from the non-volatile storage medium into the cache.

[0079] After loading the L2P pages from non-volatile storage media into the cache, the controller can traverse each node in the L2P linked list and update the physical block addresses corresponding to the logical unit addresses in the L2P pages in batches. For example, in an L2P page, update the physical block address corresponding to LUA a01, update the physical block address corresponding to LUA a09, and update the physical block address corresponding to LUA a03.

[0080] Once all nodes in the L2P linked list have been processed, the controller can write the updated L2P page from the cache back to non-volatile storage. Then, the above steps are repeated until all L2P pages corresponding to all L2P linked lists have been updated, at which point the L2P mapping table update is considered complete.

[0081] In this application, for the sake of brevity, the logical unit address of the node is used to represent the node; that is, the logical unit address of the node is used to represent the node, thereby constructing the L2P linked list; however, in reality, the nodes in the L2P linked list include the mapping relationship from physical block address to logical unit address.

[0082] In some embodiments, the aforementioned acquisition of L2P page index matching results for each node returned by the hardware matching engine includes: Receive the L2P page index matching results obtained by the hardware matching engine based on the L2P page index array, which is matched item by item by the L2P page index; The L2P page index of a node is obtained by the hardware matching engine through a shift operation on the logical unit address of the node based on the size of the L2P page.

[0083] In this embodiment, when the controller executes step S120, it receives the L2P page index matching result returned by the hardware matching engine. The controller receives the L2P page index matching result obtained by the hardware matching engine through item-by-item matching of the L2P page index array. The L2P page index of a node is obtained by the hardware matching engine through a shift operation on the logical unit address of the node based on the size of the L2P page.

[0084] The hardware matching engine is configured to: extract the logical unit address of the input node, perform a shift operation on the logical unit address based on the preset L2P page size to obtain the L2P page index value, and use the obtained L2P page index value to perform matching in the L2P page index array.

[0085] In a preferred embodiment, the hardware matching engine is configured to: receive the logical unit addresses of one or more nodes input by the controller, wherein a node is a mapping relationship from any physical block address to a logical unit address in the P2L mapping table to be matched; extract the logical unit addresses of the nodes, perform a shift operation on the logical unit addresses of each node based on the size of the L2P page, and obtain the L2P page index of each node; match the L2P page index of each node item by item in the L2P page index array to obtain the L2P page index matching result of each node; and return the L2P page index matching result of each node to the controller.

[0086] In this embodiment, the hardware matching engine can receive the logical unit addresses of one or more nodes input by the controller. Here, a node represents the mapping relationship between any physical block address and logical unit address in the P2L mapping table to be matched.

[0087] After receiving the logical unit addresses of one or more nodes, the hardware matching engine can extract the logical unit addresses of the nodes and, based on the size of the L2P page, perform a shift operation on the logical unit addresses of each node to obtain the L2P page index of each node. The size of the L2P page is a predefined fixed value, such as 4KB (kilobyte), 8KB, or 16KB. The essence of the shift operation is to remove the low-order bits of the "internal offset" in the logical unit address and retain the high-order bits of the "page index".

[0088] For example: If the size of an L2P page is 4KB (1KB = 1024 = 2KB), then... 10If 4KB = 2¹², then each L2P page contains 4096 logical unit addresses. A shift operation right-shifts the logical unit address by 12 bits to obtain the L2P page index. The result of the shift operation, 0, is defined as L2P Index a, the result of the shift operation, 1, is defined as L2P Index b, and so on.

[0089] If the logical unit address is LUA a01=0x0000_0123, LUA a09=0x0000_0F88, LUA a03=0x0000_0567, LUA b03=0x0001_0ABC. Thus: the logical unit address of node LUA a01 is 0x0000_0123, and the result after shifting is 0, which means the L2P page index is L2P Index a; the logical unit address of node LUA a09 is 0x0000_0F88, and the result after shifting is 0, which means the L2P page index is L2P Index a; the logical unit address of node LUA a03 is 0x0000_0567, and the result after shifting is 0, which means the L2P page index is L2P Index a; the logical unit address of node LUA b03 is 0x0001_0ABC, and the result after shifting is 1, which means the L2 page index is L2P Index b.

[0090] After obtaining the L2P page indexes of each node, the hardware matching engine can match each node's L2P page index item by item in the preset L2P page index array to obtain the L2P page index matching results for each node. The L2P page index array is created and maintained by the controller in the cache, and the hardware matching engine reads and matches from the cache.

[0091] After obtaining the L2P page index matching results for each node, the L2P page index matching results for each node can be returned to the controller.

[0092] In some embodiments, the L2P page index matching result obtained by the aforementioned receiving hardware matching engine based on the L2P page index array through item-by-item matching includes: Receive the failed L2P page index matching result generated when the hardware matching engine does not find a matching L2P page index; or, Receives the successfully matched L2P page index matching result generated when the hardware matching engine matches the same L2P page index.

[0093] In this embodiment, the L2P page index matching result received by the controller includes either a failed match or a successful match. The controller receives a failed L2P page index matching result generated when the hardware matching engine fails to find a matching L2P page index; or, the controller receives a successful L2P page index matching result generated when the hardware matching engine finds a matching L2P page index. The successful L2P page index matching result includes a target offset address. The target offset address refers to the offset address of the L2P page index that is the same as the node's L2P page index within the L2P page index array.

[0094] In a preferred embodiment, for any node's L2P page index, the hardware matching engine traverses and matches item by item from the beginning of the L2P page index array and determines whether the element at the current traversal position is an invalid value. If it is not an invalid value, then check if the element at the current traversal position is consistent with the L2P page index of the node; if it is consistent, then the target offset address in the L2P page index array containing the L2P page index of the node is successfully matched; if it is inconsistent, continue to traverse the next element and repeat the step of checking if the element at the current traversal position is invalid. If the value is invalid, the matching is terminated and an L2P page index containing the node is generated. Matches not found in the L2P page index array fail.

[0095] In this embodiment, for any node's L2P page index, the hardware matching engine can traverse and match item by item starting from the beginning of the L2P page index array, and determine whether the element at the current traversal position is an invalid value.

[0096] If the element at the current traversal position is not invalid, the hardware matching engine needs to further determine whether the element at the current traversal position is consistent with the node's L2P page index. If they are consistent, the target offset address containing the node's L2P page index in the L2P page index array can be successfully matched. If they are inconsistent, it is necessary to continue traversing the next element and repeat the step of determining whether the element at the current traversal position is invalid.

[0097] If the element at the current traversal position is invalid, the hardware matching engine can terminate the matching and generate an L2P page index containing the node. Matches that are not found in the L2P page index array have failed.

[0098] Specifically, based on Tables 1, 3, and 6 above, the process by which the hardware matching engine matches the L2P page index of each node item by item in the L2P page index array to obtain the L2P page index matching results for each node is explained: If the L2P page index of node LUA a01 is L2P Index a, the L2P page index of node LUA a09 is L2PIndex a, the L2P page index of node LUA a03 is L2P Index a, the L2P page index of node LUA b03 is L2P Index b, and the L2P page index of node LUA b07 is L2P Index b.

[0099] Assuming the hardware matching engine first processes node LUA a01, it iterates through Table 1 based on L2P Index a. At this point, the hardware matching engine starts its iteration from the starting position (Offset 0) in Table 1 (the starting position is the current iteration position). The hardware matching engine can then determine that the element at the current iteration position is invalid. At this point, the matching can be terminated, and a match failure message containing the node's L2P page index not found in the L2P page index array is generated. This match failure message is then returned to the controller. After processing by the controller, Table 3 is obtained.

[0100] Next, node LUA a09 is processed. Based on L2P Index a, Table 3 is traversed. At this point, the hardware matching engine begins traversing each item from the starting position (Offset 0) in Table 3 (the starting position is now the current traversal position). The hardware matching engine can then determine that the element at the current traversal position is not an invalid value. Then, it can determine whether the element at the current traversal position (L2P Index a) matches the node's L2P page index (L2P Index a). Based on Table 3, it is clear that they match. At this point, the hardware matching engine generates a successful match for the target offset address (Offset 0) of the node's L2P page index in the L2P page index array. Similarly, the processing of node LUA a03 is also performed in the same way, and will not be elaborated further here.

[0101] Then, node LUA b03 is processed. Based on L2P Index b, Table 3 is traversed. At this point, the hardware matching engine begins traversing item by item from the starting position (Offset 0) in Table 3 (the starting position is the current traversal position). The hardware matching engine can then determine that the element at the current traversal position is not an invalid value. It then checks whether the element at the current traversal position (L2P Index a) matches the node's L2P page index (L2P Index b). Based on Table 3, it is clear that they are inconsistent. Therefore, the engine can continue traversing the next element, but the next element is invalid. At this point, the matching is terminated, and a failure to match is generated, containing the node's L2P page index not found in the L2P page index array. This failure is then returned to the controller. After processing by the controller, Table 6 is obtained.

[0102] Next, node LUA b07 is processed. Based on L2P Index b, Table 6 above is traversed. At this point, the hardware matching engine starts traversing item by item from the starting position (Offset 0) in Table 6 (at this moment, the starting position is the current traversal position). The hardware matching engine can determine that the element at the current traversal position is not an invalid value. Then, it can determine whether the element at the current traversal position (L2P Index a) is consistent with the node's L2P page index (L2P Index b). Based on Table 6, it can be seen that they are inconsistent. At this point, the next element can be traversed. The next element is L2P Index b, which is consistent. At this point, the hardware matching engine generates a target offset address (Offset 1) containing the node's L2P page index in the L2P page index array, indicating a successful match.

[0103] The technical solution of this application matches all nodes belonging to the same L2P page in the P2L mapping table to be matched into an L2P linked list. In this way, when updating the L2P mapping table, each L2P page can be updated sequentially according to each L2P linked list, avoiding the inefficient mode of multiple traversals. Furthermore, the parallel matching mechanism of the hardware matching engine is used to achieve high-speed matching in the chain building process, thereby improving the update efficiency of the L2P mapping table.

[0104] This application further proposes a storage device, referring to... Figure 9 , Figure 9 This is a schematic diagram of the structure of a storage device according to an embodiment of the present application. In some embodiments, the storage device includes a storage controller, a hardware matching engine, and a flash memory chip; the storage device is capable of executing the chaining method of the L2P linked list in the storage controller described above.

[0105] In this embodiment, as Figure 9 As shown, the storage device includes a storage controller, a hardware matching engine, and flash memory chips. The storage controller is connected to both the hardware matching engine and the flash memory chips, and is used to implement data read / write control, address mapping management, and data interaction scheduling. The hardware matching engine is a hardware acceleration module used for parallel matching and index calculation of address information. The flash memory chips are used for non-volatile storage of data, L2P mapping tables, and P2L mapping tables.

[0106] When responding to a write operation from the host computer, the storage controller collects the updated nodes in the P2L mapping table to form a P2L mapping table to be matched, and inputs each node in the P2L mapping table to the hardware matching engine. The hardware matching engine performs a shift operation on the logical unit address of each node to obtain the L2P page index corresponding to each node, and performs item-by-item matching in the L2P page index array, outputting the L2P page index matching result for each node. Based on the L2P page index matching result, the storage controller categorizes nodes with the same L2P page index into L2P linked lists, and constructs multiple L2P linked lists for multiple different L2P page indices. The storage controller further performs batch updates on the L2P pages to be updated according to each L2P linked list, and writes the updated L2P pages back to the storage area to complete the update of the L2P mapping table.

[0107] The L2P page index array, L2P chain head array, and L2P chain tail array are all stored in the cache area. The hardware matching engine can also directly access them and perform fast matching operations, thereby achieving efficient construction of the L2P linked list and improving the update speed of the mapping table and the overall write performance of flash memory.

[0108] The above description is only a part or preferred embodiment of this application. Neither the text nor the drawings should limit the scope of protection of this application. All equivalent structural transformations made using the content of this application's specification and drawings under the overall concept of this application, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A method for establishing an L2P linked list in a storage controller, characterized in that, include: Read the P2L mapping table to be matched; Input each node in the P2L mapping table to be matched into the hardware matching engine; Obtain the L2P page index matching results of each node returned by the hardware matching engine; Multiple L2P linked lists are constructed based on the L2P page index matching results, wherein each L2P linked list includes all nodes belonging to the same L2P page; Update the corresponding L2P page in the L2P mapping table according to each of the L2P linked lists.

2. The method for establishing an L2P linked list in a storage controller according to claim 1, characterized in that, Before inputting each node in the P2L mapping table to be matched into the hardware matching engine, the following steps are also included: Construct an L2P page index array, an L2P chain head array, and an L2P chain tail array, wherein the L2P page index array is used to store the L2P page index values ​​to be matched, and the L2P chain head array and L2P chain tail array are used to manage the linked list nodes by offset address indexing. Then initialize all elements of the L2P page index array, L2P chain head array, and L2P chain tail array to invalid values.

3. The method for establishing an L2P linked list in a storage controller according to claim 2, characterized in that, Before constructing the L2P page index array, L2P chain head array, and L2P chain tail array, the following steps are also included: Determine the number of nodes in the P2L mapping table to be matched; Based on the number of nodes, create the L2P page index array, L2P chain head array, and L2P chain tail array, wherein the space of the L2P page index array, L2P chain head array, and L2P chain tail array is greater than or equal to the number of nodes.

4. The method for establishing an L2P linked list in a storage controller according to claim 2, characterized in that, The step of inputting each node in the P2L mapping table to be matched into the hardware matching engine includes: One or more nodes to be processed are obtained in batches from the P2L mapping table to be matched, forming the current batch of nodes; The logical unit addresses of each node in the current processing batch node set are concurrently input into the hardware matching engine for matching.

5. The method for establishing an L2P linked list in a storage controller according to claim 4, characterized in that, After obtaining the L2P page index matching results of each node returned by the hardware matching engine, the process also includes: Determine whether there are any unprocessed nodes in the P2L mapping table to be matched; If there are unprocessed nodes in the P2L mapping table to be matched, then return to the step of retrieving one or more nodes to be processed in batches from the P2L mapping table to be matched, forming the current batch of nodes; If there are no unprocessed nodes in the P2L mapping table to be matched, then the L2P page index matching result of all nodes in the P2L mapping table to be matched is confirmed.

6. The method for establishing an L2P linked list in a storage controller according to claim 5, characterized in that, The step of constructing multiple L2P linked lists based on the L2P page index matching results includes: Iterate through each node in the current batch of nodes; For the current node being processed, determine whether the L2P page index matching result of the current node is a match failure; If the L2P page index matching result is a failure, the first element marked as invalid in the L2P page index array is located as the new offset address, and the L2P page index of the current node is written to the location. The newly added L2P index will be used for matching in the next matching. The current node is used as the head and tail of the new L2P linked list, and the element values ​​at the corresponding index positions in the L2P head array and the L2P tail array are updated to the address of the current node based on the new offset address.

7. The method for establishing an L2P linked list in a storage controller according to claim 6, characterized in that, After determining whether the L2P page index matching result of the current node is a match failure, the process also includes: If the L2P page index matching result is a successful match, then obtain the matched target offset address; Based on the target offset address, query the L2P chain head array and the L2P chain tail array to determine the target L2P linked list corresponding to the target offset address; The node is appended to the tail of the target L2P linked list, and the element value corresponding to the target offset address in the L2P tail array is updated to the address of the current node based on the target offset address.

8. The method for establishing an L2P linked list in a storage controller according to claim 7, characterized in that, The step of updating the corresponding L2P page in the L2P mapping table according to each of the L2P linked lists includes: The L2P linked lists are selected sequentially, and the L2P pages corresponding to the L2P linked lists are loaded from the non-volatile storage medium into the cache area; Traverse each node in the L2P linked list and update the physical block address corresponding to the logical unit address in the L2P page in batches; After all nodes in the L2P linked list have been processed, the updated L2P page is written back from the cache to the non-volatile storage medium. Repeat the above steps until all L2P pages corresponding to all L2P linked lists have been updated, then the L2P mapping table update is complete.

9. The method for establishing an L2P linked list in a storage controller according to any one of claims 2-8, characterized in that, The process of obtaining the L2P page index matching results for each node returned by the hardware matching engine includes: Receive the L2P page index matching results obtained by the hardware matching engine based on the L2P page index array, matching each item of the L2P page index; The L2P page index of the node is obtained by the hardware matching engine through a shift operation on the logical unit address of the node based on the size of the L2P page.

10. The method for establishing an L2P linked list in a storage controller according to claim 9, characterized in that, The L2P page index matching results obtained by the receiving hardware matching engine based on the L2P page index array are as follows: Receive the L2P page index matching result that failed to match when the hardware matching engine did not find a matching L2P page index; or, Receive the L2P page index matching result generated when the hardware matching engine matches the same L2P page index.

11. A storage device, characterized in that, The storage device includes a storage controller, a hardware matching engine, and a flash memory chip; the storage device is capable of executing the chaining method of the L2P linked list in the storage controller according to any one of claims 1 to 10.

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