Cache coherency interconnect method, cache coherency node, and multiprocessor system

Abstract

The application discloses a cache consistency interconnection method, a cache consistency node and a multi-processor system, relates to the field of computers, aims at the problem of large hardware resource consumption and insufficient flexibility of a traditional cache consistency interconnection module, and provides a cache consistency interconnection method: when a memory access request needing to be monitored is received, the memory access request is parsed to determine a source identifier; the source identifier is a unique identifier corresponding to a source processor of a memory access request sender; a monitoring address frame carrying the source identifier and corresponding to the memory access request is generated, and the monitoring address frame is sent to other processors through an interconnection module; and after monitoring data payload returned in response is received, the memory access request is completed according to the monitoring data payload. The method can get rid of the dependence on a complex structure such as a directory, can realize the cache consistency function by using less hardware resources, and can realize decoupling between the cache consistency function and the interconnection structure, so that the application of the cache consistency function is more flexible.

Description

Technical Field

[0001] This invention relates to the field of computers, and in particular to a cache coherent interconnect method, a cache coherent node, and a multiprocessor system. Background Technology

[0002] A processor system can be simplified as a processor (CPU), peripherals, interconnect modules, and memory (DDR). For example... Figure 1 As shown. In practice, the processor initiates a bus request, and the interconnect module, based on the system's address mapping, sends configuration, operation information, and data access requests to the corresponding peripherals and memory controllers to achieve functional control and data updates. In a multiprocessor architecture, the existence of private caches necessitates maintaining cache data consistency between processors.

[0003] To address cache data consistency issues, most multiprocessor systems currently rely on cache coherent interconnect modules for their interconnects, such as the Cache Coherent Interconnect (CCI) and Coherent Mesh Network (CMN) in ARM (a processor architecture). These cache coherent interconnect modules typically contain complex directory and snoop structures to manage and track the state of all processor caches. Their design is complex, incurs significant hardware resource overhead, and is tightly coupled with the interconnect structure. This is particularly problematic for lightweight RISC-V (an instruction set architecture) systems, where they cannot be flexibly adapted to different application scenarios, leading to inconvenience in application.

[0004] Therefore, those skilled in the art urgently need a cache coherence interconnect method to solve the problems of high hardware resource overhead and insufficient flexibility of traditional cache coherence interconnect modules. Summary of the Invention

[0005] The purpose of this invention is to provide a cache coherence interconnect method, a cache coherence node, and a multiprocessor system to solve the problems of high hardware resource overhead and insufficient flexibility of traditional cache coherence interconnect modules.

[0006] To address the aforementioned technical problems, this invention provides a cache coherence interconnect method applied to a cache coherence node; wherein the cache coherence node is an independent node in a processor system; in the processor system, the interconnect module is connected to the memory through the cache coherence node.

[0007] The method includes: upon receiving a memory access request that needs to be monitored, parsing the memory access request to determine a source identifier; wherein the source identifier is a unique identifier corresponding to the source processor that is the issuer of the memory access request; generating a monitoring address frame carrying the source identifier and corresponding to the memory access request, and sending the monitoring address frame to other processors besides the source processor through the interconnect module; and after receiving the monitoring data payload returned in response, completing the memory access request according to the monitoring data payload.

[0008] In one optional embodiment, the step of completing the memory access request based on the listening data payload after receiving the response includes: if the memory access request is a write request, then integrating the listening data payload returned by the response with the write data carried in the memory access request, and completing the write operation according to the write address of the write request; if the memory access request is a read request, then returning the listening data payload returned by the response as the read data of the read request.

[0009] In an optional embodiment, the memory access request is transmitted in the form of an AXI Consistency Extension Protocol frame. The method further includes: encapsulating request data transmitted via the write address path, write data path, read address path, listener response path, and listener data path into groups in parallel; storing the encapsulated data groups in corresponding cache areas and releasing the interface cache resources of the corresponding paths; wherein the cache areas include: a write address cache area, a write data cache area, a read address cache area, and a listener feedback cache area; the write address cache area corresponds to the write address path, the write data cache area corresponds to the write data path, the read address cache area corresponds to the read address path, and the listener feedback cache area corresponds to the listener response path and the listener data path; when any of the cache areas is not empty, the request data is read from each of the non-empty cache areas in parallel for processing.

[0010] In an optional embodiment, when processing the request data in each of the caches in parallel, if a conflict occurs between different memory access requests, the processing order of the conflicting memory access requests is determined according to a processing priority rule; wherein, the processing priority rule includes: when a read request that needs to be monitored and a write request that needs to be monitored conflict, the write request is processed first.

[0011] In an optional embodiment, the method further includes: upon receiving a memory access request that does not require monitoring, performing a corresponding write or read operation on the memory based on the memory access request.

[0012] In an optional embodiment, the processing priority rule further includes: when there is a conflict between memory access requests that need to be monitored and memory access requests that do not need to be monitored, the memory access requests that need to be monitored are processed first.

[0013] In an optional embodiment, when a conflict arises between a memory access request that needs to be monitored and a memory access request that does not need to be monitored, prioritizing the processing of the memory access request that needs to be monitored includes: if the memory access request that does not need to be monitored is a write request, and the write data of the write request is being transferred in the cache, the memory access request that needs to be monitored should be executed only after the write data transfer is completed.

[0014] In an optional embodiment, the processing priority rule further includes: when memory access requests of the same transaction type conflict, the multiple conflicting memory access requests are merged into one memory access request and processed; if they cannot be merged, they are processed according to the order in which they are received.

[0015] In one alternative embodiment, the buffer is a first-in-first-out buffer.

[0016] In an optional embodiment, before the steps of encapsulating the request data received by the parallel write address path, write data path, read address path, and listener response path / listener data path into groups, storing the encapsulated data groups in the corresponding cache areas, and releasing the interface cache resources of the corresponding paths are completed, the method further includes: determining whether the status bit of the cache consistency function is set to the enabled state; if yes, then proceeding to the steps of encapsulating the request data received by the parallel write address path, write data path, read address path, and listener response path / listener data path into groups, storing the encapsulated data groups in the corresponding cache areas, and releasing the interface cache resources of the corresponding paths; if no, then directly performing the corresponding write operation or read operation on the memory after receiving the memory access request.

[0017] In one optional embodiment, the source identifier of the memory access request is determined based on the interface number corresponding to the interface used by the interconnect module to receive the memory access request.

[0018] In an optional embodiment, upon receiving the memory access request, the method further includes: parsing the memory access request; determining the monitoring transaction type of the memory access request based on the monitoring signal, domain signal, and barrier signal in the memory access request; and determining whether the memory access request is a write request or a read request, and whether monitoring is required or not, based on the monitoring transaction type.

[0019] To address the aforementioned technical problems, this invention also provides a cache consistency node, comprising: a write path control module, a read path control module, a listening control module, a write memory control module, and a read memory control module; the write path control module is connected to the listening control module and the write memory control module; the write path control module is configured to: receive a write request and determine whether the write request needs to be listened to; the read path control module is connected to the listening control module and the read memory control module; the read path control module is configured to: receive a read request and determine whether the read request needs to be listened to; the listening control module is configured to: upon receiving a memory access request that needs to be listened to, parse the memory access request to determine a source identifier; wherein, the source identifier is a unique identifier corresponding to the source processor that issues the memory access request; generate a listening address frame carrying the source identifier and corresponding to the memory access request, and send the listening address frame to other processors besides the source processor through the interconnect module; and upon receiving the listening data payload returned in response, complete the memory access request according to the listening data payload.

[0020] In an optional embodiment, the system further includes: a protocol frame encapsulation cache module; the protocol frame encapsulation cache module is connected to the interconnect module, the write path control module, and the read path control module; the protocol frame encapsulation cache module is used to: receive request data transmitted in parallel from the write address path, write data path, read address path, listener response path, and listener data path, encapsulate them into groups respectively, store them in the corresponding cache areas, and release the interface cache resources of the corresponding paths; wherein, the cache areas include: a write address cache area, a write data cache area, a read address cache area, and a listener feedback cache area; the write address cache area corresponds to the write address path, the write data cache area corresponds to the write data path, the read address cache area corresponds to the read address path, and the listener feedback cache area corresponds to the listener response path and the listener data path.

[0021] To address the aforementioned technical problems, the present invention also provides a multiprocessor system, comprising: multiple processor systems; wherein each of the multiple processor systems includes: a processor, a connection module, a peripheral device, and a memory; the connection module is respectively connected to the processor, the peripheral device, and the memory; the connection modules of each processor system are interconnected; at least one processor system further includes: a cache coherence node as described above; the connection module in this processor system is connected to the memory through the cache coherence node.

[0022] In one alternative embodiment, each of the processor systems includes the cache coherence node.

[0023] This invention provides a cache-coherent interconnect method applied to a cache-coherent node (LCN). The memory access request is extended with a source identifier that uniquely identifies the source processor that issued the request. This allows the LCN in any processor system to determine the originator of the memory access request upon receiving it. Furthermore, if monitoring is required, the request can be sent to other processors besides the source processor for processing, and the memory access request is completed based on the returned listening data payload (CD data), ensuring cache consistency across multiple processors. Therefore, the cache consistency function implemented based on this method identifies the originator of the memory access request based on the source identifier, thus eliminating dependence on complex structures such as directories. It achieves cache consistency with fewer hardware resources and avoids the strong coupling problem between the directory structure and the interconnect structure. Regardless of whether any processor is added or removed from the interconnect structure, as long as the processor has a unique source identifier, it can be accurately identified, thereby achieving cache consistency with other processors through this method. Moreover, this method is implemented based on an LCN that is independent of the original components in the processor system. Based on this setting, regardless of the specific interconnect structure of the multiprocessor system, as long as LCN is set in the processor system that needs to apply cache coherency, cache coherency between the current processor and other processors can be achieved. This further ensures the decoupling between cache coherency and the interconnect structure, making the application of cache coherency more flexible.

[0024] The cache coherence node and multiprocessor system provided by this invention correspond to the above method and have the same effect. Attached Figure Description

[0025] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a structural diagram of a processor system;

[0027] Figure 2 A structural diagram of a multiprocessor system provided in an embodiment of the present invention;

[0028] Figure 3 A flowchart of a cache coherence interconnection method provided in an embodiment of the present invention;

[0029] Figure 4 A structural diagram of a cache consistency node provided in an embodiment of the present invention;

[0030] Figure 5A flowchart of another cache coherence interconnection method provided in an embodiment of the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0032] The core of this invention is to provide a cache coherence interconnect method, a cache coherence node, and a multiprocessor system.

[0033] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1 As shown, a processor system can be simplified as a processor (such as a CPU), peripherals, interconnect modules, and memory (such as DDR). A multiprocessor system can be viewed as a single processor system containing multiple processors, or as a collection of multiple single-processor systems (each with only one processor). In particular, in a multiprocessor architecture, the existence of private caches necessitates maintaining cache data consistency between processors.

[0035] To address the consistency issues of cached data between processors, current solutions largely rely on cache coherent interconnect modules (CCIs) for data exchange. Common CCIs include the Cache Coherent Interconnect (CCI) and Coherent Mesh Network (CMN) for ARM (a processor architecture). These CCIs contain complex directory and snoop structures to manage and track the state of all processor caches. However, these CCIs are complex in design, consume significant hardware resources, and are tightly coupled to the interconnect structure (the directory configuration depends on the interconnect structure). This makes them particularly inconvenient for lightweight RISC-V (an instruction set architecture) systems, as they cannot be flexibly adapted to different application scenarios.

[0036] To address the aforementioned problems, this invention provides a cache consistency interconnection method applied to cache consistency nodes. Wherein, for example... Figure 2As shown, a cache coherent node (LCN) is an independent node in the processor system. Within the processor system, the interconnect module connects to memory through the cache coherent node.

[0037] The procedure is as follows: Figure 3 As shown, the process includes: S11: Upon receiving a memory access request that needs to be monitored, the memory access request is parsed to determine the source identifier. The source identifier is a unique identifier corresponding to the source processor that issued the memory access request. S12: A monitoring address frame carrying the source identifier and corresponding to the memory access request is generated, and the monitoring address frame is sent to other processors besides the source processor via the interconnect module. S13: After receiving the monitoring data payload returned in the response, the memory access request is completed based on the monitoring data payload.

[0038] In step S11, the memory access request is the memory access request issued by the processor, including read requests and write requests. Since the LCN is located between the interconnect module and the memory, and is the necessary path for the processor to access the memory, the LCN can receive the memory access requests issued by the processor. As for the format of the memory access request, existing communication protocols can be used, and this embodiment does not limit it. Specifically, in the cache coherence scenario targeted by this invention, many cache coherence protocols can be used, including but not limited to: ACE (AXI Coherency Extensions; AXI, Advanced eXtensible Interface), MESI (M: Modified; E: Exclusive; S: Shared; I: Invalid), etc.

[0039] Based on the aforementioned cache consistency protocol, memory access requests carry corresponding signal flags to indicate whether the request is for direct memory access or requires a snooping request. Specifically, the snooping type of the memory access request can be determined based on signals such as snoop, domain, and bar signals (the specific signal flags may vary depending on the protocol used; this example uses protocols such as ACE mentioned above as representatives), thus determining whether snooping is required.

[0040] Based on the above, this embodiment also provides a further adapted embodiment. When a memory access request is received, the method further includes: S141: parsing the memory access request and determining the monitoring transaction type of the memory access request based on the monitoring signal, domain signal, and barrier signal in the memory access request. S142: determining whether the memory access request is a write request or a read request, and whether monitoring is required or not, based on the monitoring transaction type.

[0041] In this embodiment, by reusing existing cache consistency protocols (such as ACE, MESI, etc.), memory access requests can be parsed based on the existing protocol format to determine whether they need to be monitored, thus laying the foundation for subsequent steps in this method to ensure cache consistency. This embodiment reuses existing protocols, eliminating the need for manual writing or extension of the memory access protocol format, and can be directly applied to most cache consistency scenarios, reducing the application threshold and implementation difficulty.

[0042] Furthermore, the source identifier (source ID) in the memory access request is a unique identifier used to identify the source processor (i.e., the processor that issued the memory access request). The generation rules for the source identifier can be set arbitrarily, as long as the source identifier corresponding to each processor is unique; this embodiment does not impose any restrictions on this. Moreover, this embodiment does not restrict where the source identifier is generated, as long as it is generated before the current LCN that receives the memory access request. For example, the generator of the source identifier can be at least the source processor itself, and the interconnect module connected to the current LCN, etc. (If the source processor and the current LCN do not belong to the same processor system, it can also include the interconnect module in the processor system where the source processor resides).

[0043] In one optional embodiment, the source ID is generated as follows: the source identifier of the memory access request is determined based on the interface number corresponding to the interface used by the interconnect module to receive the memory access request. It is readily known that interconnect modules (processor systems) are generally interconnected via wired communication. One interconnect module communicates with other different interconnect modules through different lines, with different lines connected to different interfaces of the interconnect module. Each interface of an interconnect module also has a unique interface number (ID), which meets the above requirements for the source ID. Therefore, the interface ID of the interface used by the interconnect module when receiving the memory access request can be used as the source ID. This ensures both the uniqueness of the source ID and allows the interconnect module to mark the source identifier in the memory access request, guaranteeing the successful implementation of the cache consistency function of this method. The entire scheme is logically simple and easy to implement.

[0044] Step S12 involves adding the source ID carried in the memory access request to the AC frame, based on the original cache coherency protocol's procedure of generating a listening address frame (AC frame) based on a memory access request. (Cache coherency protocols such as ACE and MESI support the extension and customization of AC frame content, allowing the addition of a source ID.) The AC frame carrying the source ID is then forwarded to any processor other than the source processor for execution. If the source processor is not a processor belonging to the same processor system as the current LCN, it can be forwarded to a processor belonging to the same processor system as the current LCN to improve processing efficiency. However, it can also be forwarded to a processor of a different processor system; this embodiment does not impose such restrictions. The purpose of this step is to eliminate the dependency on the directory structure to process listening requests, thereby achieving cache coherency.

[0045] Step S13 involves forwarding the listening request to a processor other than the source processor, receiving the listening data payload (SD data) returned by that processor, and executing the corresponding memory access request (read or write) on the memory currently connected to the LCN. This process is also part of the existing cache coherence protocols, and this embodiment does not impose any restrictions on it.

[0046] As explained above, memory access requests involve monitoring requirements, mainly including read requests and write requests that need to be monitored. Therefore, this embodiment also provides an optional specific implementation scheme for read and write requests that need to be monitored. Step S13 above further includes: S13-A: If the memory access request is a write request, the monitoring data payload returned in the response is integrated with the write data carried in the memory access request, and the write operation is completed according to the write address of the write request. S13-B: If the memory access request is a read request, the monitoring data payload returned in the response is returned as the read data of the read request.

[0047] It's important to note that the processing flow for write and read requests that require monitoring is similar to that of regular write and read requests. The only difference is that the data being read or written needs to consider the processing of SD data by processors other than the source processor after monitoring. For write requests, the original write data is supplemented with the SD data returned by the monitoring process to form the final write data used for the write operation. For read requests, the SD data returned by the monitoring process is returned to the request initiator as the read request response (i.e., the read data mentioned above).

[0048] In summary, the core improvements made in this invention are twofold: First, there is a methodological improvement, specifically by carrying a unique source ID corresponding to the source processor in the memory access request. This allows any processor system's LCN, upon receiving this memory access request, to forward it to other processors for processing to meet the monitoring requirements. Then, based on the monitored SD data processed by other processors, a memory access request is made to the corresponding memory (the memory directly connected to the current LCN) to achieve cache consistency between the source processor and the current processor system. When extended to the entire multiprocessor system, cache consistency between the source processor and other processors can be achieved. Second, there is a hardware structural improvement. The above method is applied to an independent node in the processor system, namely the LCN, which implements the cache consistency function. Therefore, in practical applications, when any processor system needs to apply cache consistency, only an LCN needs to be added, supporting the addition of any number of processor systems or processors, making implementation very flexible.

[0049] In other words, this invention uniquely identifies the initiator of a memory access request based on the source ID and forwards the AC frame of this memory access request to other processors for processing, thereby ensuring cache consistency among processors. Using the source ID eliminates the need for a complex directory structure, simplifying the entire solution and avoiding strong coupling between the directory structure and the interconnect structure. Based on this, this method can be implemented using an LCN independent of the interconnect structure. For any interconnect structure, cache consistency can be achieved simply by setting up an LCN in the processor system requiring cache consistency functionality. The implementation of this solution is extremely flexible and particularly suitable for lightweight RISC-V (a processor architecture) systems.

[0050] On the other hand, besides memory access requests with monitoring requirements, LCN also supports processing memory access requests that do not require consistency maintenance. Read and write operations can be performed directly on the memory according to the normal memory access process. Accordingly, this embodiment provides an optional implementation scheme, in which the above method further includes: S2: When a memory access request that does not require monitoring is received, the corresponding write or read operation is directly performed on the memory according to the memory access request.

[0051] It should be noted that the LCN is positioned between the interconnect module and the memory, and inherently possesses the capability to receive memory access requests issued by the processor through the interconnect module, and to perform read or write operations on the directly connected memory based on these requests. Therefore, the process of how the LCN handles memory access requests can be referenced from the current general memory access request processing flow, and will not be elaborated upon in this embodiment.

[0052] Regarding how to distinguish whether a memory access request received by LCN needs to be listened to, the above embodiments have already illustrated, using the ACE protocol as an example, that the Snoop type can be identified by parsing signals such as Snoop, Domain, and Bar in the memory access request, thereby determining whether the request needs to be listened to. That is, when applying an existing cache consistency protocol, the identification of whether a memory access request needs to be listened to can be achieved using the existing cache consistency protocol standards and specifications, without the need for additional settings.

[0053] Furthermore, as described above, the LCN node provided by this invention can support processing memory access requests that do not require consistency maintenance. Considering that in a possible application scenario, memory access requests may not require consistency maintenance at all, even if the method provided in the above embodiments is used for judgment, additional resources and time are required, which is not conducive to efficient request processing. Therefore, this embodiment provides a further implementation scheme. The above method further includes: S0: determining whether the status bit of the cache consistency function is set to the enabled state; if yes, it is necessary to determine whether the memory access request needs to be monitored, and proceed to the corresponding step S11 or step S2 according to the judgment result; if no, directly proceed to step S2, and process the memory access request as a normal request that does not require monitoring.

[0054] In other words, the method described in this embodiment supports on / off control of cache consistency functionality, implemented based on consistency status bits. When cache consistency is enabled, the normal process flow provided in the above embodiment determines whether memory access requests need to be monitored before proceeding to the corresponding processing flow. When cache consistency is disabled, the determination process of whether monitoring is required is skipped, and memory access requests that do not require consistency maintenance are processed directly, improving processing efficiency.

[0055] On the other hand, the above has clearly stated that the present invention includes improvements in both software and hardware. Regarding the software process, the main improvement lies in carrying a unique source ID corresponding to the source processor in the memory access request. This allows any processor system's LCN to forward this memory access request to other processors for processing when it receives it. The memory access request is then completed based on the monitored SD data processed by other processors, thus achieving cache consistency. Other steps such as data parsing, processing, and forwarding can be implemented using existing cache consistency protocols, such as ACE and MESI protocols as described above. To better illustrate the cache consistency interconnection method provided by the present invention, the following embodiments use the ACE protocol as an example to provide further implementation schemes. However, it should be understood that the same principle applies when using other protocols such as MESI, and the present invention will not elaborate further.

[0056] For example, this embodiment provides an optional implementation: memory access requests are transmitted in the form of AXI Consistency Extended Protocol frames. The method further includes: S31: Encapsulating request data transmitted through the write address path, write data path, read address path, listen response path, and listen data path into groups in parallel. S32: Storing the encapsulated data groups in the corresponding cache areas and releasing the interface cache resources of the corresponding paths.

[0057] The listener response (CR) path (also called the channel) and the listener data (CD) path can share the same path (CR / CD path) or share a buffer. The write address (AW) path, write data (W) path, and read address (AR) path are generally independent paths, each with its own independent buffer. Therefore, the aforementioned buffers can include: a write address buffer, a write data buffer, a read address buffer, and a listener feedback buffer. Specifically, the write address buffer corresponds to the write address path, the write data buffer corresponds to the write data path, the read address buffer corresponds to the read address path, and the listener feedback buffer corresponds to the listener response path and the listener data path.

[0058] S33: When any cache is not empty, the requested data is read from each non-empty cache in parallel for processing.

[0059] In this embodiment, corresponding buffers are set up for all data paths involved in the ACE protocol to cache received data. Based on this, the LCN used to execute this method can cache data transmitted from any path in the corresponding buffer upon receipt, quickly achieving bus handshake and releasing bus permissions, thus enabling fast data reception. Furthermore, to facilitate rapid data processing, this embodiment encapsulates the data from each path into independent data groups within the LCN. Each data group is processed immediately without additional waiting time, minimizing data processing latency. Further, after caching the corresponding data in the buffers, this embodiment can achieve parallel processing by reading data from different paths from the buffers, thereby achieving rapid data processing. Based on this embodiment, rapid data reception and processing by the LCN can be achieved, thereby minimizing data processing latency.

[0060] Furthermore, the above embodiments provide a scheme for enabling or disabling cache consistency functionality, and another embodiment provides an implementation scheme for encapsulating data into groups. In conjunction with these two embodiments, this embodiment also provides an implementation scheme for combined application. Before step S31, the above method further includes: S30: determining whether the status bit of the cache consistency function is set to the enabled state; if not, then directly performing the corresponding write or read operation on the memory after receiving a memory access request; if yes, then proceeding to step S31.

[0061] Furthermore, when applying the previous embodiment, multiple different memory access requests can be processed simultaneously. However, in practical applications, if multiple memory access requests access the same cache line address, address conflicts may occur. To address this problem, this embodiment provides a suitable solution: when processing request data in each cache in parallel, if conflicts occur between different memory access requests, the processing order of the conflicting memory access requests is determined according to processing priority rules.

[0062] Furthermore, this embodiment also provides an optional implementation scheme for the aforementioned processing priority rules. The aforementioned processing priority rules include: when a conflict arises between read requests and write requests that need to be monitored, write requests are processed first.

[0063] It should be clarified that the read-then-write priority processing order given in this embodiment is only an optional scheme. Its purpose is to clarify the processing order of read and write requests when conflicts occur between read and write requests during the parallel processing of multiple memory access requests, thereby resolving the conflict problem. The specific processing order is relatively unimportant. In another optional embodiment, a read-then-write priority processing rule can also be adopted, and this invention does not limit this.

[0064] As described above, this embodiment proposes a clear conflict handling process. When read and write requests conflict, the priority handling rule of prioritizing write transactions clarifies the processing order among the conflicting requests, thereby ensuring normal and efficient processing of requests.

[0065] On the other hand, the above embodiments also provide a processing scheme for memory access requests that do not require monitoring. That is, the cache consistency interconnect method provided by this invention supports the processing of both monitored and unmonitored memory access requests. Similarly, when these two types of memory access requests conflict during parallel processing, this embodiment also provides a corresponding implementation scheme. The above-mentioned processing priority rule also includes: when a conflict arises between a memory access request that requires monitoring and a memory access request that does not require monitoring, the memory access request that requires monitoring is processed first. In other words, this embodiment provides a processing order that prioritizes monitoring requests when they conflict with ordinary requests, thereby resolving the conflict between monitoring requests and ordinary requests.

[0066] Furthermore, regarding the priority handling rules provided for listening requests and normal requests in the above embodiments, this embodiment also provides a further optional implementation. The aforementioned priority rule of prioritizing the listening memory access request when a conflict arises between a memory access request that needs to be listened to and a memory access request that does not need to be listened to, specifically: if the memory access request that does not need to be listened to is a write request, and the write data for the write request is being transferred to the cache, the listening memory access request must wait until the write data transfer is complete before execution. This embodiment addresses a special case where a conflict arises between listening requests and normal requests, namely, a normal request is a write request, and the write data is being transferred to the write data cache. In this scenario, if the listening request is prioritized and the write data transfer process is stopped, it may lead to the loss of write data, which in turn may prevent the subsequent normal write request from proceeding normally. To solve this problem, this embodiment specifically sets a priority handling rule. That is, in the above situation, even a listening request must wait for the write data transfer to complete, and then it can be processed according to the priority order of processing listening requests first and normal requests later, to ensure orderly and efficient processing among multiple memory access requests.

[0067] Furthermore, this embodiment also provides an optional priority processing rule from another perspective. The aforementioned priority processing rule further includes: when memory access requests of the same transaction type conflict, the multiple conflicting memory access requests are merged into one memory access request and processed; if they cannot be merged, they are processed according to the order in which they are received.

[0068] The aforementioned "same transaction type" can refer to two requests being either read or write requests, and both requests either requiring listening or not requiring listening. Furthermore, it's possible that the cache consistency protocol may support more transaction types (or listening types).

[0069] For request merging, one option is to merge the target data. For example, if two write requests involve overlapping data, they can be merged. Specifically, this could be because one write request completely contains the data from another, or the identical data in the two write requests reaches a certain proportion, making merged writes more efficient than separate writes. The same principle applies to read requests, primarily merging the read data. However, considering that the request doesn't actually contain the read data itself, but rather the cache line address to be read, merging read requests often involves merging the target cache line address, combining multiple data reads into a single read.

[0070] Furthermore, if requests of the same type cannot be merged (e.g., due to failure to meet preset merging conditions or merging failure), they are processed in the order they were received. In the embodiment described above, which uses a cached data buffer, data for requests of the same type are cached in the same buffer. Moreover, in practical applications, the possibility of multiple memory access requests of the same type arriving simultaneously is negligible. That is, it can be assumed that requests of the same type have a specific order of arrival. Based on this, this embodiment specifically provides an optional processing priority rule that processes memory access requests according to the order in which they are received, thereby resolving the problem of multiple request conflicts.

[0071] Furthermore, the priority processing rule based on the order in which memory access requests are received, as provided in the previous embodiment, can be implemented by setting corresponding software logic. However, this embodiment also provides an optional hardware implementation: a first-in-first-out (FIFO) cache. As described in the previous embodiment, data for requests of the same type are cached in the same cache, and it can be assumed that requests of the same type must have an order of arrival. Therefore, in order to implement the priority processing rule based on the order in which memory access requests are received, the data in the cache must be "first-in, first-out," which is the characteristic of a FIFO cache. Thus, this embodiment uses FIFO as the aforementioned cache, and the above-mentioned priority processing rule can be implemented in hardware without setting additional corresponding software logic.

[0072] Furthermore, it should be noted that, in addition to the priority processing rules given in the above embodiments, other corresponding priority processing rules can be added based on other needs in practical applications, and this embodiment does not impose any restrictions on this. As long as there is no conflict between the priority processing rules, multiple priority processing rules can be implemented together; for example, the priority processing rules provided in the above embodiments can be implemented together.

[0073] In the above embodiments, a cache consistency interconnection method has been described in detail. The present invention also provides an embodiment corresponding to a cache consistency node (LCN). Figure 4 As shown, the cache consistency node provided by the present invention includes: a write path control module 11, a read path control module 12, a listener control module 13, a write memory control module 14, and a read memory control module 15.

[0074] The write path control module 11 is connected to the listening control module 13 and the write memory control module 14. The write path control module 11 is used to receive write requests and determine whether listening is required for the write request. The read path control module 12 is connected to the listening control module 13 and the read memory control module 15; the read path control module 12 is used to receive read requests and determine whether listening is required for the read request.

[0075] The monitoring control module 12 is used to: when receiving a memory access request that needs to be monitored, parse the memory access request to determine the source identifier; wherein, the source identifier is a unique identifier corresponding to the source processor that is the sender of the memory access request; generate a monitoring address frame carrying the source identifier and corresponding to the memory access request, and send the monitoring address frame to other processors other than the source processor through the interconnect module; and complete the memory access request according to the monitoring data payload after receiving the monitoring data payload returned in the response.

[0076] The specific process for handling memory access requests has been explained in the above method implementation section, referring to the normal memory read or write process. That is, the write memory control module and the read memory control module are functional modules used to complete the corresponding memory access processing based on the allocated read and write requests.

[0077] Furthermore, corresponding to the embodiments of the above method section, this embodiment also provides a corresponding embodiment on the LCN side, such as... Figure 4 As shown, the LCN also includes a protocol frame encapsulation buffer module 16. The protocol frame encapsulation buffer module 16 is connected to the interconnect module (which serves as the input of the LCN and receives memory access requests sent by the interconnect module), the write path control module 11, and the read path control module 12.

[0078] The protocol frame encapsulation and caching module 16 is used to: receive request data transmitted in parallel from the write address path, write data path, read address path, listener response path, and listener data path, encapsulate them into groups, and store them in the corresponding cache areas, releasing the interface cache resources of the corresponding paths. The cache areas include: a write address cache area, a write data cache area, a read address cache area, and a listener feedback cache area; the write address cache area corresponds to the write address path, the write data cache area corresponds to the write data path, the read address cache area corresponds to the read address path, and the listener feedback cache area corresponds to the listener response path and the listener data path.

[0079] Since the embodiments of the cache consistency node part correspond to the embodiments of the cache consistency interconnect method part, please refer to the description of the embodiments of the cache consistency interconnect method part for the embodiments of the cache consistency node part, which will not be repeated here. This embodiment further explains the overall cache consistency processing flow based on the embodiments of the above-mentioned method part.

[0080] like Figure 5 As shown, the LCN provided in this embodiment supports different functional configurations. Depending on application requirements, the cache size of each channel, the extended ID of the processor, and the real-time enabling and disabling of consistency functions can be set. According to the ACE protocol, LCN supports parallel data path processing. When cache consistency is disabled, memory access processes for read and write requests can be performed directly, reducing memory access latency. When cache consistency is enabled, write address (AW), write data (W), read address (AR), and listener response (CR / CD) path data can be cached in parallel, quickly achieving bus handshake and releasing bus permissions. To facilitate rapid data processing, the data of each path within LCN is uniformly encapsulated into independent data groups. Each group of data is processed instantly without additional waiting time, minimizing data processing latency.

[0081] Subsequently, if the memory read / write process is a normal memory access process, the memory data read / write and response feedback are quickly completed based on whether the requested data exists in the read / write request cache. When there is an address conflict in the read / write request, the read request can be responded to quickly, or it can be handled in a write-then-read mode. When the consistency function is enabled (i.e., the cache consistency function status bit is enabled) and each cache area is not empty, LCN parses the data of each path in parallel, and determines its Snoop type based on the snoop, domain, and barrier signals in the read / write request.

[0082] When a Snoop operation is needed, the encapsulated read / write request information, extended with a Snoop transaction identifier, is transferred to the corresponding cache and the interface cache resources are released. Data in the cache is processed sequentially normally; when read / write requests conflict, write transactions are processed first. When processing listener requests, the CacheLine address is first calculated based on the read / write request address. Then, based on the Snoop transaction type and the request frame ID, corresponding AC frame information is generated and broadcast or directed. An additional ID signal (i.e., source identifier) ​​is added to the AC path of the ACE protocol, allowing the AC frame to carry the source ID. General interconnect modules and RISC-V processors that support the ACE protocol's AC frame extension can complete protocol frame routing and response return based on the extended source ID, thereby maintaining cache consistency. After the AC frame is sent, a response is awaited. The presence of listener response (CR) frames is used to determine if there is a listener response. Read / write requests without a listener response can quickly proceed with memory access, releasing Snoop process permissions. For write requests with a listener response, the returned CD data and the actual write data are integrated based on the write address and data validity signal, and the write request operation is quickly completed according to the write memory process. For read requests with a listener response, the CD return information can be matched based on the read address to quickly respond with read data return, reducing read data latency. At the same time, the CD data is updated in memory according to the normal write memory control process. When there is a conflict between the Snoop process and normal memory accesses, the Snoop process takes priority. However, if write data is being cached and transferred, it is necessary to wait for the transfer to complete.

[0083] When no Snoop operation is needed, it checks if there is an ongoing Snoop process and whether the requested address belongs to the Snoop CacheLine address. If so, it waits for the Snoop operation to complete before processing; otherwise, it can process in parallel to quickly complete the memory access operation. Specifically, for write requests, write response channel information (i.e., B channel information) must be returned after writing data. For read requests, read data channel information (i.e., R channel information) must be returned after reading data.

[0084] As described above, the read, write, and listen processing flow of the LCN provided in this embodiment is interdependent yet relatively decoupled. Efficiency is improved through parallel execution, while sequential execution ensures data accuracy in case of conflicts. It supports cache consistency data maintenance for lightweight multi-processor nodes, has a simple interface, minimal resource overhead, and is easy to expand and maintain.

[0085] Furthermore, the present invention also provides a multiprocessor system, such as Figure 2 As shown, it includes multiple processor systems ( Figure 2Taking two single-processor systems as an example (in reality, the number is unlimited; a single processor system can also include multiple processors), each processor system includes: a processor, a connectivity module, peripherals, and memory. The connectivity module is connected to the processor, peripherals, and memory, respectively. The connectivity modules of each processor system are interconnected. At least one processor system also includes a cache coherence node as described in any of the above embodiments. The connectivity module in this processor system is connected to the memory through the cache coherence node.

[0086] It should be noted that the above embodiments have explicitly stated that LCN needs to be added in processor systems that only require cache coherency functionality. That is, for processor systems in multi-processor systems that do not require cache coherency functionality, LCN can be omitted, making the deployment and implementation of the entire cache coherency function more flexible. However, this embodiment also provides an optional implementation scheme for a specific scenario: such as... Figure 2 As shown, each processor system includes a cache coherence node. In this embodiment, all processor systems include an LCN and support cache coherence functionality, representing a multiprocessor system architecture with optimal cache data consistency.

[0087] The cache coherence interconnect method, cache coherence node, and multiprocessor system provided by this invention have been described in detail above. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

[0088] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A cache coherence interconnection method, characterized in that, It is applied to a cache coherence node; wherein the cache coherence node is an independent node in a processor system; in the processor system, the interconnect module is connected to the memory through the cache coherence node; The methods include: Upon receiving a memory access request that needs to be monitored, the memory access request is parsed to determine the source identifier; wherein, the source identifier is a unique identifier corresponding to the source processor that issued the memory access request; Generate a listening address frame carrying the source identifier and corresponding to the memory access request, and send the listening address frame to other processors other than the source processor through the interconnect module; Upon receiving the listening data payload returned in the response, the memory access request is completed based on the listening data payload.

2. The cache coherence interconnection method according to claim 1, characterized in that, The step of completing the memory access request based on the listening data payload after receiving the response includes: If the memory access request is a write request, the listening data payload returned in the response is integrated with the write data carried in the memory access request, and the write operation is completed according to the write address of the write request. If the memory access request is a read request, the listening data payload returned in the response will be returned as the read data for the read request.

3. The cache coherence interconnection method according to claim 1, characterized in that, The memory access request is transmitted in the form of an AXI Consistency Extended Protocol frame; The method also includes: Parallel processing encapsulates the request data transmitted through the write address path, write data path, read address path, listen response path, and listen data path into groups respectively. The encapsulated data group is stored in the corresponding cache area, and the interface cache resources of the corresponding path are released; wherein, the cache area includes: write address cache area, write data cache area, read address cache area and listener feedback cache area; the write address cache area corresponds to the write address path, the write data cache area corresponds to the write data path, the read address cache area corresponds to the read address path, and the listener feedback cache area corresponds to the listener response path and the listener data path; When any of the caches is not empty, the request data is read from each of the non-empty caches in parallel for processing.

4. The cache coherence interconnection method according to claim 3, characterized in that, When processing request data in each of the caches in parallel, if a conflict occurs between different memory access requests, the processing order of the conflicting memory access requests is determined according to the processing priority rule. The processing priority rule includes: when there is a conflict between read requests and write requests that need to be monitored, write requests are processed first.

5. The cache coherence interconnection method according to claim 4, characterized in that, Also includes: When a memory access request that does not require monitoring is received, the corresponding write or read operation is performed directly on the memory according to the memory access request.

6. The cache coherence interconnection method according to claim 5, characterized in that, The processing priority rules also include: When there is a conflict between memory access requests that need to be monitored and memory access requests that do not need to be monitored, the memory access requests that need to be monitored should be processed first.

7. The cache coherence interconnection method according to claim 6, characterized in that, When a conflict arises between memory access requests that need to be monitored and memory access requests that do not need to be monitored, the priority given to handling the memory access requests that need to be monitored includes: If the memory access request that does not need to be monitored is a write request, and the write data of the write request is being transferred to the cache, the memory access request that needs to be monitored should be executed only after the write data has been transferred.

8. The cache coherence interconnection method according to claim 7, characterized in that, The processing priority rules also include: When memory access requests of the same transaction type conflict, the multiple conflicting memory access requests are merged into one memory access request and processed. If they cannot be merged, they will be processed according to the order in which the memory access requests are received.

9. The cache coherence interconnection method according to claim 8, characterized in that, The buffer is a first-in-first-out (FIFO) buffer.

10. The cache coherence interconnection method according to claim 3, characterized in that, Before the parallel encapsulation of request data received by the write address path, write data path, read address path, and listener response path / listener data path into groups, storing the encapsulated data groups in the corresponding cache areas, and releasing the interface cache resources of the corresponding paths, the process further includes: Determine whether the status bit of the cache consistency feature is set to enabled; If so, proceed to the steps of encapsulating the request data received by the parallel write address path, write data path, read address path, and listen response path / listen data path into groups, storing the encapsulated data groups in the corresponding cache area, and releasing the interface cache resources of the corresponding path. If not, the corresponding write or read operation will be performed directly on the memory upon receiving a memory access request.

11. The cache coherence interconnection method according to any one of claims 1 to 10, characterized in that, The source identifier of the memory access request is determined based on the interface number corresponding to the interface used by the interconnect module to receive the memory access request.

12. The cache coherence interconnection method according to any one of claims 1 to 10, characterized in that, Upon receiving the memory access request, the following is also included: The memory access request is parsed, and the monitoring transaction type of the memory access request is determined based on the monitoring signals, domain signals, and barrier signals in the memory access request; The type of the monitored transaction determines whether the memory access request is a write request or a read request, and whether it needs to be monitored or not.

13. A cache consistency node, characterized in that, include: Write path control module, read path control module, listening control module, write memory control module, and read memory control module; The write path control module is connected to the listening control module and the write memory control module; the write path control module is used to: receive write requests and determine whether the write request needs to be listened to. The read path control module is connected to the monitoring control module and the read memory control module; the read path control module is used to: receive read requests and determine whether the read request needs to be monitored; The monitoring control module is configured to: upon receiving a memory access request that needs to be monitored, parse the memory access request to determine a source identifier; wherein the source identifier is a unique identifier corresponding to the source processor that issued the memory access request; generate a monitoring address frame carrying the source identifier and corresponding to the memory access request, and send the monitoring address frame to other processors besides the source processor through the interconnect module; and complete the memory access request based on the monitoring data payload after receiving the monitoring data payload returned in response.

14. The cache consistency node according to claim 13, characterized in that, Also includes: Protocol frame encapsulation buffer module; The protocol frame encapsulation and buffer module is connected to the interconnect module, the write path control module, and the read path control module; The protocol frame encapsulation and caching module is used to: receive request data transmitted by the write address path, write data path, read address path, listen response path and listen data path in parallel, encapsulate them into groups and store them in the corresponding cache area, and release the interface cache resources of the corresponding path. The cache area includes: a write address cache area, a write data cache area, a read address cache area, and a listener feedback cache area; the write address cache area corresponds to the write address path, the write data cache area corresponds to the write data path, the read address cache area corresponds to the read address path, and the listener feedback cache area corresponds to the listener response path and the listener data path.

15. A multiprocessor system, characterized in that, include: Multiple processor systems; Each of the aforementioned processor systems includes: a processor, a connection module, peripherals, and a memory; the connection module is connected to the processor, the peripherals, and the memory, respectively. The connection modules of each of the processor systems are interconnected; At least one of the processor systems further includes: a cache coherence node as described in claim 13 or 14; the connectivity module in the processor system is connected to the memory via the cache coherence node.

16. The multiprocessor system according to claim 15, characterized in that, Each of the aforementioned processor systems includes the cache coherence node.

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