Generation method and device of unified power format (UPF) file, equipment and medium

Abstract

The invention relates to the technical field of chip design, and particularly provides a generation method and device of a unified power format (UPF) file, equipment and a medium. The method comprises the following steps: determining a function module identifier under an instance corresponding to a system-level power supply according to a first corresponding relation and a second corresponding relation of a chip; wherein the first corresponding relationship comprises a corresponding relationship between the instance and the system-level power supply, and the second corresponding relationship comprises a corresponding relationship between the instance and each functional module; acquiring UPF information of the corresponding function module based on the function module identifier; and generating a UPF file of the chip based on the UPF information. By adopting the method, the UPF file generation efficiency of the chip can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, in particular to a generation method, device and equipment of a unified power format (UPF) file and a medium. BACKGROUND

[0002] In modern chip design, with the continuous increase of chip size and the increasing strictness of power consumption requirements, the unified power format (UPF) file as a standard format file for describing the chip power intention is increasingly important.

[0003] The traditional UPF file generation method mainly relies on manual writing, which is low in efficiency and seriously affects the progress of chip design. SUMMARY

[0004] Therefore, it is necessary to provide a generation method, device and equipment of a unified power format (UPF) file capable of improving the UPF file generation efficiency of a chip and a medium.

[0005] In a first aspect, the present application provides a generation method of a unified power format (UPF) file, comprising: determining a function module identifier under an instance corresponding to a system-level power according to a first correspondence relationship and a second correspondence relationship of a chip; wherein the first correspondence relationship comprises a correspondence relationship between an instance and a system-level power, and the second correspondence relationship comprises a correspondence relationship between an instance and each function module; obtaining UPF information of a corresponding function module based on the function module identifier; and generating a UPF file of the chip based on the UPF information.

[0006] In one embodiment, the generating the UPF file of the chip based on the UPF information comprises: determining a first mapping relationship, a second mapping relationship, a third mapping relationship and a fourth mapping relationship based on the UPF information; and generating the UPF file of the chip based on the first mapping relationship, the second mapping relationship, the third mapping relationship and the fourth mapping relationship; wherein the first mapping relationship reflects a correspondence relationship between a system-level power identifier of the chip and system-level power pin information; the second mapping relationship reflects a correspondence relationship between a module-level power identifier of the chip and module-level power pin information; the third mapping relationship reflects a correspondence relationship between state information corresponding to the module-level power identifier of the chip and state information corresponding to the system-level power identifier; and the fourth mapping relationship reflects a correspondence relationship between the module-level power identifier of the chip and voltage information.

[0007] In one of the embodiments, the determining the first mapping relationship based on the UPF information comprises: obtaining, from the UPF information, a system-level power supply pin identifier corresponding to a system-level power supply identifier of a system-level power supply; determining a system-level power supply pin address name of the first instance according to a first instance identifier of the first instance corresponding to the function module identifier and the system-level power supply pin identifier; and generating the first mapping relationship according to the system-level power supply identifier and the system-level power supply pin address name of the first instance.

[0008] In one of the embodiments, the determining the second mapping relationship based on the UPF information comprises: obtaining, from the UPF information, a first module-level power supply identifier corresponding to any target function module; determining a second module-level power supply identifier of the chip according to a target function module identifier of the target function module and the first module-level power supply identifier; determining a module-level power supply pin address name of a second instance corresponding to the target function module identifier according to a second instance identifier of the second instance and the first module-level power supply identifier; and generating the second mapping relationship according to the second module-level power supply identifier and the module-level power supply pin address name of the second instance.

[0009] In one of the embodiments, the determining the third mapping relationship based on the UPF information comprises: obtaining first state information corresponding to a system-level power supply identifier of a system-level power supply and second state information corresponding to a target power supply identifier of a target power supply in the system-level power supply, the target power supply being configured to supply power to a control module of the chip; obtaining, from the UPF information, third state information corresponding to the target power supply identifier and fourth state information corresponding to a third module-level power supply identifier, the third module-level power supply identifier being an identifier of a function module corresponding to the third state information; the first state information, the second state information, the third state information and the fourth state information being configured to represent working states and output voltages of power supplies; in a case where the second state information is consistent with the third state information, determining a fourth module-level power supply identifier of the chip according to the function module identifier and the third module-level power supply identifier, and establishing a corresponding relationship between the fourth module-level power supply identifier and the fourth state information; and generating the third mapping relationship according to the fourth state information and the first state information.

[0010] In one of the embodiments, the determining the fourth mapping relationship based on the UPF information comprises: obtaining, from the UPF information, a first module-level power supply identifier corresponding to any target function module and voltage information corresponding to the first module-level power supply identifier; determining a second module-level power supply identifier of the chip according to a target function module identifier of the target function module and the first module-level power supply identifier; and generating the fourth mapping relationship according to the second module-level power supply identifier and the voltage information.

[0011] In one of the embodiments, the generating the UPF file of the chip based on the UPF information comprises: obtaining a fifth mapping relationship reflecting a correspondence between a system-level power supply identifier of the chip and a preset voltage range; obtaining input-output pin power supply information of the chip; and generating the UPF file of the chip based on the UPF information, the fifth mapping relationship and the input-output pin power supply information.

[0012] In one of the embodiments, the method further comprises: before the step of generating the UPF file of the chip based on the UPF information, the method further comprises: obtaining voltage information of a first system-level power supply from the UPF information; the first system-level power supply is any power supply in the plurality of system-level power supplies; obtaining preset voltage information of the first system-level power supply; in a case where the voltage information of the first system-level power supply matches the preset voltage information, generating the UPF file of the chip based on the UPF information; in a case where the voltage information of the first system-level power supply does not match the preset voltage information, outputting indication information; and in a case where the UPF information is modified, obtaining modified UPF information, and generating the UPF file of the chip based on the modified UPF information; wherein the indication information is used to indicate that the voltage information of the first system-level power supply in the UPF information is modified.

[0013] In one of the embodiments, the determining the function module identifier under the instance corresponding to the system-level power supply according to the first correspondence relationship and the second correspondence relationship of the chip comprises: determining an instance identifier corresponding to each system-level power supply of the chip according to the first correspondence relationship; and determining a function module identifier corresponding to the instance identifier of each system-level power supply according to the second correspondence relationship.

[0014] In a second aspect, the application further provides a generation device of a unified power format (UPF) file, comprising:

[0015] The first determining module is configured to determine the function module identifier under the instance corresponding to the system-level power supply according to the first correspondence relationship and the second correspondence relationship of the chip, wherein the first correspondence relationship comprises a correspondence relationship between the instance and the system-level power supply, and the second correspondence relationship comprises a correspondence relationship between the instance and each function module.

[0016] The first obtaining module is configured to obtain the UPF information of the corresponding function module based on the function module identifier.

[0017] The first generating module is configured to generate the UPF file of the chip based on the UPF information.

[0018] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the method provided in the first aspect of the present application when executing the computer program.

[0019] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method provided in the first aspect of the present application.

[0020] In a fifth aspect, the present application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to implement the method provided in the first aspect of the present application.

[0021] The above method, device, computer device, computer readable storage medium and computer program product for generating a unified power format (UPF) file can determine the function module identifier under the instance corresponding to the system-level power supply according to the first correspondence relationship and the second correspondence relationship of the chip, wherein the first correspondence relationship comprises a correspondence relationship between the instance and the system-level power supply, and the second correspondence relationship comprises a correspondence relationship between the instance and each function module; obtain the UPF information of the corresponding function module based on the function module identifier; and generate the UPF file of the chip based on the UPF information. The embodiments of the present application can not only automatically generate the UPF file of the whole chip, but also generate the UPF file of the chip by combining the UPF information of the function module of the chip, that is, by using a bottom-up manner to combine the whole chip (the top layer of the chip) and the function module of the bottom layer of the chip, so as to generate the UPF file of the whole chip, thereby improving the generation efficiency of the UPF file of the chip. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application or the related art. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0023] Figure 1 The application environment diagram of the generation method of the unified power format UPF file in one embodiment;

[0024] Figure 2 The flowchart of the generation method of the unified power format UPF file in one embodiment;

[0025] Figure 3 The flowchart of the step 203 in one embodiment; Figure 2 The flowchart of the step 203 in one embodiment;

[0026] Figure 4 The flowchart of the step 301 in one embodiment; Figure 3 The flowchart of the step 301 in one embodiment;

[0027] Figure 5 The flowchart of the step 301 in one embodiment; Figure 3 The flowchart of the step 301 in one embodiment;

[0028] Figure 6 The flowchart of the step 301 in one embodiment; Figure 3 The flowchart of the step 301 in one embodiment;

[0029] Figure 7 The flowchart of the step 301 in one embodiment; Figure 3 The flowchart of the step 301 in one embodiment;

[0030] Figure 8 The flowchart of the step 203 in another embodiment; Figure 2 The flowchart of the step 203 in another embodiment;

[0031] Figure 9 The power connection diagram of each instance of the chip in one example;

[0032] Figure 10 The flowchart of the generation method of the UPF file of the chip in one specific example;

[0033] Figure 11 The structural block diagram of the generation device of the unified power format UPF file in one embodiment;

[0034] Figure 12 The internal structure diagram of the computer device in one embodiment. DETAILED DESCRIPTION

[0035] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0036] It should be noted that the terms "first", "second", and the like used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "multiple" used in the present application refers to two or more. The term "and / or" used in the present application refers to one of the options or any combination of multiple options.

[0037] In the related art, when generating a unified power format (UPF) file of a chip, either a UPF file of a single (bottom) functional module of the chip is generated, or a UPF file of the entire chip (top) is generated, and the UPF file is not generated by combining the bottom layer and the single bottom layer functional module as a system. The disadvantage of this way is that if the UPF file of the top layer of the chip is to be generated, the low-power consumption scheme of the entire project needs to be understood in detail to generate the UPF file of the top layer, and the functional modules of the top layer and the bottom layer are separated. If different modules come from different design teams, there is a high possibility of conflicts between modules and between modules and the top layer. Therefore, the related art has the following disadvantages in generating the UPF file of the chip: a top-down generation method is used, and the top layer and the modules are separated, either the UPF file of the top layer is generated or the UPF file of a certain module is generated, which is low in efficiency. Therefore, the related art still has the disadvantage of low efficiency in automatically generating the UPF file of the chip.

[0038] Therefore, the embodiments of the present application propose a generation method of a unified power format UPF file, which adopts a bottom-up generation method, combines the top layer and the module, and generates the UPF file of the top layer required by the entire chip by complementing each other and unifying the two. The disadvantages of generating the UPF file of the top layer and the module separately are solved, and the efficiency of generation is greatly improved.

[0039] The generation method of the unified power format UPF file provided by the embodiments of the present application can be applied to, for example Figure 1The application environment shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data required by the server 104 to process. The data storage system can be integrated on the server 104, or placed on the cloud or other network servers. Among them, the terminal 102 can be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, unmanned aerial vehicles, low-altitude aircraft, Internet of Things devices and portable wearable devices. The server 104 can be a standalone physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0040] In an exemplary embodiment, as shown, a method for generating a unified power format (UPF) file is provided. The method is applied to the server 104 in Figure 2 Figure 1 for example, including the following steps 201 to 203. Among them:

[0041] Step 201, according to the first correspondence and the second correspondence of the chip, the function module identifier under the instance corresponding to the system-level power supply is determined.

[0042] Among them, the function module identifier is the unique identifier of the function module of the chip. The function module refers to the tile inside the chip that has a specific function and is physically indivisible. Each function module has its own UPF information, and each function module is integrated on the top layer of the chip through at least one instantiation. Each function module may include, for example, a display output module (dptx), a communication module (usb), a graphics module (gpu), and a clock module (gpu_crg), etc. The display output module is used for display output, the communication module is used for USB communication, the graphics module is used for graphics computation, and the clock module is used for clock generation. The system-level power supply refers to the global power supply for the entire chip or the main functional area in the chip, which is the main part of the chip power architecture and can also be called the main power supply. The number of system-level power supplies is at least one. In contrast to the system-level power supply, the module-level power supply refers to the power supply inside the function module other than the system-level power supply.

[0043] ​Each function module corresponds to at least one instance, the first corresponding relationship includes the corresponding relationship between the instance and the system-level power supply, and the second corresponding relationship includes the corresponding relationship between the instance and each function module. The first corresponding relationship and the second corresponding relationship are set by a chip designer in advance according to actual needs. Optionally, the corresponding relationship specifically includes the corresponding relationship between the identifiers, for example, the first corresponding relationship includes the corresponding relationship between the instance identifier and the system-level power supply identifier, and the second corresponding relationship includes the corresponding relationship between the instance identifier and each function module identifier, wherein the instance identifier refers to the unique identifier of the instance, and the system-level power supply identifier refers to the unique identifier of the system-level power supply.

[0044] Exemplarily, first, the first corresponding relationship and the second corresponding relationship of the chip can be obtained from the database of each delivery node of the chip design. Then, according to the corresponding relationship between the instance and the system-level power supply in the first corresponding relationship, the instance corresponding to each system-level power supply is determined, and according to the instance and the corresponding relationship between the instance and each function module in the second corresponding relationship, the function module identifier under the instance is determined, so as to obtain the function module identifier under the instance corresponding to the system-level power supply.

[0045] Optionally, the division information of the system-level power supply of the whole chip is obtained from the database of the delivery node of the chip design, that is, the first corresponding relationship is obtained. Taking the system-level power supply including VDD_SOC, VDD_GPU and VDD_L, and each function module including a display output module (dptx), a communication module (usb), a graphics module (gpu), an interface module (vdci_gpu) connected to the gpu module, an interface module (vdci_sm) connected to the system management module and a clock module (gpu_crg) as an example, the file name of the first corresponding relationship can be main_power_domain.partition, and the format and content are as follows:

[0046] top:{VDD_SOC}

[0047] u_dptx:{VDD_SOC}

[0048] u_usb:{VDD_SOC}

[0049] u_vdci_gpu:{VDD_SOC,VDD_GPU}

[0050] u_gpu:{VDD_GPU}

[0051] u_vdci_sm:{VDD_L,VDD_GPU}

[0052] u0_gpu_crg:{VDD_L}

[0053] u1_gpu_crg: {VDD_L}.

[0054] Wherein, top represents the whole chip (chip top layer), u_dptx, u_usb, u_vdci_gpu, u_gpu, u_vdci_sm, u0_gpu_crg and u1_gpu_crg respectively represent: instance identifier of dptx module, instance identifier of usb module, instance identifier of vdci_gpu module, instance identifier of gpu module, instance identifier of vdci_sm module, first instance identifier of gpu_crg module and second instance identifier of gpu_crg module. Wherein, the gpu_crg module is instantiated twice at the chip top layer to obtain two instances, so there are two instance identifiers. Top: {VDD_SOC} represents that the default power supply of the chip top layer is VDD_SOC, u_vdci_gpu: {VDD_SOC, VDD_GPU} represents that the system-level power supply of instance u_vdci_gpu is VDD_SOC and VDD_GPU respectively, and the like.

[0055] Optionally, the corresponding relationship between the instances of each functional module of the whole chip at the top layer and the functional modules in the database of the delivery node of the chip design is obtained, that is, the second corresponding relationship is obtained. In the above example, the file name of the second corresponding relationship can be tile_instance.map.yaml, and the format and content are as follows:

[0056] u_dptx: dptx

[0057] u_usb: usb

[0058] u_vdci_gpu: vdci_gpu

[0059] u_gpu: gpu

[0060] u_vdci_sm: vdci_sm

[0061] u0_gpu_crg: gpu_crg

[0062] u1_gpu_crg: gpu_crg.

[0063] Wherein, u_dptx: dptx represents that the instance identifier u_dptx corresponds to the functional module identifier dptx, u_usb: usb represents that the instance identifier u_usb corresponds to the functional module identifier usb, and the like.

[0064] In step 202, the UPF information of the corresponding functional module is obtained based on the functional module identifier.

[0065] Each function module identifier corresponds to a function module, and each function module has independent UPF information, which is information required for generating a UPF file of the function module. The UPF information can include the identifier of the function module to which the UPF information belongs, and therefore, the UPF information of the corresponding function module can be found from a database storing the UPF information according to the function module identifier. The UPF information is designed in advance based on a low-power supply domain division architecture and whether each function module contains an IP (intellectual property core) or not. The UPF information of each function module includes power domain information, power definition information, hard core IP power connection information, power state information, and input and output pin power information. The power domain information includes the identifier (such as the name) of each power domain, the main power supply and the main ground, and the contained design instance. The power definition information covers the name of all power supplies and the voltage range. The hard core IP power connection information records the correspondence between the power supply identifier (such as the power supply name) and the internal hard core IP power pin address name. The power state information describes the state of each power supply in various working scenarios. The input and output pin power information relates to the power handling strategy of the chip input and output pins.

[0066] Optionally, the UPF information can be in the form of a table, and each function module corresponds to one UPF table information. Taking the usb module (a function module with a module identifier or a module name of usb) as an example, the name of the corresponding UPF table information is usb_ss.power_table.xlsx, and the table includes a power domain information table, a power definition information table, a hard core IP power connection information table, a power state information table, and an input and output pin power information table. The details are as follows:

[0067] The power domain information table is shown in Table 1: The table contains the division of the power domains in the usb module, the default power supply of each power domain, and the corresponding power ground. VDD_SOC_PD refers to the default power domain, and VDD_SOC_SW_PD refers to the switchable power domain. VDD_SOC_SW_PD only corresponds to an instance with an identifier of u_dptx_pg, and u_dptx_pg corresponds to the VDD_SOC_SW power supply and the power ground VSS.

[0068] Table 1: Power domain information table

[0069]

[0070] The power definition information table is shown in Table 2: The table contains all the power supply information of the usb module, including the power supply identifier (such as the power supply name), the power supply voltage (including the minimum voltage, the standard voltage, and the maximum voltage), and the power ground:

[0071] Table 2: Power definition information table

[0072]

[0073] In which all the standard voltage of system-level power supply is split into minimum voltage and maximum voltage. For example, the standard voltage of VDD_SOC is 0.75V, which is split into minimum voltage: 0.675V and maximum voltage: 0.825V.

[0074] The hard-core IP power connection information table is shown in Table 3: the table contains the correspondence between the power supply identification (such as power supply name) of the usb module and the power pin address name of the internal hard-core IP instance, in which u_usb_pg / u_usb_phy / VDD represents the VDD pin of the sub-instance u_usb_phy under the instance with the instance identification u_usb_pg, which is connected to the power supply VDD_SOC_SW.

[0075] Table 3 Hard-core IP power connection information table

[0076]

[0077] The power state information table is shown in Table 4: the table contains the power-on and power-off scenario information between all the power supplies inside the usb module, in which VDD_SOC_PD refers to the power domain associated with the state identification, in the state identification ALL_OFF state, all the power supplies are in the off state; in the state identification SLEEP_H state, only the power supply VDD_SOC operates at the maximum voltage (HON), and other power supplies are in the off state; in the state identification ALL_ON_H state, all the power supplies are turned on, the power supplies VDD_SOC and VDD_SOC_SW operate at the maximum voltage, and the power supplies USB_AVDD1P18 and USB_AVDD1P18 operate at the standard voltage (SON).

[0078] Table 4 Power state information table

[0079]

[0080] In which HON represents the maximum voltage state, LON represents the minimum voltage state, and SON represents the standard voltage state, so that HON, SON and LON are corresponded to the voltage, realizing the correspondence between the voltage and the power state.

[0081] The input and output pin power information table is shown in Table 5: the table contains the power supply information of the input and output pins of the usb module, first defines the pins and their types corresponding to the default power supply of the top-level power domain, and then defines a small number of pins and their types corresponding to the power supply different from the default power supply, greatly reducing the number of pins.

[0082] Table 5 Input and output pin power information table

[0083]

[0084] All the above tables contain the UPF information of the usb module, and the designers of the functional modules use the above tables as templates to fill in the tables according to the situation of each functional module, and then parse the information stored in the tables of each functional module into a hash data structure through a corresponding script for the system to query when generating the UPF file of the chip.

[0085] Exemplarily, after obtaining the functional module identifier, the UPF table information of the corresponding functional module is obtained from the chip design database (located at the delivery node) according to the functional module identifier, and each UPF table information can come from different design teams, and then the UPF information is obtained. The UPF information includes the system-level power supply (such as the system-level power supply VDD_SOC recorded in the UPF table information of the usb module) and the module-level power supply (such as the module-level power supply USB_AVDD1P18 and USB_AVDD1P12 recorded in the UPF table information of the usb module), and the power supply pin information, state information and voltage information corresponding to the system-level power supply and the module-level power supply, etc., wherein the state information is used to represent the working state (such as high-voltage state, low-voltage state, etc.) and output voltage of the power supply.

[0086] Step 203, generating the UPF file of the chip based on the UPF information.

[0087] The UPF file of the chip refers to a file containing the top-level UPF information of the chip and the UPF information of each functional module of the chip, and coupling the top-level UPF information and the module UPF information.

[0088] Exemplarily, after obtaining the UPF information of the functional module corresponding to the identification of the functional module, first, the UPF information of each functional module is processed, integrated, and the like to obtain the UPF information of the chip as a whole (top layer) reflecting the UPF information of all functional modules of the chip, including power domain information, power supply definition information, power state definition, isolation strategy and level conversion strategy, input and output pin power information, and the like. Then, a pre-defined UPF file template of the chip is loaded, the template includes the basic structure and common statements of the UPF file, such as power domain definition, power supply definition, power state definition, level conversion strategy definition, input and output pin power definition, and the like, and the UPF information of the chip as a whole (top layer) is filled into the UPF file template to obtain the UPF file of the chip as a whole, which integrates the UPF information of each functional module of the chip. For example, the power domain information is filled into the power domain definition part, the power supply definition information is filled into the corresponding power supply description statement, the power state information is filled into the power state definition framework, the isolation strategy and level conversion strategy are filled into the isolation strategy and level conversion strategy definition framework, and the input and output pin power information is filled into the input and output pin power definition framework, and the like. Finally, a complete chip top layer UPF file is generated according to the filled template, and the file is optimized, such as removing redundant statements, adjusting the order of statements to improve the readability and execution efficiency of the file, and the like. The generated UPF file is output to a designated storage location, and the generation time, related design version, and the like are recorded for subsequent query and traceability.

[0089] In the generation method of the unified power format UPF file, the functional module identification under the instance corresponding to the system-level power supply is determined according to the first correspondence relationship and the second correspondence relationship, the first correspondence relationship includes the correspondence relationship between the instance and the system-level power supply, and the second correspondence relationship includes the correspondence relationship between the instance and each functional module; the UPF information of the corresponding functional module is obtained based on the functional module identification; and the UPF file of the chip is generated based on the UPF information. The embodiments of the present application can not only automatically generate the UPF file of the whole chip, but also generate the UPF file of the chip in combination with the UPF information of the functional module of the chip, adopt the bottom-up manner, combine the whole chip (chip top layer) and the functional module of the bottom layer of the chip, and generate the UPF file of the whole chip, so as to improve the generation efficiency of the UPF file of the chip.

[0090] In one exemplary embodiment, as shown in Figure 3 Step 203 includes step 301 and step 302. Wherein:

[0091] Step 301, based on the UPF information, determining a first mapping relationship, a second mapping relationship, a third mapping relationship and a fourth mapping relationship.

[0092] The first mapping relationship reflects a corresponding relationship between a system-level power supply identifier of the chip and system-level power supply pin information.

[0093] The second mapping relationship reflects a corresponding relationship between a module-level power supply identifier of the chip and module-level power supply pin information.

[0094] The third mapping relationship reflects a corresponding relationship between state information corresponding to the module-level power supply identifier of the chip and state information corresponding to the system-level power supply identifier.

[0095] The fourth mapping relationship reflects a corresponding relationship between the module-level power supply identifier of the chip and voltage information.

[0096] The power supply identifier is a unique identifier of each power supply of the chip, including a system-level power supply identifier and a module-level power supply identifier. The power supply pin information (including system-level power supply pin information and module-level power supply pin information) can be understood as a power supply pin path name or address name of an instance, for example, for an instance, the power supply pin information includes an instance identifier and a power supply pin identifier.

[0097] Exemplarily, after obtaining the UPF information of the functional module, the first mapping relationship and the second mapping relationship are determined based on the power supply pin information in the UPF information, the third mapping relationship is determined based on the power supply state information in the UPF information, and the fourth mapping relationship is determined based on the power supply voltage information in the UPF information.

[0098] Step 302, generating a UPF file of the chip based on the first mapping relationship, the second mapping relationship, the third mapping relationship, and the fourth mapping relationship.

[0099] Exemplarily, after obtaining each mapping relationship, the UPF information contained in each mapping relationship is filled into a UPF file template to obtain a UPF file of the chip.

[0100] Therefore, according to the UPF information of the functional module, the embodiment obtains the system-level corresponding relationship and the module-level corresponding relationship of all power supplies of the chip, which specifically includes the mapping relationship between the power supply and the power supply pin information, the state information, and the voltage information. These mapping relationships combine the UPF information of the functional module, so that the obtained UPF file of the chip contains the UPF information of the functional module, and the compatibility of the top-level UPF file of the chip is ensured.

[0101] How to generate the first mapping relationship, which is a system-level mapping relationship, is described below.

[0102] In an exemplary embodiment, as shown in FIG. 4, step 301 includes steps 401 to 403. Wherein: Figure 4

[0103] ​Step 401, obtaining the system-level power pin identifier corresponding to the system-level power identifier from the UPF information.

[0104] The system-level power pin identifier of the functional module is consistent with the system-level power identifier of the chip. For example, for the system-level power identifiers VDD_SOC, VDD_GPU, VDD_L, and VSS, the corresponding system-level power pin identifiers of the functional module are also VDD_SOC, VDD_GPU, VDD_L, and VSS. This is a strong rule, and the purpose of doing so is: a, when generating the UPF file, it will check whether the system-level power identifier of the top layer is consistent with the system-level power pin identifier, and if not, an error will be reported; b, check whether the top layer voltage of the corresponding power supply is consistent with the voltage of the functional module, otherwise an error will be reported; c, check whether the state information (i.e. power-on and power-off sequence) of the system-level power supply is consistent with the functional module, and if not, an error will be reported.

[0105] For example, from the power definition information of the UPF information of the usb module, the system-level power identifier of the module, such as VDD_SOC, is obtained, and then the identifier VDD_SOC is determined as the system-level power pin identifier corresponding to the system-level power identifier.

[0106] Step 402, determining the system-level power pin address name of the first instance according to the first instance identifier of the functional module identifier corresponding first instance and the system-level power pin identifier.

[0107] The first instance refers to the instance corresponding to the functional module identifier, and the first instance identifier refers to the unique identifier of the first instance.

[0108] For example, the first instance identifier of the first instance corresponding to each functional module identifier, such as the first instance identifier u_usb corresponding to the functional module identifier usb, is combined with the system-level power pin identifier to obtain the system-level power pin address name of the first instance.

[0109] According to the above example, for the first instance identifier u_usb, u_usb is combined with the system-level power pin identifier VDD_SOC to obtain the system-level power pin address name of the first instance, which can be in the form of u_usb / VDD_SOC, indicating the VDD_SOC power pin of the first instance u_usb, which is unique.

[0110] Step 403, generating a first mapping relationship according to the system-level power identifier and the system-level power pin address name of the first instance.

[0111] Exemplarily, for each first instance, the system-level power supply identifier and the system-level power supply pin address name are corresponded, a mapping relationship between the two is established, and the correspondence between the system-level power supply identifier and the system-level power supply pin address name is realized. For example, the system-level power supply identifier VDD_SOC corresponds to the system-level power supply pin address name u_usb / VDD_SOC, indicating that the system-level power supply VDD_SOC is connected to the VDD_SOC pin of the instance u_usb.

[0112] In this embodiment, by establishing a mapping relationship between the system-level power supply identifier and the system-level power supply pin address name of the first instance, the power supply connection relationship between the system-level power supply and the instance is represented, which can ensure the consistency of the connection between the top-level power supply (system-level power supply) and the power supply pin of the instance, and avoid power supply error connection.

[0113] Further, how to generate a second mapping relationship, which is a module-level mapping relationship, is described.

[0114] That is, in an exemplary embodiment, as shown in Figure 5 Step 301 further includes steps 501 to 504. Wherein:

[0115] Step 501, obtaining a first module-level power supply identifier corresponding to any target functional module from the UPF information.

[0116] Wherein, the target functional module refers to any one of the functional modules. The first module-level power supply identifier refers to the unique identifier of the module-level power supply (i.e. the power supply other than the system-level power supply) corresponding to the target functional module.

[0117] Exemplarily, taking the target functional module as the usb module as an example, the first module-level power supply identifier of the usb module is obtained from the power supply definition information (Table 2 above) of the UPF information of the usb module. The module-level power supply refers to the power supply inside the module other than the system-level power supply. For example, the module-level power supply identifiers of the usb module are AVDD1P8V and AVDD1P2V.

[0118] Step 502, obtaining a second module-level power supply identifier of the chip according to the target functional module identifier and the first module-level power supply identifier of the target functional module.

[0119] Wherein, the second module-level power supply identifier refers to the unique identifier of the module-level power supply corresponding to the chip.

[0120] Exemplarily, for any target function module, the target function module identifier is combined with the first module level power supply identifier to obtain the second module level power supply identifier of the chip. If the target function module identifier is composed of lowercase letters, the uppercase letters of the target function module identifier are combined with the first module level power supply identifier to obtain the second module level power supply identifier of the chip. For example, for the target function module usb module, the uppercase letters of the target function module identifier, i.e. USB, are combined with the first module level power supply identifiers AVDD1P8V and AVDD1P2V respectively to obtain two second module level power supply identifiers of the chip: USB_AVDD1P8V and USB_VDD_1P2V.

[0121] In step 503, the module level power supply pin address name of the second instance is determined according to the second instance identifier of the second instance corresponding to the target function module identifier and the first module level power supply identifier.

[0122] The second instance refers to the instance corresponding to the target function module identifier, and the second instance identifier refers to the unique identifier of the second instance. The number of instance identifiers corresponding to each function module is at least one. Taking the function module identifier usb as an example, it can be known from the second correspondence tile_instance.map.yaml that the corresponding instance identifier is one, and the one instance identifier u_usb corresponding to usb is obtained.

[0123] Exemplarily, for the target function module, the second instance identifier corresponding to the target function module identifier of the second instance is combined with the first module level power supply identifier obtained in step 501 to obtain the module level power supply pin address name of the second instance. For example, the second instance identifier u_usb is combined with the first module level power supply identifiers AVDD1P8V and AVDD1P2V respectively to obtain two module level power supply pin address names of the second instance u_usb: u_usb / AVDD1P8V and u_usb / AVDD1P2V.

[0124] In step 504, a second mapping relationship is generated according to the second module level power supply identifier and the module level power supply pin address name of the second instance.

[0125] Exemplarily, the mapping relationship between the second module level power supply identifier USB_AVDD1P8V of the chip obtained in step 502 and the module level power supply pin address name u_usb / AVDD1P8V of the second instance obtained in step 503, and the mapping relationship between USB_VDD_1P2V and u_usb / AVDD1P2V are established.

[0126] By Figure 4 and Figure 5The mapping relationship between all power supply identifiers of the chip and the power pin address name of the instance is obtained by the step, and the connection relationship between the power supply and the power pin of the instance is represented, such as the mapping relationship between USB_VDD_1P2V and u_usb / AVDD1P2V, which represents the connection relationship between the module-level power supply USB_VDD_1P2V of the chip and the power pin AVDD1P2V of the instance u_usb. Optionally, by the steps of Figure 4 and Figure 5 A table file named power_map.xlsx is obtained, as shown in Table 6:

[0127] Table 6: Table of all power supply identifiers and power pin address names of instances

[0128]

[0129] The system-level mapping relationship is directly obtained from the system-level power supply identifier and generated according to the consistency rule, such as the system-level power supply identifier VDD_SOC corresponding to the power pin address name u_dptx / VDD_SOC. The second module-level power supply identifier is directly obtained from the power supply definition information of the UPF table information of the functional module, and the first module-level power supply identifier is integrated into the power supply identifier naming of the top layer to obtain the second module-level power supply identifier of the chip, and the naming rule is: the capital letter of the target functional module identifier and the first module-level power supply identifier are combined. For example, the first module-level power supply identifier of the target functional module usb is: AVDD1P8V, VDD_1P2V and AVSS, and the corresponding second module-level power supply identifier of the chip is USB_AVDD1P8V, USB_VDD_1P2V and USB_AVSS. If a functional module is instantiated multiple times in the top layer, a number sequence n can be added to the identifier to distinguish it, n=0, 1, 2……, for example: in Table 6, the gpu_crg module is instantiated twice in the top layer, and the corresponding instances are u0_gpu_crg and u1_gpu_crg, and the corresponding second module-level power supply identifiers of the chip are GPU_CRG0_PLL_ADD0P18V and GPU_CRG1_PLL_ADD0P18V, respectively, to ensure the uniqueness of the second module-level power supply identifier of the chip. In this way, the mapping relationship of all power supplies of the functional module in the top layer of the chip is obtained, which lays a foundation for the generation of the UPF file of the chip.

[0130] Thus, the embodiment realizes the naming of the second module-level power supply identification of the chip based on the target function module identification of the target function module and the first module-level power supply identification, determines the module-level power supply pin address name of the second instance, and generates the second mapping relationship, so that the first module-level power supply (unique power supply) of the function module is integrated into the top layer of the chip, and it is ensured that these power supplies are correctly named and connected in the top layer.

[0131] Next, an embodiment is described below to obtain the third mapping relationship, which includes both the system-level mapping relationship and the module-level mapping relationship.

[0132] In an exemplary embodiment, as shown in Figure 6 Step 301 further includes steps 601 to 604. Wherein:

[0133] In step 601, the first state information corresponding to the system-level power supply identification of the system-level power supply and the second state information corresponding to the target power supply identification of the target power supply in the system-level power supply are obtained.

[0134] The target power supply is used to supply power to the control module of the chip. The target power supply refers to the default system-level power supply VDD_SOC in the top layer of the chip, which is specified by the top layer file (provided by the designer and stored in the database) and is used to supply power to the control module in the chip.

[0135] The first state information refers to the state information of the system-level power supply, and the second state information refers to the state information of the target power supply. The first state information corresponding to the system-level power supply identification includes the second state information corresponding to the target power supply identification. The state information represents the working state and output voltage of the power supply, for example, the state information can include at least one of standard voltage (SON), maximum voltage (HON), minimum voltage (LON), and OFF state.

[0136] Exemplarily, the top layer file of the chip can be obtained from the database, and the system-level power supply identification and the first state information corresponding thereto, and the target power supply identification (such as VDD_SOC) and the second state information corresponding thereto can be obtained from the top layer file. The system-level power supply identification and the first state information corresponding thereto can be embodied by a table. Alternatively, taking the system-level power supply identifications VDD_SOC, VDD_L, and VDD_GPU as examples, the first state information corresponding to the system-level power supply identification is shown in Table 7. The table includes the power-on and power-off scenario information between the three main power supplies, and the default top layer power supply domain is VDD_SOC_PD. The table also includes the second state information corresponding to the target power supply identification VDD_SOC, wherein the state information can be embodied by a state identification.

[0137] Table 7 State information table of system-level power supply

[0138]

[0139] Each row of state information of Table 7 can be stored in a dictionary, resulting in a dictionary named Top_power_sequence:

[0140] Top_power_sequence={

[0141] ALL_OFF:{VDD_GPU:OFF,VDD_SOC:OFF,VDD_L:OFF}

[0142] VDD_L_HON:{VDD_GPU:OFF,VDD_SOC:OFF,VDD_L:HON}

[0143] VDD_L_LON:{VDD_GPU:OFF,VDD_SOC:OFF,VDD_L:LON}

[0144] VDD_SOC_HON:{VDD_GPU:OFF,VDD_SOC:HON,VDD_L:LON}

[0145] VDD_SOC_LON:{VDD_GPU:OFF,VDD_SOC:LON,VDD_L:LON}

[0146] VDD_GPU_HON:{VDD_GPU:HON,VDD_SOC:LON,VDD_L:LON}

[0147] VDD_GPU_LON:{VDD_GPU:LON,VDD_SOC:HON,VDD_L:HON}

[0148] ALL_LON:{VDD_GPU:LON,VDD_SOC:LON,VDD_L:LON}

[0149] ALL_HON:{VDD_GPU:HON,VDD_SOC:HON,VDD_L:HON}

[0150] }.

[0151] Since the above table and dictionary only include the state information corresponding to the system-level power supply identification, and do not embody the state information of the module-level power supply (unique power supply) of the underlying functional module, it is necessary to add the state information of the module-level power supply (unique power supply) of the functional module based on Table 7. That is, in addition to the first state information (power-on and power-off scenarios) of the three main power supplies, the power-on and power-off relationship between the unique power supply of the functional module and the three power supplies is also needed, so it is necessary to combine the power-on and power-off sequence (state information) of all module-level power supplies of the functional module into the above Table 7 or dictionary through a preset algorithm. See the subsequent steps for details.

[0152] Step 602, from the UPF information, obtain the third state information corresponding to the target power supply identification, and the fourth state information corresponding to the third module-level power supply identification.

[0153] Among them, the third state information refers to the state information corresponding to the target power supply identification in the UPF information, the third module-level power supply identification is the identification of the functional module corresponding to the third state information, and the first state information, the second state information, the third state information and the fourth state information are used to represent the working state and output voltage of the power supply.

[0154] Exemplarily, taking the functional module identification usb as an example, first find the corresponding UPF information according to the identification, and then obtain the third state information corresponding to the target power supply identification and the fourth state information corresponding to the third module-level power supply identification in the power supply state information (such as the above Table 4) of the UPF information. For example, according to the first row of the above Table 4, when the third state information of the target power supply VDD_SOC is OFF, the fourth state information of the third module-level power supply is: AVDD1P18: OFF and AVDD1P18: OFF.

[0155] Step 603, in the case where the second state information and the third state information are consistent, determining the fourth module-level power supply identification of the chip according to the functional module identification and the third module-level power supply identification, and establishing the corresponding relationship between the fourth module-level power supply identification and the fourth state information.

[0156] Exemplarily, the third state information of VDD_SOC in Table 4 and the second state information of VDD_SOC in Table 7 are compared, if both are consistent, the fourth module level power supply identifier of the chip is named: if the function module identifier is composed of lowercase letters, the third module level power supply identifier is combined with the uppercase letters of the function module identifier to obtain the fourth module level power supply identifier of the chip. For example, for the usb module, the uppercase USB of the function module identifier is combined with the third module level power supply identifiers AVDD1P8V and AVDD1P2V respectively to obtain the fourth module level power supply identifiers of the chip: USB_AVDD1P8V and USB_VDD1P2V. And the fourth module level power supply identifiers are corresponded to the fourth state information in Table 4, taking the first row of Table 4 as an example, USB_AVDD1P8V and USB_VDD1P2V are corresponded to the fourth state information OFF and OFF in the UPF table information respectively to obtain the corresponding relationship between the fourth module level power supply identifiers of the chip and the fourth state information.

[0157] In step 604, the third mapping relationship is generated according to the fourth state information and the first state information.

[0158] Wherein, the mapping relationship between the third module level power supply identifier and the fourth state information corresponding thereto is A, the mapping relationship between the system level power supply identifier and the first state information corresponding thereto is B, the mapping relationship between A and B is established, that is, the third mapping relationship, that is: the mapping relationship between the fourth state information corresponding to the third module level power supply identifier and the first state information corresponding to the system level power supply identifier is the third mapping relationship.

[0159] Exemplarily, taking the state information of VDD_SOC in the first row of Table 4 and Table 7 as an example, the mapping relationship A: USB_AVDD1P8V: OFF and USB_VDD1P2V: OFF is corresponded to the mapping relationship B: VDD_SOC: OFF, VDD_GPU: OFF and VDD_L: OFF, to obtain the state information of the top layer combined with the bottom layer module. For example, the third state information of VDD_SOC in Table 4 and the first state information of VDD_SOC in Table 7 are compared, if they are consistent, the third module level power supply identification corresponding to the third state information and its corresponding fourth state information (AVDD1P8V and VDD_1P2V relative to the state of VDD_SOC) are merged into Table 7 or the above dictionary Top_power_sequence1 according to the interpolation method, so as to integrate the module level power supply state information to the chip top layer. If there are multiple state identifications, the key values of the dictionary are changed at the same time, for example, the state identification VDD_SOC_HON has two, and the key values of the dictionary are named as VDD_SOC_HON_1 and VDD_SOC_HON_2 respectively. Thus, the above dictionary is updated to obtain the following new dictionary Top_power_sequence, which can be stored in the form of table and named as power_state.xlsx:

[0160] Top_power_sequence={

[0161] ALL_OFF:{VDD_GPU:OFF,VDD_SOC:OFF,USB_AVDD1P8V:OFF,USB_VDD_1P2V:OFF,VDD_L:OFF}

[0162] VDD_L_HON:{VDD_GPU:OFF,VDD_SOC:OFF,USB_AVDD1P8V:OFF,USB_VDD_1P2V:OFF,VDD_L:HON}

[0163] VDD_L_LON:{VDD_GPU:OFF,VDD_SOC:OFF,USB_AVDD1P8V:OFF,USB_VDD_1P2V:OFF,VDD_L:LON}

[0164] VDD_SOC_HON_1:{VDD_GPU:OFF,VDD_SOC:HON,USB_AVDD1P8V:OFF,USB_VDD_1P2V:OFF,VDD_L:LON}

[0165] VDD_SOC_HON_2: {VDD_GPU: OFF, VDD_SOC: HON, USB_AVDD1P8V: SON, USB_VDD_1P2V: SON, VDD_L: LON}

[0166] VDD_SOC_LON_1: {VDD_GPU: OFF, VDD_SOC: LON, USB_AVDD1P8V: OFF, USB_VDD_1P2V: OFF, VDD_L: LON}

[0167] VDD_SOC_LON_2: {VDD_GPU: OFF, VDD_SOC: LON, USB_AVDD1P8V: SON, USB_VDD_1P2V: SON, VDD_L: LON}

[0168] VDD_GPU_HON_1: {VDD_GPU: HON, VDD_SOC: LON, USB_AVDD1P8V: OFF, USB_VDD_1P2V: OFF, VDD_L: LON}

[0169] VDD_GPU_HON_2: {VDD_GPU: HON, VDD_SOC: LON, USB_AVDD1P8V: SON, USB_VDD_1P2V: SON, VDD_L: LON}

[0170] VDD_GPU_LON_1: {VDD_GPU: LON, VDD_SOC: HON, USB_AVDD1P8V: OFF, USB_VDD_1P2V: OFF, VDD_L: HON}

[0171] VDD_GPU_LON_2: {VDD_GPU: LON, VDD_SOC: HON, USB_AVDD1P8V: SON, USB_VDD_1P2V: SON, VDD_L: HON}

[0172] ALL_LON_1: {VDD_GPU: LON, VDD_SOC: LON, USB_AVDD1P8V: OFF, USB_VDD_1P2V: OFF, VDD_L: LON}

[0173] ALL_LON_2: {VDD_GPU: LON, VDD_SOC: LON, USB_AVDD1P8V: SON, USB_VDD_1P2V: SON, VDD_L: LON}

[0174] ALL_HON_1 : { VDD_GPU : HON, VDD_SOC : HON, USB_AVDD1P8V : OFF, USB_VDD_1P2V : OFF, VDD_L : HON}

[0175] ALL_HON_2 : { VDD_GPU : HON, VDD_SOC : HON, USB_AVDD1P8V : SON, USB_VDD_1P2V : SON, VDD_L : HON}

[0176]

[0177] In the dictionary, as an example of the first row, under the state identifier ALL_OFF, the fourth state information of the third module level power supply identifier and the first state information of the corresponding system level power supply (i.e., the third mapping relationship) are: USB_AVDD1P8V:OFF and USB_VDD_1P2V:OFF, which respectively represent that the fourth state information of the newly added third module level power supply identifiers USB_AVDD1P8V and USB_VDD_1P2V is in the off state; VDD_GPU:OFF, VDD_SOC:OFF and VDD_L:OFF, which respectively represent that the first state information of the system level power supplies VDD_GPU, VDD_SOC and VDD_L is in the off state. In this way, the mapping relationship between the fourth state information of the third module level power supply identifier (i.e., the corresponding relationship between the third module level power supply identifier and its fourth state) and the first state information of the system level power supply (i.e., the corresponding relationship between the system level power supply identifier and its first state) is obtained. For specific mapping relationships, refer to the new dictionary above.

[0178] In the related art, due to the complex power supply state corresponding relationship between the top layer and the bottom layer functional modules of the chip, and with the increase in the number of module level power supplies of the functional modules (the order of magnitude is one hundred), when integrating the module level power supply states of each functional module into the top layer power supply state table (i.e., in the process of generating the third mapping relationship), if there is a lack of effective algorithm support, it is easy to cause the power supply state of the top layer to be unable to completely cover the power supply state of the functional module, or the power supply state of the functional module to be unable to completely match the power supply state of the top layer. As a result, it may lead to the missing of the overall power supply state of the chip, and then cause some power supply strategies to be not actually implemented in the hardware design stage of the chip. Since the number of power supplies involved is large, such problems are often difficult to troubleshoot, which will consume a lot of manpower and time cost. The embodiment effectively solves the power supply state compatibility problem between the top layer and the bottom layer functional modules through a certain algorithm, and reduces the manpower and time cost.

[0179] ​Thus, the embodiment determines the mapping relationship between the fourth state information corresponding to the third module level power supply identifier and the first state information corresponding to the system level power supply identifier according to the state information of the target power supply in the chip system (top layer) and the functional module, solves the power supply state conflict problem of the top layer and the module, ensures that the top layer power supply state covers all state information scenarios of the functional module, ensures that the state of the target power supply in the module is consistent with the top layer, and provides accurate data basis for the chip top layer power supply state generation.

[0180] In order to more reliably generate the UPF file of the chip top layer, in addition to the mapping relationship between the power supply identifier and the power supply pin information and the state information, the voltage information corresponding to all power supply identifiers (module level power supply identifier and system level power supply identifier) of the chip is also needed, and the voltage information is used to represent the size of the power supply voltage. The following will be described in detail.

[0181] In an exemplary embodiment, as shown in Figure 7 Step 301 includes steps 701 to 703, wherein:

[0182] Step 701, from the UPF information, obtaining the first module level power supply identifier of any target functional module and the voltage information corresponding to the first module level power supply identifier.

[0183] Exemplarily, taking the target functional module as the usb module as an example, the first module level power supply identifier of the target functional module usb module and the voltage information thereof are obtained from the power supply definition information (the above table 2) of the UPF information of the target functional module. The module level power supply refers to the power supply inside the module except the system level power supply. For example, the voltage information corresponding to the first module level power supply identifier AVDD1P8V and AVDD1P2V of the target functional module usb module is 1.8V and 1.2V respectively.

[0184] Step 702, obtaining the second module level power supply identifier of the chip according to the target functional module identifier of the target functional module and the first module level power supply identifier.

[0185] Exemplarily, the target functional module identifier and the first module level power supply identifier are combined to obtain the second module level power supply identifier of the chip. Optionally, if the functional module identifier is composed of lowercase letters, the first module level power supply identifier and the uppercase letters of the functional module identifier are combined to obtain the second module level power supply identifier of the chip. For example, for the usb module, the uppercase letters USB of the functional module identifier are combined with the two first module level power supply identifiers AVDD1P8V and AVDD1P2V respectively to obtain two second module level power supply identifiers of the chip: USB_AVDD1P8V and USB_VDD_1P2V.

[0186] In step 703, a fourth mapping relationship is generated according to the second module level power supply identifier and the voltage information.

[0187] Exemplarily, the second module level power supply identifier USB_AVDD1P8V of the chip is corresponded to the standard voltage 1.8V, and the second module level power supply identifier USB_VDD_1P2V of the chip is corresponded to the standard voltage 1.2V, so that the mapping relationship between the second module level power supply identifier of the chip and the voltage information thereof is established, and the voltage information of the module-specific power supply is integrated in the top layer of the chip.

[0188] Therefore, the first module level power supply identifier and the voltage information thereof are obtained from the UPF information in the embodiment, the target function module identifier is combined with the first module level power supply identifier to obtain the second module level power supply identifier of the chip, and the mapping relationship between the second module level power supply identifier of the chip and the voltage information is generated. The voltage information of the module level power supply of the function module can be automatically integrated into the file of the chip as a whole (the top layer), so as to avoid manual input errors, ensure that the generated chip UPF file can reflect the voltage information of the module level power supply, and improve the accuracy and integrity of the chip UPF file.

[0189] Figure 7 The generation steps of the voltage information corresponding to the module level power supply identifier are given, in addition to which the voltage information corresponding to the system level power supply identifier is also needed. In order to obtain the voltage information corresponding to the system level power supply identifier, in an example, as shown in FIG. 8, step 203 further includes steps 801 to 803: Figure 8

[0190] In step 801, a fifth mapping relationship is obtained, which reflects the corresponding relationship between the system level power supply identifier of the chip and a preset voltage range.

[0191] Exemplarily, first, the preset voltage range of the system level power supply is obtained from the top layer file of the chip, for example, the minimum voltage of VDD_SOC is 0.675V, and the maximum voltage is 0.825V. Then, the corresponding relationship between the system level power supply identifier VDD_SOC of the chip and 0.675V and 0.825V is established, that is, VDD_SOC corresponds to 0.675V and 0.825V.

[0192] Through Figure 7 ​The voltage information corresponding to each of the second module-level power supply identifiers and the system-level power supply identifiers is integrated into a table according to the corresponding relationship, and a table file integrating the system-level and module-level voltage information is obtained, which can be named power_voltage.xlsx, as shown in Table 8. The voltage information of the system-level power supply identifiers VDD_SOC, VDD_GPU and VDD_L is directly specified by the top layer (which can be obtained from the top layer file), and the voltage information of the other power supply identifiers is automatically obtained from the UPF table information of the bottom function module by the script.

[0193] Table 8: Voltage information table of all power supplies of the chip

[0194]

[0195] Step 802: Obtain the input and output pin power supply information of the chip.

[0196] For example, the power supply information table related to the input and output of the chip top layer is obtained from the chip top layer file, which is provided by the designer and has a file name of top_io.xlsx, as shown in Table 9.

[0197] Table 9: Input and output pin power supply information table of the chip

[0198]

[0199] Step 803: Generate the UPF file of the chip based on the UPF information, the fifth mapping relationship and the input and output pin power supply information.

[0200] Finally, according to Table 6 (power pin information), the new dictionary (power state information), Table 8 (power voltage information) and Table 9 (input and output pin power supply information), the UPF file of the chip top layer is generated. The power pin information is filled into the pin information definition framework of the UPF template, the power state information is filled into the power state definition framework, the power voltage information is filled into the power voltage information definition framework, and the input and output pin power supply information is filled into the input and output pin definition framework, so as to ensure the integrity of the UPF file of the chip. In addition, since the top layer is only responsible for wiring and has no logic unit, it does not involve low-power design, and therefore it is not necessary to set the isolation strategy and the level conversion strategy in the top layer. The isolation strategy and the level conversion strategy are implemented in each function module.

[0201] Based on the above tables, the specification of the module level power supply identification of the chip, the rationality of the voltage value in the power supply definition information of each module, the correctness of the power supply pin connection relationship, and the consistency of the power supply state of the top layer and the module can be further verified. If the data that does not meet the requirements is verified, an error prompt can be issued and the error position and reason are recorded.

[0202] Therefore, by combining the power supply information of the bottom function module in Table 6 (power supply pin information), the new dictionary (power supply state information), Table 8 (power supply voltage information), and Table 9 (input and output pin power supply information), the UPF file of the chip top layer is generated, the mechanism of integration from the bottom module to the top is realized, the top layer and the bottom module are combined in a bottom-up manner, the two complement each other and are unified to generate the UPF file of the top layer, the generation efficiency is improved, and the accuracy of the UPF file is improved.

[0203] In order to ensure the consistency and integrity of the voltage information of the system level power supply of the top layer and the bottom layer, the UPF information of the bottom module is analyzed and verified.

[0204] That is, in an exemplary embodiment, step 203 includes: obtaining voltage information of a first system level power supply from the UPF information; the first system level power supply is any power supply in the plurality of system level power supplies; obtaining preset voltage information of the first system level power supply; in the case that the voltage information of the first system level power supply matches the preset voltage information, generating the UPF file of the chip based on the UPF information; in the case that the voltage information of the first system level power supply does not match the preset voltage information, outputting indication information, the indication information being used to indicate that the voltage information of the first system level power supply in the UPF information is modified; in the case that the UPF information modification is completed, obtaining the modified UPF information, and generating the UPF file of the chip based on the modified UPF information.

[0205] The first system level power supply refers to any system level power supply in the plurality of system level power supplies obtained from the UPF information corresponding to the function module identification, which can be embodied by a power supply identification, such as obtaining the voltage information of the first system level power supply VDD_SOC from the power supply definition information table (Table 2) in the UPF table information of the usb module: the minimum voltage is 0.675V and the maximum voltage is 0.825V. The preset voltage information includes the minimum voltage and the maximum voltage, which is the preset voltage information of the first system level power supply such as VDD_SOC obtained from the chip top layer file.

[0206] Exemplarily, taking the first system-level power supply VDD_SOC as an example, the voltage information of the first system-level power supply VDD_SOC is obtained from Table 2 of the usb module, that is, the minimum voltage is 0.675V and the maximum voltage is 0.825V, and the preset voltage information of the first system-level power supply VDD_SOC is obtained from the chip top-level file, that is, the preset minimum voltage is also 0.675V and the preset maximum voltage is also 0.825V. After comparison, it is found that the minimum voltages of the two are consistent, and the maximum voltages are consistent, which means that the two are consistent or matched. Therefore, step 203 is directly executed, that is, the UPF file of the chip is generated based on the UPF information. Specifically, based on the UPF information, the first mapping relationship, the second mapping relationship, the third mapping relationship and the fourth mapping relationship are determined, and the UPF file of the chip is generated based on these mapping relationships.

[0207] Alternatively, if the minimum voltage and the maximum voltage of the first system-level power supply VDD_SOC obtained from Table 2 of the usb module do not match the preset minimum voltage and the preset maximum voltage of the first system-level power supply VDD_SOC obtained from the chip top-level file (the minimum voltage does not match the preset minimum voltage, and / or the maximum voltage does not match the preset maximum voltage), it means that the two do not match. Then, an error is reported, and the indication information is output. According to the indication information, the voltage information of the first system-level power supply in the UPF information can be modified so that the voltage information of the first system-level power supply in the UPF information matches or is consistent with the preset voltage information of the first system-level power supply in the chip top-level file. Then, in the case where the UPF information is modified, the modified UPF information is obtained, and step 203 is executed, that is, the UPF file of the chip is generated based on the modified UPF information. Specifically, based on the modified UPF information, the first mapping relationship, the second mapping relationship, the third mapping relationship and the fourth mapping relationship are determined, and the UPF file of the chip is generated based on these mapping relationships.

[0208] Alternatively, in order to ensure the accuracy of the UPF file of the functional module, the UPF file of the corresponding functional module can also be generated according to the modified UPF information. For example, after modifying the voltage information of the first system-level power supply in the UPF table information of the usb module, the modified UPF information is filled into the UPF template of the usb module to obtain the UPF file of the usb module, thereby ensuring the accuracy of the UPF file of the usb module.

[0209] Thus, the mapping relationship is determined only when the voltage information of the system-level power supply in the UPF information is consistent with the preset voltage information of the system-level power supply specified in the chip top-level file, and then the UPF file of the chip is generated according to each mapping relationship; when the voltage information of the system-level power supply in the UPF information is inconsistent with the preset voltage information of the system-level power supply specified in the chip top-level file, the UPF information is modified, the mapping relationship is determined based on the modified UPF information, and then the UPF file of the chip is generated according to each mapping relationship, which can ensure the accuracy of the UPF file of the chip. In addition, the UPF file of the corresponding functional module is generated according to the modified UPF information, which can ensure the accuracy of the UPF file of the functional module.

[0210] The following describes a specific embodiment of determining the functional module identifier in step 201.

[0211] In an exemplary embodiment, step 201 includes: determining, according to a first correspondence relationship, an instance identifier corresponding to each system-level power supply of the chip; and determining, according to a second correspondence relationship, a functional module identifier corresponding to the instance identifier of each system-level power supply.

[0212] The instance identifier refers to the identifier of an instance of the functional module.

[0213] For example, first, the top-level file of the chip is obtained from the database, and the system-level power supply identifiers of all system-level power supplies of the chip, such as VDD_SOC, VDD_GPU and VDD_L, are determined from the top-level file. The first correspondence relationship and the second correspondence relationship of the chip are obtained from the database, and then for each system-level power supply, the instance identifier corresponding to the system-level power supply is determined according to the system-level power supply identifier and the first correspondence relationship, and the functional module identifier corresponding to the instance identifier of the system-level power supply is determined from the second correspondence relationship. Taking the system-level power supply VDD_GPU as an example, according to the first correspondence relationship main_power_domain.partition, the VDD_GPU and the corresponding instance identifier u_vdci_gpu and u_vdci_sm are determined. According to the instance identifier u_vdci_gpu and u_vdci_sm, and the second correspondence relationship tile_instance.map.yaml, it is determined that the functional module identifier corresponding to u_vdci_gpu is vdci_gpu, and the functional module identifier corresponding to u_vdci_sm is vdci_sm.

[0214] Thus, in this embodiment, the functional module identifier under each instance of each system-level power supply is determined according to the first correspondence relationship and the second correspondence relationship. Since the first correspondence relationship and the second correspondence relationship have accuracy, the accuracy of the functional module identifier can be ensured, and the system-level power supply can be correctly associated with the underlying functional module, providing an accurate basis for subsequent UPF information extraction.

[0215] Compared with the related art, in the generation of the top-level UPF, on the one hand, the power information of the functional module required by the top-level is obtained from the UPF information of each functional module, and on the other hand, the information of the main power supply (i.e. the system-level power supply) of the chip is transmitted from the top-level to the bottom-level. In addition, the application embodiment also solves the compatibility problem of the power supply state of the top-level and the bottom-level functional module. As shown in Figure 9 For example, the chip 900 with dptx, vdci_gpu, usb, gpu, u_vdci_sm and gpu_crg as functional modules, the instance of dptx in the chip is u_dptx, the instance of vdci_gpu is u_vdci_gpu, the instance of usb is u_usb, the instance of gpu is u_gpu, the instance of vdci_sm is u_vdci_sm, and the instances of pu_crg are u0_gpu_crg and u1_gpu_crg, wherein u_dptx and u_usb are VDD_SOC power supply domains, u_gpu is a VDD_GPU power supply domain, u_gpu_crg and u1_gpu_crg are VDD_L power supply domains, u_vdci_gpu is used to realize the cross-domain connection between the VDD_SOC and VDD_GPU two power supply domains, and u_vdci_sm is used to realize the cross-domain connection between the VDD_GPU and VDD_L two power supply domains, Figure 9 The power connection principle of each instance is shown in

[0216] The generation method of the UPF file of the chip according to the application embodiment will be described below through a specific example.

[0217] In a specific example, as shown in Figure 10 The generation method of the UPF file of the chip includes the following steps:

[0218] Step 1001, according to the first correspondence relationship and the second correspondence relationship of the chip, the functional module identifier under the instance corresponding to the system-level power supply is determined;

[0219] The first correspondence relationship and the second correspondence relationship can be the main_power_domain.partition file and the tile_instance.map.yaml file described above.

[0220] Step 1002, the voltage information of the first system-level power supply is obtained from the UPF information corresponding to the functional module identifier;

[0221] Step 1003, the preset voltage information of the first system-level power supply is obtained;

[0222] Step 1004, the voltage information and the preset voltage information are parsed;

[0223] Step 1005, determine whether the voltage information of the first system-level power supply matches the preset voltage information, if not, execute step 1006; if yes, execute step 1007;

[0224] Step 1006, modify the UPF information, and return to step 1002;

[0225] Step 1007, based on the UPF information, determine the power_map.xlsx file containing the first mapping relationship between the power supply identifier and the power pin information and the second mapping relationship, and the power_state.xlsx file containing the third mapping relationship between the power supply identifier and the state information;

[0226] Wherein, the mapping relationship between the power supply identifier and the power pin information is shown in Table 6 (power_map.xlsx) described above, and the mapping relationship between the power supply identifier and the state information is shown in the new dictionary power_state.xlsx.

[0227] Step 1008, based on the UPF information, determine the fourth mapping relationship between the module-level power supply identifier of the chip and the voltage information;

[0228] Step 1009, obtain the fifth mapping relationship between the chip system-level power supply identifier and the preset voltage range;

[0229] Step 1010, obtain the power_voltage.xlsx file according to the fourth mapping relationship and the fifth mapping relationship;

[0230] Specifically, refer to Table 8 (power_voltage.xlsx).

[0231] Step 1011, obtain the top_io.xlsx file recording the input and output pin power information of the chip;

[0232] Specifically, refer to Table 9 (top_io.xlsx).

[0233] Step 1012, generate the UPF file of the top layer of the chip according to the power_map.xlsx, power_state.xlsx, power_state.xlsx, power_voltage.xlsx and top_io.xlsx files;

[0234] Step 1013, generate the UPF file of each functional module according to the UPF information of the functional module.

[0235] The UPF file of all modules and the UPF file of the top layer can be automatically generated according to the relevant information of chip design, so that the generation efficiency and accuracy of the UPF file are significantly improved, the workload and error rate of manual writing are reduced, and a series of conflict problems caused by separation of the top layer and the module and inability to generate the UPF file as a unified system in the traditional scheme are solved, such as power naming conflict, power state conflict, power voltage conflict and the like. The generation mechanism from bottom to top is adopted, the top layer UPF file integrating all function modules is efficiently generated in one process, and the UPF file of each function module is synchronously generated, so that the generation efficiency is greatly improved, and the accuracy of the UPF file of the chip is ensured.

[0236] In summary, the embodiments of the present application have the following effects:

[0237] (1) The error rate is significantly reduced: the rule predefinition and automatic data checking are performed through the structured table, and the error rate is reduced by 92%. For example, the power domain nesting relationship is automatically checked to prevent the sub-domain from being covered by the parent domain; it is ensured that the power voltage of the top layer is consistent with the power voltage of the module, the power state of the top layer is matched with the power state of the module, and the power naming conforms to the specification, and the like;

[0238] (2) The efficiency is greatly improved: the UPF file writing of the traditional large chip needs several person-weeks (such as 14 person-days), and the cycle can be compressed to 0.5 person per day by the embodiments of the present application, and the efficiency is improved by more than 20 times;

[0239] (3) Dynamic updating and version tracing are supported: the power information is managed in the form of a table, real-time tracking of changes (such as power increase or decrease, power state adjustment, etc.) is facilitated, and is automatically synchronized to the UPF file, so that the version confusion problem caused by manual modification in the traditional text editing mode is effectively avoided;

[0240] (4) Power state conflict detection is realized: the power state information is represented by LON, SON and HON, and the LON, SON and HON are associated with the voltage value, so that the LON, SON and HON can be automatically converted into specific voltage values, the automatic conversion from the power state to the voltage is realized, the state definition ambiguity is avoided, and the state consistency and verifiability are ensured.

[0241] It should be understood that although each step in the flowchart involved in the above-described embodiments is shown in sequence according to the arrow, the steps are not necessarily executed in the order indicated by the arrow. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowchart involved in the above-described embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time but can be executed at different times, and the execution order of the steps or stages is not necessarily sequential but can be alternately or alternately executed with at least some of the other steps or steps or stages in the other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0242] Based on the same inventive concept, the embodiments of the present application also provide a unified power format UPF file generation apparatus for implementing the above-mentioned unified power format UPF file generation method. The problem-solving implementation scheme provided by the apparatus is similar to the implementation scheme described in the above method, so the specific limitations in one or more unified power format UPF file generation apparatus embodiments provided below can refer to the limitations of the unified power format UPF file generation method in the above text, which will not be repeated here.

[0243] In one exemplary embodiment, as shown in Figure 11 A unified power format UPF file generation apparatus is provided, comprising: a first determination module 1101, a first acquisition module 1102, and a first generation module 1103, wherein:

[0244] The first determination module 1101 is configured to determine the functional module identifier under the instance corresponding to the system-level power according to the first correspondence and the second correspondence of the chip; wherein the first correspondence includes the correspondence between the instance and the system-level power, and the second correspondence includes the correspondence between the instance and each functional module;

[0245] The first acquisition module 1102 is configured to acquire the UPF information of the corresponding functional module based on the functional module identifier;

[0246] The first generation module 1103 is configured to generate the UPF file of the chip based on the UPF information.

[0247] In an embodiment, the first generation module 1103 comprises a first determination unit and a first generation unit, wherein: the first determination unit is configured to determine a first mapping relationship, a second mapping relationship, a third mapping relationship and a fourth mapping relationship based on the UPF information; and the first generation unit is configured to generate a UPF file of the chip based on the first mapping relationship, the second mapping relationship, the third mapping relationship and the fourth mapping relationship. The first mapping relationship reflects a correspondence between a system-level power supply identifier of the chip and system-level power supply pin information; the second mapping relationship reflects a correspondence between a module-level power supply identifier of the chip and module-level power supply pin information; the third mapping relationship reflects a correspondence between state information corresponding to the module-level power supply identifier of the chip and state information corresponding to the system-level power supply identifier; and the fourth mapping relationship reflects a correspondence between the module-level power supply identifier of the chip and voltage information.

[0248] In an embodiment, when generating the first mapping relationship, the first determination unit is specifically configured to: obtain, from the UPF information, a system-level power supply identifier corresponding to a system-level power supply pin identifier of a system-level power supply; obtain, according to a first instance identifier of a first instance corresponding to the function module identifier and the system-level power supply pin identifier, a system-level power supply pin address name of the first instance; and generate the first mapping relationship according to the system-level power supply identifier and the system-level power supply pin address name of the first instance.

[0249] In an embodiment, when generating the second mapping relationship, the first determination unit is specifically configured to: obtain, from the UPF information, a first module-level power supply identifier corresponding to any target function module; determine a second module-level power supply identifier of the chip according to a target function module identifier of the target function module and the first module-level power supply identifier; determine a module-level power supply pin address name of a second instance corresponding to the target function module identifier according to a second instance identifier of the second instance and the first module-level power supply identifier; and generate the second mapping relationship according to the second module-level power supply identifier and the module-level power supply pin address name of the second instance.

[0250] In one embodiment, when generating the third mapping relationship, the first determining unit is specifically configured to: obtain first state information corresponding to the system-level power identifier of the system-level power supply, and second state information corresponding to the target power identifier of the target power supply in the system-level power supply, wherein the target power supply is used to supply power to the control module of the chip; obtain third state information corresponding to the target power identifier and fourth state information corresponding to the third module-level power identifier from the UPF information; wherein the third module-level power identifier is the identifier of the functional module corresponding to the third state information, and the first state information, the second state information, the third state information and the fourth state information are used to characterize the working state and output voltage of the power supply; when the second state information is consistent with the third state information, determine the fourth module-level power identifier of the chip according to the functional module identifier and the third module-level power identifier, and establish a correspondence between the fourth module-level power identifier and the fourth state information; generate the third mapping relationship according to the fourth state information and the first state information.

[0251] In one embodiment, when generating the fourth mapping relationship, the first determining unit is specifically configured to: obtain from the UPF information a first module-level power identifier corresponding to any target functional module and voltage information corresponding to the first module-level power identifier; determine a second module-level power identifier of the chip based on the target functional module identifier of the target functional module and the first module-level power identifier; and generate the fourth mapping relationship based on the second module-level power identifier and the voltage information.

[0252] In another embodiment, the first generation module 1103 includes: a first acquisition unit, a second acquisition unit, and a second generation unit. The first acquisition unit is used to acquire a fifth mapping relationship, which reflects the correspondence between the chip's system-level power identifier and a preset voltage range; the second acquisition unit is used to acquire the chip's input / output pin power information; and the second generation unit is used to generate a UPF file for the chip based on the UPF information, the fifth mapping relationship, and the input / output pin power information.

[0253] In yet another embodiment, the first generation module 1103 includes: a third acquisition unit, a fourth acquisition unit, a third generation unit, an output unit, and a fourth generation unit, wherein:

[0254] The third acquisition unit is used to acquire the voltage information of the first system-level power supply from the UPF information; the first system-level power supply is any one of the multiple system-level power supplies.

[0255] The fourth acquisition unit is used to acquire the preset voltage information of the first system-level power supply;

[0256] a third generation unit, configured to generate a UPF file of the chip based on the UPF information in a case where the voltage information of the first system-level power supply matches the preset voltage information;

[0257] an output unit, configured to output indication information in a case where the voltage information of the first system-level power supply does not match the preset voltage information; a fourth generation unit, configured to obtain modified UPF information in a case where the modification of the UPF information is completed, and generate a UPF file of the chip based on the modified UPF information; wherein the indication information is used to indicate that the voltage information of the first system-level power supply in the UPF information is modified.

[0258] In one embodiment, the first determination module 1101 is specifically configured to: determine, according to the first correspondence relationship, an instance identifier corresponding to each system-level power supply of the chip; and determine, according to the second correspondence relationship, a functional module identifier corresponding to the instance identifier corresponding to each system-level power supply.

[0259] The modules in the above generation apparatus of the unified power supply format UPF file can be all or partially implemented by software, hardware, and combinations thereof. The modules can be embedded in or independent of a processor in a computer device in a hardware form, or can be stored in a memory in the computer device in a software form, so as to be called and executed by a processor to perform operations corresponding to the modules.

[0260] In one exemplary embodiment, a computer device is provided, which can be a server, and an internal structure diagram of the computer device can be as shown in Figure 12 The computer device includes a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store data required for generation of the unified power supply format UPF file. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a generation method of the unified power supply format UPF file.

[0261] Those skilled in the art can understand that Figure 12The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0262] In an exemplary embodiment, a computer device is provided, comprising a memory and a processor, the memory storing a computer program, and the processor implementing the method of the above-mentioned embodiments of the present application when executing the computer program.

[0263] In an embodiment, a computer readable storage medium is provided, storing a computer program, and the computer program being executed by a processor to implement the method of the above-mentioned embodiments of the present application.

[0264] In an embodiment, a computer program product is provided, comprising a computer program, and the computer program being executed by a processor to implement the method of the above-mentioned embodiments of the present application.

[0265] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0266] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0267] The above-described embodiments are merely illustrative of several embodiments of the present application, and the description is relatively specific and detailed, but should not be understood as a limitation on the scope of the patent. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method for generating a Unified Power Format (UPF) file, characterized in that, The method includes: Based on the first and second correspondence relationships of the chips, the functional module identifiers under the instance corresponding to the system-level power supply are determined; wherein, the first correspondence relationship includes the correspondence between the instance and the system-level power supply, and the second correspondence relationship includes the correspondence between the instance and each functional module; Based on the functional module identifier, obtain the UPF information of the corresponding functional module; The UPF file for the chip is generated based on the UPF information.

2. The method according to claim 1, characterized in that, The process of generating the UPF file for the chip based on the UPF information includes: Based on the UPF information, a first mapping relationship, a second mapping relationship, a third mapping relationship, and a fourth mapping relationship are determined; Based on the first mapping relationship, the second mapping relationship, the third mapping relationship, and the fourth mapping relationship, the UPF file of the chip is generated; Wherein, the first mapping relationship reflects the correspondence between the system-level power identifier and the system-level power pin information of the chip; the second mapping relationship reflects the correspondence between the module-level power identifier and the module-level power pin information of the chip; the third mapping relationship reflects the correspondence between the status information corresponding to the module-level power identifier and the status information corresponding to the system-level power identifier of the chip; and the fourth mapping relationship reflects the correspondence between the module-level power identifier and the voltage information of the chip.

3. The method according to claim 2, characterized in that, Determining the first mapping relationship based on the UPF information includes: From the UPF information, obtain the system-level power pin identifier corresponding to the system-level power identifier of the system-level power supply; Based on the first instance identifier of the first instance corresponding to the functional module identifier and the system-level power pin identifier, the system-level power pin address name of the first instance is determined; The first mapping relationship is generated based on the system-level power identifier and the system-level power pin address name of the first instance.

4. The method according to claim 2, characterized in that, Determining the second mapping relationship based on the UPF information includes: From the UPF information, obtain the first module-level power identifier corresponding to any target functional module; The second module-level power identifier of the chip is determined based on the target function module identifier and the first module-level power identifier. Based on the second instance identifier of the second instance corresponding to the target functional module identifier and the first module-level power identifier, determine the module-level power pin address name of the second instance; The second mapping relationship is generated based on the second module-level power identifier and the module-level power pin address name of the second instance.

5. The method according to claim 2, characterized in that, The step of determining the third mapping relationship based on the UPF information includes: The system obtains the first status information corresponding to the system power identifier of the system power supply and the second status information corresponding to the target power identifier of the target power supply in the system power supply, wherein the target power supply is used to supply power to the control module of the chip. From the UPF information, obtain the third state information corresponding to the target power identifier and the fourth state information corresponding to the third module-level power identifier; wherein, the third module-level power identifier is the identifier of the functional module corresponding to the third state information, and the first state information, the second state information, the third state information and the fourth state information are used to characterize the working state and output voltage of the power supply; When the second state information is consistent with the third state information, the fourth module-level power identifier of the chip is determined according to the functional module identifier and the third module-level power identifier, and a correspondence between the fourth module-level power identifier and the fourth state information is established. The third mapping relationship is generated based on the fourth state information and the first state information.

6. The method according to claim 2, characterized in that, The step of determining the fourth mapping relationship based on the UPF information includes: From the UPF information, obtain the first module-level power identifier and the voltage information corresponding to the first module-level power identifier for any target functional module. The second module-level power identifier of the chip is determined based on the target function module identifier and the first module-level power identifier. The fourth mapping relationship is generated based on the second module-level power identifier and the voltage information.

7. The method according to any one of claims 1-6, characterized in that, The process of generating the UPF file for the chip based on the UPF information includes: Obtain the fifth mapping relationship, which reflects the correspondence between the chip's system-level power identifier and the preset voltage range; Obtain the power supply information of the chip's input and output pins; Based on the UPF information, the fifth mapping relationship, and the input / output pin power information, the UPF file of the chip is generated.

8. The method according to claim 1, characterized in that, Before the step of generating the UPF file for the chip based on the UPF information, the method further includes: The voltage information of the first system-level power supply is obtained from the UPF information; the first system-level power supply is any one of the multiple system-level power supplies. Obtain the preset voltage information of the first system-level power supply; If the voltage information of the first system-level power supply matches the preset voltage information, a UPF file for the chip is generated based on the UPF information; If the voltage information of the first system-level power supply does not match the preset voltage information, an indication message is output; and if the UPF information is modified, the modified UPF information is obtained, and a UPF file of the chip is generated based on the modified UPF information; wherein, the indication message is used to indicate that the voltage information of the first system-level power supply in the UPF information is modified.

9. The method according to claim 1, characterized in that, The step of determining the functional module identifier under the instance corresponding to the system-level power supply based on the first and second correspondence relationships of the chips includes: Based on the first correspondence, determine the instance identifier corresponding to each system-level power supply of the chip; Based on the second correspondence, determine the functional module identifier corresponding to the instance identifier of each system-level power supply.

10. An apparatus for generating a Unified Power Format (UPF) file, characterized in that, The device includes: The first determining module is used to determine the functional module identifier under the instance corresponding to the system-level power supply based on the first correspondence relationship and the second correspondence relationship of the chip; wherein, the first correspondence relationship includes the correspondence relationship between the instance and the system-level power supply, and the second correspondence relationship includes the correspondence relationship between the instance and each functional module; The first acquisition module is used to acquire the UPF information of the corresponding functional module based on the functional module identifier; The first generation module is used to generate the UPF file of the chip based on the UPF information.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 9.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 9.

Images