Novel chip verification automatic regression method and program product
By providing automated regression script tools for chip verification, the problem of low efficiency in the traditional chip verification regression stage is solved, realizing an efficient and reliable regression process, and improving the iteration efficiency and accuracy of chip design results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU HUACHUANG MICROSYSTEM CO LTD
- Filing Date
- 2025-12-11
- Publication Date
- 2026-04-10
AI Technical Summary
Traditional chip verification regression phases are inefficient, time-consuming, involve many repetitive operations, consume a lot of manpower, and affect the efficiency of verification iterations.
This invention provides a novel automated regression script tool for chip verification. It reads the regression test case list, simulation configuration, and compilation rules, creates a directory structure, automatically executes regression test cases, records execution information in real time, saves files in categories, automatically judges test case results, and supports a multi-task locking mechanism to prevent process conflicts.
It significantly improves the efficiency and reliability of the chip verification regression stage, realizes the standardization and automation of the regression process, shortens the verification cycle, reduces labor costs, and improves the iteration efficiency of chip design.
Smart Images
Figure CN121835534A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip verification, in particular to a novel chip verification automatic regression method and program product. BACKGROUND
[0002] With the continuous evolution of technologies such as the Internet of Things, MCU chip design is rapidly developing in China, the design complexity of MCU chips is continuously improving, and the project development cycle is increasingly tight, which puts higher requirements on the standardization and process of chip verification. Therefore, pursuing higher efficiency in the verification process is a long-term task for chip verification personnel. In the process of chip function verification, a test platform based on systemverilog is usually used, and a large number of software test cases are used for rtl function verification. After the simulation of the test cases is completed, the chip verification enters the regression stage. In this stage, all test cases are simulated again to ensure that all functions of the latest version of the rtl code are tested and covered, and the verification personnel can still find design bugs in the regression. However, due to the large number of test cases, if only manual regression is performed and the results are checked one by one, a lot of time and manpower will be consumed, which will seriously affect the verification iteration efficiency. Therefore, in the verification regression stage, an efficient and reliable automatic regression script tool is needed to assist verification personnel to quickly complete regression testing and result analysis, thereby accelerating the positioning of design problems and the iteration of rtl code, and further shortening the chip marketing cycle. SUMMARY
[0003] The present application solves the problems of low regression efficiency, time-consuming, repeated operation, and consumption of manpower in the traditional verification process. Therefore, a novel chip verification automatic regression script tool is proposed to standardize the regression process and improve the efficiency of the verification process.
[0004] The present application provides a novel chip verification automatic regression method, comprising the following steps:
[0005] S1: reading the regression case list, simulation configuration, and compilation rules; creating multiple directories for storing different types of record files;
[0006] S2: reading the content of each regression case in turn according to the content of the regression case list; reading and executing the corresponding file according to the content of each regression case;
[0007] S3: when all regression cases in the regression case list are executed, recording the information of all regression cases in the total log file.
[0008] Preferably, in step S2,
[0009] The execution process information is displayed in real time to the user through the terminal and recorded in a total log file.
[0010] Preferably, the record files generated during the execution process are classified and saved in corresponding folders.
[0011] Preferably, whether the check result of each regression use case is passed or failed is determined through preset keywords.
[0012] Preferably, when the execution time of a single regression use case exceeds a preset time length, the regression use case is automatically skipped and recorded in the total log file.
[0013] The application further provides a computer program product comprising a computer program, wherein the computer program is executed by a processor to implement the method.
[0014] Advantages:
[0015] The application has the advantages of significantly improving the efficiency and reliability of the chip verification regression phase. The temporary files (record files) are automatically classified and saved, and a clear directory structure is established, which greatly facilitates the review and management of logs and results. The timeout case is automatically identified to avoid blocking the overall regression progress due to individual case lag. The script also supports a multi-task locking mechanism to prevent process conflict and interference and ensure accurate results. The flexible parameter configuration adapts to the needs of different verification scenarios.
[0016] Overall, the script tool realizes the standardization and automation of the regression process, effectively shortens the verification period, reduces labor costs, and improves the iteration efficiency of chip design. BRIEF DESCRIPTION OF DRAWINGS
[0017] Fig. 1 The flowchart of the application is shown in the figure.
[0018] Fig. 2 The directory structure of the application is shown in the figure. DETAILED DESCRIPTION
[0019] In order to make the purpose, features and advantages of the application more obvious and easy to understand, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of the application.
[0020] As Figs. 1-2As shown, a novel automated regression method for chip verification includes the following steps:
[0021] S1: Read the regression test case list, simulation configuration, and compilation rules; create multiple directories to store different types of log files.
[0022] In this embodiment, the regression test case list, simulation configuration, and compilation rules read are case.lst, single.cfg, and Makefile, respectively; the created directory includes a sim_batch folder as the main directory, which is used to store all log files, and multiple subfolders are created in the sim_batch folder, namely log, fsdb, cov, and uart_log, which are used to store logs, UART print logs, waveform files, and coverage, respectively;
[0023] S2: Based on the list of regression test cases, read the content of each regression test case in sequence; based on the content of each regression test case, read the corresponding file and execute it;
[0024] The execution process information is displayed to the user in real time through the terminal, and the execution process information is recorded in the master log file;
[0025] Log files generated during execution are categorized and saved to their corresponding folders.
[0026] The system uses preset keywords to determine whether the check result for each regression test case is pass or fail; the preset keywords include uvm fatal and warning.
[0027] If the execution time of a single regression test case exceeds the preset duration, the regression test case will be automatically skipped and recorded in the master log file.
[0028] In this embodiment, the case name, macro definitions, and other information for each regression test case are read from case.lst. Then, based on this information, the corresponding C case file is recursively searched for in the specified software directory to execute the regression test case. After each regression test case is executed, the generated log files compile.log, sim.log, uart.log, sim_soc.fsdb, and sim_soc.vdb are stored in the log (log file), uart.log (UART print log), fsdb (waveform file), and cov (coverage) folders, respectively. The total log file is reg.log, stored in the sim_batch folder. If multiple regression test cases read the same C case file simultaneously, a locking state is generated, which avoids mutual interference during the compilation process and prevents misleading results from erroneous simulations.
[0029] S3: Once all regression test cases in the regression test case list have been executed, record the information of all regression test cases in the master log file.
[0030] In this embodiment, the above method is implemented in the form of a script tool, i.e., a program product.
[0031] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A novel automated regression method for chip verification, characterized in that, Includes the following steps: S1: Read the regression test case list, simulation configuration, and compilation rules; create multiple directories to store different types of log files. S2: Based on the list of regression test cases, read the content of each regression test case in sequence; based on the content of each regression test case, read the corresponding file and execute it; S3: Once all regression test cases in the regression test case list have been executed, record the information of all regression test cases in the master log file.
2. The novel automated regression method for chip verification according to claim 1, characterized in that, In step S2, The execution process information is displayed to the user in real time through the terminal, and the execution process information is recorded in the master log file.
3. The novel automated regression method for chip verification according to claim 1, characterized in that, In step S2, Log files generated during the execution process are categorized and saved to their respective folders.
4. The novel automated regression method for chip verification according to claim 1, characterized in that, In step S2, The system uses preset keywords to determine whether each regression test case passes or fails.
5. A novel automated regression method for chip verification according to claim 1, characterized in that, In step S2, If the execution time of a single regression test case exceeds the preset duration, the regression test case will be automatically skipped and recorded in the master log file.
6. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the method described in any one of claims 1 to 5.