Register description file generation method and program product
By automating the extraction of register description files, the problems of low extraction and management efficiency and inconsistent formats in existing technologies are solved, achieving efficient and accurate generation of register description files and improving the quality and efficiency of chip verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JIANGSU HUACHUANG MICROSYSTEM CO LTD
- Filing Date
- 2025-12-17
- Publication Date
- 2026-04-10
AI Technical Summary
In existing technologies, the extraction and management of register description files are inefficient, prone to errors, and have inconsistent formats, which affects the quality and efficiency of chip verification.
The automated script extracts register description files from IP datasheets, including reading module information, register lists, and function descriptions, calculating read/write mask bits, generating a specification-compliant description file, and saving it as macro definitions and test functions.
This improves the efficiency of register description file extraction, ensures file accuracy and format consistency, and enhances the quality of chip verification and collaborative work efficiency.
Smart Images
Figure CN121835535A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip verification, and in particular to a register description file generation method and program product. BACKGROUND
[0002] In current system-level chip design, integrating various mature IPs to shorten the research and development cycle has become the mainstream trend in the industry. The register of integrated IP is the core interface for software configuration hardware and verification scenario control, and the accuracy of its description file directly affects the quality of verification, which is a key prerequisite for IP integration verification.
[0003] Current system-level chips often integrate dozens or even hundreds of IPs, which may come from third-party suppliers, historical project reuse, or cross-team development, resulting in the following problems with register description files: First, the description format is fragmented. The register information provided by the IP is mostly in the data manual, but the description format of specific register names, types, domain segments, etc. is quite different, which makes it impossible to form a standard register description file for subsequent register verification. Second, the register information is incomplete. Some IPs may come from historical projects, and their data manuals may be incomplete, missing key information such as register type, reset value, and function description. Third, version management is cumbersome. Some self-developed IPs may have multiple versions before the demand stabilizes, and each version update requires alignment of the register description file. To address the above problems, current register description file extraction and management usually relies on manual writing. However, manual extraction is inefficient, difficult to manage, and prone to errors due to minor calculation mistakes. Therefore, a new technical solution is needed to automatically and accurately extract the register description file of integrated IP cores and ensure its consistency and accuracy, thereby improving the efficiency and quality of chip verification. SUMMARY
[0004] Objective: The present application provides an efficient and accurate integrated IP register description file extraction method and system, which solves the problems of low efficiency, easy errors, and inconsistent formats in existing register description file extraction and management.
[0005] A register description file generation method, comprising the following steps:
[0006] S1: According to the user-specified address, read the IP data manual; find the register description chapter from the IP data manual; if the register description chapter is not found, prompt the user to re-specify the address of the IP data manual;
[0007] S2: Read the module information from the content of the register description chapter;
[0008] S3: According to the module information, extract the register list of each module; according to the register list, read the function description content of each register;
[0009] According to the function description content of each register, calculate the read-write mask bit of each register;
[0010] S4: According to the obtained all information of the register, generate a register description file conforming to the chip verification process specification.
[0011] Preferably, the module information includes the number of modules, and the name, base address and offset address of each module.
[0012] Preferably, the function description content includes register bit field, bit field name, bit width, initial value and access type.
[0013] Preferably, in step S4, the register address information is saved in the form of macro definition as a separate file.
[0014] Preferably, in step S4, the register test function is generated according to the obtained all information of the register, and saved as a separate file.
[0015] The application also provides a computer program product comprising a computer program, which, when executed by a processor, implements the above method.
[0016] Advantages:
[0017] 1. Improve the extraction efficiency: by automatically extracting the register description file, the workload of manual writing is reduced, the efficiency of the extraction process is greatly improved, and the chip verification period is shortened.
[0018] 2. Ensure the accuracy of the file: by parsing the IP data manual data and verifying, the completeness and correctness of the extracted register description file content are ensured, and the verification error caused by human error is effectively reduced.
[0019] 3. Unified file format and content: provide a standardized register description file format, ensure the consistency of the files extracted from different IPs, facilitate the unified management of the verification tools and processes, and improve the collaborative work efficiency of the verification process. BRIEF DESCRIPTION OF DRAWINGS
[0020] Figure 1 The flow structure diagram of the application; DETAILED DESCRIPTION
[0021] In order to make the objectives, characteristics and advantages of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the embodiments described below are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.
[0022] As shown in Figure 1 a register description file generation method, comprising the following steps:
[0023] S1: reading an IP data manual according to a user-specified address; searching for a register description chapter from the IP data manual; if the register description chapter is not found, prompting the user to re-specify the address of the IP data manual;
[0024] S2: reading module information from the content of the register description chapter; the module information includes the number of modules, and the name, base address and offset address of each module;
[0025] S3: extracting the register list of each module according to the module information; reading the function description content of each register according to the register list, the function description content including the register bit field, bit field name, bit width, initial value and access type; the function description content of the register is usually recorded in the form of a register function description table in the IP data manual;
[0026] calculating the read-write mask bit of each register according to the function description content of each register;
[0027] S4: generating a register description file conforming to the chip verification flow specification according to all the information of the obtained registers;
[0028] As a further implementation, the register address information is saved in the form of a macro definition as a separate file;
[0029] As a still further implementation, a register test function is also generated according to all the information of the obtained registers and saved as a separate file.
[0030] In the above steps, if a step fails to read, the process returns to the initial step and prompts the user to input the correct IP data manual address.
[0031] One possible implementation form of the above register description file generation method is an automated extraction script, i.e., a program product.
[0032] The above merely describes the preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, several improvements and refinements can be made without departing from the principles of the present application, and these improvements and refinements should also be considered as falling within the protection scope of the present application.
Claims
1. A method for generating a register description file, characterized in that, Includes the following steps: S1: Read the IP datasheet based on the address specified by the user; locate the register description section in the IP datasheet; if the register description section is not found, prompt the user to specify the address of the IP datasheet again; S2: Read module information from the register description section; S3: Extract the register list of each module based on the module information; read the function description of each register based on the register list; Calculate the read / write mask bits for each register based on its functional description. S4: Based on all the information obtained from the registers, generate a register description file that conforms to the chip verification process specifications.
2. The register description file generation method according to claim 1, characterized in that, The module information includes the number of modules, as well as the name, base address, and offset address of each module.
3. The method for generating a register description file according to claim 1, characterized in that, The functional description includes register bit fields, bit field names, bit widths, initial values, and access types.
4. The method for generating a register description file according to claim 1, characterized in that, Step S4 also includes: saving the register address information in the form of macro definitions as a separate file.
5. The method for generating a register description file according to claim 1, characterized in that, Step S4 also includes: generating a register test function based on all the information obtained from the registers, and saving it as a separate file.
6. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the method described in any one of claims 1 to 5.