Electronic chip layout and wiring method based on generative model

Abstract

The invention discloses an electronic chip layout and wiring method based on a generative model. The electronic chip layout and wiring method comprises the following steps: step 1, collecting preliminary topological data of electronic chip design to construct a preliminary chip topological graph; 2, setting a multi-target optimization target initialization topology dynamic constraint; step 3, carrying out feature extraction on the circuit topology of the chip through a GraphSAGE network; 4, inputting the structure perception feature set and the topology dynamic constraint into an improved DBM model to obtain a preliminary layout and wiring scheme; 5, optimizing the preliminary layout and wiring scheme through a differential evolution algorithm; step 6, carrying out region identification and equalization on the differential layout wiring scheme; and 7, carrying out global optimization on the local optimization layout scheme to obtain an electronic chip layout and wiring scheme. Through the improved DBM model, the layout and wiring efficiency and the design quality of the electronic chip are improved.

Description

Technical Field

[0001] This invention relates to the field of chip layout optimization technology, and in particular to an electronic chip layout and routing method based on a generative model. Background Technology

[0002] With the rapid development of integrated circuit (IC) technology, the complexity and functionality of chips are increasing daily, especially in fields such as high-performance computing, storage, and communication, making electronic chip design increasingly challenging. One of the core aspects of chip design is routing and placement optimization. Routing not only directly affects chip area, power consumption, and signal transmission speed, but also significantly impacts key performance indicators such as signal integrity and clock synchronization. However, traditional placement and routing methods often rely on manual design experience or rule-based optimization algorithms. These methods struggle to fully consider multi-objective optimization requirements when facing complex chip design needs, and are inefficient in large-scale designs, often leading to suboptimal solutions or unsatisfactory optimization results. Most existing electronic chip placement and routing methods are based on traditional optimization methods such as heuristic algorithms, genetic algorithms, and simulated annealing algorithms. While these methods have achieved some success on certain specific problems, they typically rely on extensive computation and iterative exploration, requiring significant computational resources and time. This computational overhead increases dramatically, especially in complex chip designs. Traditional methods often handle chip placement optimization and routing optimization separately, which prevents the full consideration of the interaction between placement and routing during the optimization process, thus hindering the search for the optimal solution.

[0003] Signal interference, power consumption, and thermal density are becoming increasingly important in chip design, and traditional methods struggle to adequately balance these constraints under multi-objective optimization. For example, excessive wiring density can lead to increased signal interference, while longer wiring paths can cause signal transmission delays, affecting clock synchronization performance. Traditional methods often lack a comprehensive consideration of these issues, making it difficult to guarantee signal integrity and clock synchronization. Furthermore, existing technologies largely rely on manual or semi-automated methods for design adjustment and optimization, lacking intelligent and automated optimization strategies, resulting in low design efficiency and accuracy. Although optimization methods based on machine learning and generative models have emerged in recent years, their application is still in its early stages, and most techniques are limited to optimizing only one aspect, making it difficult to achieve comprehensive optimization of multiple objectives such as signal integrity, wiring density, and clock synchronization.

[0004] Therefore, how to provide a method for electronic chip layout and routing based on a generative model is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] One objective of this invention is to propose a generative model-based electronic chip placement and routing method. This invention improves the efficiency and accuracy of electronic chip placement and routing through a multi-objective optimization method based on a generative model. Combining GraphSAGE network feature extraction and an improved DBM model, it can simultaneously optimize multiple design objectives such as signal integrity, routing density, clock synchronization, and power consumption, automatically generating high-quality placement schemes. Differential evolutionary algorithms are used to optimize routing schemes, avoiding local optima problems. Simultaneously, the local optimization mechanism effectively solves signal interference and routing congestion, achieving efficient, intelligent, and automated chip design.

[0006] An electronic chip placement and routing method based on a generative model according to an embodiment of the present invention includes the following steps: Step 1: Collect preliminary topology data for the electronic chip design, and construct a preliminary chip topology diagram for each circuit element node; Step 2: Based on the preliminary chip topology diagram, initialize the topology dynamic constraints of the electronic chip design by setting multi-objective optimization objectives; Step 3: Input the topological dynamic constraints of the electronic chip design into the structure-aware encoder. The encoder GraphSAGE network extracts features from the circuit topology of the chip and generates a structure-aware feature set for each node. Step 4: Input the structure-aware feature set and topology dynamic constraints into the improved DBM model, and obtain the preliminary layout and routing scheme of the electronic chip through the feature encoder, layout candidate generation module, dynamic constraint optimization module and layout and routing scheme generation module. Step 5: Optimize the preliminary layout and routing scheme using a differential evolution algorithm to obtain the differential layout and routing scheme for the electronic chip; Step 6: Perform region identification on the differential layout routing scheme to obtain a local region identification set, and perform averaging to obtain a local optimized layout scheme; Step 7: Perform global optimization on the local optimization layout scheme, and integrate signal integrity, wiring density and clock synchronization to obtain the final electronic chip layout and routing scheme.

[0007] Optionally, step one specifically includes: Collect information on circuit elements in chip design, including logic gates, memory cells, and input / output interfaces, specifically including: Obtain information on the type, function, and physical dimensions of each circuit element in the chip design; Collect the electrical characteristics of each circuit element, including resistance, capacitance, and power consumption parameters; Obtain the interface type and electrical connection method for each circuit component; Each circuit element is considered a node, and the electrical connections between nodes are represented by edges. Specifically, these include: Each circuit element in the chip is treated as a node in the initial chip topology diagram. The electrical connection between nodes is represented by edges, and the weight of the edge is the weighted sum of the signal transmission delay rate and the current intensity according to preset weights. Construct each electrical connection in the circuit and record the direction of each connection; Obtain the geometrical occupancy area of ​​each circuit element in the chip design, wherein the geometrical occupancy area includes the actual space occupation and shape of each circuit element in the chip layout; Obtain layout constraints, which include the minimum and maximum spacing between each element; Collect power consumption requirements related to circuit elements, including the maximum power consumption and thermal management limits for each circuit element; The collected circuit element information, electrical connection relationships, and layout constraints are integrated to generate a preliminary chip topology diagram.

[0008] Optionally, step two specifically involves: Based on the circuit element layout and electrical connection relationship in the preliminary chip topology diagram, the signal crossings of the electronic chip are determined, and signal crossing constraints are set based on the distance and electrical characteristics between the circuit elements. Based on the layout of the clock network in the circuit, set clock synchronization constraints; Power consumption constraints are set based on the power consumption characteristics of each circuit element in the chip design, and heat density distribution analysis is performed based on the heat generated by each circuit element during operation to limit the overall heat density of the chip. Based on the electrical characteristics and layout of circuit components, signal interference constraints are set to obtain the topological dynamic constraints for electronic chip design.

[0009] Optionally, step three specifically includes: The topological dynamic constraints of the electronic chip design are input into the neighborhood sampling layer of the GraphSAGE network, and each node randomly samples a fixed number of neighboring nodes from the neighborhood for feature aggregation. At each node, the features from neighboring nodes are aggregated by averaging the features of the neighboring nodes to obtain the neighborhood sampling feature set; The neighborhood sampled feature set is input into the feature update layer. At each node, the sampled neighborhood features are fused with the node's own features and updated through a linear transformation of the fully connected layer to obtain the updated node feature set. The updated node feature set is input into a multi-layer information fusion layer. Neighborhood sampling and feature updates are performed in each layer, and the node features output by each layer are used as the input of the next layer. At each layer, information from neighboring nodes is aggregated and further fused and updated in combination with the node features of the previous layer. Nonlinear transformation is performed through an activation function to obtain structure-aware features, which include the position of each circuit element in the entire circuit topology, signal transmission characteristics, and electrical and geometric characteristics of power consumption. The structure-aware feature set is obtained by combining the structure-aware features of all nodes.

[0010] Optionally, the improved DBM model is specifically as follows: The structure-aware feature set and topological dynamic constraints are input into the feature encoder, which cyclically transmits information between nodes through a recurrent neural network to obtain a node feature representation set. The node feature representation set is input into the layout candidate generation module, and multiple layout candidates are generated by the generative adversarial encoder, specifically including: A generator is used to generate a preliminary layout scheme based on node characteristics and electrical constraints, and a discriminator is used to judge the preliminary layout scheme. Optimize the signal interference and wiring density in the layout candidates according to the constraints until each layout candidate meets the design constraints; The various objectives of the candidate layouts are optimized until each layout scheme achieves a balance in power consumption, signal integrity, and wiring length, resulting in a set of candidate layout schemes. The set of candidate layout schemes is input into the dynamic constraint optimization module, and the dynamic constraint optimized layout set is obtained through the constraint adjustment mechanism. The dynamic constraint optimized layout set is input into the layout and routing scheme generation module, and the circuit elements in the dynamic constraint optimized layout set are initially located according to functional and space requirements; by identifying the type of circuit element, its space occupation area in the chip layout is determined, and a preliminary layout and positioning scheme is obtained. Based on the preliminary layout and positioning scheme, preliminary connection lines are generated between circuit components to connect all components that require signal transmission; The Dijkstra algorithm is used to calculate the optimal signal transmission path between each pair of circuit elements, and a preliminary layout and wiring scheme for the electronic chip is obtained.

[0011] Optionally, the constraint adjustment mechanism specifically includes: Obtain the preliminary layout constraints from the candidate layout schemes; The initial layout constraints are set as the initial state and correspond one-to-one with the current layout scheme to obtain the initial constraint set, which includes all design constraints in the initial layout scheme. For each layout that does not meet the constraints, dynamic adjustments are made, and the constraints for dynamic adjustment include: If the wiring density in a region exceeds a preset density threshold, the density in that region can be reduced by adjusting the position of circuit components in the layout or by introducing more wiring layers. If the signal interference exceeds the preset interference threshold, the layout and wiring path of the signal components will be adjusted according to the signal transmission path and clock synchronization requirements. If the chip's power consumption or heat density exceeds the set limit, adjust the position of the component with the highest power consumption; If the transmission delay of the clock signal is greater than a preset delay threshold, then the clock network wiring is required. Real-time feedback is provided for each adjusted constraint to obtain a dynamic constraint optimization layout set, which includes the optimized layout scheme and constraint conditions.

[0012] Optionally, step five specifically includes: Based on the layout data in the preliminary layout and routing scheme, initialize the population of the differential evolution algorithm. Each individual in the population represents a layout scheme, and the initial layout population is obtained. The initial layout population includes the position, routing path and power consumption of each circuit element. In each generation, new individuals are generated through mutation operations of the differential evolution algorithm. The mutation operation involves randomly selecting three individuals from the population, selecting two parent individuals, calculating the differences between them, and adding them to the genes of the third individual to generate new mutated individuals. Each mutated individual will generate a new layout scheme, resulting in a set of mutated layout schemes. The individuals in the mutated layout scheme set are cross-crossed with other individuals in the population. The cross-crossing operation is performed by selecting two individuals through single-point cross-crossing to exchange their features, thereby generating a cross-crossed layout scheme set. The single-point cross-crossing is to randomly select a cross-crossing point from the parent layout scheme and exchange the wiring path and component position information. Repeat the iteration until the maximum number of generations is reached to obtain the differential layout and routing scheme of the electronic chip.

[0013] Optionally, step six specifically includes: Based on the differential layout cabling scheme, the cabling path is analyzed to identify areas in the signal transmission path where there is interference, congestion, or delay. By calculating the spatial density of each wiring path, areas where the wiring density or number of paths exceeds a preset threshold are identified. Signal crosstalk analysis identifies areas in the layout that cause signal interference, including signal path intersections and electrical interference between adjacent signal lines. The local region identification set is obtained by summing up all identified regions; The mean value processing is performed on each local region in the local region identification set to obtain a local optimized layout scheme. The mean value processing is as follows: for each local region, the characteristic mean value of all wiring paths is calculated, including wiring length, signal delay, power consumption and wiring density. Based on the average value of each local area, adjust the spatial distribution of circuit components and wiring paths within the corresponding local area.

[0014] Optionally, step seven specifically includes: Based on the analysis of signal interference, attenuation and reflection problems in the wiring path based on the local optimization layout scheme, for areas where the signal integrity is lower than the preset threshold, the signal transmission is optimized by adjusting the signal path, and a global signal optimization layout scheme is obtained. A wiring density analysis is performed on the global signal optimization layout scheme to identify areas where the wiring density is greater than a preset threshold and the signal intersection and component spacing are less than a preset threshold. The relative positions of the circuit components are then adjusted to obtain the global wiring density optimization layout scheme. The clock signal transmission of the global wiring density optimization layout scheme is analyzed, the delay difference of the clock signal in different areas is checked, and the path of the clock signal is adjusted until the transmission delay of the clock signal from the source node to the target node is within the preset range, so as to obtain the final electronic chip layout and wiring scheme.

[0015] The beneficial effects of this invention are: This invention significantly improves the efficiency and accuracy of layout and routing optimization in electronic chip design by introducing a generative model-based electronic chip placement and routing method. Unlike traditional heuristic algorithms or single-objective optimization methods, this invention can simultaneously handle multiple complex design objectives, such as signal integrity, routing density, clock synchronization, and power consumption. By introducing multi-objective optimization, designers no longer need to compromise between various optimization objectives, thus achieving a more balanced and globally optimal placement and routing scheme. Feature extraction based on the GraphSAGE network accurately captures the structure-aware features of the circuit topology, providing precise data support for subsequent optimization and making the layout scheme more in line with actual design requirements. Utilizing an improved DBM model, this invention introduces multiple optimization modules, including a feature encoder, a layout candidate generation module, a dynamic constraint optimization module, and a placement and routing scheme generation module. The combination of these modules enables the design process to be completed automatically and efficiently without extensive manual intervention. The differential evolution algorithm fully leverages the advantages of population mutation, crossover, and selection operations during the layout scheme optimization process, quickly finding the globally optimal solution in a large-scale design space, avoiding the local optima problem common in traditional methods.

[0016] To address issues such as wiring congestion and signal interference, this invention provides a local area optimization mechanism. This mechanism identifies potential problems in local areas and makes fine-tuning adjustments, effectively avoiding issues like signal transmission delay and crosstalk. Furthermore, power consumption and thermal density in the layout are effectively controlled, ensuring thermal management and stability of the chip during operation. Finally, through a global optimization module, multiple factors such as signal integrity, wiring density, and clock synchronization are integrated to obtain a layout and routing scheme that meets design constraints and achieves high performance. The advantage of this method is that it significantly improves the automation level of chip design, reduces the workload of designers, and shortens the design cycle. Because it can simultaneously optimize multiple design goals, it greatly improves the design quality and reliability of the chip, and also provides an efficient solution for the design of complex chips, possessing high practical value and broad application prospects. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0018] Figure 1 This is an overall flowchart of an electronic chip placement and routing method based on a generative model proposed in this invention. Figure 2 This is a schematic diagram of the improved DBM model processing steps of the electronic chip placement and routing method based on the generative model proposed in this invention. Figure 3 This is a flowchart illustrating the generation process of a dynamically constrained optimization layout set for an electronic chip layout and routing method based on a generative model, as proposed in this invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0020] refer to Figure 1-3 A method for electronic chip placement and routing based on a generative model includes the following steps: Step 1: Collect preliminary topology data for the electronic chip design, and construct a preliminary chip topology diagram for each circuit element node; Step 2: Based on the preliminary chip topology diagram, initialize the topology dynamic constraints of the electronic chip design by setting multi-objective optimization objectives; Step 3: Input the topological dynamic constraints of the electronic chip design into the structure-aware encoder. The encoder GraphSAGE network extracts features from the circuit topology of the chip and generates a structure-aware feature set for each node. Step 4: Input the structure-aware feature set and topology dynamic constraints into the improved DBM model, and obtain the preliminary layout and routing scheme of the electronic chip through the feature encoder, layout candidate generation module, dynamic constraint optimization module and layout and routing scheme generation module. Step 5: Optimize the preliminary layout and routing scheme using a differential evolution algorithm to obtain the differential layout and routing scheme for the electronic chip; Step 6: Perform region identification on the differential layout routing scheme to obtain a local region identification set, and perform averaging to obtain a local optimized layout scheme; Step 7: Perform global optimization on the local optimization layout scheme, and integrate signal integrity, wiring density and clock synchronization to obtain the final electronic chip layout and routing scheme.

[0021] In this embodiment, step one specifically includes: Collect information on circuit elements in chip design, including logic gates, memory cells, and input / output interfaces, specifically including: Obtain the type, function, and physical dimensions of each circuit element in the chip design: The type of each circuit element may include basic logic gates (such as AND gates, OR gates, NOT gates), flip-flops, registers, memory cells (such as RAM, ROM), input / output interfaces (such as GPIO, PCIe interfaces), etc. For each element, obtain its specific functional description, such as whether it is used to perform logical operations, store data, or transmit signals. The physical dimensions of each element include its length, width, and height, typically in micrometers (μm) or millimeters (mm). For example, a logic gate might be 50μm × 50μm, and a memory cell might be 200μm × 100μm.

[0022] The electrical characteristics of each circuit element are collected, including resistance, capacitance, and power consumption parameters: resistance typically ranges from 1Ω to 10kΩ, capacitance from a few picofarads to a few nanofarads, and power consumption from a few milliwatts to tens of watts, depending on the element type and operating state. For example, a common logic gate can consume between 50mW and 200mW. These power consumption parameters are calculated based on the element's electrical operating mode and affect the overall power consumption design and thermal management of the chip.

[0023] Obtain the interface type and electrical connection method for each circuit component: Interface types include standard input / output interfaces such as USB, HDMI, PCIe, and Ethernet, each with specific electrical connection protocols and characteristics. Electrical connection methods include serial connections, parallel connections, or differential signal connections, specifically conducted through wires or copper foil to transmit electrical signals.

[0024] Each circuit element is considered a node, and the electrical connections between nodes are represented by edges. Specifically, these include: Each circuit element in the chip is treated as a node in the initial chip topology diagram, and the electrical connections between nodes are represented by edges: each circuit element (such as a logic gate, memory cell, etc.) is represented as a node, and the edges between nodes represent their electrical connections. The edge weights are calculated based on the signal transmission delay rate and current intensity, and the weighted sum of the edges is adjusted using preset weights. For example, the weight of the signal transmission delay rate is set to 0.6, the weight of the current intensity is set to 0.4, and the final weight of the edge is obtained after combining the weights.

[0025] Construct each electrical connection in the circuit and record the direction of each connection: For each pair of components in the circuit (such as the connection between two logic gates), the direction of the electrical connection needs to be clearly recorded, that is, from which component to which component the signal is transmitted. For example, the direction of data transfer from the processor to memory will be recorded as "processor → memory".

[0026] Obtain the geometrical occupancy area of ​​each circuit element in the chip design. This geometrical occupancy area includes the actual space occupied and shape of each circuit element within the chip layout: the geometrical occupancy area of ​​each circuit element represents its space requirement in the chip's physical layout. This space requirement is determined by the size and shape of the element, and may be rectangular, circular, or a custom shape. The size of the geometrical occupancy area typically ranges from tens to hundreds of micrometers, depending on the type of element and the process node.

[0027] Obtain layout constraints, including minimum and maximum spacing between components: To ensure that circuit components in the chip layout do not experience electrical interference or physical overlap, minimum and maximum spacing needs to be set between each component. The minimum spacing is typically set at the micrometer level, such as 20 μm, while the maximum spacing is set according to the specific requirements and area limitations of the chip design, and may be several millimeters.

[0028] Collect power consumption requirements related to circuit elements, including the maximum power consumption and thermal management limits for each element. The power consumption parameters and thermal management limits of each element must be considered to ensure the chip design meets thermal balance requirements. The maximum power consumption for each element is typically determined by the manufacturing process; for example, the maximum power consumption of a certain type of memory cell might be 5W, while the maximum power consumption of a logic gate might be 200mW.

[0029] The collected circuit component information, electrical connections, and layout constraints are integrated to generate a preliminary chip topology diagram: All collected circuit component information, their electrical connections, and layout constraints are comprehensively organized into a preliminary chip topology diagram. This topology diagram graphically represents the relationships between circuit components and indicates the electrical characteristics, layout space, and connection methods of each node with other components, providing a foundation for subsequent layout optimization and routing.

[0030] Through these detailed collection steps and data integration, this invention can provide a highly accurate topology map for chip design, providing comprehensive and reliable input data for subsequent optimization, and ensuring optimization of signal integrity, clock synchronization, power consumption, and other aspects of the design.

[0031] In this embodiment, step two specifically includes: Based on the circuit component layout and electrical connections in the preliminary chip topology diagram, signal crossings in the electronic chip are identified, and signal crossing constraints are set based on the distance and electrical characteristics between circuit components. In this step, the signal transmission paths in the chip are first analyzed based on the component positions and electrical connections in the preliminary chip topology diagram to determine which signal paths may cross or overlap. Signal crossings can lead to problems such as signal crosstalk and increased delay, thus affecting signal integrity. Next, constraints on signal crossings are set based on the actual distance between circuit components, signal transmission characteristics (such as signal frequency and transmission rate), and electrical characteristics (such as impedance and current). Specifically, a signal crossing constraint might be set such that a distance of less than 10 μm between signal paths is considered a signal crossing, thereby forcing layout adjustments to avoid crossing areas.

[0032] Based on the clock network layout in the circuit, clock synchronization constraints are set: clock signal transmission is a crucial factor in chip design, and clock synchronization directly affects the system's timing performance. According to the clock network layout in the circuit, the transmission path of the clock signal from the clock source to each node is analyzed to ensure that the transmission delay of all clock signals is within the allowable range, avoiding timing errors caused by excessive differences in clock path delays. The clock synchronization constraint can be set to limit the maximum delay of the clock signal to within 500ps, ensuring that the clock signal can be transmitted synchronously between all components.

[0033] Power consumption constraints are set based on the power consumption characteristics of each circuit element in the chip design. Furthermore, heat density distribution analysis is performed based on the heat generated by each circuit element during operation to limit the overall heat density of the chip. Power consumption is a crucial consideration in chip design; excessive power consumption can not only lead to overheating issues but also affect the chip's long-term stability. A maximum power consumption limit is set for each circuit element based on its power consumption characteristics. For example, the maximum power consumption might be set to 100mW for each logic gate and 500mW for a memory cell. Simultaneously, the heat density of the entire chip is analyzed based on the power consumption characteristics of the components to ensure uniform heat distribution and optimization through thermal management schemes. The heat density constraint is typically set so that the overall maximum heat density of the chip does not exceed 5W / cm², thereby avoiding thermal overload and interference with the normal operation of other components.

[0034] Based on the electrical characteristics and layout of circuit components, signal interference constraints are set to obtain the topological dynamic constraints of the electronic chip design. Signal interference is another important factor affecting chip performance; excessive interference can not only cause signal distortion but also lead to system instability. By analyzing the electrical characteristics (such as voltage, current, and impedance) and layout of circuit components, signal interference constraints are set. For example, when the electrical coupling strength between adjacent signal paths exceeds a certain threshold, the wiring path needs to be adjusted to ensure that signal interference is minimized. Specific settings for signal interference constraints may include: when the electrical coupling strength between two signal paths is greater than 0.8 (such as voltage coupling strength or current coupling strength), the spacing between them needs to be adjusted to avoid interference.

[0035] By comprehensively setting multiple design constraints, such as signal crossover, clock synchronization, power consumption, and signal interference, the topological dynamic constraints of the electronic chip design are obtained. These constraints provide a comprehensive foundation for subsequent layout optimization and ensure the stability and reliability of the chip in terms of physical design, signal transmission, and timing.

[0036] In this embodiment, step three specifically includes: The topological dynamic constraints of the electronic chip design are input into the neighborhood sampling layer of the GraphSAGE network, and each node randomly samples a fixed number of neighboring nodes from the neighborhood for feature aggregation. At each node, the features from neighboring nodes are aggregated by averaging the features of the neighboring nodes to obtain the neighborhood sampling feature set; The neighborhood sampled feature set is input into the feature update layer. At each node, the sampled neighborhood features are fused with the node's own features and updated through a linear transformation of the fully connected layer to obtain the updated node feature set. The updated node feature set is input into a multi-layer information fusion layer. Neighborhood sampling and feature updates are performed in each layer, and the node features output by each layer are used as the input of the next layer. At each layer, information from neighboring nodes is aggregated and further fused and updated in combination with the node features of the previous layer. Nonlinear transformation is performed through an activation function to obtain structure-aware features, which include the position of each circuit element in the entire circuit topology, signal transmission characteristics, and electrical and geometric characteristics of power consumption. The structure-aware feature set is obtained by combining the structure-aware features of all nodes.

[0037] This step significantly improves the accuracy and efficiency of chip placement and routing optimization by utilizing the GraphSAGE network to extract structure-aware features from the circuit topology in chip design. Through multi-level feature aggregation and updates, the network can effectively capture the complex electrical and geometric relationships between circuit elements, generating comprehensive structure-aware features. These features not only consider the spatial location of circuit elements but also signal transmission characteristics, power consumption, and geometric properties, thus providing accurate data support for subsequent placement optimization. Compared with traditional methods, the graph structure processing approach of this invention can accurately identify and adjust problems such as interference, signal delay, and wiring density in the placement at both global and local levels, effectively improving the automation and optimization capabilities of chip design.

[0038] Furthermore, through a multi-layer information fusion mechanism, this invention can progressively enhance node features at each layer, capturing deeper-level topological relationships and avoiding the local optima problem in traditional optimization methods. Ultimately, the generated structure-aware feature set provides an efficient and accurate optimization foundation for chip design, improving design quality and stability while reducing design cycle time and computational resource consumption. This method not only addresses increasingly complex chip design needs but also significantly improves overall performance under multi-objective optimization, providing stronger support for future electronic chip design.

[0039] In this embodiment, the improved DBM model is specifically as follows: The structure-aware feature set and topological dynamic constraints are input into the feature encoder, which cyclically transmits information between nodes through a recurrent neural network to obtain a node feature representation set. The node feature representation set is input into the layout candidate generation module, and multiple layout candidates are generated by the generative adversarial encoder, specifically including: A generator is used to generate a preliminary layout scheme based on node characteristics and electrical constraints, and a discriminator is used to judge the preliminary layout scheme. Optimize the signal interference and wiring density in the layout candidates according to the constraints until each layout candidate meets the design constraints; The various objectives of the candidate layouts are optimized until each layout scheme achieves a balance in power consumption, signal integrity, and wiring length, resulting in a set of candidate layout schemes. The set of candidate layout schemes is input into the dynamic constraint optimization module, and the dynamic constraint optimized layout set is obtained through the constraint adjustment mechanism. The dynamic constraint optimized layout set is input into the layout and routing scheme generation module, and the circuit elements in the dynamic constraint optimized layout set are initially located according to functional and space requirements; by identifying the type of circuit element, its space occupation area in the chip layout is determined, and a preliminary layout and positioning scheme is obtained. Based on the preliminary layout and positioning scheme, preliminary connection lines are generated between circuit components to connect all components that require signal transmission; The Dijkstra algorithm is used to calculate the optimal signal transmission path between each pair of circuit elements, and a preliminary layout and wiring scheme for the electronic chip is obtained.

[0040] This step significantly enhances the optimization capability of electronic chip placement and routing schemes by introducing an improved DBM model. Compared with traditional methods, the feature encoder, which combines Generative Adversarial Networks (GANs) and Recurrent Neural Networks (RNNs), can efficiently extract circuit topology features in chip design, achieving multi-objective optimization. The generator automatically generates multiple placement candidate schemes based on input node features and electrical constraints, and evaluates them through a discriminator, ensuring that each placement scheme meets design constraints such as signal integrity, wiring density, and power consumption. This method not only improves the accuracy of chip placement optimization but also significantly enhances design efficiency. The generated placement schemes can find the optimal balance between power consumption, wiring density, and signal integrity, greatly shortening the design cycle, reducing design costs, and meeting the diverse needs of complex chip designs.

[0041] In this embodiment, the constraint adjustment mechanism is specifically as follows: The initial layout constraints from candidate layout schemes are obtained, including all design constraints that may affect layout optimization, such as wiring density, signal interference, power consumption, thermal density, and clock synchronization. These initial layout constraints are then set as initial states and mapped one-to-one with the current layout schemes to obtain an initial constraint set. This initial constraint set contains all design constraints from the layout schemes and provides the foundational data for subsequent layout optimization. Each layout constraint is recorded in detail to ensure a one-to-one correspondence during adjustment and to avoid conflicts. Dynamic adjustments are performed on each layout that does not meet the constraints. Specific dynamic adjustment constraints include the following aspects:

[0042] Wiring density adjustment: If the wiring density in a certain area exceeds a preset density threshold (e.g., a wiring density greater than 0.8 mm²), it is necessary to reduce the wiring density in that area by adjusting the position of circuit components in the layout or introducing more wiring layers. For example, the circuit components of a functional block may be rearranged or split into different layers to alleviate the problem of overcrowded wiring, thereby improving space utilization and reducing the risk of signal interference.

[0043] Signal interference optimization: If signal interference exceeds a preset interference threshold (e.g., signal coupling strength greater than 0.7), the layout and routing paths of signal components are adjusted according to the signal transmission path and clock synchronization requirements. Signal interference can cause signal attenuation and distortion, especially in high-frequency signal transmission. Optimization methods employed during adjustment include increasing the spacing between signal paths and changing the direction of signal transmission paths to ensure uninterrupted signal transmission from the source node to the target node.

[0044] Power consumption and heat density adjustment: If the chip's power consumption or heat density exceeds the set limits (e.g., power consumption exceeding 5W or heat density exceeding 10W / cm²), adjust the location of the component with the highest power consumption. Excessive heat density can affect the chip's stability and long-term performance; therefore, it is necessary to adjust the wiring and component placement to distribute the heat generated by power consumption and ensure that thermal management meets design requirements. Depending on the heat distribution, components may be relocated to areas with lower heat, or additional heat dissipation channels may be added.

[0045] Clock signal transmission delay optimization: If the clock signal transmission delay exceeds a preset delay threshold (e.g., greater than 1ns), clock network routing optimization is performed. Excessive clock signal delay can lead to timing errors and affect the normal operation of the chip. Therefore, by optimizing the clock signal path and shortening the signal propagation time, all clock signals can reach the target component at the appropriate time, ensuring clock synchronization.

[0046] Finally, each adjusted constraint is fed back in real time, forming a dynamic constraint-optimized layout set. This layout set includes the optimized layout scheme and new constraints, ensuring that the optimized scheme meets all design requirements. After feedback and optimization, the layout scheme is finally improved, achieving the optimal design effect and providing a reliable layout foundation for subsequent chip design and physical implementation.

[0047] In this embodiment, step five specifically includes: Based on the layout data in the preliminary placement and routing scheme, an initial population for the differential evolution algorithm is established. Each individual in the population represents a placement scheme, resulting in an initial placement population. This initial placement population includes the location, routing path, and power consumption of each circuit element. In this step, the location information, routing path, and power consumption data of each circuit element are extracted from the preliminary placement and routing scheme to form individuals in the initial population. Each individual represents a complete placement scheme, including the spatial location of each circuit element in the chip, its connection path to other elements, and the power consumption parameters of each element. The individuals in the initial placement population will serve as the basis for differential evolution algorithm optimization. Typically, the population size is set to 100 to 500 individuals, adjusted according to the complexity of the design.

[0048] In each generation, new individuals are generated through mutation operations using the Differential Evolutionary Algorithm (DE). This mutation operation involves randomly selecting three individuals from the population, choosing two as parent individuals, calculating the difference between them, and adding this difference vector to the third individual's genes to generate a new mutated individual. Each mutated individual generates a new layout scheme, resulting in a set of mutated layout schemes. The mutation operation is the core of the Differential Evolutionary Algorithm, aiming to explore more design spaces by generating new individuals through mutation of parent individuals. Specifically, three individuals are first randomly selected, with two serving as parent individuals and the third as a reference individual for the genes. A difference vector is obtained by calculating the difference between the two parent individuals and adding this difference vector to the reference individual to generate a new mutated individual. Each mutated individual represents a new layout scheme, which is then provided for further optimization in the next crossover operation. The mutation operation typically employs the Differential Mutation (DE) algorithm, which increases population diversity, thereby improving the chance of finding the global optimum.

[0049] The crossover operation involves exchanging features between individuals in the mutated layout scheme set and other individuals in the population. This crossover operation selects two individuals for a single-point crossover, exchanging their features to generate a new set of layout schemes. The single-point crossover involves randomly selecting a crossover point from the parent layout schemes and exchanging routing paths and component location information. In this crossover operation, new individuals are generated from the population through this single-point crossover. Specifically, a crossover point is randomly selected from two parent layout schemes, and then the routing paths and component location information before and after the crossover point are exchanged to generate a new layout scheme. The purpose of the crossover operation is to generate better new individuals through information exchange between parent individuals. Crossover operations can accelerate the global search and help the population find more suitable layout schemes. The commonly used crossover rate is generally set to 60%-80% to ensure sufficient diversity in the population.

[0050] The differential placement and routing scheme for the electronic chip is obtained through iterative iteration until the maximum number of generations is reached. The differential evolution algorithm continues to iterate until the preset maximum number of generations is reached or a convergence condition is met (e.g., the change in the fitness function is less than a certain threshold). Each generation evaluates the merits of the placement scheme based on the fitness function and generates new placement individuals through mutation and crossover operations. After multiple generations of evolution, the algorithm will eventually converge to a relatively ideal placement scheme that meets the predetermined multi-objective optimization requirements, including wiring length, signal integrity, power consumption, and thermal management. The final differential placement and routing scheme will serve as the optimized routing scheme for the electronic chip and will proceed to the subsequent physical implementation and verification stages.

[0051] This optimization method based on differential evolution algorithm can efficiently search for globally optimal or near-optimal layout schemes in a huge design space, greatly improving the automation and accuracy of chip design.

[0052] In this embodiment, step six specifically includes: Based on the differential cabling layout scheme, the cabling paths are analyzed to identify areas with interference, congestion, or delay in the signal transmission path. First, all cabling paths are extracted from the differential cabling layout scheme, and the signal transmission situation of each path is analyzed. Through signal propagation analysis, areas where signal interference, path congestion, or signal delay may be identified. Interference may originate from signal path intersections or electrical coupling between adjacent paths; congestion may be due to excessively dense cabling or excessively long signal paths; and delay is caused by excessively long paths or unreasonable cabling design. Each potential problem area is marked, providing a basis for subsequent optimization steps.

[0053] By calculating the spatial density of each wiring path, areas where the wiring density or number of paths exceeds a preset threshold are identified. This step calculates the spatial density of each wiring path, taking into account the space occupied by each component and its connection path within the chip layout. Spatial density refers to the number of wiring paths per unit area. When the wiring density exceeds a set threshold, it can lead to signal interference and path delay. The preset threshold is typically set based on chip process and design requirements; for example, a wiring density exceeding 0.7 mm² / μm² is considered overcrowded. Areas with high density are identified as requiring optimization to ensure signal paths can transmit within sufficient space and avoid congestion.

[0054] Signal crosstalk analysis identifies areas in the layout that cause signal interference, including signal path intersections and electrical interference between adjacent signal lines. Next, signal crosstalk analysis assesses the mutual influence between different signal paths. Signal crosstalk is caused by electrical coupling between circuit components or wiring paths, and is particularly significant in high-frequency signal transmission. By calculating the coupling strength of adjacent signal paths, areas of electrical interference between signal path intersections and adjacent signal lines are identified. If the electrical coupling strength between two signal paths exceeds a preset interference threshold (e.g., coupling strength exceeding 0.8), it is considered to have strong signal interference, and optimization must be performed in these areas. Common signal interference problems include path intersections, signal attenuation, and reflections, which can lead to signal distortion, increased latency, or synchronization errors.

[0055] The identified regions are aggregated to form a local region identification set. After the above analysis, all identified regions with signal interference, path congestion, or excessive latency will be aggregated to form a "local region identification set". This identification set contains all local regions that need to be optimized, each region has its specific problems (such as signal interference, congestion, or latency), providing clear target regions for subsequent averaging and layout optimization.

[0056] The local region identification set is averaged to obtain a local optimized layout scheme. The averaging process involves: for each local region, calculating the average characteristics of all wiring paths, including wiring length, signal delay, power consumption, and wiring density; during the averaging process, calculating the average characteristics of each wiring path within each local region. For example, calculating the average wiring length within the region to evaluate its signal delay, power consumption, and wiring density. Signal delay can be obtained by calculating the total delay time of the path (e.g., signal propagation time), power consumption is calculated by the power consumption of each wiring path, and wiring density is calculated by the space occupied by the path. By calculating these average characteristics, a specific basis for optimizing each local region can be provided, enabling the layout optimization process to balance the impact of different characteristics on the layout.

[0057] Based on the average value of each local region, the spatial distribution of circuit components and wiring paths within that local region are adjusted. Furthermore, based on the average characteristics of each local region, the positions of circuit components and wiring paths within that region are adjusted. For example, in regions with long wiring paths or significant signal delays, the relative positions of components are adjusted to optimize path length and shorten signal transmission time. For regions with high wiring density, the layout of circuit components is adjusted to increase the spacing between paths, thereby reducing wiring congestion and optimizing the utilization efficiency of wiring space. Through these adjustments, wiring paths can be optimized within local regions, reducing signal interference and delay, and improving the performance and signal integrity of the overall chip layout.

[0058] Through these processing steps, this implementation method can significantly improve the optimization efficiency of electronic chip layout, ensure the signal integrity of the wiring path, reduce congestion problems caused by excessive wiring density, and thus obtain a more efficient and stable electronic chip layout scheme.

[0059] In this embodiment, step seven specifically includes: This paper analyzes signal interference, attenuation, and reflection issues in routing paths based on a local optimization layout scheme. For areas where signal integrity falls below a preset threshold, signal transmission is optimized by adjusting the signal paths, resulting in a global signal optimization layout scheme. In this step, each routing path in the local optimization layout scheme is first analyzed, focusing on evaluating interference, attenuation, and reflection during signal transmission. Interference during signal transmission may originate from electrical coupling between adjacent paths; attenuation is typically related to the length of the routing path and the current intensity; and reflection may be caused by discontinuities or mismatches in signal transmission. By calculating the signal integrity of each path, areas where signal integrity falls below a preset threshold are identified. A common threshold is set to 0.8 (i.e., signal attenuation greater than 20%), or specific tolerance ranges are set according to different signal types (e.g., high-frequency or low-frequency signals). When signal integrity is found to be unsatisfactory, interference is eliminated or signal loss on the path is reduced by adjusting the signal path, such as by changing the path direction, increasing the spacing between signal paths, or adding appropriate impedance matching components. The final result of this process is the "global signal optimization layout scheme," which ensures the transmission quality of all signals in the chip and avoids signal distortion or errors.

[0060] A wiring density analysis is performed on the global signal optimization layout scheme to identify areas where the wiring density exceeds a preset threshold and signal crossings and component spacing are less than a preset threshold. The relative positions of circuit components are then adjusted to obtain the global wiring density optimization layout scheme. In this step, the wiring density of the "global signal optimization layout scheme" is first analyzed, calculating the number of wiring paths and the spatial distribution of signal paths in each area. Areas with high wiring density may cause signal transmission problems, especially in high-frequency signal transmission. By calculating the wiring density of each area, areas with wiring density exceeding a preset threshold (e.g., 0.7 mm² / μm²) are identified. Simultaneously, signal path crossings and component spacing are checked. If the electrical coupling between two signal paths is too strong or the spacing between two circuit components is less than a preset value (e.g., less than 20 μm), these areas require further optimization. During the optimization process, the relative positions of circuit components are adjusted to increase the distance between signal paths, reduce signal crossings, and avoid signal interference. Finally, the optimized "global wiring density optimization layout scheme" is obtained, which effectively reduces problems caused by wiring density and improves signal transmission efficiency and stability.

[0061] This section analyzes the clock signal transmission in the global routing density optimization layout scheme, examining the delay differences of the clock signal in different regions. By adjusting the clock signal path, the transmission delay from the source node to the target node is kept within a preset range, resulting in the final electronic chip layout and routing scheme. This step focuses on analyzing the clock signal in the global routing density optimization layout scheme. Clock signal transmission delay is a crucial factor affecting chip performance; excessive clock signal delay can lead to timing errors and impact system stability. By analyzing the transmission path and delay differences of the clock signal from the source node to each target node, it is checked whether the signal transmission is within a preset maximum delay threshold (e.g., the maximum transmission delay of the clock signal is set to 1 ns). For clock signal paths with delays exceeding the preset threshold, the clock network layout is optimized to reduce signal transmission delay. This can be achieved by adjusting the clock signal transmission path, increasing the straightness of the path, and reducing detours or excessively long wiring. After clock signal optimization, the resulting clock synchronization layout will ensure that all clock signals arrive at the target node within a preset time, guaranteeing clock synchronization performance. Ultimately, the "final electronic chip layout and routing scheme" was obtained. This scheme not only ensured optimization in various aspects such as signal transmission quality, wiring density and power consumption, but also guaranteed clock synchronization and signal integrity. It is the final efficient layout scheme used for physical implementation.

[0062] Through the above steps, this implementation method can comprehensively optimize the chip layout and routing scheme, reduce signal interference and clock delay, improve the quality and speed of signal transmission, and improve the utilization efficiency of wiring density, ensuring that the chip design achieves the best balance in terms of performance, power consumption and signal integrity.

[0063] Example 1: To verify the feasibility of this invention in practice, it was applied to a processor chip in a data center. The complex circuit layout of this chip required handling a large number of computational tasks within a limited space, while maintaining low power consumption and efficient signal transmission. The main challenges in the design included excessive wiring density, signal interference, and clock synchronization issues, all of which severely impacted chip performance and energy efficiency.

[0064] In this design scenario, we first constructed a preliminary chip topology diagram by collecting initial topology data from the chip design, including the type, function, physical size, electrical characteristics (such as resistance, capacitance, power consumption, etc.) and electrical connections of all circuit elements. This topology diagram reflects each circuit element and its connections, providing fundamental data for subsequent layout optimization. Next, based on the preliminary chip topology diagram, we set multiple optimization objectives, especially constraints such as signal integrity, wiring density, and clock synchronization, and initialized dynamic topology constraints. Factors such as signal crossing, clock network layout, power consumption, and thermal density limitations were all incorporated into the optimization objectives. These objectives are not simple, as they require balancing multiple complex constraints. For example, longer signal transmission paths lead to greater signal attenuation and delay, while excessive wiring density can cause electrical interference and signal crosstalk, thus affecting the overall chip performance and stability.

[0065] After feature extraction via the GraphSAGE network, the structure-aware features of each circuit element are supported by deep learning, further improving the accuracy of topology information extraction. Through multi-level feature aggregation, the network can effectively identify the relationships between circuit elements, helping us optimize chip layout. In this process, node features are not only simple physical dimensions and electrical characteristics, but also signal transmission characteristics, such as signal delay, power consumption, and heat density distribution. The generative adversarial encoder generates multiple candidate layout schemes through adversarial training between the generator and discriminator. These schemes are optimized under multiple design constraints, ultimately yielding a preliminary layout scheme that meets the design requirements. During the optimization process, we introduce a differential evolution algorithm, further optimizing the layout scheme through mutation, crossover, and selection operations. Through analysis of the preliminary layout routing scheme, congested areas and signal interference hotspots in the routing path are identified, especially signal path intersections and signal attenuation areas. By adjusting the position of circuit elements, optimizing routing paths, and reducing congestion, signal interference is significantly reduced. Power consumption optimization is also effectively controlled, with a final power consumption reduction of 15% compared to before optimization.

[0066] To verify the effectiveness of this method, we also combined local and global optimization, and further adjusted the signal path using the generated layout scheme to ensure clock signal synchronization and signal transmission integrity. After optimization, the chip's wiring density was reduced by 20%, signal integrity was improved by 10%, power consumption was reduced by 15%, and clock delay was controlled within 1ns.

[0067] Table 1 Comparison of Electronic Chip Layout and Routing Optimization Schemes

[0068] Table 1 compares the layout data at different optimization stages, demonstrating the significant optimization effect. In the initial layout, signal integrity was only 85%, while after optimization using the differential evolution algorithm, signal integrity improved by 7%, and wiring density decreased from 0.8 mm² / μm² to 0.6 mm² / μm². Further global optimization increased signal integrity to 98%, further reduced wiring density to 0.5 mm² / μm², reduced power consumption to 4.0W, and controlled clock latency to within 1.0 ns. Through these optimizations, the overall performance of the chip was significantly improved, particularly in signal integrity and power consumption control, achieving the expected design goals. The optimized layout not only improved the chip's stability and processing power but also provided a feasible design solution for actual production. This process verifies the effectiveness of the method of this invention under multi-objective optimization, especially in complex chip design environments, where it can efficiently handle multiple mutually constraining design requirements, ensuring the efficiency and reliability of the final design.

[0069] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for electronic chip placement and routing based on a generative model, characterized in that, Includes the following steps: Step 1: Collect preliminary topology data for the electronic chip design, and construct a preliminary chip topology diagram for each circuit element node; Step 2: Based on the preliminary chip topology diagram, initialize the topology dynamic constraints of the electronic chip design by setting multi-objective optimization objectives; Step 3: Input the topological dynamic constraints of the electronic chip design into the structure-aware encoder. The encoder's GraphSAGE network extracts features from the chip's circuit topology and generates a structure-aware feature set for each node. Step 4: Input the structure-aware feature set and topology dynamic constraints into the improved DBM model, and obtain the preliminary layout and routing scheme of the electronic chip through the feature encoder, layout candidate generation module, dynamic constraint optimization module and layout and routing scheme generation module. Step 5: Optimize the preliminary layout and routing scheme using a differential evolution algorithm to obtain the differential layout and routing scheme for the electronic chip; Step 6: Perform region identification on the differential layout routing scheme to obtain a local region identification set, and perform averaging to obtain a local optimized layout scheme; Step 7: Perform global optimization on the local optimization layout scheme, and integrate signal integrity, wiring density and clock synchronization to obtain the final electronic chip layout and routing scheme.

2. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step one specifically involves: Collect information on circuit elements in chip design, including logic gates, memory cells, and input / output interfaces, specifically including: Obtain information on the type, function, and physical dimensions of each circuit element in the chip design; Collect the electrical characteristics of each circuit element, including resistance, capacitance, and power consumption parameters; Obtain the interface type and electrical connection method for each circuit component; Each circuit element is considered a node, and the electrical connections between nodes are represented by edges. Specifically, these include: Each circuit element in the chip is treated as a node in the initial chip topology diagram. The electrical connection between nodes is represented by edges, and the weight of the edge is the weighted sum of the signal transmission delay rate and the current intensity according to preset weights. Construct each electrical connection in the circuit and record the direction of each connection; Obtain the geometrical occupancy area of ​​each circuit element in the chip design, wherein the geometrical occupancy area includes the actual space occupation and shape of each circuit element in the chip layout; Obtain layout constraints, which include the minimum and maximum spacing between each element; Collect power consumption requirements related to circuit elements, including the maximum power consumption and thermal management limits for each circuit element; The collected circuit element information, electrical connection relationships, and layout constraints are integrated to generate a preliminary chip topology diagram.

3. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step two specifically involves: Based on the circuit element layout and electrical connection relationship in the preliminary chip topology diagram, the signal crossings of the electronic chip are determined, and signal crossing constraints are set based on the distance and electrical characteristics between the circuit elements. Based on the layout of the clock network in the circuit, set clock synchronization constraints; Power consumption constraints are set based on the power consumption characteristics of each circuit element in the chip design, and heat density distribution analysis is performed based on the heat generated by each circuit element during operation to limit the overall heat density of the chip. Based on the electrical characteristics and layout of circuit components, signal interference constraints are set to obtain the topological dynamic constraints for electronic chip design.

4. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step three specifically involves: The topological dynamic constraints of the electronic chip design are input into the neighborhood sampling layer of the GraphSAGE network, and each node randomly samples a fixed number of neighboring nodes from the neighborhood for feature aggregation. At each node, the features from neighboring nodes are aggregated by averaging the features of the neighboring nodes to obtain the neighborhood sampling feature set; The neighborhood sampled feature set is input into the feature update layer. At each node, the sampled neighborhood features are fused with the node's own features and updated through a linear transformation of the fully connected layer to obtain the updated node feature set. The updated node feature set is input into a multi-layer information fusion layer. Neighborhood sampling and feature updates are performed in each layer, and the node features output by each layer are used as the input of the next layer. At each layer, information from neighboring nodes is aggregated and further fused and updated in combination with the node features of the previous layer. Nonlinear transformation is performed through an activation function to obtain structure-aware features, which include the position of each circuit element in the entire circuit topology, signal transmission characteristics, and electrical and geometric characteristics of power consumption. The structure-aware feature set is obtained by combining the structure-aware features of all nodes.

5. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, The improved DBM model is specifically as follows: The structure-aware feature set and topological dynamic constraints are input into the feature encoder, which cyclically transmits information between nodes through a recurrent neural network to obtain a node feature representation set. The node feature representation set is input into the layout candidate generation module, and multiple layout candidates are generated by the generative adversarial encoder, specifically including: A generator is used to generate a preliminary layout scheme based on node characteristics and electrical constraints, and a discriminator is used to judge the preliminary layout scheme. Optimize the signal interference and wiring density in the layout candidates according to the constraints until each layout candidate meets the design constraints; The various objectives of the candidate layouts are optimized until each layout scheme achieves a balance in power consumption, signal integrity, and wiring length, resulting in a set of candidate layout schemes. The set of candidate layout schemes is input into the dynamic constraint optimization module, and the dynamic constraint optimized layout set is obtained through the constraint adjustment mechanism. The dynamic constraint optimized layout set is input into the layout and routing scheme generation module, and the circuit elements in the dynamic constraint optimized layout set are initially located according to functional and space requirements; by identifying the type of circuit element, its space occupation area in the chip layout is determined, and a preliminary layout and positioning scheme is obtained. Based on the preliminary layout and positioning scheme, preliminary connection lines are generated between circuit components to connect all components that require signal transmission; The Dijkstra algorithm is used to calculate the optimal signal transmission path between each pair of circuit elements, and a preliminary layout and wiring scheme for the electronic chip is obtained.

6. The electronic chip placement and routing method based on a generative model according to claim 5, characterized in that, The constraint adjustment mechanism is specifically as follows: Obtain the preliminary layout constraints from the candidate layout schemes; The initial layout constraints are set as the initial state and correspond one-to-one with the current layout scheme to obtain the initial constraint set, which includes all design constraints in the initial layout scheme. For each layout that does not meet the constraints, dynamic adjustments are made, and the constraints for dynamic adjustment include: If the wiring density in a region exceeds a preset density threshold, the density in that region can be reduced by adjusting the position of circuit components in the layout or by introducing more wiring layers. If the signal interference exceeds the preset interference threshold, the layout and wiring path of the signal components will be adjusted according to the signal transmission path and clock synchronization requirements. If the chip's power consumption or heat density exceeds the set limit, adjust the position of the component with the highest power consumption; If the transmission delay of the clock signal is greater than a preset delay threshold, then the clock network wiring is required. Real-time feedback is provided for each adjusted constraint to obtain a dynamic constraint optimization layout set, which includes the optimized layout scheme and constraint conditions.

7. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step five specifically involves: Based on the layout data in the preliminary layout and routing scheme, initialize the population of the differential evolution algorithm. Each individual in the population represents a layout scheme, and the initial layout population is obtained. The initial layout population includes the position, routing path and power consumption of each circuit element. In each generation, new individuals are generated through mutation operations of the differential evolution algorithm. The mutation operation involves randomly selecting three individuals from the population, selecting two parent individuals, calculating the differences between them, and adding them to the genes of the third individual to generate new mutated individuals. Each mutated individual will generate a new layout scheme, resulting in a set of mutated layout schemes. The individuals in the mutated layout scheme set are cross-crossed with other individuals in the population. The cross-crossing operation is performed by selecting two individuals through single-point cross-crossing to exchange their features, thereby generating a cross-crossed layout scheme set. The single-point cross-crossing is to randomly select a cross-crossing point from the parent layout scheme and exchange the wiring path and component position information. Repeat the iteration until the maximum number of generations is reached to obtain the differential layout and routing scheme of the electronic chip.

8. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step six specifically involves: Based on the differential layout cabling scheme, the cabling path is analyzed to identify areas in the signal transmission path where there is interference, congestion, or delay. By calculating the spatial density of each wiring path, areas where the wiring density or number of paths exceeds a preset threshold are identified. Signal crosstalk analysis identifies areas in the layout that cause signal interference, including signal path intersections and electrical interference between adjacent signal lines. The local region identification set is obtained by summing up all identified regions; The mean value processing is performed on each local region in the local region identification set to obtain a local optimized layout scheme. The mean value processing is as follows: for each local region, the characteristic mean value of all wiring paths is calculated, including wiring length, signal delay, power consumption and wiring density. Based on the average value of each local area, adjust the spatial distribution of circuit components and wiring paths within the corresponding local area.

9. The electronic chip placement and routing method based on a generative model according to claim 1, characterized in that, Step seven specifically involves: Based on the analysis of signal interference, attenuation and reflection problems in the wiring path based on the local optimization layout scheme, for areas where the signal integrity is lower than the preset threshold, the signal transmission is optimized by adjusting the signal path, and a global signal optimization layout scheme is obtained. A wiring density analysis is performed on the global signal optimization layout scheme to identify areas where the wiring density is greater than a preset threshold and the signal intersection and component spacing are less than a preset threshold. The relative positions of the circuit components are then adjusted to obtain the global wiring density optimization layout scheme. The clock signal transmission of the global wiring density optimization layout scheme is analyzed, the delay difference of the clock signal in different areas is checked, and the path of the clock signal is adjusted until the transmission delay of the clock signal from the source node to the target node is within the preset range, so as to obtain the final electronic chip layout and wiring scheme.

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