Accelerator and server

Abstract

The invention discloses an accelerator and a server, and relates to the technical field of computers, the original complex three-dimensional convolution operation is converted into a plurality of small-scale two-dimensional and one-dimensional convolution calculations by performing step-by-step dimension decomposition on convolution calculations, the calculation complexity of single calculation is reduced, and the calculation efficiency is improved. And the access times and access bandwidth requirements of the external storage device are reduced. The one-dimensional convolution calculation module and the two-dimensional convolution calculation module can realize data multiplexing, so that the power consumption of repeatedly reading data from external equipment can be reduced, and the hardware utilization rate and the energy efficiency ratio are improved. The technical problem of contradiction between high power consumption and performance limitation in the prior art is solved, and the technical effect of effectively reducing the overall power consumption and calculation delay of the end side accelerator on the premise of not sacrificing the model precision is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to an accelerator and a server. BACKGROUND

[0002] In recent years, deep neural networks have achieved great success in image recognition, speech processing and other fields. With the improvement of the computing power of end-side computing devices such as smart phones and Internet of Things devices and the development of model compression technology, the application scenarios of deep neural networks are migrating from cloud computing centers to network edge devices. Running deep neural networks on end-side devices has significant advantages. First, data is processed locally, without the need to upload to the cloud, saving network bandwidth and reducing transmission delay, improving real-time performance. Second, it does not rely on the stable connection of the cloud server, enhancing the reliability of the service. Third, sensitive data does not leave the device, better protecting user privacy.

[0003] However, end-side devices are usually limited by strict power budgets (such as the need to ensure long battery life), which fundamentally contradicts the large amount of computation and memory access operations involved in deep neural networks, especially the convolutional layers. Therefore, how to significantly reduce the power consumption overhead in the convolution calculation process without sacrificing performance has become a core challenge for the design of accelerators for end-side devices. SUMMARY

[0004] The present application provides an accelerator and a server to at least solve the technical problem of the contradiction between high power consumption and performance limitation in the related art, achieving the technical effect of effectively reducing the overall power consumption and calculation delay of the end-side accelerator without sacrificing model accuracy.

[0005] The present application provides an accelerator, comprising: a storage interface and a convolution calculation module; the storage interface is configured to be connected with a storage device, and the convolution calculation module comprises a convolution splitting module, a one-dimensional convolution calculation module and a two-dimensional convolution calculation module; the convolution splitting module is connected to the storage interface and is configured to perform dimension decomposition processing on input features and convolution kernels obtained from the storage interface; the dimension decomposition processing comprises decomposing a three-dimensional convolution into a plurality of two-dimensional convolutions in the channel dimension to obtain two-dimensional input features and two-dimensional convolution kernels, and decomposing each two-dimensional convolution into a plurality of one-dimensional convolutions in the vertical direction to obtain one-dimensional input features and one-dimensional convolution kernels; the one-dimensional convolution calculation module is connected to the convolution splitting module and is configured to perform one-dimensional convolution calculation according to the one-dimensional input features and the one-dimensional convolution kernels to obtain one-dimensional convolution results; the two-dimensional convolution calculation module is connected to the convolution splitting module and is configured to combine and accumulate a plurality of one-dimensional convolution results according to the two-dimensional input features and the two-dimensional convolution kernels to obtain two-dimensional convolution results.

[0006] The application further provides a server comprising the accelerator.

[0007] By the application, since the originally complex three-dimensional convolution operation is converted into a plurality of smaller two-dimensional and one-dimensional convolution calculations by performing hierarchical dimension decomposition on the convolution calculation, not only the operation complexity of single calculation is reduced, but also the access frequency and access bandwidth demand of external storage devices are reduced, the one-dimensional convolution calculation module and the two-dimensional convolution calculation module can realize data multiplexing, can reduce the power consumption of repeatedly reading data from external devices, and improve the hardware utilization rate and energy efficiency ratio. The technical problem of the contradiction between high power consumption and performance limitation in the related art is solved, and the technical effect of effectively reducing the overall power consumption and calculation delay of the end-side accelerator without sacrificing the model accuracy is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0009] Figure 1 A schematic block diagram of an accelerator provided for an embodiment of the application.

[0010] Figure 2 A schematic block diagram of an accelerator provided for an embodiment of the application.

[0011] Figure 3 A schematic diagram of a one-dimensional convolution calculation process provided for an embodiment of the application.

[0012] Figure 4 A schematic diagram of a two-dimensional convolution array provided for an embodiment of the application.

[0013] Figure 5 A schematic diagram of a two-dimensional convolution calculation process provided for an embodiment of the application.

[0014] Figure 6 A schematic diagram of data interaction between consecutive convolution layers provided for an embodiment of the application.

[0015] Figure 7 A schematic diagram of adjacent block overlapping part multiplexing provided for an embodiment of the application.

[0016] Figure 8 A schematic diagram of odd-even table splitting provided for an embodiment of the application.

[0017] Figure 9 A schematic diagram of a two-dimensional non-convolution calculation process provided for an embodiment of the application.

[0018] Figure 10 A schematic diagram of weight compression provided for an embodiment of the present application.

[0019] Figure 11 A flowchart of an instruction analysis module provided for an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0021] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0022] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0023] In a first aspect, as Figure 1 and Figure 2 An accelerator is provided in an embodiment of the present application, comprising: a storage interface and a convolution calculation module; the storage interface is configured to be connected with a storage device, and the convolution calculation module comprises a convolution splitting module, a one-dimensional convolution calculation module and a two-dimensional convolution calculation module; the convolution splitting module 11 is connected to the storage interface and is configured to perform dimension decomposition processing on input features and convolution kernels obtained from the storage interface; the dimension decomposition processing comprises decomposing a three-dimensional convolution into a plurality of two-dimensional convolutions in a channel dimension to obtain two-dimensional input features and two-dimensional convolution kernels, and decomposing each two-dimensional convolution into a plurality of one-dimensional convolutions in a vertical direction to obtain one-dimensional input features and one-dimensional convolution kernels; the one-dimensional convolution calculation module 12 is connected to the convolution splitting module 11 and is configured to perform one-dimensional convolution calculation according to the one-dimensional input features and the one-dimensional convolution kernels to obtain one-dimensional convolution results; the two-dimensional convolution calculation module 13 is connected to the convolution splitting module 11 and is configured to combine and accumulate the plurality of one-dimensional convolution results according to the two-dimensional input features and the two-dimensional convolution kernels to obtain two-dimensional convolution results.

[0024] In the embodiment, the accelerator implements hierarchical processing of convolution operation through a modular computing architecture. The storage interface is configured to connect with the storage device and is used to obtain data of input features and convolution kernels from the storage device before performing convolution calculation. The input features and the convolution kernels are usually stored in the form of three-dimensional tensors, and the storage interface transmits and distributes these multi-dimensional data in the format required by the convolution splitting module 11 to ensure the continuity and timing consistency of data in the hardware pipeline. Through the storage interface, the convolution calculation module can realize the ordered transmission of input and output between different computing stages, so that the entire computing process has an independent data path.

[0025] The convolution calculation module includes a convolution splitting module 11, which implements dimension decomposition function in the embodiment. The convolution splitting module 11 is configured to perform dimension decomposition processing on the input features and the convolution kernels obtained from the storage interface. The dimension decomposition processing includes two levels of operation. First, the three-dimensional convolution is decomposed into multiple two-dimensional convolutions in the channel dimension. At this time, the convolution splitting module 11 extracts data segments from multiple channels of the input features in turn, and expands the three-dimensional convolution kernel along the channel direction, thereby obtaining multiple two-dimensional input features and corresponding two-dimensional convolution kernels. Through this decomposition method, the convolution splitting module 11 can split the operation task of simultaneously processing multi-channel convolution into several independent two-dimensional convolution tasks, so that each two-dimensional convolution can be independently executed in the subsequent computing module.

[0026] After completing the decomposition in the channel dimension, the convolution splitting module 11 continues to perform vertical direction decomposition processing on each two-dimensional convolution. The decomposition operation is based on the height dimension of the two-dimensional convolution, which is divided into multiple one-dimensional convolution tasks. The one-dimensional input features and one-dimensional convolution kernels obtained after decomposition retain the local feature mapping relationship in the original two-dimensional convolution, while greatly reducing the number of data elements required for each convolution operation. At this time, the convolution splitting module 11 sends each one-dimensional input feature and one-dimensional convolution kernel to the one-dimensional convolution calculation module 12 in sequence or batch mode, so that the subsequent computing process can be completed under a smaller data scale.

[0027] The one-dimensional convolution calculation module 12 performs specific convolution calculation operation in the embodiment. The module completes one-dimensional convolution calculation process according to the received one-dimensional input features and one-dimensional convolution kernels. The convolution calculation process includes element-by-element multiplication and summation operation of input data and convolution kernel weights. The module can use a sliding window method to sample the input features in turn, and perform cumulative summation operation combined with the length of the convolution kernel. In this way, the module outputs one-dimensional convolution result. Since the one-dimensional convolution calculation module 12 receives a small input scale, the calculation process can be continuously performed in the form of pipeline, thereby ensuring that the convolution result is output in time sequence, providing input data for the subsequent two-dimensional convolution combination.

[0028] The two-dimensional convolution calculation module 13 is in data connection with the convolution splitting module 11 in this embodiment, for completing the spatial reconstruction of the convolution result. The module combines and accumulates a plurality of one-dimensional convolution results according to the two-dimensional input features and the two-dimensional convolution kernel provided by the convolution splitting module 11, to restore the complete two-dimensional convolution result. In this process, the two-dimensional convolution calculation module 13 performs position addition and corresponding mapping processing on the convolution results from different row directions or channels, so that the output result remains consistent in the spatial dimension. Finally, the two-dimensional convolution calculation module 13 transmits the generated two-dimensional convolution result to the back-end calculation module, and after the calculation is completed, it is transmitted to the storage interface, which is written back to the storage device or delivered to the subsequent calculation unit, thereby completing the entire calculation process from the input features to the convolution result.

[0029] In summary, by performing step-by-step dimension decomposition on convolution calculation, the originally complex three-dimensional convolution operation is converted into a plurality of smaller two-dimensional and one-dimensional convolution calculations, which not only reduces the operation complexity of single calculation, but also reduces the access frequency and access bandwidth demand of external storage devices. The one-dimensional convolution calculation module 12 and the two-dimensional convolution calculation module 13 can be implemented in parallel and pipelined, improving hardware utilization and energy efficiency. The technical problem of the contradiction between high power consumption and performance limitation in the related art is solved, and the technical effect of effectively reducing the overall power consumption and calculation delay of the end-side accelerator without sacrificing model accuracy is achieved.

[0030] In an exemplary embodiment, the one-dimensional convolution calculation module 12 includes at least one one-dimensional convolution unit, and the one-dimensional convolution unit includes: a convolution kernel register group configured to store weight elements of a one-dimensional convolution kernel; an input feature shift register configured to store one-dimensional input features in a sliding window manner; and a dot product calculation module having a first input end connected with the convolution kernel register group and a second input end connected with the input feature shift register; the dot product calculation module is configured to perform parallel dot product operation on the weight elements of the one-dimensional convolution kernel and the one-dimensional input features in the sliding window, and output one-dimensional convolution results.

[0031] In this embodiment, the one-dimensional convolution calculation module 12 is specifically implemented to include at least one one-dimensional convolution unit, and each one-dimensional convolution unit independently completes the convolution operation between the input features and the convolution kernel. The one-dimensional convolution unit is provided with two register structures of a convolution kernel register group and an input feature shift register. The convolution kernel register group is used to store the weight elements of the one-dimensional convolution kernel, which remains unchanged during the entire convolution calculation process. The input feature shift register is configured to store one-dimensional input features in a sliding window manner, i.e., the input data is sequentially shifted to the right after each calculation, and the new input points are sequentially written to the end of the register queue. Such a register structure enables the convolution unit to continuously update data in time sequence, thereby realizing continuous convolution calculation.

[0032] In this embodiment, the dot product calculation module is connected between the convolution kernel register group and the input feature shift register to perform the core dot product operation. The dot product calculation module receives input signals from both register groups, where each convolution kernel weight element is connected one-to-one with the corresponding input feature data, forming, for example, an S-group multiplication input channel. When the clock signal is triggered, the dot product calculation module simultaneously performs parallel multiplication operations on the S-group inputs and accumulates the resulting products to output the convolution value corresponding to the current sliding window. The output results are summed by the accumulation circuit to form a one-dimensional convolution result. To reduce the additional power consumption caused by invalid computation, this embodiment sets a judgment logic at the input of the dot product calculation module. When a zero value is detected in the convolution kernel or input data, the clock of the multiplier is temporarily turned off through a clock gating mechanism, thereby keeping the channel in a static state and preventing additional power consumption from invalid computation.

[0033] like Figure 3 During the computation, the one-dimensional convolutional unit first receives the weight sequence (W0, W1…WS-1) of the one-dimensional convolutional kernel and the first S data points (F0, F1…FS-1) of the input features, storing them respectively in the convolutional kernel register group and the input feature shift register. The dot product calculation module performs the product calculation from W0×F0 to WS-1×FS-1 according to the correspondence of the input ports, and accumulates all product results to output the first convolution result. After that, the convolutional kernel register group remains unchanged, the input feature shift register is shifted one position to the right, the new input data point FS is written to the end of the register, and the original data is updated sequentially, that is, the data in the input feature shift register is F1, F1…FS. The dot product calculation module triggers the calculation again and repeats the above process. Through this sliding window mechanism, the one-dimensional convolutional unit completes (N-S+1) dot product operations in sequence without repeatedly loading the convolutional kernel, obtaining the one-dimensional convolutional output sequence of the entire input sequence (i.e., Figure 3 (O0, O1, ... ON-S)).

[0034] In this embodiment, the input feature shift register plays a crucial role in convolution calculations. Since the input features only need to be shifted right by one bit and updated with a new data point after each calculation, the reuse rate of input data is improved, thereby reducing the number of accesses to external memory. The updating of input features is synchronized with the calculation of the dot product module, ensuring the continuous flow of the entire calculation process. Through this shift register-based data reuse structure, the one-dimensional convolution unit can perform convolution calculations on the complete input feature sequence while maintaining a low data transmission frequency, guaranteeing the accuracy and continuity of the convolution results.

[0035] like Figure 3In one exemplary embodiment, the dot product calculation module includes: a multiplier, whose first input is connected to a convolution kernel register group and whose second input is connected to an input feature shift register; the multiplier is configured to perform parallel multiplication operations on the corresponding weight elements and one-dimensional input features to obtain multiple multiplication results; and an adder, connected to the output of the multiplier, configured to accumulate and sum the multiplication results to output a one-dimensional convolution result.

[0036] In this embodiment, the dot product calculation module comprises a multiplier and an adder. The first input of the multiplier is connected to the convolution kernel register set to receive the stored convolution kernel weight elements; the second input is connected to the input feature shift register to receive the one-dimensional input feature corresponding to the current sliding window. The convolution kernel register set and the input feature shift register are in one-to-one correspondence, forming S groups of input channels. Driven by a clock signal, the multiplier performs multiplication operations simultaneously on each group of input channels, multiplying the convolution kernel weight elements by the corresponding input features, thereby generating multiple multiplication results in parallel.

[0037] An adder is positioned at the output of the multiplier to receive all multiplication results within the same computation cycle. Following a pre-defined accumulation logic, the adder performs a step-by-step summation operation on the results from the multiplier outputs, obtaining the summation output value corresponding to the current sliding window. This output value is the one-dimensional convolution result for that window and can be directly output to subsequent modules or temporarily stored for later computation. Through this structural arrangement, the dot product calculation module can complete multiple multiplications and one addition accumulation within the same clock cycle, thereby achieving rapid generation of one-dimensional convolution results.

[0038] like Figure 4 In one exemplary embodiment, the two-dimensional convolution calculation module 13 includes a two-dimensional processing array. This array reuses multiple one-dimensional convolution units from the one-dimensional convolution calculation module 12. The number of rows in each one-dimensional convolution unit is the same as the number of rows in the two-dimensional convolution kernel. The number of columns in each one-dimensional convolution unit is determined based on the number of rows of the input features and the number of rows in the two-dimensional convolution kernel. The two-dimensional processing array is configured to input the weight elements of each row of the two-dimensional convolution kernel to the convolution kernel register group of all one-dimensional convolution units in the corresponding row. Figure 3 In the diagram, the one-dimensional convolutional units corresponding to coordinates (0,0), (0,1) up to (0,MR-1), (0,MR) are all one-dimensional convolutional units in the same row. Each row of data from the two-dimensional input features is sequentially input into the input feature shift register of the corresponding one-dimensional convolutional unit on the diagonal direction, according to the computation time sequence; for example... Figure 3In the diagram, the first diagonal one-dimensional convolutional unit includes a one-dimensional convolutional unit with coordinates (0,0), the second diagonal one-dimensional convolutional unit includes one-dimensional convolutional units with coordinates (1,0) and (0,1), and so on. Finally, the outputs of the one-dimensional convolutional units in the same column are summed to generate the final two-dimensional convolution result.

[0039] In this embodiment, the two-dimensional convolution calculation module 13 includes a two-dimensional processing array. The two-dimensional processing array reuses multiple one-dimensional convolution units in the one-dimensional convolution calculation module 12 to achieve data reuse and reduce data reading volume. The number of rows in the two-dimensional processing array is the same as the number of rows in the two-dimensional convolution kernel, and each row corresponds to the calculation task of one row of weight elements in the convolution kernel. The number of columns in the one-dimensional convolution unit is determined according to the number of rows of input features and the number of rows of convolution kernel to ensure that each row of input features can be matched with the corresponding row of convolution kernel in the array during the entire calculation process. The units inside the two-dimensional processing array are connected in a matrix manner through the regular arrangement of rows and columns. Each one-dimensional convolution unit can perform one-dimensional convolution calculation independently and can also form a complete two-dimensional convolution accumulation path through data transfer between columns.

[0040] During computation, each row of weights in the 2D convolutional kernel is input into the corresponding row of the 2D processing array and stored in the kernel register set of all 1D convolutional units in that row. Simultaneously, each row of input feature data is sequentially input into the input feature shift registers of each 1D convolutional unit arranged diagonally in the 2D processing array, according to a predetermined computation timeline. This diagonal input method allows different rows of input features to be matched sequentially with multiple rows of weights in the convolutional kernel within the array, enabling each 1D convolutional unit to participate in convolution operations at different computational stages simultaneously, thus creating a continuous data flow in space.

[0041] After the 2D processing array completes the matching and loading of input features and convolutional kernel weights, each 1D convolutional unit in the array performs a 1D convolution operation at its corresponding position, outputting a 1D convolution result. The 2D processing array vertically accumulates the outputs of multiple 1D convolutional units within the same column. That is, the output of the first 1D convolutional unit in each column is passed to the next unit in the same column, which sums it with its own convolutional output, and so on, until the last unit in the column completes the summation. Finally, the bottom-most unit in the same column outputs the accumulated result for that column, which corresponds to a row in the 2D convolution result. The multi-column structure of the array ensures that the accumulation process of different columns can be performed in parallel, thus forming a complete 2D convolutional output matrix.

[0042] In the entire computation process, the input features and convolution kernels are first format-transformed, decomposing the 3D convolution task into 2D convolution and multi-channel summation operations. Assume the 2D convolution kernel size is R×S, the input feature size is M×N, and the output feature size is (M-R+1)×(N-S+1). The 2D processing array contains R×(M-R+1) one-dimensional convolution units, divided into R rows, with (M-R+1) one-dimensional convolution units in each row. The computation logic is as follows: the m-th row of the convolution kernel is input to the convolution kernel register group corresponding to all one-dimensional convolution units in the m-th row; the n-th row of the input features is input to the input feature shift register corresponding to all one-dimensional convolution units along the nth diagonal; the output of the one-dimensional computation unit in the same column is sequentially passed to adjacent one-dimensional computation units for accumulation, for example, when the last row is the 0th row (i.e.,...). Figure 3 The top row of the array (the one-dimensional computational unit in row 0) outputs the sum of the same column, and the sum of the kth column is the result of the kth row of the two-dimensional convolution. For example... Figure 5 The input features and weights are transformed into their input format, and the output simultaneously includes the weight elements corresponding to the R rows of two-dimensional convolution kernels and the M rows of two-dimensional input features. The two-dimensional processing array realizes single-channel two-dimensional convolution and multi-channel result accumulation to obtain the convolutional layer result. After the calculation is completed, the result is converted into a standard data format through output format transformation and then transmitted to other modules for subsequent feature extraction or network layer calculation.

[0043] In one exemplary embodiment, the outputs of one-dimensional convolutional units within the same column are accumulated, including: for all one-dimensional convolutional units in the j-th column, the output of the one-dimensional convolutional unit in the i-th row is passed to the accumulation input of the one-dimensional convolutional unit in the (i+1)-th row for accumulation; the accumulated sum of the outputs of the one-dimensional convolutional units in the last row of the j-th column is the convolution result of the j-th row in the two-dimensional convolution result; 1≤j≤the number of columns of the one-dimensional convolutional unit, 1≤i≤the number of rows of the one-dimensional convolutional unit - 1, and i and j are both integers.

[0044] In this embodiment, each column in the two-dimensional processing array corresponds to a set of one-dimensional convolutional units, and the accumulation of convolution results is performed sequentially along the column direction. Specifically, for all one-dimensional convolutional units in the j-th column, after the unit in the i-th row completes the multiplication and addition operation of the current input features and the convolution kernel weights, the output result is passed to the accumulation input of the one-dimensional convolutional unit in the (i+1)-th row through the internal connection path, so that the unit in the next row accumulates the output result from the unit in the previous row while performing its own convolution operation. Through this column-oriented cascading method, the accumulation process of the entire column can be completed step by step as the data flows through each row.

[0045] After all the one-dimensional convolutional units in column j have completed their accumulation and propagation, the output of the one-dimensional convolutional units in the last row of that column outputs the accumulated sum of that column. This result corresponds to the convolution output in the j-th row of the two-dimensional convolution result matrix. In other words, the accumulated output of each column represents a row of the two-dimensional convolution result matrix, thus realizing the column-by-column accumulation generation of the two-dimensional convolution. Through this column-by-column propagation and accumulation calculation logic, this embodiment can complete the calculation of the complete two-dimensional convolution result while maintaining a compact array structure.

[0046] like Figure 6 There are a total of p computation layers, where p is an integer greater than 1. In an exemplary embodiment, a convolutional cache and a convolutional cache loading module are also included. The convolutional cache is configured to store the input features, convolutional kernels, and output features required by the convolutional computation module. The convolutional cache loading module is configured to: if the current computation layer is the starting layer of the convolutional computation module, load the input features and convolutional kernels from the storage interface so that the current computation layer can perform computations based on the input features and convolutional kernels; if the next computation layer of the current computation layer is a convolutional layer, write the output features of the current computation layer into the convolutional cache for the convolutional layer to read; if the next computation layer of the current computation layer is a non-convolutional layer, directly input the output features of the current computation layer into the next computation layer; if the current computation layer is the last layer of the convolutional computation module, transmit the output features of the current computation layer to the storage interface.

[0047] In this embodiment, the convolution cache is used to store the required input features, convolution kernels, and generated output features during the convolution calculation process. The convolution cache is connected to the convolution calculation module via an internal data bus, allowing the convolution calculation module to directly read the input features and convolution kernel data from the cache during calculation. Through this structure, the convolution calculation module in this embodiment does not need to frequently access external memory during convolution operations, thus maintaining the continuity of data access and the consistency of the calculation process.

[0048] In actual operation, the convolutional cache loading module manages the loading and transfer of data between different computational layers. When the current computational layer is the starting layer of the convolutional computation module, the convolutional cache loading module receives input features and convolutional kernel data from the storage interface and loads them into the convolutional cache, enabling the convolutional computation module to perform convolutional computation on the current layer based on the loaded data. This loading process follows the computational sequence of the convolutional computation module, ensuring that the input features and convolutional kernels are accurately delivered to the corresponding computational units when needed.

[0049] After the convolution calculation is completed, the convolution cache loading module determines the storage and transmission path of the output features based on the relationship between the current layer and the next layer. When the next calculation layer is also a convolutional layer, the convolution cache loading module directly writes the output features of the current layer into the convolution cache, allowing the next layer's convolution calculation module to directly read data from the convolution cache, thereby achieving continuous calculation between layers. When the current layer is an output layer, the convolution cache loading module writes the convolution result to an external storage device for system output or subsequent processing.

[0050] Furthermore, when the current computation layer is an intermediate layer and the next layer is a non-convolutional computation layer such as an activation layer or a pooling layer, the convolution cache loading module transmits the convolution result to the subsequent one-dimensional or two-dimensional computation module for corresponding processing. If the current layer is an intermediate layer and the next layer is a convolutional layer, the convolution cache loading module maintains the continuous storage state of the data in the convolution cache, so that the next layer can directly read the cached data to perform convolution operations, thereby maintaining the hierarchical data association and flow of the entire computation process.

[0051] The convolution loading module reads input features (in blocks) and weights from external storage devices, such as DDR (Double Data Rate), first reading the compressed weight data, then reading the corresponding non-zero weight elements, and finally reading the weight compression flags, and writes them to the convolution cache.

[0052] By setting up a convolutional cache and a convolutional cache loading module, this embodiment enables hierarchical storage and reuse of data during multi-layer computation in the convolutional computation module, allowing input features, convolutional kernels, and output features to be used locally and cyclically across different computational layers. When the next layer is still a convolutional layer, the output features can be directly stored in the convolutional cache and read by subsequent layers, thereby reducing frequent access to the DDR and lowering data migration overhead. When the next layer is a non-convolutional layer or an output layer, data can be sent to the corresponding module or written to the DDR as needed, achieving unified data flow management and computational layer connection.

[0053] In one exemplary embodiment, the convolutional cache is further configured to read and write data in units of data blocks; the convolutional cache loading module is further configured to load data in units of data blocks, and for adjacent data blocks with overlapping data, when loading subsequent data blocks, only the non-overlapping data is loaded, and the overlapping data of the preceding data blocks already stored in the convolutional cache is reused.

[0054] In this embodiment, the convolutional cache is configured to be read and written in units of data blocks. A data block refers to a feature sub-region divided spatially or by channel during the convolution calculation process. The convolutional cache loading module uses data blocks as the smallest transmission unit, reading input features or convolutional kernels from the storage interface or the previous computation layer and writing them into the convolutional cache. Subsequent computation units retrieve the required data from the convolutional cache in blocks for computation. Due to the sliding window characteristic of convolution operations, when the entire layer input is decomposed into blocks, adjacent data blocks often have overlapping areas caused by the convolutional kernel window. Therefore, in this embodiment, the granularity of data access is fixed at blocks to establish a clear and consistent interface between access and computation.

[0055] In this embodiment, the convolutional cache loading module employs a differential loading strategy for overlapping portions when loading adjacent data blocks. Before loading subsequent data blocks, it first calculates the size of the overlapping region between the subsequent block and the cached preceding block. Then, it reads only the non-overlapping data from the subsequent block from external storage, while the overlapping data already existing in the convolutional cache is reused without being read repeatedly. Specifically, if the block size is B and the overlap size is O, the subsequent block only needs to read B0 data units from external storage and merge them into the overlapping region with the preceding block in the convolutional cache to form a complete block view, thereby avoiding redundant transmission and repeated writing of overlapping data.

[0056] To support the reuse of overlapping portions and the overwriting of non-overlapping portions, the feature storage area of ​​the convolutional cache in this embodiment adopts a circular cache structure to implement circular address mapping. The addresses of the circular cache are incremented sequentially from 0, and when a preset maximum address is reached, they wrap around to 0, achieving circular overwriting of consecutive blocks. When writing the next block of data, the convolutional cache loading module calculates the position of the overlapping region in the circular address space, prioritizing the writing of non-overlapping data read from the outside into the corresponding non-overlapping address segment, while keeping the corresponding overlapping region data in the circular buffer unoverwritten, or ensuring that the overlapping data is copied to a new location before overwriting the original address when overwriting is required, thereby achieving effective reuse and ordered overwriting of overlapping data within the circular space.

[0057] like Figure 7 The first time block 1 is read, block 1 includes the overlapping part of block 1 and block 2. When block 2 is read the second time, only the overlapping part of block 2, block 1 and block 2 is read. Assuming that only these two data blocks are included, the last block 2 and the first block 1 still have the part of block 2 covering block 1. So when block 1 is read again, it is only necessary to read the part of block 1, block 2 covering block 1. And so on, which can reduce the repeated reading of data.

[0058] In this embodiment, the convolutional cache loading module and the convolutional computation module work together to ensure data consistency and continuous computation. The loading module dynamically calculates the overlap range between the block to be loaded and the existing blocks in the cache based on the current computation sequence and the position of the convolutional kernel window, and triggers loading only the non-overlapping parts or triggering an overwrite operation at appropriate times. Before reading data from the convolutional cache each time, the convolutional computation module checks the valid bits or block descriptors of the corresponding block to confirm that the required data is ready. For cross-layer data streams, if the next layer is a convolutional layer, the convolutional cache loading module writes the output of the current layer into the circular convolutional cache for the next layer to read; if the next layer is a non-convolutional processing module, the data is forwarded or written back to the storage device according to the predetermined path. Through the above mechanism, this embodiment achieves the reuse and orderly overwriting of adjacent overlapping data in block-level read / write and circular cache address management, supports a continuous pipelined convolutional computation process, reduces the amount of data read, and thus reduces power consumption.

[0059] like Figure 8 In one exemplary embodiment, the system further includes a one-dimensional non-convolution module, which includes a first single-port memory and a second single-port memory. Even-numbered index values ​​of the lookup table are stored in the first single-port memory, and odd-numbered index values ​​of the lookup table are stored in the second single-port memory. The one-dimensional non-convolution module is configured to read two adjacent lookup table values ​​from the first single-port memory and the second single-port memory in parallel within the same clock cycle, based on the parity of the input values, to calculate the output value of the activation function.

[0060] This embodiment also includes a one-dimensional non-convolutional module, which comprises a first single-port memory and a second single-port memory. Even-numbered index values ​​of the lookup table are stored in the first single-port memory, and odd-numbered index values ​​are stored in the second single-port memory; both are single-port memories and are independent of each other. Figure 8 When N is even, the original table (i.e., the most basic lookup table) stores LUT[0]-LUT[N-1]. After parity grouping, we get the even table ELUT and the odd table OLUT. The even table ELUT stores LUT[0]-LUT[N-2], and the odd table OLUT stores LUT[0]-LUT[N-1]. When N is odd, the original table stores LUT[0]-LUT[N-1]. After parity grouping, we get the even table ELUT and the odd table OLUT. The even table ELUT stores LUT[0]-LUT[N-1], and the odd table OLUT stores LUT[1]-LUT[N-2].

[0061] During module operation, the input value is rounded or quantized to obtain the lookup index x. The module determines the parallel reading method of the two single-port memories based on the parity of the index to meet the requirement of simultaneously obtaining two adjacent lookup values, LUT[x] and LUT[x+1], within the same clock cycle.

[0062] In this embodiment, to achieve simultaneous reading of LUT[x] and LUT[x+1] within the same clock cycle, an even / odd table splitting mechanism is used for address and data layout. When the index x is even, LUT[x] is read from the first single-port memory (even-number table ELUT), and LUT[x+1] is read from the second single-port memory (odd-number table OLUT). When the index x is odd, LUT[x] is read from the second single-port memory (OLUT), and LUT[x+1] is read from the first single-port memory (ELUT). Since the two single-port memories respond independently to their respective address and read requests, this embodiment can return two adjacent lookup table values ​​in parallel within one clock cycle without using dual-port memory or register sets to copy the entire table.

[0063] Regarding the implementation of activation functions, this embodiment clearly distinguishes between the implementation methods of linear and nonlinear activation functions. Linear activation functions directly calculate the output value using multipliers and adders (the aforementioned one-dimensional convolution calculation module 12). Nonlinear activation functions (such as sigmoid and tanh) use lookup tables to replace direct calculation. For nonlinear functions using lookup tables, the module calculates the final output according to the given interpolation or weighting formula y=a×LUT[x+1]+(1-a)×LUT[x], where y is the calculated value of the nonlinear function, x is the lookup table index, and a is the interpolation coefficient. This embodiment requires that LUT[x] and LUT[x+1] be obtained simultaneously within the same clock cycle to complete one interpolation calculation. Therefore, parallel table lookup is a necessary condition for this calculation process.

[0064] Compared to implementations using register caches or dual-port memory, this embodiment achieves parallel read capability at the memory level through parity table splitting, thereby using a single-port memory with lower capacity and implementation cost while maintaining the requirement of same-cycle access for table lookup. After receiving the input value, the module first determines the parity of the index and issues corresponding address requests to the two single-port memories. Then, it returns LUT[x] and LUT[x+1] in parallel point-to-point. The multiplier and adder then perform interpolation calculations in the form y=a×LUT[x+1]+(1-a)×LUT[x] or the corresponding circuit calculates the linear activation output, and finally outputs the activation function result.

[0065] like Figure 9The system also includes a 2D nonconvolutional computation module for performing two types of nonconvolutional computations: pooling and data shape transformation (splitting and merging). This module uses a unified internal cache as a data scheduling center, receiving input data from a shared cache. Internally, the module employs a time-sharing multiplexing mechanism, with scheduling handled by two mutually exclusive logic units: pooling control and shape transformation control. During pooling computation, the control logic imports input data into the internal cache to generate the required 2D sliding window. After pooling, the result is output through a selector and a data write-out unit. Similarly, during data shape transformation (such as splitting or merging along the channel direction), the control logic reuses the internal cache to reorganize and temporarily store the data, ultimately outputting the transformed data. This design efficiently completes various 2D post-processing operations through hardware reuse by sharing the internal cache and control path, avoiding the need for independent circuits for each function and optimizing chip area and energy efficiency.

[0066] In one exemplary embodiment, a weight compression module is further included; the weight compression module is configured to: set a flag bit for the weight elements in the convolution kernel, remove weight elements with zero values ​​from the convolution kernel, and obtain compressed weight data including consecutive non-zero weight elements; the compressed weight information includes the flag bit of each weight element, the compressed weight data, and the number of non-zero weight elements; the convolution kernel includes multiple weight elements, and the flag bit includes a first flag bit and a second flag bit, the first flag bit indicating that the weight element is a zero value, and the second flag bit indicating that the weight element is a non-zero value.

[0067] This embodiment includes a weight compression module for sparsifying and compressing the convolution kernels used in convolution calculations. The weight compression module sets a flag bit for each weight element in the convolution kernel to distinguish its numerical state. Specifically, when a weight element is zero, its corresponding flag bit is the first flag bit (denoted as 0); when a weight element is non-zero, its corresponding flag bit is the second flag bit (denoted as 1). The flag bits of all weight elements are combined sequentially according to the order of the weight elements in the convolution kernel, forming a continuous set of weight compression flag data. Through this flag data, this embodiment can clearly define the logical position of each weight in the original matrix during subsequent calculations or loading.

[0068] While generating weight compression flags, this embodiment filters the weight data in the original convolutional kernel. The module determines whether the current weight is non-zero based on the flag value. If it is zero, it is directly discarded and no longer stored or calculated; if it is non-zero, it is retained and arranged sequentially into a continuous sequence of compressed weight data. After processing, the original convolutional kernel is decomposed into two parts: one part is compressed flag information composed of flag bits, used to record the sparse distribution of weights; the other part is the continuously stored compressed non-zero weight data. This embodiment removes invalid zero-value weights from the convolutional kernel in this way, making the data storage structure more compact.

[0069] Furthermore, this embodiment adds a record of the number of non-zero weights in the compressed weight information. The weight compression module counts the number of non-zero weight elements in each convolutional kernel while generating the compressed weight data, and incorporates this count as part of the compression result. Thus, as... Figure 10 The compressed weight information consists of three parts: including the weight compression flag (i.e., ... Figure 10 The three pieces of information—the flags of each weight element in the convolution kernel, the compressed weight data, and the number of non-zero weight elements after compression—together describe the complete sparse features and data content of a convolution kernel, enabling accurate recovery of the weight distribution and corresponding data during subsequent loading or decoding.

[0070] This embodiment, through the aforementioned compression mechanism, enables the convolution calculation module to store and read only the compressed non-zero weight data and corresponding flag bits when loading weight data, without needing to access all the original weight data. Since the storage size of the compressed weight data is significantly smaller than the original weight data, the module's data access volume during weight loading, transmission, and storage is reduced, and the reading cycle is shortened. In this way, this embodiment achieves effective management of sparse weights while maintaining the convolution kernel's logical structure, allowing the convolution calculation module to perform fixed-point calculations on non-zero weights based on the compressed weight structure, while simultaneously reducing overall data access bandwidth and system power consumption.

[0071] In one exemplary embodiment, a weight decompression module is further included, the input of which is configured to receive compressed weight information and the output of which is connected to the convolution calculation module. The weight decompression module is configured to fill the non-zero values ​​in the compressed weight data into the corresponding positions according to the data order of the original convolution kernel, based on the flag bits, and fill the positions where the flag bits indicate zero values ​​with zero, so as to recover the complete convolution kernel.

[0072] This embodiment includes a weight decompression module to restore the compressed weight information before the convolution calculation module performs its operations. The input of the weight decompression module receives the compressed weight information generated by the weight compression module, including a weight compression flag, compressed weight data, and the number of non-zero weight elements. Internally, the module parses the structural position of the convolution kernel bit by bit according to the weight compression flag and reconstructs the complete convolution kernel data step by step according to the order of the flag bits. When the flag bit is the second flag bit (e.g., 1), a non-zero weight value is read from the compressed weight data and filled into the corresponding position; when the flag bit is the first flag bit (e.g., 0), a zero value is filled into that position. Through this process, the module can logically recover the weight matrix structure in the original convolution kernel.

[0073] The output of the weight decompression module is connected to the convolution calculation module. After weight restoration, the recovered complete convolution kernel is transmitted to the convolution calculation module in real time to participate in subsequent convolution calculations. This embodiment adds a weight decompression module to the data stream, enabling the convolution calculation module to receive convolution kernel input in the same way as uncompressed weights, without requiring additional control logic, thus ensuring the continuity and structural consistency of convolution calculations. Furthermore, the logic in this embodiment does not require repeatedly storing and retrieving zero-value weight elements, reducing bandwidth consumption, data processing time, and power consumption.

[0074] In one exemplary embodiment, a convolutional data distribution module is further included, with its first output end connected to the convolutional calculation module and its second output end connected to the weight decompression module; the convolutional data distribution module is configured to output the acquired input features to the convolutional calculation module and output the compressed weight information to the weight decompression module.

[0075] This embodiment includes a convolutional data distribution module to achieve parallel distribution and independent transmission of input features and compressed weight information during the input phase of the convolution calculation process. The input end of the convolutional data distribution module receives a data stream from a storage interface or a convolutional cache loading module, which simultaneously contains input feature data and compressed weight information. The module performs type identification and stream splitting on the received data, transmitting the input feature data to the convolution calculation module via the first output end for convolution calculation operations; simultaneously, it transmits the compressed weight information to the weight decompression module via the second output end for weight restoration.

[0076] This structural design enables parallel transmission and processing of input features and compressed weights within the system. The convolution calculation module and the weight decompression module can operate simultaneously, maintaining the continuity of the computation pipeline. This embodiment allows the convolution calculation module to receive input features while simultaneously waiting for the convolution kernel decompression to complete, avoiding the idle periods caused by the sequential loading of inputs and weights in traditional structures. This ensures efficient data flow and synchronous processing between convolutional layers, improving the utilization of computational units and reducing overall latency.

[0077] In one exemplary embodiment, the system further includes an instruction parsing module, whose input is connected to the storage interface and whose output is connected to the convolutional data distribution module and the convolutional calculation module, respectively. The instruction parsing module is configured to read custom instructions in units of neural network layers from the storage interface and parse each custom instruction into a sequence of micro-instructions in units of data blocks.

[0078] This embodiment includes an instruction parsing module, used to decompose and control the execution of neural network layer instructions during the accelerator's computation scheduling phase. For example... Figure 11 The instruction parsing module's input is connected to the storage interface, used to read instructions from the instruction cache in the external storage device. It retrieves custom instructions, organized by neural network layer, which contain control information such as layer type, input / output data location, weight data location, and execution order. After reading the custom instructions, the module parses and structurally divides them, breaking each custom instruction down into multiple micro-instruction sequences processed in data blocks. Based on the instruction content, the module distributes the corresponding micro-instructions to the convolutional data distribution module and the convolutional computation module to control their execution.

[0079] This embodiment introduces an instruction parsing module into the hardware structure, enabling the accelerator to perform autonomous task scheduling on a layer-by-layer basis and to achieve fine-grained management of the computation process at the data block level. This design allows the system to flexibly configure data paths and computation flows based on custom instructions when dealing with different layer structures (such as convolutional layers, pooling layers, and activation layers). This allows for layered execution of edge-side neural networks without relying on external controllers, enhancing the accelerator's versatility and scalability, and making computational switching between different layers more efficient and seamless.

[0080] like Figure 2 In one specific embodiment, the execution flow of this accelerator begins with the instruction parsing module, which reads instructions from the storage device through the bus interface module and the on-chip network, and parses them into microinstructions which are then distributed to each submodule. Figure 2(The communication connections between the module and its various sub-modules are not shown in the diagram.) The convolutional cache loading module loads the input features and compressed weight data from the storage device into the convolutional cache according to instructions. Subsequently, the convolutional data distribution module reads out the data, where the weight data is restored by the weight decompression module and sent together with the feature data to the convolutional calculation module to complete the core convolution operation. The calculation results can be directly passed to the one-dimensional or two-dimensional non-convolutional module for further processing, or used for data interaction and temporary storage between modules via the shared cache. The shared cache access module is responsible for the unified reading and writing of data between the shared cache and the storage device, thereby achieving high-efficiency inference of the edge neural network under the premise of strictly controlling off-chip memory access.

[0081] Secondly, this application also provides a server, including the aforementioned accelerator.

[0082] The server includes the aforementioned accelerator for performing convolutional computation tasks of deep neural networks in edge or data center environments. By integrating the accelerator, the server achieves efficient processing of input feature and weight data, including multiple circuit modules such as one-dimensional and two-dimensional convolutional computation, weight compression and decompression, convolutional data distribution, and instruction parsing, thereby supporting parallel computation and efficient data flow management for each layer of the neural network.

[0083] For further details regarding the server, please refer to the above embodiments; this application will not repeat them here.

[0084] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] The above provides a detailed description of an accelerator and server provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An accelerator, characterized in that, include: Storage interface and convolution calculation module; The storage interface is configured to connect to a storage device, and the convolution calculation module includes a convolution splitting module, a one-dimensional convolution calculation module, and a two-dimensional convolution calculation module. The convolution decomposition module is connected to the storage interface and configured to perform dimensionality decomposition processing on the input features and convolution kernels obtained from the storage interface. The dimensionality decomposition processing includes decomposing the three-dimensional convolution into multiple two-dimensional convolutions in the channel dimension to obtain two-dimensional input features and two-dimensional convolution kernels, and decomposing each two-dimensional convolution into multiple one-dimensional convolutions in the vertical direction to obtain one-dimensional input features and one-dimensional convolution kernels. The one-dimensional convolution calculation module is connected to the convolution splitting module and is configured to perform one-dimensional convolution calculation based on the one-dimensional input features and the one-dimensional convolution kernel to obtain a one-dimensional convolution result. The two-dimensional convolution calculation module is connected to the convolution splitting module and is configured to combine and accumulate multiple one-dimensional convolution results based on the two-dimensional input features and the two-dimensional convolution kernel to obtain a two-dimensional convolution result.

2. The accelerator according to claim 1, characterized in that, The one-dimensional convolution calculation module includes at least one one-dimensional convolution unit, and the one-dimensional convolution unit includes: The kernel register group is configured to store the weight elements corresponding to the one-dimensional convolution kernel; An input feature shift register is configured to store the one-dimensional input features in a sliding window manner; The dot product calculation module has its first input connected to the convolution kernel register group and its second input connected to the input feature shift register. The dot product calculation module is configured to perform parallel dot product operations on the weight elements corresponding to the one-dimensional convolution kernel and the one-dimensional input features in the sliding window, and output the one-dimensional convolution result.

3. The accelerator according to claim 2, characterized in that, The dot product calculation module includes: A multiplier has its first input connected to the convolution kernel register group and its second input connected to the input feature shift register; the multiplier is configured to perform parallel multiplication operations on the weight elements in the convolution kernel register group and the one-dimensional input features in the input feature shift register to obtain multiple multiplication results; An adder, connected to the output of the multiplier, is configured to sum the multiplication results and output the one-dimensional convolution result.

4. The accelerator according to claim 2, characterized in that, The two-dimensional convolution calculation module includes a two-dimensional processing array, which reuses multiple one-dimensional convolution units in the one-dimensional convolution calculation module. The number of rows of the one-dimensional convolution unit is the same as the number of rows of the two-dimensional convolution kernel. The number of columns of the one-dimensional convolution unit is determined according to the number of rows of the two-dimensional input features and the number of rows of the two-dimensional convolution kernel. The two-dimensional processing array is configured to input each row of weight elements of the two-dimensional convolution kernel into the convolution kernel register group of the corresponding one-dimensional convolution unit in the same row, input each row of data of the two-dimensional input features into the input feature shift register of the corresponding one-dimensional convolution unit in the diagonal direction according to the calculation time sequence, and accumulate the outputs of the one-dimensional convolution units in the same column to generate the final two-dimensional convolution result.

5. The accelerator according to claim 4, characterized in that, Accumulating the outputs of the one-dimensional convolutional units within the same column includes: For all the one-dimensional convolutional units in the j-th column, the output of the one-dimensional convolutional unit in the i-th row is passed to the accumulation input of the one-dimensional convolutional unit in the (i+1)-th row for accumulation. The sum of the outputs of the one-dimensional convolutional units in the last row of the j-th column is the convolution result of the j-th row in the two-dimensional convolution result; 1≤j≤ the number of columns of the one-dimensional convolutional unit, 1≤i≤ the number of rows of the one-dimensional convolutional unit - 1, and i and j are both integers.

6. The accelerator according to claim 1, characterized in that, It also includes a convolution cache and a convolution cache loading module; The convolution cache is configured to store the input features, convolution kernels, and output features required by the convolution calculation module. The convolutional cache loading module is configured as follows: if the current computation layer is the starting layer of the convolutional computation module, the input features and the convolutional kernel are loaded from the storage interface so that the current computation layer can perform computations based on the input features and the convolutional kernel; if the next computation layer of the current computation layer is a convolutional layer, the output features of the current computation layer are written into the convolutional cache for the convolutional layer to read; if the next computation layer of the current computation layer is a non-convolutional layer, the output features of the current computation layer are directly input into the next computation layer; if the current computation layer is the last layer of the convolutional computation module, the output features of the current computation layer are transmitted to the storage interface. The convolutional cache is also configured to perform read and write operations in units of data blocks. The convolutional cache loading module is further configured to load data in units of data blocks. For adjacent data blocks that have data overlap, when loading subsequent data blocks, only the non-overlapping data is loaded, and the overlapping data of the preceding data blocks already stored in the convolutional cache is reused.

7. The accelerator according to claim 1, characterized in that, Also includes: A one-dimensional non-convolution module, comprising a first single-port memory and a second single-port memory, wherein even-numbered index values ​​of a lookup table are stored in the first single-port memory and odd-numbered index values ​​of the lookup table are stored in the second single-port memory. The one-dimensional non-convolutional module is configured to read two adjacent lookup table values ​​from the first single-port memory and the second single-port memory in parallel within the same clock cycle, based on the parity of the input value, in order to calculate the output value of the activation function.

8. The accelerator according to any one of claims 1-7, characterized in that, It also includes a weight compression module; The weight compression module is configured to: set a flag bit for the weight elements in the convolution kernel, remove weight elements with zero values ​​from the convolution kernel, and obtain compressed weight data including consecutive non-zero weight elements; The compressed weight information includes the flag bits of each weight element, the compressed weight data, and the number of non-zero weight elements; the convolution kernel includes multiple weight elements, and the flag bits include a first flag bit and a second flag bit, where the first flag bit indicates that the weight element is zero and the second flag bit indicates that the weight element is non-zero. The weight decompression module is configured to receive the compressed weight information at its input end and to be connected to the convolution calculation module at its output end. The weight decompression module is configured to: fill the non-zero values ​​in the compressed weight data into the corresponding positions according to the flag bit and the order of the weight elements in the original convolution kernel, and fill the positions where the flag bit indicates a zero value with zero, so as to recover the complete original convolution kernel.

9. The accelerator according to claim 8, characterized in that, It also includes a convolutional data distribution module, whose first output is connected to the convolutional calculation module, and whose second output is connected to the weight decompression module; The convolutional data distribution module is configured to: output the acquired input features to the convolutional calculation module, and output the compressed weight information to the weight decompression module.

10. A server, characterized in that, Including the accelerator as described in any one of claims 1-9.

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