Graphic processor, image processing method and electronic equipment

Abstract

The invention relates to a graphics processor, an image processing method and electronic equipment, and relates to the technical field of image processing. The graphics processor comprises a gradient LOD calculation circuit and a shader. The LOD calculation circuit is used for obtaining the gradient LOD of a plurality of effective pixels in the image frame in the texture space, and the effective pixels are used for forming primitives in the image; and the shader is used for coloring the plurality of effective pixels according to the LOD of the plurality of effective pixels. Therefore, computing resources can be saved.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and more particularly to a graphics processor, an image processing method, and an electronic device. Background Technology

[0002] In graphics processing systems, texture values ​​(such as color, brightness, and transparency) from texture maps can be applied to the surface of an image to color it. MipMap is a texture mapping technique used to optimize graphics texture rendering for better performance and visual effects. MipMap pre-stores texture maps of different resolutions. When coloring an image, the texture map of the appropriate resolution is selected based on the distance of the object. For example, a lower-resolution texture map is selected for distant objects, and a higher-resolution texture map is selected for closer objects. This improves rendering efficiency. However, using MipMap for image coloring can lead to wasted computational resources. Summary of the Invention

[0003] This application provides a graphics processor, an image processing method, and an electronic device, which solves the problem of wasted computing resources in the prior art.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] Firstly, a graphics processing unit (GPU) is provided, comprising a level of detail (LOD) calculation circuit and a shader. The LOD calculation circuit is used to obtain the LOD of multiple effective pixels in texture space within an image frame; these effective pixels are used to constitute primitives in the image. The shader is used to color the multiple effective pixels based on their LODs.

[0006] In the above technical solution, by setting up a LOD calculation circuit outside the shader, the processor's rendering pipeline flow is altered, bringing LOD calculation forward to before pixels are input into the shader. The shader would normally color all input pixels. The LOD calculation circuit can output only the LOD of valid pixels to the shader. Therefore, the shader only colors valid pixels. This reduces the number of threads required for shader execution, minimizes wasted computational resources, and improves GPU processing efficiency.

[0007] In one possible implementation of the first aspect, the LOD calculation circuit is specifically used to obtain the LOD of multiple valid pixels based on the texture coordinates of multiple valid pixels. In the above possible implementation, the LOD of valid pixels can be calculated using the texture coordinates of the valid pixels, requiring less data and having lower data caching requirements.

[0008] In one possible implementation of the first aspect, the image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels. The LOD calculation circuit is specifically used to obtain the LOD of multiple valid pixels based on the texture coordinates of the multiple valid pixels and the texture coordinates of the auxiliary pixels corresponding to the multiple valid pixels. In the above possible implementations, the LOD of the valid pixels can be calculated using the texture coordinates of the valid pixels and the texture coordinates of the auxiliary pixels, making the calculation method relatively simple.

[0009] In one possible implementation of the first aspect, the multiple valid pixels include a first valid pixel and a second valid pixel, wherein the first valid pixel and the second valid pixel are located in different primitives in the image. In the above possible implementations, the multiple valid pixels colored by the shader are not limited to valid pixels in the same primitive; valid pixels from multiple primitives can be input to the shader in the same processing. Thus, the number of pixels input to the shader in the same processing does not need to be changed, and this scheme is compatible with the original shader input procedure.

[0010] In one possible implementation of the first aspect, the GPU further includes a packing circuit. The packing circuit is used to acquire basic unit information, where each basic unit consists of multiple valid pixels. The basic unit information includes the texture coordinates of the multiple valid pixels in texture space. A shader is specifically used to shade the multiple valid pixels based on the texture coordinates of the multiple valid pixels in the basic unit information and the LOD of the multiple valid pixels. In the above possible implementation, the shader shades all pixels in a basic unit. Since the basic unit input to the shader only includes valid pixels, the first pixel shader only shades the valid pixels that need to be shaded. The first pixel shader does not shade auxiliary pixels that do not need to be shaded. Therefore, the number of threads required for shader operation can be reduced, the problem of wasted computational resources can be decreased, and the processing efficiency of the GPU can be improved.

[0011] Secondly, an image processing method is provided, which is applied to a GPU, the GPU including a Level of Depth (LOD) calculation circuit and a shader. The image processing method includes: obtaining the gradient LOD of multiple effective pixels in texture space through the LOD calculation circuit, the effective pixels being used to constitute primitives in the image; and coloring the multiple effective pixels according to their LODs using the shader.

[0012] In one possible implementation of the second aspect, obtaining the gradient LOD of multiple effective pixels in the texture space of an image frame includes: obtaining the LOD of multiple effective pixels based on the texture coordinates of the multiple effective pixels using an LOD calculation circuit.

[0013] In one possible implementation of the second aspect, the image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels. Obtaining the gradient LOD of multiple valid pixels in the texture space includes: using an LOD calculation circuit to obtain the LOD of multiple valid pixels based on their texture coordinates and the texture coordinates of the corresponding auxiliary pixels.

[0014] In one possible implementation of the second aspect, the plurality of valid pixels includes a first valid pixel and a second valid pixel, the first valid pixel and the second valid pixel being located in different primitives in the image.

[0015] In one possible implementation of the second aspect, the GPU further includes a packing circuit. The image processing method also includes: obtaining basic unit information via the packing circuit, wherein each basic unit consists of multiple valid pixels, and the basic unit information includes the texture coordinates of the multiple valid pixels in texture space; and coloring the multiple valid pixels according to their LODs via a shader, including: coloring the multiple valid pixels according to the texture coordinates of the multiple valid pixels in the basic unit information and the LODs of the multiple valid pixels via a shader.

[0016] Thirdly, an electronic device is provided, comprising a circuit board and a GPU provided by the first aspect or any possible implementation thereof.

[0017] In another aspect, this application provides a computer-readable storage medium storing program code that can be invoked by a processor to execute the image processing method provided by the second aspect or any possible implementation thereof.

[0018] In another aspect, this application provides a computer program product that, when run on a computer, causes the computer to perform the image processing method provided by the second aspect or any possible implementation thereof.

[0019] Understandably, any of the image processing methods, electronic devices, computer storage media, or computer program products provided above are used in the corresponding GPUs provided above. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding GPUs provided above, and will not be repeated here. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0021] Figure 2 A schematic diagram of a processor provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of a texture mapping technique provided in an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of a multi-level texture technology provided in an embodiment of this application;

[0024] Figure 5 A schematic diagram illustrating gradient calculation provided in an embodiment of this application;

[0025] Figure 6 A schematic diagram of an effective pixel and auxiliary pixels provided for an embodiment of this application;

[0026] Figure 7 A schematic diagram of a first processor and a corresponding rendering pipeline provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram of pixel coloring provided in an embodiment of this application. Figure 1 ;

[0028] Figure 9 A schematic diagram of a second processor and a corresponding rendering pipeline provided in an embodiment of this application;

[0029] Figure 10 A schematic diagram of pixel coloring provided in an embodiment of this application. Figure 2 ;

[0030] Figure 11 This application provides an illustration of an image processing method. Figure 1 ;

[0031] Figure 12 This application provides an illustration of an image processing method. Figure 2 . Detailed Implementation

[0032] It should be noted that the terms "first" and "second" used in the embodiments of this application are only used to distinguish features of the same type and should not be construed as indicating relative importance, quantity, order, etc.

[0033] The terms "exemplary" or "for example" used in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0034] The terms "coupling" and "connection" used in the embodiments of this application should be interpreted broadly. For example, they can refer to a physical direct connection or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0035] First, the application scenarios of the embodiments of this application will be introduced. The embodiments of this application can be applied to electronic devices with image processing functions.

[0036] like Figure 1 As shown, the electronic device 1000 may include a processor 100, a memory 200, a multimedia component 300, and a sensor component 400. The electronic device 1000 may also include a circuit board (…). Figure 1 (Not shown), the processor 100 and memory 200 can be mounted on this circuit board.

[0037] The memory 200 includes internal memory and external memory. The internal memory may be RAM and integrated with the processor 100. The memory 200 stores data, software programs, and various software modules, primarily including a program storage area and a data storage area. The program storage area can store the operating system and at least one application program required to implement functional modules; the data storage area can store various data created according to the usage status of the electronic device 1000, such as audio data, display data, or spreadsheet data. The memory 200 may also include high-speed random access memory or non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0038] The processor 100 is the control center of the electronic device 1000. It connects various parts of the device via different interfaces and lines, and implements various functions of the electronic device 1000 by running or executing applications stored in the memory 200 and accessing various data in the memory 200. The processor 100 typically includes one or more processing units. In this embodiment, the processor 100 may include a central processing unit (CPU) and a graphics processing unit (GPU). Optionally, the processor 100 may also include an application processor (AP), a modem processor, an image signal processor (ISP), a controller, a video playback codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc.

[0039] The multimedia component 300 includes a display screen 311 and an audio / video unit 312. The display screen 311 may be a touch panel, which includes one or more touch sensors for receiving user input signals, such as swiping, touching, or clicking on the display screen 311. The display screen 311 also receives and displays data to be displayed. Furthermore, when the electronic device 1000 is in video playback mode, the audio / video unit 312 can support video playback by the electronic device 1000.

[0040] Sensor assembly 400 includes one or more sensors, such as power consumption sensor 411 and application sensor 412, for providing various aspects of status assessment for electronic device 1000. Sensor assembly 400 can detect power consumption, orientation, on / off state, relative positioning of components, or temperature changes of electronic device 1000. Sensor assembly 400 may also include gyroscope sensors, magnetic sensors, pressure sensors, or temperature sensors. Furthermore, sensor assembly 400 may include scene sensors for detecting the application scenario of electronic device 1000, such as 2D watch faces, time displays, fitness tracking, information displays, mobile payments, mobile calls, video playback, music playback, or 3D watch faces. Power supply 500 provides power to the various components of electronic device 1000. Power supply 500 may include a power management system, one or more power supplies, or other components associated with the generation, management, and distribution of power by electronic device 1000.

[0041] like Figure 2 As shown, processor 100 can be a GPU. Processor 100 may include a vertex shader 110, a rasterizer 120, a pixel shader (PS) 130, a pixel processing circuit 140, a texture processing circuit 150, and a tile buffer 160. The coupling relationships between these components can be found in [reference needed]. Figure 2 Vertex shader 110 and pixel shader 130 can be set in the same entity, for example, both vertex shader 110 and pixel shader 130 can be set in the shader kernel ( Figure 2 (Not shown)

[0042] Processor 100 can divide a frame of image into multiple tiles, each tile including at least one primitive. A tile is a unit for parallel processing of a frame of image. A primitive can be a point, line, or polygon formed by one or more vertices. For example, a primitive can be a triangle formed by connecting three vertices. Multiple primitives constitute an object or background, forming an image visible to the human eye. Each primitive can include at least one pixel, which is the basic unit of coloring.

[0043] The processor 100 can process all tiles constituting an image frame in parallel through multiple channels including a vertex shader 110, a rasterizer 120, a pixel shader 130, and a pixel processing circuit 140, and store the processed results in a tile buffer 160. When all tiles of an image frame have been processed, the processor 100 can send the multiple processing results stored in the tile buffer 160 to the frame buffer of the memory 200. Figure 1 and Figure 2 (Not shown).

[0044] Vertex shader 110 can be used to generate primitives in a tile and output the primitives to rasterizer 120. Rasterizer 120 can be used to rasterize the primitives to generate pixels and output the rasterized image data to pixel shader 130. Pixel shader 130 can be used to perform pixel shading on the rasterized image data to determine the pixel value. The pixel value may include information such as color, brightness, surface texture, etc. During pixel shading, pixel shader 130 can generate stereoscopic and realistic 3D graphics using the pixel values ​​generated by the texture. Texture processing circuitry 150 can be used to store texture maps, or texture processing circuitry 150 can be used to retrieve texture maps from memory 200. Pixel shader 130 can be used to request texture processing circuitry 150 to send the pixel value corresponding to the pixel. Texture processing circuitry 150 can be used to output the pixel value generated based on the texture map to pixel shader 130. The pixel processing circuit 140 can be used to perform a late depth test on the pixels to determine the final displayed pixel value. The tile buffer 160 can be used to store all the pixel values ​​corresponding to a tile. When the processing of all tiles of a frame image is completed, the tile buffer 160 can be used to send the processing results stored in the tile buffer 160 to the frame buffer of the memory 200.

[0045] After introducing the application scenarios of the embodiments of this application, some technologies involved in the embodiments of this application will be introduced.

[0046] Figure 3 An example of texture mapping technology is shown. Pixels produced by rasterization can be screen pixels located in screen space, using screen coordinates. Pixels in a texture map can be texture pixels (Texels) located in texture space, using texture coordinates. A mapping relationship exists between the screen coordinates of screen pixels and the texture coordinates of texture pixels. For example, in... Figure 3 In this model, the four vertices of a screen pixel correspond one-to-one with the four vertices of a texture pixel. Based on the mapping relationship between screen coordinates and texture coordinates, the texture coordinates corresponding to the screen pixel can be determined, and the texture value (such as color, brightness, roughness, and transparency) at the corresponding coordinates of the texture map can be obtained. Based on the texture value corresponding to that screen pixel, the screen pixel can be shading.

[0047] In 3D images, there may be thousands of objects, each corresponding to a texture map. Typically, both distant and near objects use high-resolution texture maps. However, distant objects may have fewer screen pixels, while high-resolution texture maps have more texture pixels. This means that the screen pixels of distant objects cover a large number of texture pixels, making it difficult for the texture processing circuitry 150 to retrieve the correct pixel values. Therefore, the MipMap technique proposes a scheme that uses low-resolution texture maps for distant objects and high-resolution texture maps for near objects.

[0048] Figure 4 An example of the MipMap technique is shown. The MipMap technique pre-stores texture maps at different resolutions. For example, in... Figure 4 In this context, the number of mip levels is abbreviated as L. L=0 corresponds to a texture map resolution of 8x8, L=1 corresponds to a texture map resolution of 4x4, and L=2 corresponds to a texture map resolution of 2x2. When shading an image, a texture map with a resolution appropriate to the distance of the object is selected. For example, a lower-resolution texture map is selected for distant objects, making it less noticeable to the user; a higher-resolution texture map is selected for nearby objects. This reduces the number of texture pixels in the texture map for distant objects, allowing the texture processing circuit 150 to more easily retrieve the correct pixel values ​​for them. Furthermore, less memory cache is involved when retrieving pixel values ​​for distant objects, improving rendering efficiency.

[0049] Next, combine Figure 5 This section illustrates how to determine the appropriate number of texture layers for an object based on the level of detail (LOD) of screen pixels in texture space. LOD refers to the precision of a 3D image. The screen coordinates of a screen pixel can refer to the center point of that pixel, for example... Figure 5 The shaded area in the image shows the screen coordinates of the screen pixel, which can refer to the coordinates of the center point P4. The four vertices of this screen pixel can be replaced by the center point P1 of the top-left screen pixel, the center point P2 of the screen pixel above it, the center point P3 of the screen pixel to its left, and the center point P4 of the screen pixel. The four vertices of the texture pixel are Q1, Q2, Q3, and Q4.

[0050] In screen space, the coordinates of P1 can be (x, y), the coordinates of P2 can be (x+1, y), the coordinates of P3 can be (x, y+1), and the coordinates of P4 can be (x+1, y+1). The lengths of |P1P2| and |P1P3| are both 1.

[0051] In texture space, the coordinates of Q1 can be (m1, n1), the coordinates of Q2 can be (m2, n2), and the coordinates of Q3 can be (m3, n3).

[0052]

[0053]

[0054] The LOD value corresponding to this screen pixel can be... or LOD can be the larger of these two values. The number of texture layers can be equal to LOD.

[0055] As can be seen, determining the appropriate number of texture layers for a screen pixel requires not only the screen coordinates of that pixel but also the screen coordinates of its adjacent pixels. For example... Figure 6 As shown, the triangular primitive comprises three screen pixels, which can be referred to as valid pixels. The screen pixels surrounding the triangular primitive can be divided into helper pixels and invalid pixels. Helper pixels are screen pixels used to calculate the LOD of valid pixels. Invalid pixels are screen pixels that cannot be used to calculate the LOD of valid pixels. Neither helper pixels nor invalid pixels are included within the triangular primitive.

[0056] In one possible implementation, both effective pixels and auxiliary pixels are colored during pixel coloring.

[0057] like Figure 7 As shown in Figure (a), processor 100 can be a first processor 100A, pixel shader 130 can be a first pixel shader 130A, and first processor 100A may also include warp circuitry 170. It is understood that first processor 100A may include more or fewer devices, and this application embodiment does not limit this. First processor 100A uses MipMap technology to enable the rendering pipeline to... Figure 7 As shown in Figure (b), vertex shader 110 can be used to generate primitives. Rasterizer 120 can be used to rasterize the primitives to obtain image data. The image data may include the screen coordinates and texture coordinates of valid pixels belonging to the primitive, the screen coordinates and texture coordinates of auxiliary pixels not belonging to the primitive, and the screen coordinates and texture coordinates of invalid pixels not belonging to the primitive.

[0058] In some examples, the packing circuitry can be used to divide multiple screen pixels in the image data into multiple basic units that can be scheduled in parallel by a first pixel shader 130A, and output the coordinates of these basic units to the first pixel shader 130A. Each basic unit includes multiple screen pixels. For example, if the image data includes 64 screen pixels, it can be divided into 4 basic units, each of which includes 16 screen pixels. Optionally, a basic unit can include both active pixels and auxiliary pixels.

[0059] The first pixel shader 130A takes multiple basic units as input and performs Level of Detail (LOD) calculations for each screen pixel within a basic unit. After calculating the LOD, the number of texture layers for each screen pixel is determined, and an appropriate texture map is selected to shade each screen pixel. The pixel processing circuit 140 can be used for depth testing, and the tested screen pixels are then blended. Valid pixels are ultimately stored in the frame buffer, while auxiliary pixels are not stored in the frame buffer.

[0060] For example, such as Figure 8 As shown, a basic unit consists of 16 screen pixels arranged in a 4x4 (4 rows and 4 columns) grid. Five of these pixels constitute the triangular primitive: A3 (2nd row, 2nd column), A6 (2nd row, 3rd column), A9 (3rd row, 2nd column), A12 (3rd row, 3rd column), and A11 (4th row, 2nd column). The remaining screen pixels A0, A1, A2, A4, A5, A7, A8, A10, A13, A14, and A15 are auxiliary pixels.

[0061] In this implementation, the first pixel shader 130A calculates the Level of Rendering (LOD) and colors all screen pixels (e.g., 16 screen pixels, A0 to A15) within a basic unit. Since a basic unit includes both effective pixels and auxiliary pixels, the first pixel shader 130A needs to run multiple threads to color auxiliary pixels that wouldn't normally require coloring (e.g., 11 auxiliary pixels, A0, A1, A2, A4, A5, A7, A8, A10, A13, A14, and A15). Therefore, when using MipMap technology for image coloring, there is a waste of computational resources. Furthermore, as game models become increasingly sophisticated, the number of primitives increases, while the number of effective pixels covered by these primitives decreases, leading to even greater waste.

[0062] In another possible implementation, during pixel coloring, the effective pixels are colored, but the auxiliary pixels are not colored.

[0063] like Figure 9As shown in Figure (a), processor 100 can be a second processor 100B, pixel shader 130 can be a second pixel shader 130B, and the second processor 100B may further include warp circuitry 170 and LOD calculation circuitry 180. It is understood that the second processor 100B may include more or fewer devices, and this embodiment does not limit this. The second processor 100B uses MipMap technology to enable the rendering pipeline to... Figure 9 As shown in Figure (b), vertex shader 110 can be used to generate primitives. Rasterizer 120 can be used to rasterize the primitives to obtain image data. The image data may include the screen coordinates and texture coordinates of valid pixels belonging to the primitive, the screen coordinates and texture coordinates of auxiliary pixels not belonging to the primitive, and the screen coordinates and texture coordinates of invalid pixels not belonging to the primitive.

[0064] In some examples, the LOD calculation circuit 180 can be used to obtain the LOD of multiple valid pixels in texture space in an image frame, where the valid pixels are used to constitute primitives in the image. The second pixel shader 130B can be used to shade the multiple valid pixels based on their LODs.

[0065] For example, the LOD calculation circuit 180 can be used to input image data. The LOD calculation circuit 180 can be used to calculate the LOD of multiple valid pixels. The LOD calculation circuit 180 is also used to output the screen coordinates, texture coordinates, and LOD of the multiple valid pixels to the second pixel shader 130B. The second pixel shader 130B can be used to input the screen coordinates, texture coordinates, and LOD of the multiple valid pixels, determine a texture map corresponding to the resolution based on the LOD of each valid pixel, and shade the valid pixel based on the texture map and screen coordinates of each valid pixel. The pixel processing circuit 140 can be used for depth testing, and the tested screen pixels are blended. Valid pixels are ultimately stored in the frame buffer, while auxiliary pixels are not stored in the frame buffer.

[0066] In this embodiment, by setting up a LOD calculation circuit 180 outside the second pixel shader 130B, the rendering pipeline of the second processor 100B is altered, and the LOD calculation is advanced to before the pixels are input into the second pixel shader 130B. The second pixel shader 130B shades all input pixels. The LOD calculation circuit 180 can output only the LOD of valid pixels to the second pixel shader 130B. Therefore, the second pixel shader 130B only shades valid pixels and does not shade auxiliary pixels. This reduces the number of threads required for the second pixel shader 130B to run, decreases wasted computational resources, and improves the processing efficiency of the second processor 100B.

[0067] In some examples, the LOD calculation circuit 180 calculates the LOD of the effective pixels by using the texture coordinates of the effective pixels and the texture coordinates of the auxiliary pixels.

[0068] For example, the image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels. The LOD calculation circuit 180 is specifically used to obtain the LOD of multiple valid pixels based on the texture coordinates of the multiple valid pixels and the texture coordinates of the auxiliary pixels corresponding to the multiple valid pixels. For example, the LOD of the valid pixels is obtained by interpolating the texture coordinates of the valid pixels and the corresponding auxiliary pixels and then performing a difference calculation.

[0069] In this embodiment, the LOD of the effective pixel can be calculated using the texture coordinates of the effective pixel and the texture coordinates of the auxiliary pixel, which is a relatively simple calculation method.

[0070] In some examples, the LOD calculation circuit 180 calculates the LOD of the effective pixels using the texture coordinates of the effective pixels, without using the texture coordinates of the auxiliary pixels.

[0071] For example, the LOD calculation circuit 180 is specifically used to obtain the LOD of multiple effective pixels based on the texture coordinates of multiple effective pixels. For example, the LOD of the effective pixels is obtained by differentiating the interpolation formula.

[0072] In this implementation, the LOD of the effective pixels can be calculated using the texture coordinates of the effective pixels. The calculation process requires less data and has a smaller data caching requirement.

[0073] In some examples, the LOD calculation circuit 180 can output the screen coordinates, texture coordinates, and LOD of multiple valid pixels to the second pixel shader 130B via a packing circuit.

[0074] The packing circuit can be used to input the screen coordinates, texture coordinates, and LOD of multiple valid pixels. The packing circuit can also be used to divide the multiple valid pixels into multiple basic units that can be scheduled in parallel by the second pixel shader 130B. A basic unit consists of multiple valid pixels. For example, image data includes 64 screen pixels, of which 32 are valid pixels. These valid pixels are divided into two basic units, each containing 16 valid pixels. Optionally, a basic unit may only include valid pixels and not auxiliary pixels. The packing circuit can also be used to acquire basic unit information, which may include the texture coordinates of the multiple valid pixels in texture space, and may also include screen coordinates and LOD. The packing circuit can also be used to output the screen coordinates, texture coordinates, and LOD of the multiple basic units to the second pixel shader 130B.

[0075] The second pixel shader 130B can be used to take multiple basic unit information as input and shade each valid pixel in a basic unit. Specifically, the second pixel shader 130B can shade multiple valid pixels based on the texture coordinates and LOD of the multiple valid pixels in the basic unit information.

[0076] In some examples, multiple valid pixels in a basic unit include a first valid pixel and a second valid pixel, which are located in different primitives in the image.

[0077] For example, such as Figure 10 As shown, a basic unit comprises 16 screen pixels in a 4x4 (4 rows and 4 columns) grid. Five of these constitute the triangular primitive: screen pixel B3 (2nd row, 2nd column), screen pixel B6 (2nd row, 3rd column), screen pixel B9 (3rd row, 2nd column), screen pixel B12 (3rd row, 3rd column), and screen pixel B11 (4th row, 2nd column). The remaining screen pixels B0, B1, B2, B4, B5, B7, B8, B10, B13, B14, and B15 are auxiliary pixels. The LOD calculation circuit 180 calculates the LOD of effective pixel B3 based on B0–B3, the LOD of effective pixel B6 based on B4–B7, the LODs of effective pixels B9 and B11 based on B8–B11, and the LOD of effective pixel B12 based on B12–B15. The LOD calculation circuit 180 outputs the LODs of effective pixels B3, B6, B9, B11, and B12 to the packing circuit. The packing circuit divides these five effective pixels into a basic unit, which may also include effective pixels from other primitives. The packing circuit outputs the screen coordinates, texture coordinates, and LODs of multiple effective pixels in this basic unit to the second pixel shader 130B.

[0078] In this embodiment, the second pixel shader 130B shades all screen pixels in a basic unit. Since the basic unit input to the second pixel shader 130B only includes valid pixels, it only shades the valid pixels that need shading (e.g., five pixels: B3, B6, B9, B11, and B12). The second pixel shader 130B does not shade auxiliary pixels that do not need shading (e.g., eleven auxiliary pixels: B0, B1, B2, B4, B5, B7, B8, B10, B13, B14, and B15). Therefore, the number of threads required for the second pixel shader 130B to run is reduced, minimizing wasted computational resources and improving the processing efficiency of the second processor 100B. Furthermore, multiple valid pixels in a basic unit are not limited to valid pixels in the same primitive; valid pixels from multiple primitives can be merged and divided into the same basic unit. Thus, the number of pixels in a basic unit does not need to be changed, and this scheme is compatible with the original packing circuit without requiring modifications to the packing process. The number of pixels input to the shader in the same process does not need to be changed, and this scheme is compatible with the original shader input procedure.

[0079] based on Figure 9 The second processor 100B shown in this application embodiment also provides an image processing method. This image processing method can be applied to the second processor 100B. For example... Figure 11 As shown, the image processing method may include at least one of the following steps:

[0080] S100: The LOD of multiple valid pixels in the image frame in texture space is obtained through the LOD calculation circuit 180. For example, valid pixels are used to constitute primitives in the image.

[0081] S200: Using a shader, multiple effective pixels are shaded according to their LOD.

[0082] In one possible implementation, S100 may specifically include: obtaining the LOD of multiple effective pixels based on the texture coordinates of multiple effective pixels through the LOD calculation circuit 180.

[0083] In another possible implementation, the image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels. S100 may specifically include: obtaining the LOD of multiple valid pixels based on the texture coordinates of multiple valid pixels and the texture coordinates of the auxiliary pixels corresponding to the multiple valid pixels through the LOD calculation circuit 180.

[0084] In one possible implementation, the multiple valid pixels colored by the shader include a first valid pixel and a second valid pixel, the first valid pixel and the second valid pixel being located in different primitives in the image.

[0085] In one possible implementation, such as Figure 12 As shown, the image processing method may further include S300: obtaining basic unit information through a packing circuit, wherein the basic unit consists of multiple valid pixels. Exemplarily, the basic unit information includes the texture coordinates of the multiple valid pixels in the texture space. S200 may specifically include S210: coloring the multiple valid pixels using a shader based on the texture coordinates of the multiple valid pixels in the basic unit information and the LOD of the multiple valid pixels.

[0086] It is understood that the above image processing method is applied to the processor in the aforementioned device embodiments. Since the effects and functions of the processor have been described in detail in the aforementioned device embodiments, they will not be repeated here.

[0087] This application also provides a computer-readable storage medium storing program code. When the medium is run on a device (e.g., a microcontroller, chip, computer, or processor), the program code can be invoked by the processor to execute one or more steps in the above method embodiments.

[0088] This application also provides a computer program product containing instructions. The technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or its processor to execute all or part of the steps of the methods described in the various embodiments of this application.

[0089] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A graphics processor, characterized in that, The graphics processor includes a gradient LOD calculation circuit and a shader; The LOD calculation circuit is used to obtain the gradient LOD of multiple effective pixels in the texture space in the image frame, and the effective pixels are used to constitute primitives in the image. The shader is used to color the plurality of valid pixels according to the LOD of the plurality of valid pixels.

2. The graphics processor according to claim 1, characterized in that, The LOD calculation circuit is specifically used to obtain the LOD of the plurality of effective pixels based on the texture coordinates of the plurality of effective pixels.

3. The graphics processor according to claim 1, characterized in that, The image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels; The LOD calculation circuit is specifically used to obtain the LOD of the plurality of effective pixels based on the texture coordinates of the plurality of effective pixels and the texture coordinates of the auxiliary pixels corresponding to the plurality of effective pixels.

4. The graphics processor according to any one of claims 1-3, characterized in that, The plurality of valid pixels includes a first valid pixel and a second valid pixel, wherein the first valid pixel and the second valid pixel are located in different primitives in the image.

5. The graphics processor according to any one of claims 1-4, characterized in that, The graphics processor also includes a packaging circuit; The packing circuit is used to obtain basic unit information, wherein the basic unit is composed of the plurality of valid pixels, and the basic unit information includes the texture coordinates of the plurality of valid pixels in the texture space. The shader is specifically used to shade the plurality of valid pixels according to the texture coordinates of the plurality of valid pixels in the basic unit information and the LOD of the plurality of valid pixels.

6. An image processing method, characterized in that, The image processing method is applied to a graphics processor, which includes a gradient LOD calculation circuit and a shader; the image processing method includes: The LOD calculation circuit obtains the gradient LOD of multiple effective pixels in the texture space of the image frame, and the effective pixels are used to form primitives in the image. The shader colors the plurality of valid pixels according to their LOD.

7. The method according to claim 6, characterized in that, The step of obtaining the gradient LOD of multiple valid pixels in the image frame in texture space includes: The LOD calculation circuit obtains the LOD of the multiple effective pixels based on their texture coordinates.

8. The method according to claim 6, characterized in that, The image frame also includes auxiliary pixels, which share vertices with the corresponding valid pixels; obtaining the gradient LOD of multiple valid pixels in the image frame in texture space includes: The LOD calculation circuit obtains the LOD of the multiple effective pixels based on the texture coordinates of the multiple effective pixels and the texture coordinates of the auxiliary pixels corresponding to the multiple effective pixels.

9. The method according to any one of claims 6-8, characterized in that, The plurality of valid pixels includes a first valid pixel and a second valid pixel, wherein the first valid pixel and the second valid pixel are located in different primitives in the image.

10. The method according to any one of claims 6-9, characterized in that, The graphics processor further includes a packaging circuit; the image processing method further includes: The basic unit information is obtained through the packaging circuit. The basic unit is composed of the plurality of effective pixels. The basic unit information includes the texture coordinates of the plurality of effective pixels in the texture space. The step of coloring the plurality of valid pixels according to the LOD of the plurality of valid pixels through the shader includes: The shader colors the plurality of valid pixels according to the texture coordinates of the plurality of valid pixels in the basic unit information and the LOD of the plurality of valid pixels.

11. An electronic device, characterized in that, The electronic device includes a circuit board and a graphics processor as described in any one of claims 1-5.

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