Configurable parallel coding and decoding circuit and method suitable for post quantum cryptography algorithm
Through the collaborative design of register groups, barrel shifters, and buffer control modules, the requirements of multi-bit width and parallelism in the post-quantum cryptography algorithm encoding and decoding circuit were solved, achieving efficient and flexible encoding and decoding operations, and improving hardware resource utilization and system applicability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-10
AI Technical Summary
Existing encoding and decoding circuits suffer from problems such as increased processing latency, limited throughput, low hardware resource utilization, and insufficient configurability when processing multi-bit-width and multi-configuration post-quantum cryptography algorithms.
By employing a collaborative design of register banks, barrel shifters, and buffer control modules, and through dynamic configuration of parallel processing paths, the shift amount is automatically calculated and data timing is controlled, achieving efficient encoding and decoding operations.
It improves data processing efficiency, enhances the reuse rate of hardware resources and system flexibility, adapts to different bit width and parallelism requirements, and supports multi-algorithm compatibility.
Smart Images
Figure CN121841618A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of encoding and decoding circuit technology, and in particular to a configurable parallel encoding and decoding circuit and method suitable for post-quantum cryptography algorithms. Background Technology
[0002] In the hardware implementation of cryptographic algorithms, the coefficient sets processed internally often have varying bit widths, while communication interfaces and storage units typically use fixed byte lengths (e.g., 64 bits) for data exchange. Therefore, encoding / decoding modules are needed to convert between different formats. This is especially true in post-quantum cryptographic algorithms such as ML-KEM and ML-DSA, which involve extensive modular arithmetic, vector and polynomial operations. Their data streams are complex and their bit widths change frequently, placing clear demands on the efficiency and flexibility of the encoding / decoding process.
[0003] Existing technologies typically employ a structure based on shift registers and serial control logic to perform data concatenation and shift operations. These schemes process data bits sequentially through a fixed hardware path, relying on state machines or counters to coordinate each step, making them logically intuitive.
[0004] However, the above implementation methods have significant limitations when dealing with multi-bit-width and multi-configuration post-quantum cryptography algorithms: First, due to the serial processing mechanism, multiple shifts and concatenations are required when dealing with multi-bit-width data, leading to increased processing latency and limited overall throughput. Second, the fixed hardware structure makes it difficult to flexibly adapt to the diverse bit-width and parallelism requirements of different algorithms such as ML-KEM and ML-DSA, resulting in insufficient configurability. Third, the data shifting and concatenation processes are executed in stages, leaving hardware resources idle for part of the clock cycle, resulting in low resource utilization. Furthermore, improving performance by increasing register depth or control state machines leads to increased area, control complexity, and power consumption. Therefore, how to implement a configurable, highly parallel, and low-latency encoding and decoding circuit while ensuring effective utilization of hardware resources has become an urgent technical problem to be solved in the hardware implementation of post-quantum cryptography algorithms. Summary of the Invention
[0005] This application provides a configurable parallel encoding and decoding circuit and method suitable for post-quantum cryptography algorithms, in order to solve the problem that encoding and decoding circuits cannot meet diverse bit width and parallelism requirements.
[0006] The first aspect of this application provides a configurable parallel encoding and decoding circuit suitable for post-quantum cryptography algorithms, including: a register group, a barrel shifter, and a buffer control module; The register group is used to cache multiple sets of input data with unequal bit widths and record the number of valid data bits currently cached. The barrel shifter is connected to the register group and is used to perform shift and alignment operations on the data cached in the register group to generate standard bit-width output data. The buffer control module is connected to the register group and the barrel shifter. The buffer control module is configured to: dynamically configure the parallel processing path according to the algorithm mode selection signal and the encoding mode signal, and automatically calculate the shift amount required by the barrel shifter and control the timing of data input and output based on the effective data bits recorded in the register group.
[0007] Through the coordinated operation of register groups, barrel shifters, and buffer control modules, parallel processing paths can be dynamically configured according to the algorithm mode, supporting different bit widths and parallelism requirements. By automatically calculating shift amounts and controlling data timing, data processing efficiency is improved, while hardware resource reuse and system flexibility are enhanced. This provides an efficient and scalable encoding and decoding solution for the hardware implementation of post-quantum cryptography algorithms, addressing the problem that encoding and decoding circuits cannot meet diverse bit width and parallelism requirements.
[0008] Optionally, the buffer control module is configured to support at least two parallel modes, including a first parallel mode and a second parallel mode; in the first parallel mode, the buffer control module is configured to process four sets of input data with unequal bit widths simultaneously; in the second parallel mode, the buffer control module is configured to process two sets of input data with unequal bit widths simultaneously.
[0009] The buffer control module supports at least two parallel modes, including the first and second parallel modes that simultaneously process four or two sets of input data with unequal bit widths. This enables the circuit to adapt to the data processing requirements of different post-quantum cryptography algorithms, thereby achieving multi-algorithm compatibility in a single hardware structure and helping to improve the utilization of hardware resources and the applicability of the system.
[0010] Optionally, the first parallel mode corresponds to the ML-KEM algorithm, and the bit width of the four sets of input data with unequal bit widths is independently selected from groups consisting of 4 bits, 5 bits, 10 bits, 11 bits, or 12 bits; the second parallel mode corresponds to the ML-DSA algorithm, and the bit width of the two sets of input data with unequal bit widths is independently selected from groups consisting of 3 bits, 4 bits, 10 bits, 13 bits, 18 bits, or 20 bits.
[0011] The first parallel mode is adapted to the ML-KEM algorithm, supporting independent configuration of four data sets with bit widths ranging from 4, 5, 10, 11, or 12 bits. The second parallel mode is adapted to the ML-DSA algorithm, supporting independent configuration of two data sets with bit widths ranging from 3, 4, 10, 13, 18, or 20 bits. This specific bit width adaptation design allows the circuit to accurately match the standard data structures of different post-quantum cryptography algorithms, thereby improving the accuracy of data processing and algorithm compatibility.
[0012] Optionally, the buffer control module is configured to perform an encoding operation, the encoding operation including: Monitor the current number of valid data bits in the register set; When the remaining space in the register group is not less than the bit width of the data to be input, new data is allowed to be input to the high bit of the register group and the number of valid data bits is updated; When the number of valid data bits reaches or exceeds the standard bit width, the barrel shifter is triggered to perform a shift operation, output the standard bit width data, and update the number of valid data bits in the register group.
[0013] The buffer control module monitors the number of valid data bits in the register bank and allows new data input when the remaining space meets the requirements. It triggers a barrel shifter to shift the output when the data volume reaches or exceeds the standard bit width. This automated control process facilitates continuous data processing, thereby optimizing data throughput efficiency and reducing the complexity of external control.
[0014] Optionally, in the execution of the encoding operation, the buffer control module calculates the shift amount by using the difference between the effective data bits and the standard bit width as the shift number of the barrel shifter.
[0015] The buffer control module uses the difference between the effective number of data bits and the standard bit width as the shift number of the barrel shifter. This calculation method is directly based on the data buffer state, which simplifies the logic of shift amount generation, helps to reduce calculation latency and improve the efficiency of alignment operations.
[0016] Optionally, the buffer control module is configured to perform a decoding operation, which includes: Multiple sets of preset bit-width data segments are parsed from the input data stream of the standard bit width; The effective number of bits in the register group is dynamically adjusted according to the algorithm mode selection signal and the bit width of the data segment to be parsed.
[0017] During decoding, the buffer control module can parse multiple sets of preset-width data segments from the standard-width input stream and dynamically adjust the effective bit width of the register group according to the algorithm mode and the data segment width. This dynamic adjustment capability can adapt to the different requirements of buffer capacity under different algorithm modes, thereby improving the utilization of hardware resources and the stability of the decoding process.
[0018] Optionally, when the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is 11 bits, all storage units of the register group are enabled; In other cases, the lower-order storage units of the register group are enabled, and the higher-order storage units are disabled.
[0019] When the algorithm mode is ML-KEM and the width of the data segment to be parsed is 11 bits, all storage units of the register bank are enabled; otherwise, only the lower-order storage units are enabled. This mechanism dynamically allocates register resources according to different working scenarios, which helps to reduce hardware resource overhead in unnecessary situations while meeting the data capacity requirements of specific algorithms, thereby optimizing the area efficiency of the overall circuit.
[0020] Optionally, the standard bit width is 64 bits, and the total bit width of the register group is 104 bits.
[0021] Setting the standard output bit width to 64 bits and configuring the total bit width of the register group to 104 bits provides ample buffer space for the temporary storage and splicing of multiple sets of data with unequal bit widths, which helps to ensure the integrity of the output data. At the same time, it supports pipelined continuous data processing, thereby maintaining a high data throughput.
[0022] A second aspect of this application provides a configurable parallel encoding / decoding method suitable for post-quantum cryptography algorithms, applied to the configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms described in the first aspect, the method comprising: The buffer control module receives algorithm mode selection signals and encoding mode signals to dynamically configure parallel processing paths. The register bank buffers multiple sets of input data with unequal bit widths and records the number of valid data bits currently buffered. The buffer control module automatically calculates the required shift amount for the barrel shifter based on the number of valid data bits. Based on the shift amount, control the barrel shifter to perform shift and alignment operations on the data cached in the register group; The buffer control module controls the generation of standard bit-width output data from the shifted and aligned data and outputs it, while also controlling the timing of data input and output.
[0023] By dynamically configuring parallel processing paths, caching data with unequal bit widths, and automatically calculating shift amounts, a barrel shifter is then controlled to perform shift alignment and generate a standard bit width output. This method automates and streams the encoding and decoding process, helping to reduce dependence on external control logic and improve data processing efficiency and overall system response performance.
[0024] Optionally, the method further includes: performing encoding and decoding operations; The steps for performing the encoding operation include: Monitor the current number of valid data bits in the register set; Determine whether the remaining space in the register group is not less than the bit width of the data to be input; If so, new data is allowed to be input to the high-order bits of the register group and the number of valid data bits is updated; Determine whether the number of valid data bits reaches or exceeds the preset standard bit width; If so, the barrel shifter is triggered to perform a shift alignment operation based on the shift amount automatically calculated by the buffer control module, output standard bit width data, and update the number of valid data bits in the register group; The steps for performing the decoding operation include: Parse multiple sets of preset bit-width data segments from a standard bit-width input data stream; The effective number of bits in the register group is dynamically adjusted based on the selection of signals and the bit width of the data segment to be parsed according to the algorithm mode.
[0025] By performing encoding and decoding operations, automatic data input and triggered output are achieved during encoding based on dynamic judgment of register space and data volume. During decoding, the number of bits enabled in the registers is dynamically adjusted according to the algorithm and data bit width. This process integrates encoding and decoding functions under a unified control logic, which helps reduce the control switching overhead between different processing modes and improves the overall execution efficiency and hardware synergy of encoding and decoding tasks.
[0026] As can be seen from the above technical solutions, this application provides a configurable parallel encoding and decoding circuit and method suitable for post-quantum cryptography algorithms. The configurable parallel encoding and decoding circuit includes: a register group, a barrel shifter, and a buffer control module. The register group is used to buffer multiple sets of input data with unequal bit widths and record the number of currently buffered valid data bits. The barrel shifter is connected to the register group and is used to perform shift and alignment operations on the data buffered in the register group to generate standard bit width output data. The buffer control module is connected to the register group and the barrel shifter. The buffer control module dynamically configures the parallel processing path according to the algorithm mode selection signal and the encoding mode signal, and automatically calculates the shift amount required by the barrel shifter and controls the timing of data input and output based on the number of valid data bits recorded in the register group, so as to solve the problem that the encoding and decoding circuit cannot meet the diverse bit width and parallelism requirements. Attached Figure Description
[0027] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 An architecture diagram of a configurable parallel encoder-decoder circuit suitable for post-quantum cryptography algorithms provided for embodiments of this application; Figure 2 A flowchart illustrating the execution of encoding operations in a configurable parallel encoding / decoding method suitable for post-quantum cryptography algorithms provided in this application embodiment; Figure 3 The flowchart illustrates the process of performing decoding operations in a configurable parallel encoding and decoding method for post-quantum cryptography algorithms provided in this application embodiment when the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is 11 bits. Figure 4 This is a flowchart illustrating the process of performing decoding operations in other cases within a configurable parallel encoding / decoding method for post-quantum cryptography algorithms provided in an embodiment of this application. Detailed Implementation
[0029] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application.
[0030] In the hardware implementation of post-quantum cryptography algorithms, since the data processed internally by the algorithm consists of coefficient sets with varying bit widths, while the communication interface and storage unit are usually in fixed-length bytes (such as 64 bits), format conversion needs to be completed through an encoding and decoding module.
[0031] This invention addresses the problem that the encoding and decoding circuits in the hardware implementation of post-quantum cryptography algorithms cannot meet diverse bit width and parallelism requirements. (See [link to relevant documentation]). Figure 1 This application provides a configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms, including: a register group, a barrel shifter, and a buffer control module.
[0032] The register bank is used to buffer multiple sets of input data with unequal bit widths and record the number of valid data bits currently buffered. The barrel shifter is connected to the register bank and is used to perform shift and alignment operations on the data buffered in the register bank to generate standard bit width output data. The buffer control module is connected to the register bank and the barrel shifter. The buffer control module is configured to: dynamically configure the parallel processing path according to the algorithm mode selection signal and the encoding mode signal, and automatically calculate the shift amount required by the barrel shifter and control the timing of data input and output based on the number of valid data bits recorded in the register bank.
[0033] It should be understood that the various modules of the configurable parallel encoding / decoding circuit cooperate with each other to complete the task in actual operation. The register bank can be selected as a 104-bit register bank. As the initial storage unit for data, the register bank can flexibly buffer multiple sets of input data with unequal bit widths. This feature allows the circuit to adapt to data input from different sources and in different formats. Simultaneously, its function of recording the currently buffered effective data bits (cnt) provides a crucial information foundation for subsequent data processing, allowing subsequent modules to accurately understand the actual data situation.
[0034] A barrel shifter is closely connected to a register bank. Based on the number of valid data bits recorded in the register bank, it performs precise shift and alignment operations on the buffered data (date) in the register bank. This operation allows data of different bit widths to be converted into standard bit width output data (date_out), achieving fast alignment and output.
[0035] The buffer control module plays a crucial regulatory role in the entire circuit. It connects to both the register bank and the barrel shifter, receiving information from both modules. Based on the algorithm mode selection signal (sel) and the encoding mode signal (code_mode), it can dynamically configure the parallel processing path. This means that under different algorithm requirements and encoding demands, the circuit can flexibly adjust its processing method to complete the task with optimal parallelism. Simultaneously, it automatically calculates the shift amount required by the barrel shifter based on the number of valid data bits (cnt) recorded in the register bank, generating a write enable signal (push) that controls the register bank to write data. The register bank outputs data under the control of the read enable signal (pop) and generates a count of the currently stored data (cnt). The shifter performs shift processing on the data output from the register bank based on the count information (cnt), finally outputting aligned data (data_out), ensuring the accuracy of the shift operation. Furthermore, it can precisely control the timing of data input and output, making the entire circuit operate more orderly and efficiently, avoiding data conflicts and chaos.
[0036] Through the coordinated operation of register groups, barrel shifters, and buffer control modules, parallel processing paths can be dynamically configured according to the algorithm mode, supporting different bit widths and parallelism requirements. By automatically calculating shift amounts and controlling data timing, data processing efficiency is improved, while hardware resource reuse and system flexibility are enhanced. This provides an efficient and scalable encoding and decoding solution for the hardware implementation of post-quantum cryptography algorithms, addressing the problem that encoding and decoding circuits cannot meet diverse bit width and parallelism requirements.
[0037] In some embodiments, the buffer control module is configured to support at least two parallel modes, including a first parallel mode and a second parallel mode; in the first parallel mode, the buffer control module is configured to process four sets of input data with unequal bit widths simultaneously; in the second parallel mode, the buffer control module is configured to process two sets of input data with unequal bit widths simultaneously.
[0038] The buffer control module supports at least two parallel modes, including the first and second parallel modes that simultaneously process four or two sets of input data with unequal bit widths. This enables the circuit to adapt to the data processing requirements of different post-quantum cryptography algorithms, thereby achieving multi-algorithm compatibility in a single hardware structure and helping to improve the utilization of hardware resources and the applicability of the system.
[0039] In some embodiments, the first parallel mode corresponds to the ML-KEM algorithm, where the bit widths of the four sets of input data with unequal bit widths are independently selected from groups consisting of 4 bits, 5 bits, 10 bits, 11 bits, or 12 bits; the second parallel mode corresponds to the ML-DSA algorithm, where the bit widths of the two sets of input data with unequal bit widths are independently selected from groups consisting of 3 bits, 4 bits, 10 bits, 13 bits, 18 bits, or 20 bits.
[0040] It should be understood that the ML-KEM algorithm refers to a key encapsulation mechanism algorithm based on modular lattices. This algorithm holds an important position in the field of post-quantum cryptography. It utilizes difficult problems in lattice theory to build a security foundation. Through specific mathematical operations and structural design, it achieves secure encapsulation and decapsulation operations of keys, providing reliable confidentiality guarantees for data transmission. The ML-DSA algorithm refers to a digital signature algorithm based on modular lattices. This algorithm also relies on mathematical problems in lattice theory. Through a unique algorithmic process and parameter settings, it generates digital signatures with unforgeable properties, ensuring the integrity of data and the authenticity of its source. It plays a crucial role in scenarios such as identity authentication and data integrity verification.
[0041] In the first parallel mode, corresponding to the ML-KEM algorithm, the buffer control module simultaneously processes four sets of input data with unequal bit widths. These four sets of data have independent bit width selection rights, allowing selection from a specific group of 4, 5, 10, 11, or 12 bits. This design enables the mode to precisely adapt to the different bit width requirements of the ML-KEM algorithm during data processing, ensuring efficient operation of the algorithm at the hardware level. In the second parallel mode, corresponding to the ML-DSA algorithm, the buffer control module simultaneously processes two sets of input data with unequal bit widths. These two sets of data also have independent bit width selection characteristics, allowing selection from groups consisting of 3, 4, 10, 13, 18, or 20 bits. This arrangement satisfies the specific requirements of the ML-DSA algorithm for different bit widths during data processing, ensuring the stability and accuracy of the algorithm in hardware implementation. Through flexible parallelism configuration, it can efficiently support multi-bit width data structures under different algorithm standards, balancing speed and area efficiency.
[0042] In some embodiments, see Figure 2 The buffer control module is configured to perform encoding operations, which include: Monitor the current number of valid data bits in the register set; When the remaining space in the register bank is not less than the bit width of the data to be input, new data is allowed to be input to the high bit of the register bank and the number of valid data bits is updated. When the number of valid data bits reaches or exceeds the standard bit width, the barrel shifter is triggered to perform a shift operation, outputting data of the standard bit width and updating the number of valid data bits in the register group.
[0043] It should be understood that the buffer control module plays a crucial scheduling role in the encoding process. First, the buffer control module continuously and in real-time monitors the current number of valid data bits (cnt) in the register bank, down to each bit, to ensure accurate data storage status. When the remaining space in the register bank (104-cnt) is not less than the bit width of the input data, it's like opening a door for new data; the buffer control module then allows new data input (date_in) to the higher bits of the register bank. After successful data input, the number of valid data bits is updated promptly to ensure the recorded data matches the actual situation. When the number of valid data bits reaches or exceeds the standard bit width (set to 64 bits), it's like reaching a critical threshold. At this point, the buffer control module triggers a barrel shifter to perform a shift operation. The barrel shifter precisely shifts the data according to the calculated shift number and then outputs data of the standard bit width. After the data is output, the number of valid data bits in the register group will also be updated, so that the entire encoding operation forms a complete and orderly loop, ensuring that the encoding module can run stably and efficiently.
[0044] The buffer control module monitors the number of valid data bits in the register bank and allows new data input when the remaining space meets the requirements. It triggers a barrel shifter to shift the output when the data volume reaches or exceeds the standard bit width. This automated control process facilitates continuous data processing, thereby optimizing data throughput efficiency and reducing the complexity of external control.
[0045] In some embodiments, during the encoding operation, the buffer control module calculates the shift amount by using the difference between the effective data bits and the standard bit width as the shift number of the barrel shifter.
[0046] The buffer control module uses the difference between the effective number of data bits and the standard bit width as the shift number of the barrel shifter. This calculation method is directly based on the data buffer state, which simplifies the logic of shift amount generation, helps to reduce calculation latency and improve the efficiency of alignment operations.
[0047] In some embodiments, see Figure 3 The buffer control module is configured to perform decoding operations, which include: Parse multiple sets of preset bit-width data segments from a standard bit-width input data stream; The effective number of bits in the register bank is dynamically adjusted based on the algorithm mode selection signal and the bit width of the data segment to be parsed.
[0048] During decoding, the buffer control module can parse multiple sets of preset-width data segments from the standard-width input stream and dynamically adjust the effective bit width of the register group according to the algorithm mode and the data segment width. This dynamic adjustment capability can adapt to the different requirements of buffer capacity under different algorithm modes, thereby improving the utilization of hardware resources and the stability of the decoding process.
[0049] In some embodiments, when the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is 11 bits, all memory units of the register group are enabled.
[0050] It should be understood that when the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is precisely set to 11 bits, all storage units of the register bank are enabled. This is because, when processing 11-bit wide data blocks in ML-KEM mode, the data volume is relatively large. If only the lower-order storage units of the register bank are enabled, the lower 96 bits of the register bank may not be able to hold more data, leading to data not being able to continue input or output, affecting the smoothness and accuracy of the entire data processing flow. Therefore, to ensure that a larger amount of data can be accommodated and to guarantee the correct input and output of data, the entire 104-bit register bank is enabled at this time.
[0051] Specifically, when the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is precisely set to 11 bits, the entire 104-bit register set will be enabled, such as... Figure 3 As shown, the data width is 64 bits, and the total number of bits of data received and temporarily stored is 103 bits, which are stored in the data buffer (decode_fifo_aligned[103:0]). The high-order part of the buffer ([103:40]) is the valid data that has not yet been output, while the low-order part ([39:0]) is the valid data that will be output soon. Based on the number of bits stored (cnt) and the number of bits shifted (sft), the buffer is shifted to the right to align the original high-order data to the low-order data, so that the valid data is output from the low-order part of the aligned buffer (decode_fifo_aligned[47:0]), thus realizing the continuous aligned output of the data stream.
[0052] In other cases, the lower-order memory of the register set is enabled, while the higher-order memory is disabled.
[0053] Specifically, in other cases, only the lower 96 bits of the registers are enabled, such as... Figure 4As shown. The input data is 64 bits (data_in[63:0]), and the received data totals 96 bits, which are temporarily stored in the data buffer (decode_fifo_aligned[103:0]). In this buffer, the high-order part ([95:32]) is the valid data that has not yet been output, while the adjacent 32 bits ([95:64]) is a specific intermediate data segment, and the low-order part ([31:0]) is the valid data that will be output soon. Based on the number of bits already stored (cnt) and the number of bits shifted (sft), the contents of the buffer are shifted and aligned by a right shift operation, so that the valid data moves to the low-order part, thereby outputting the valid data from the low-order part of the aligned buffer (decode_fifo_aligned[47:0]), realizing the continuous aligned output of the data stream.
[0054] When the algorithm mode is ML-KEM and the width of the data segment to be parsed is 11 bits, all storage units of the register bank are enabled; otherwise, only the lower-order storage units are enabled. This mechanism dynamically allocates register resources according to different working scenarios, which helps to reduce hardware resource overhead in unnecessary situations while meeting the data capacity requirements of specific algorithms, thereby optimizing the area efficiency of the overall circuit.
[0055] In some embodiments, the standard bit width is 64 bits, and the total bit width of the register group is 104 bits.
[0056] Setting the standard output bit width to 64 bits and configuring the total bit width of the register group to 104 bits provides ample buffer space for the temporary storage and splicing of multiple sets of data with unequal bit widths, which helps to ensure the integrity of the output data. At the same time, it supports pipelined continuous data processing, thereby maintaining a high data throughput.
[0057] This application also provides a configurable parallel encoding / decoding method suitable for post-quantum cryptography algorithms in some embodiments, applied to the configurable parallel encoding / decoding circuit for post-quantum cryptography algorithms mentioned in the above embodiments, the method including: The buffer control module receives algorithm mode selection signals and encoding mode signals to dynamically configure parallel processing paths. The register bank buffers multiple sets of input data with unequal bit widths and records the number of valid data bits currently buffered. The buffer control module automatically calculates the required shift amount for the barrel shifter based on the number of valid data bits. Based on the shift amount, control the barrel shifter to perform shift and alignment operations on the data buffered in the register group; The buffer control module controls the generation of standard bit-width output data from the shifted and aligned data and outputs it, while also controlling the timing of data input and output.
[0058] By dynamically configuring parallel processing paths, caching data with unequal bit widths, and automatically calculating shift amounts, a barrel shifter is then controlled to perform shift alignment and generate a standard bit width output. This method automates and streams the encoding and decoding process, helping to reduce dependence on external control logic and improve data processing efficiency and overall system response performance.
[0059] In some embodiments, the method further includes performing encoding and decoding operations; The steps for performing the encoding operation include: Monitor the current number of valid data bits in the register set; Determine whether the remaining space in the register bank is not less than the bit width of the data to be input; If so, new data is allowed to be input to the high-order bits of the register bank and the number of valid data bits is updated; Determine whether the number of valid data bits reaches or exceeds the preset standard bit width; If so, the barrel shifter is triggered to perform a shift alignment operation based on the shift amount automatically calculated by the buffer control module, output standard bit-width data, and update the number of valid data bits in the register group.
[0060] Specifically, see Figure 2 First, continuously monitor the number of valid data bits currently stored in the register set. This value is reflected in real time by a counter (cnt), which represents the actual length of data stored in the register.
[0061] Next, it is determined whether the remaining space in the register bank is sufficient to accommodate the new data to be input. This involves checking whether the remaining empty space in the register (104 minus the number of bits of data currently stored, cnt) is not less than the bit width of the data to be input. If the remaining space is sufficient, i.e. not less than the bit width of the data to be input, the system allows the new data to enter from the input terminal (such as the 48-bit data input terminal data_in[47:0]), and arranges this data in the high-order part of the register bank. At the same time, the value of the counter cnt will increase accordingly to reflect the number of bits of the newly stored data.
[0062] Next, it is determined whether the number of valid data bits in the current register bank has reached or exceeded the preset standard bit width, which is 64 bits. If the number of valid data bits has reached or exceeded 64 bits, it means that enough data has accumulated in the register bank and output operations can be performed.
[0063] In this situation, the barrel shifter is triggered to start working. The barrel shifter performs a shift alignment operation based on the shift amount (sft, i.e., the number of currently stored data bits cnt minus 64) automatically calculated by the buffer control module. The purpose of this shift operation is to shift the data in the register group to the left, so that the data output from the output end (such as the 64-bit aligned output end decode_fifo_aligned[63:0]) is continuous and aligned 64 bits. After the shift operation is completed, the system outputs this 64-bit standard width data and simultaneously updates the number of valid data bits in the register group, i.e., subtracts the 64 bits of data already output, in order to continue receiving and processing subsequent data inputs. Throughout the process, the status control signal (stt) coordinates the data shift, buffering, and output to ensure the smooth progress of the encoding operation.
[0064] The steps for performing a decoding operation include: Parse multiple sets of preset bit-width data segments from a standard bit-width input data stream; The effective number of bits in the register group is dynamically adjusted based on the selection of signals and the bit width of the data segment to be parsed according to the algorithm mode.
[0065] By performing encoding and decoding operations, automatic data input and triggered output are achieved during encoding based on dynamic judgment of register space and data volume. During decoding, the number of bits enabled in the registers is dynamically adjusted according to the algorithm and data bit width. This process integrates encoding and decoding functions under a unified control logic, which helps reduce the control switching overhead between different processing modes and improves the overall execution efficiency and hardware synergy of encoding and decoding tasks.
[0066] As can be seen from the above technical solutions, the embodiments of this application provide a configurable parallel encoding and decoding circuit and method suitable for post-quantum cryptography algorithms. The configurable parallel encoding and decoding circuit includes: a register group, a barrel shifter, and a buffer control module; the register group is used to buffer multiple sets of input data with unequal bit widths and record the number of currently buffered valid data bits; the barrel shifter is connected to the register group and is used to perform shift and alignment operations on the data buffered in the register group to generate standard bit width output data; the buffer control module is connected to the register group and the barrel shifter. The buffer control module dynamically configures the parallel processing path according to the algorithm mode selection signal and the encoding mode signal, and automatically calculates the shift amount required by the barrel shifter and controls the timing of data input and output based on the number of valid data bits recorded in the register group, so as to solve the problem that the encoding and decoding circuit cannot meet the diverse bit width and parallelism requirements.
[0067] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.
Claims
1. A configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms, characterized in that, include: Register set, barrel shifter, and buffer control module; The register group is used to cache multiple sets of input data with unequal bit widths and record the number of valid data bits currently cached. The barrel shifter is connected to the register group and is used to perform shift and alignment operations on the data cached in the register group to generate standard bit-width output data. The buffer control module is connected to the register group and the barrel shifter. The buffer control module is configured to: dynamically configure the parallel processing path according to the algorithm mode selection signal and the encoding mode signal, and automatically calculate the shift amount required by the barrel shifter and control the timing of data input and output based on the effective data bits recorded in the register group.
2. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 1, characterized in that, The buffer control module is configured to support at least two parallel modes, including a first parallel mode and a second parallel mode. In the first parallel mode, the buffer control module is configured to process four sets of input data with unequal bit widths simultaneously; In the second parallel mode, the buffer control module is configured to process two sets of input data with unequal bit widths simultaneously.
3. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 2, characterized in that, The first parallel mode corresponds to the ML-KEM algorithm, and the bit width of the four sets of input data with unequal bit widths is independently selected from groups consisting of 4 bits, 5 bits, 10 bits, 11 bits, or 12 bits; The second parallel mode corresponds to the ML-DSA algorithm, where the bit widths of the two sets of unequal bit-width input data are independently selected from groups consisting of 3 bits, 4 bits, 10 bits, 13 bits, 18 bits, or 20 bits.
4. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 1, characterized in that, The buffer control module is configured to perform encoding operations, which include: Monitor the current number of valid data bits in the register set; When the remaining space in the register group is not less than the bit width of the data to be input, new data is allowed to be input to the high bit of the register group and the number of valid data bits is updated; When the number of valid data bits reaches or exceeds the standard bit width, the barrel shifter is triggered to perform a shift operation, output the standard bit width data, and update the number of valid data bits in the register group.
5. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 4, characterized in that, In the execution of the encoding operation, the buffer control module calculates the shift amount by taking the difference between the effective data bits and the standard bit width as the shift number of the barrel shifter.
6. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 1, characterized in that, The buffer control module is configured to perform a decoding operation, which includes: Multiple sets of preset bit-width data segments are parsed from the input data stream of the standard bit width; The effective number of bits in the register group is dynamically adjusted according to the algorithm mode selection signal and the bit width of the data segment to be parsed.
7. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 6, characterized in that, When the algorithm mode selection signal indicates the ML-KEM algorithm and the bit width of the data segment to be parsed is 11 bits, all storage units of the register group are enabled; In other cases, the lower-order storage units of the register group are enabled, and the higher-order storage units are disabled.
8. The configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to claim 1, characterized in that, The standard bit width is 64 bits, and the total bit width of the register group is 104 bits.
9. A configurable parallel encoding and decoding method suitable for post-quantum cryptography algorithms, characterized in that, The method, applied to a configurable parallel encoding / decoding circuit suitable for post-quantum cryptography algorithms according to any one of claims 1-8, comprises: The buffer control module receives algorithm mode selection signals and encoding mode signals to dynamically configure parallel processing paths. The register bank buffers multiple sets of input data with unequal bit widths and records the number of valid data bits currently buffered. The buffer control module automatically calculates the required shift amount for the barrel shifter based on the number of valid data bits. Based on the shift amount, control the barrel shifter to perform shift and alignment operations on the data cached in the register group; The buffer control module controls the generation of standard bit-width output data from the shifted and aligned data and outputs it, while also controlling the timing of data input and output.
10. The configurable parallel encoding / decoding method for post-quantum cryptography algorithms according to claim 9, characterized in that, The method further includes: performing encoding and decoding operations; The steps for performing the encoding operation include: Monitor the current number of valid data bits in the register set; Determine whether the remaining space in the register group is not less than the bit width of the data to be input; If so, new data is allowed to be input to the high-order bits of the register group and the number of valid data bits is updated; Determine whether the number of valid data bits reaches or exceeds the preset standard bit width; If so, the barrel shifter is triggered to perform a shift alignment operation based on the shift amount automatically calculated by the buffer control module, output standard bit width data, and update the number of valid data bits in the register group; The steps for performing the decoding operation include: Parse multiple sets of preset bit-width data segments from a standard bit-width input data stream; The effective number of bits in the register group is dynamically adjusted based on the selection of signals and the bit width of the data segment to be parsed according to the algorithm mode.