Link fault positioning circuit, method and device

Abstract

The invention discloses a link fault positioning circuit, method and device, relates to the technical field of electronic communication, comprises embedding a link fault positioning circuit with a dynamic connection state in an inter-device link, and solves the technical problems of insufficient localization of a link fault and incapability of accurately positioning a fault point in related technologies. The technical effect of real-time monitoring and positioning of faults is achieved.

Description

Technical Field

[0001] This application relates to the field of electronic communication technology, and in particular to a link fault location circuit, method and apparatus. Background Technology

[0002] In the design and operation of artificial intelligence servers, high-speed interconnect technology plays a core role in supporting their high-load computing demands. Common high-speed interconnect technologies include Peripheral Component Interconnect Express (PCIe), NVIDIA® Scalable Coherent Interface (NVLink), and InfiniBand Architecture (InfiniBand). These technologies exhibit unique advantages in communication between the Central Processing Unit (CPU) and the Graphics Processing Unit (GPU), direct GPU-to-GPU communication, and low-latency communication between large-scale clusters, respectively. However, the widespread application of these technologies also brings about the complexity of network architecture, especially when links encounter physical layer problems, such as connector malfunctions or signal integrity issues related to electrical characteristics, making fault location particularly challenging.

[0003] Currently, while most Artificial Intelligence (AI) servers are equipped with built-in diagnostic tools capable of initially detecting link status and determining the presence of faults, these tools have limited effectiveness in precise fault location, especially in automatically identifying and accurately locating fault points without human intervention. This not only increases the complexity of operation and maintenance work but also leads to unnecessary resource consumption and increased costs due to misjudgments, becoming one of the main constraints on the stability and reliability of AI computing power platforms.

[0004] Therefore, promoting collaborative innovation across all levels, from devices and boards to complete systems and applications, aims to achieve accurate and automatic identification of high-speed link faults, reduce reliance on manual labor, and avoid additional costs caused by misdiagnosis. This is a crucial direction for the evolution of AI server technology and a key to meeting the ever-increasing demand for AI computing. Intelligent fault location technology can ensure the healthy operation of AI infrastructure, providing robust hardware support for various AI applications. Summary of the Invention

[0005] This application provides a link fault location circuit, method, and apparatus to at least solve the technical problem in the related art of insufficient link fault location and inability to accurately locate the fault point.

[0006] This application provides a link fault location circuit, including at least one first connector and a second connector, wherein the first connector and the second connector are disposed on a printed circuit board, and the first connector and the second connector are connected by a first external cable and a second external cable. The first connector is connected to a first device through a trace in the first board, and the second connector is connected to a second device through a trace in the second board. A first switching unit of the first connector switches between a first connection unit and a second connection unit of the first connector, and a second switching unit of the first connector switches between the first connection unit and the second connection unit of the first connector, and a first switching unit of the second connector switches between the first connection unit and the second connection unit of the second connector, and a second switching unit of the second connector switches between the first connection unit and the second connection unit of the second connector.

[0007] This application provides a link fault location method, applied to the link fault location circuit described above. The method includes: in response to an abnormality in the link between the first device and the second device, switching the connection states of the first connector and the second connector to set a corresponding connection state; and locating the link fault based on the corresponding connection state.

[0008] This application also provides a link fault location device, including: a switching module, used to switch the first switching unit and the second switching unit of the first connector and the second connector in response to an abnormality in the link between the first device and the second device, so as to set the corresponding connection state; and a location module, used to locate the link fault based on the corresponding connection state.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described link fault location methods.

[0010] Through this application, since the first connector and the second connector switch the connection state through the switching unit, the signal flow direction can be changed without physical disassembly or reconnection. The first switching unit and the second switching unit can create an internal loopback detection environment by switching between the first connection unit and the second connection unit, which helps to locate the fault point. Therefore, it can solve the technical problem of insufficient link fault location in related technologies and the inability to accurately locate the fault point, thereby achieving the technical effect of improving the efficiency and accuracy of fault location. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a link fault location circuit provided in an embodiment of this application;

[0013] Figure 2 This is a schematic diagram of the connector structure provided in an embodiment of this application;

[0014] Figure 3 This is a schematic diagram of the connector in the first connection state provided in the embodiments of this application;

[0015] Figure 4 A schematic diagram (I) of the connector in the second connection state provided in the embodiment of this application;

[0016] Figure 5 A schematic diagram (II) of the connector in the second connection state provided in the embodiment of this application;

[0017] Figure 6 A flowchart illustrating the link fault location method provided in this application (I);

[0018] Figure 7 A schematic diagram illustrating the data transmission path under normal working conditions provided in the embodiments of this application;

[0019] Figure 8 A schematic diagram of a small loopback downlink data transmission path provided in an embodiment of this application;

[0020] Figure 9 A schematic diagram of a loopback data transmission path provided in an embodiment of this application;

[0021] Figure 10 A schematic diagram (I) of the large loopback downlink data transmission path provided in the embodiments of this application;

[0022] Figure 11 A schematic diagram (II) of the large loopback downlink data transmission path provided in the embodiments of this application;

[0023] Figure 12 This is a schematic diagram of the results of the link fault location device provided in the embodiments of this application;

[0024] Figure 13 A flowchart (II) illustrating the link fault location method provided in this application embodiment. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0026] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0027] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Current AI server link detection and fault identification processes primarily rely on two key stages: first, comprehensive pre-shipment testing of the entire machine, including functional verification and performance monitoring on the production line, with particular attention to link bandwidth, speed, and bit error rate; second, arrival testing after equipment deployment to the data center, where link performance is also rigorously monitored. If any anomalies are detected, a fault report is generated, and the repair process is initiated. This solution covers link health monitoring from production to deployment, aiming to prevent faulty equipment from entering the market or going into operation as soon as possible, ensuring the high performance and reliability of AI servers.

[0029] While the aforementioned monitoring and maintenance mechanisms ensure link stability to a certain extent, they have significant limitations in practice, specifically in the following aspects:

[0030] 1. Inaccurate fault location: During the production line inspection and the incoming inspection in the data center, the equipment can only generally identify abnormal link performance, but cannot clearly point out whether the fault is caused by the board, cable or connector. This makes the fault location process time-consuming and labor-intensive, and lacks specificity.

[0031] 2. Reliance on manual testing, resulting in low efficiency: Maintenance or operation personnel need to rely on the report content to troubleshoot the fault. This process often requires personnel to have high professional skills. Moreover, in complex multi-level connector interconnection scenarios, frequent equipment disassembly and cross-verification are not only inefficient, but may also introduce new faults and increase maintenance costs.

[0032] 3. Misjudgment in scenarios that are difficult to reproduce: For some sporadic or short-term link problems, existing technologies cannot accurately distinguish the nature of the fault, which often leads to unnecessary component replacement. This not only interferes with the review and in-depth analysis of typical faults, but also affects the efficiency of system optimization and long-term improvement.

[0033] To address the technical problems existing in the aforementioned related technologies, embodiments of this application provide a link fault location circuit. Figure 1 This is a schematic diagram of a link fault location circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, the device includes at least one first connector and a second connector, wherein the first connector and the second connector are disposed on a printed circuit board, and the first connector and the second connector are connected via a first external cable and a second external cable. The first connector is connected to a first device via a trace on a first board, and the second connector is connected to a second device via a trace on a second board.

[0034] The first switching unit of the first connector switches between the first connecting unit and the second connecting unit of the first connector, and the second switching unit of the first connector switches between the first connecting unit and the second connecting unit of the first connector.

[0035] The first switching unit of the second connector switches between the first connecting unit and the second connecting unit of the second connector, and the second switching unit of the second connector switches between the first connecting unit and the second connecting unit of the second connector.

[0036] For example, because the first connector and the second connector in this embodiment of the invention can dynamically adjust their connection state, the circuit can distinguish whether the fault originates from internal equipment, wiring connections, cable quality, or physical problems with the connectors. This function significantly improves the accuracy and efficiency of fault location without requiring physical disassembly of the equipment or cables.

[0037] In one exemplary embodiment, the first connector includes a first internal board pin, a second internal board pin, a first switching unit, a first connection unit, a second switching unit, a first external board pin, a second external board pin, a first external cable pin, a second external cable pin, and a second connection unit.

[0038] The first switching unit includes a first sub-switching unit and a second sub-switching unit; the first connection unit includes a first sub-connection unit and a second connection unit; and the second switching unit includes a third sub-switching unit and a fourth sub-switching unit.

[0039] The first sub-connecting unit includes a first connecting end and a second connecting end; the second sub-connecting unit includes a third connecting end and a fourth connecting end; and the third sub-connecting unit includes a fifth connecting end and a sixth connecting end.

[0040] The first board's internal pins and the second board's internal pins are disposed on a printed circuit board. The first board's internal pins are connected to the transmitting end of the first device via internal traces, and the second board's internal pins are connected to the receiving end of the first device via internal traces.

[0041] The first sub-switching unit switches between the first and fifth connection terminals; the second sub-switching unit switches between the third and sixth connection terminals; the third sub-switching unit switches between the second and fifth connection terminals; and the fourth sub-switching unit switches between the fourth and sixth connection terminals.

[0042] The first board external pin is connected to the first external cable pin, the second board external pin is connected to the second external cable pin, the first external cable pin is connected to the first external cable, and the second external cable pin is connected to the second external cable.

[0043] In one exemplary embodiment, the second connector includes a first board inner pin, a second board inner pin, a first switching unit, a first connection unit, a second switching unit, a first board outer pin, a second board outer pin, a first external cable pin, a second external cable pin, and a second connection unit.

[0044] The first switching unit includes a first sub-switching unit and a second sub-switching unit; the first connection unit includes a first sub-connection unit and a second connection unit; and the second switching unit includes a third sub-switching unit and a fourth sub-switching unit.

[0045] The first sub-connecting unit includes a first connecting end and a second connecting end; the second sub-connecting unit includes a third connecting end and a fourth connecting end; and the third sub-connecting unit includes a fifth connecting end and a sixth connecting end.

[0046] The pins on the first board and the pins on the second board are disposed on a printed circuit board. The pins on the first board are connected to the transmitting end of the second device through traces on the second board, and the pins on the second board are connected to the receiving end of the second device through traces on the second board.

[0047] The first sub-switching unit switches between the first and fifth connection terminals; the second sub-switching unit switches between the third and sixth connection terminals; the third sub-switching unit switches between the second and fifth connection terminals; and the fourth sub-switching unit switches between the fourth and sixth connection terminals.

[0048] The first board external pin is connected to the first external cable pin, the second board external pin is connected to the second external cable pin, the first external cable pin is connected to the first external cable, and the second external cable pin is connected to the second external cable.

[0049] For example, Figure 2 This is a schematic diagram of the connector structure provided in the embodiments of this application, as shown below. Figure 2As shown (the first connector and the second connector have the same structure). The connector includes a first board internal pin 1, a second board internal pin 8, a first switching unit (also called an internal pin DIP switch), a first connection unit (also called a unidirectional interconnection contact), a second switching unit (also called an external pin DIP switch), a first board external pin 5, a second board external pin 12, a first external cable pin 6, a second external cable pin 13, and a second connection unit 15 (also called a reverse interconnection contact).

[0050] The connector's first switching unit includes a first sub-switching unit 2 and a second sub-switching unit 9; the first connecting unit includes a first sub-connecting unit 3 and a second connecting unit 10; and the second switching unit includes a third sub-switching unit 4 and a fourth sub-switching unit 11.

[0051] The first sub-connecting unit 3 includes a first connecting end 3-1 and a second connecting end 3-2; the second sub-connecting unit 10 includes a third connecting end 10-1 and a fourth connecting end 10-2; and the second connecting unit 15 includes a fifth connecting end 15-1 and a sixth connecting end 15-2.

[0052] Pin 1 and pin 8 are mounted on a printed circuit board (PCB). Pin 1 is connected to the transmitter of the device via internal traces, and pin 8 is connected to the receiver of the device via internal traces.

[0053] The first sub-switching unit 2 switches between the first connection terminal 3-1 and the fifth connection terminal 15-1; the second sub-switching unit 9 switches between the third connection terminal 10-1 and the sixth connection terminal 15-2; the third sub-switching unit 4 switches between the second connection terminal 3-2 and the fifth connection terminal 15-1; and the fourth sub-switching unit 11 switches between the fourth connection terminal 10-2 and the sixth connection terminal 15-2.

[0054] The first external pin 5 is connected to the first external cable pin 6, the second external pin 12 is connected to the second external cable pin 13, the first external cable pin 6 is connected to the first external cable 7, and the second external cable pin 13 is connected to the second external cable 14.

[0055] For example, the first external cable pin 6 and the second external cable pin 13 can be metal contact parts, such as gold fingers, used for electrical connection with sockets on the motherboard or device. The lengths of the first external cable 7 and the second external cable 14 can be determined according to the needs of the actual scenario.

[0056] In one exemplary embodiment, wherein,

[0057] The first sub-switching unit is one of the following: electrical contacts, DIP switches, or integrated circuits.

[0058] The second sub-switching unit is one of the following: electrical contacts, DIP switches, or integrated circuits.

[0059] The third sub-switching unit is one of the following: electrical contacts, DIP switches, or integrated circuits.

[0060] The fourth sub-switching unit is one of the following: electrical contacts, DIP switches, or integrated circuits.

[0061] The first sub-connection unit is one of the following: electrical contact, DIP switch, or integrated circuit.

[0062] The second sub-connection unit is one of the following: electrical contact, DIP switch, or integrated circuit.

[0063] The second connection unit is one of the following: electrical contact, DIP switch, or integrated circuit.

[0064] For example, it can be combined Figure 2 The first sub-switching unit 2, the first sub-connection unit 3, the third sub-switching unit 4, the second sub-switching unit 9, the second sub-connection unit 10, the fourth sub-switching unit 11, and the second connection unit 15 can be logic function units. They can be implemented as physical entities such as electrical contacts and DIP switches, or as electronic devices such as integrated circuits.

[0065] In an exemplary embodiment, when the first sub-switching unit is connected to the first connection terminal, the second sub-switching unit is connected to the third connection terminal, the third sub-switching unit is connected to the second connection terminal, and the fourth sub-switching unit is connected to the fourth connection terminal, the first connector is in a first connection state.

[0066] In an exemplary embodiment, when the first sub-switching unit is connected to the first connection terminal, the second sub-switching unit is connected to the third connection terminal, the third sub-switching unit is connected to the second connection terminal, and the fourth sub-switching unit is connected to the fourth connection terminal, the second connector is in the first connection state.

[0067] For example, Figure 3 This is a schematic diagram of the connector in the first connection state provided in the embodiments of this application, as shown below. Figure 3 As shown. When the first sub-switching unit 2 is connected to the first connection terminal 3-1, the second sub-switching unit 9 is connected to the third connection terminal 10-1, the third sub-switching unit 4 is connected to the second connection terminal 3-2, and the fourth sub-switching unit 11 is connected to the fourth connection terminal 10-2, the connector is in the first connection state. In the first connection state, the pins inside the board are connected to the pins outside the board. The signal is transmitted from inside the board to outside the board, and then propagated further through the cable, or the signal from further away is transmitted through the cable to the pins outside the board, and then to the pins inside the board.

[0068] In one exemplary embodiment, when the first sub-switching unit is connected to the fifth connection terminal and the second sub-switching unit is connected to the sixth connection terminal, the first connector is in a second connection state; or...

[0069] When the third sub-switching unit is connected to the fifth connection terminal and the fourth sub-switching unit is connected to the sixth connection terminal, the first connector is in the second connection state.

[0070] In one exemplary embodiment, when the first sub-switching unit is connected to the fifth connection terminal and the second sub-switching unit is connected to the sixth connection terminal, the second connector is in a second connection state; or...

[0071] When the third sub-switching unit is connected to the fifth connection terminal and the fourth sub-switching unit is connected to the sixth connection terminal, the second connector is in the second connection state.

[0072] For example, Figure 4 A schematic diagram (I) of the connector in the second connection state provided in the embodiments of this application is shown. Figure 4 As shown. When the first sub-switching unit 2 is connected to the fifth connection terminal 15-1 and the second sub-switching unit 9 is connected to the sixth connection terminal 15-2, the connector is in the second connection state.

[0073] For example, Figure 5 A schematic diagram (II) of the connector in the second connection state provided in the embodiments of this application is shown. Figure 5 As shown. When the third sub-switching unit 4 is connected to the fifth connection terminal 15-1 and the fourth sub-switching unit 11 is connected to the sixth connection terminal 15-2, the connector is in the second connection state.

[0074] For example, in the second connection state, an on-board pin is connected to another on-board pin, and a signal is transmitted from one on-board pin to the other.

[0075] Through the above embodiments, a link fault location circuit with switchable connection state was designed, which can intelligently adjust the internal high-speed interconnect topology without physical contact or disassembly of the equipment.

[0076] An embodiment of this application provides a link fault location method, which can be applied to the link fault location circuit described above. Figure 6 A flowchart (I) illustrating the link fault location method provided in this application embodiment is shown below. Figure 6 As shown, the method includes:

[0077] Step S602: In response to an anomaly in the link between the first device and the second device, switch the connection status of the first connector and the second connector to set the corresponding connection status.

[0078] For example, when an abnormality is detected in the high-speed link performance between the first and second devices, an automatic response can be initiated and the connector status can be adjusted. By controlling the switching unit between the first and second connectors, their internal connection states can be dynamically changed to meet the needs of fault detection and location without any physical disassembly or reconnection.

[0079] For example, Figure 7 This is a schematic diagram of the data transmission path under normal working conditions provided in the embodiments of this application, as shown below. Figure 7 As shown, a high-speed bus topology with two connectors interconnected by a cable is used as an example. Both the first and second connectors are in a first connection state. The transmitting end (Tx) of the first device is connected to the receiving end (Rx) of the second device via traces on the first board, the first connector, the first external cable, the second connector, and traces on the second board. Similarly, the transmitting end (Tx) of the second device is connected to the receiving end (Rx) of the first device via traces on the second board, the second connector, the second external cable, the first connector, and traces on the first board. Bidirectional data transmission occurs between the first and second devices. If an anomaly occurs in the link between the first and second devices, the connection state of the first and second connectors can be switched.

[0080] Step S604: Locate the link fault based on the corresponding connection status.

[0081] For example, locating link faults based on the corresponding connection status can reduce reliance on the capabilities of on-site operators and mitigate the risk of new problems introduced by frequent machine removal and cross-validation actions.

[0082] In one exemplary embodiment, step S602 includes:

[0083] The first sub-switching unit of the first connector is switched to connect to the fifth connection end, and the second sub-switching unit is switched to connect to the sixth connection end, so as to set the first connector to the second connection state;

[0084] The first sub-switching unit of the second connector is switched to connect to the fifth connection end, and the second sub-switching unit is switched to connect to the sixth connection end, so as to set the second connector to the second connection state.

[0085] For example, when a high-speed link malfunctions, the first connector and the second connector can be switched to the second connection state. Figure 8 This is a schematic diagram of the small loopback downlink data transmission path provided in the embodiments of this application, as shown below. Figure 8As shown, the transmitter (Tx) of the first device returns to the receiver (Rx) of the first device via traces on the first board, the first connector, and traces on the first board. Similarly, the transmitter (Tx) of the second device returns to the receiver (Rx) of the second device via traces on the second board, the second connector, and traces on the second board. Both the first and second devices are configured in Pseudo-Random Binary Sequence (PRBS) mode. PRBS is a commonly used signal integrity detection method that detects potential electrical or physical defects in the link by sending a series of pseudo-random bit sequences and then comparing them with the received sequence at the receiver. The PRBS signal generated by the device itself loops internally, not only testing the device's signal processing capabilities but also indirectly evaluating the quality of the connector and the traces on the board. This enables small loop detection between the first device and the first connector, and between the second device and the second connector.

[0086] In one exemplary embodiment, step S604 includes:

[0087] In response to the fact that the data sent by the transmitter of the first device fails to return to the receiver of the first device through the traces in the first board and the first connector, it is determined that the link failure occurs in at least one of the first device, the first connector, and the traces in the first board.

[0088] In response to the fact that the data sent by the transmitter of the second device does not return to the receiver of the second device through the traces in the second board and the second connector, it is determined that the link failure occurs in at least one of the second device, the second connector, and the traces in the second board.

[0089] For example, if the detection result on the first device side is abnormal during the small loopback detection, this clearly indicates that the fault location is within the local network of the first device, the traces on the first board closely connected to it, and the first connector. Similarly, if the second device side encounters an anomaly in the small loopback detection, it indicates that the second device, the traces on the second board, and the second connector are possible sources of fault. The core advantage of this detection strategy is that it can quickly narrow down the scope of fault investigation and accurately pinpoint the problem node in the link, avoiding the blind and time-consuming traditional fault investigation methods.

[0090] In one exemplary embodiment, the method further includes:

[0091] In response to the fact that the sending end and receiving end of the first device are connected, and the data sent by the sending end of the first device has not been returned to the receiving end of the first device, it is determined that the link failure occurred in the first device;

[0092] If the sending end and receiving end of the second device are connected, and the data sent by the sending end of the second device is not returned to the receiving end of the second device, it is determined that the link failure occurred in the second device.

[0093] For example, when a small loopback detection anomaly occurs, the device can be further configured into a self-loopback mode. Figure 9 This is a schematic diagram of the self-loop data transmission path provided in the embodiments of this application, as shown below. Figure 9 As shown, the Tx and Rx signals of the first and second devices are internally connected within the chip, unaffected by external pin interconnections, and used to determine if the chip itself is faulty. If the small loopback of the first device is abnormal, a self-loopback is performed on the first device; similarly, if the small loopback of the second device is abnormal, a self-loopback is performed on the second device. If the small loopbacks of either the first or second device are normal, no self-loopback is required. By introducing internal signal loop detection, i.e., self-loopback detection, the functionality and integrity of the device chip itself are directly evaluated. The signal transmitting end (Tx) and receiving end (Rx) of the first and second devices are directly connected at the chip level, completely independent of the influence of external pin interconnections, thus ensuring the purity and accuracy of the detection results.

[0094] In one exemplary embodiment, the method further includes:

[0095] In response to the connection between the transmitter and receiver of the first device and the data sent by the transmitter of the first device being returned to the receiver of the first device, it is determined that the link failure occurred in at least one of the first connector and the traces in the first board;

[0096] In response to the connection between the transmitter and receiver of the second device, and the data sent by the transmitter of the second device being returned to the receiver of the second device, it is determined that the link failure occurred in at least one of the second connector and the traces within the second board.

[0097] For example, if the loopback detection of the first device and the second device does not show any abnormality, it indicates that the link failure may occur in at least one of the first connector and the traces in the first board, or it may occur in at least one of the second connector and the traces in the second board.

[0098] In one exemplary embodiment, the method further includes:

[0099] In response to the data sent by the transmitter of the first device, the data is returned to the receiver of the first device through the traces in the first board and the first connector. The first sub-switching unit of the first connector is switched to be connected to the first connection end, the second sub-switching unit is switched to be connected to the third connection end, the third sub-switching unit is switched to be connected to the second connection end, and the fourth sub-switching unit is connected to the fourth connection end, so as to set the first connector to be in the first connection state.

[0100] The third sub-switching unit of the second connector is switched to connect to the fifth connection end, and the fourth sub-switching unit is switched to connect to the sixth connection end, so as to set the second connector to the second connection state.

[0101] For example, when the small loopback detection is normal, the loopback detection range can be further expanded. Large loopback detection can be performed from the first device side or from the second device side. This embodiment takes the large loopback detection performed from the first device side as an example. Figure 10 A schematic diagram (I) of the large loopback downlink data transmission path provided in this application embodiment is shown below. Figure 10 As shown, the first device, the first board internal wiring, the first connector, the first external cable, the second external cable, and the second connector constitute the large loop path of the first device. At this time, the first connector is in the first connection state, and the second connector is in the second connection state.

[0102] In one exemplary embodiment, step S604 includes:

[0103] If the data sent by the transmitter of the first device fails to return to the receiver of the first device through the traces in the first board, the first connector, and the second connector, it is determined that the link failure occurred in the cable between the first connector and the second connector.

[0104] For example, if the results of the large loopback test still show abnormalities, the source of the fault is located in the external cable or the contact interface between the external cable and the connector. This indicates that the link problem is likely caused by factors such as physical damage, external contamination, or poor contact. These factors directly affect the transmission quality and stability of the signal in the link.

[0105] In one exemplary embodiment, step S604 includes:

[0106] In response to the data sent by the transmitter of the first device, the data is returned to the receiver of the first device through the traces in the first board, the first connector, and the second connector. If it is determined that no link failure has occurred, the first device and the second device are restarted.

[0107] For example, if the large loopback test is normal, it indicates that no faults were found in any component of the entire localization process. The fault may be an intermittent or low-probability event, rather than a persistent hardware failure. Software-level remediation measures, such as system restart or software configuration reset, can be implemented to eliminate possible software conflicts or environmental influences. Even if the link performs normally after software repair, a stricter review strategy can be adopted to further verify its long-term stability and rule out potential hardware problems that were not identified at the software level. This strategy involves extending the detection cycle and increasing the frequency or intensity of stress testing to carefully observe the link's performance under complex environments and long-term operation.

[0108] In one exemplary embodiment, the method further includes:

[0109] In response to the data sent by the transmitter of the second device, the data is returned to the receiver of the second device through the traces in the second board and the second connector. The first sub-switching unit of the second connector is switched to be connected to the first connection end, the second sub-switching unit is switched to be connected to the third connection end, the third sub-switching unit is switched to be connected to the second connection end, and the fourth sub-switching unit is connected to the fourth connection end, so as to set the second connector to be in the first connection state.

[0110] The third sub-switching unit of the first connector is switched to connect to the fifth connection end, and the fourth sub-switching unit is switched to connect to the sixth connection end, so as to set the first connector to the second connection state.

[0111] For example, when the small loopback detection is normal, the loopback detection range can be further expanded. Large loopback detection can be performed from the first device side or from the second device side. This embodiment takes the large loopback detection performed from the second device side as an example. Figure 11 A schematic diagram (II) of the large loopback downlink data transmission path provided in the embodiments of this application is shown below. Figure 11 As shown, the second device, the second board internal wiring, the second connector, the first external cable, the second external cable, and the first connector constitute the large loop path of the second device. At this time, the first connector is in the second connection state, and the second connector is in the first connection state.

[0112] In one exemplary embodiment, step S604 includes:

[0113] If the data sent by the transmitter of the second device fails to return to the receiver of the second device through the traces in the second board, the second connector, and the first connector, it is determined that the link failure occurred in the cable between the first connector and the second connector.

[0114] For example, if the results of the large loopback test still show abnormalities, the source of the fault is located in the external cable or the contact interface between the external cable and the connector. This indicates that the link problem is likely caused by factors such as physical damage, external contamination, or poor contact. These factors directly affect the transmission quality and stability of the signal in the link.

[0115] In one exemplary embodiment, step S604 includes:

[0116] The data sent by the transmitter of the second device is returned to the receiver of the second device through the traces in the second board, the second connector, and the first connector. After confirming that no link failure has occurred, the first device and the second device are restarted.

[0117] For example, if the large loopback test is normal, it indicates that no faults were found in any component of the entire localization process. The fault may be an intermittent or low-probability event, rather than a persistent hardware failure. Software-level remediation measures, such as system restart or software configuration reset, can be implemented to eliminate possible software conflicts or environmental influences. Even if the link performs normally after software repair, a stricter review strategy can be adopted to further verify its long-term stability and rule out potential hardware problems that were not identified at the software level. This strategy involves extending the detection cycle and increasing the frequency or intensity of stress testing to carefully observe the link's performance under complex environments and long-term operation.

[0118] In one exemplary embodiment, prior to step S602, the following is included:

[0119] Detect link performance metrics;

[0120] Determine if the link performance metrics are abnormal.

[0121] For example, in the maintenance and troubleshooting of high-speed links, detecting link performance indicators and determining whether they are abnormal are crucial steps to ensure data transmission efficiency, stability, and accuracy. This process, by monitoring and analyzing various technical parameters of the link, can promptly identify potential problems and provide a basis for fault location.

[0122] In one exemplary embodiment, the link performance metrics include at least one of the following: bandwidth, rate, and bit error rate.

[0123] In one exemplary embodiment, determining whether a link performance metric is abnormal includes at least one of the following:

[0124] If the bandwidth does not meet the first threshold range, the link performance indicator is judged to be abnormal; if the bandwidth meets the first threshold range, the link performance indicator is judged to be normal.

[0125] If the rate does not meet the second threshold range, the link performance indicator is judged to be abnormal; if the rate meets the second threshold range, the link performance indicator is judged to be normal.

[0126] If the bit error rate does not meet the third threshold range within the preset detection time, the link performance indicator is judged to be abnormal; if the bit error rate meets the third threshold range within the preset detection time, the link performance indicator is judged to be normal.

[0127] For example, the bandwidth and speed of a link can be obtained directly through commands in the operating system. Link bandwidth and speed are fundamental indicators reflecting link capacity and transmission efficiency. When both indicators meet pre-defined value ranges, the link is preliminarily determined to be in normal working condition. If the bandwidth does not meet the first threshold range, the link performance is considered abnormal; if the speed does not meet the second threshold range, the link performance is also considered abnormal.

[0128] For example, it can be done through formula Determine the preset detection time, where, For bus speed, This represents the confidence level, which is typically 95%, but can also be determined based on the specific application, for example, a value of 99.999%. The preset detection time is T, and BER is the bit error rate, which can be the bit error rate defined in the specification. After the preset detection time is determined, if the bit error increment is less than 1 within time T, it means that the current link's bit error rate meets the third threshold range and is compliant; otherwise, the link performance indicator is judged to be abnormal.

[0129] Through the above embodiments, loopback detection is introduced to automatically switch the connector's connection status in response to link performance anomalies, quickly completing the entire process from initial diagnosis to pinpointing the specific fault location. This reduces reliance on manual judgment, lowers the risk of misdiagnosis and missed diagnosis, and ensures the accuracy and timeliness of fault location.

[0130] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0131] Embodiments of this application also provide a link fault location device. Figure 12 This is a schematic diagram of the results of the link fault location device provided in the embodiments of this application, as shown below. Figure 12 As shown, the device 1200 includes a switching module 1202 and a positioning module 1204.

[0132] The switching module 1202 is used to switch the first switching unit and the second switching unit of the first connector and the second connector in response to an abnormality in the link between the first device and the second device, so as to set the corresponding connection status.

[0133] The positioning module 1204 is used to locate link faults based on the corresponding connection status.

[0134] In an exemplary embodiment, the switching module 1202 is further configured to switch the first sub-switching unit of the first connector to be connected to the fifth connection end and the second sub-switching unit to be connected to the sixth connection end, so as to set the first connector to a second connection state; and to switch the first sub-switching unit of the second connector to be connected to the fifth connection end and the second sub-switching unit to be connected to the sixth connection end, so as to set the second connector to a second connection state.

[0135] In one exemplary embodiment, the positioning module 1204 is further configured to determine that a link failure occurs in at least one of the first device, the first connector, and the first board trace in response to the fact that data sent by the transmitter of the first device fails to return to the receiver of the first device through the first board trace and the first connector; and to determine that a link failure occurs in at least one of the second device, the second connector, and the second board trace in response to the fact that data sent by the transmitter of the second device fails to return to the receiver of the second device through the second board trace and the second connector.

[0136] In one exemplary embodiment, the positioning module 1204 is further configured to determine that a link failure occurs in the first device in response to the fact that the transmitter and receiver of the first device are connected and the data sent by the transmitter of the first device has not been returned to the receiver of the first device; and to determine that a link failure occurs in the second device in response to the fact that the transmitter and receiver of the second device are connected and the data sent by the transmitter of the second device has not been returned to the receiver of the second device.

[0137] In one exemplary embodiment, the positioning module 1204 is further configured to determine, in response to the first device's transmitter and receiver being connected and data sent by the first device's transmitter being returned to the first device's receiver, that a link failure occurs in at least one of the first connector and the trace within the first board; and in response to the second device's transmitter and receiver being connected and data sent by the second device's transmitter being returned to the second device's receiver, that a link failure occurs in at least one of the second connector and the trace within the second board.

[0138] In an exemplary embodiment, the switching module 1202 is further configured to, in response to data sent by the transmitting end of the first device returning to the receiving end of the first device via the wiring in the first board and the first connector, switch the first sub-switching unit of the first connector to be connected to the first connection end, switch the second sub-switching unit to be connected to the third connection end, switch the third sub-switching unit to be connected to the second connection end, and switch the fourth sub-switching unit to be connected to the fourth connection end, so as to set the first connector to be in a first connection state; and switch the third sub-switching unit of the second connector to be connected to the fifth connection end and switch the fourth sub-switching unit to be connected to the sixth connection end, so as to set the second connector to be in a second connection state.

[0139] In an exemplary embodiment, the positioning module 1204 is further configured to determine that the link failure occurred in the cable between the first connector and the second connector in response to the fact that data sent by the transmitter of the first device did not return to the receiver of the first device through the wiring in the first board, the first connector, and the second connector.

[0140] In an exemplary embodiment, the positioning module 1204 is further configured to respond to the data sent by the transmitting end of the first device returning to the receiving end of the first device through the wiring in the first board, the first connector, and the second connector, determine that no link failure has occurred, and restart the first device and the second device.

[0141] In an exemplary embodiment, the switching module 1202 is further configured to, in response to data transmitted by the transmitting end of the second device returning to the receiving end of the second device via the wiring within the second board and the second connector, switch the first sub-switching unit of the second connector to be connected to the first connection end, switch the second sub-switching unit to be connected to the third connection end, switch the third sub-switching unit to be connected to the second connection end, and switch the fourth sub-switching unit to be connected to the fourth connection end, so as to set the second connector to a first connection state; and switch the third sub-switching unit of the first connector to be connected to the fifth connection end and switch the fourth sub-switching unit to be connected to the sixth connection end, so as to set the first connector to a second connection state.

[0142] In one exemplary embodiment, the positioning module 1204 is further configured to determine that the link failure occurred in the cable between the first connector and the second connector in response to the fact that the data sent by the transmitter of the second device did not return to the receiver of the second device through the traces in the second board, the second connector, and the first connector.

[0143] In an exemplary embodiment, the positioning module 1204 is further configured to respond to the data sent by the transmitting end of the second device returning to the receiving end of the second device through the wiring in the second board, the second connector, and the first connector, determine that no link failure has occurred, and restart the first device and the second device.

[0144] In one exemplary embodiment, the device 1200 further includes a detection module 1206 and a judgment module 1208.

[0145] Detection module 1206 is used to detect link performance indicators;

[0146] The judgment module 1208 is used to determine whether the link performance indicators are abnormal.

[0147] In one exemplary embodiment, the link performance metrics include at least one of the following: bandwidth, rate, and bit error rate.

[0148] In an exemplary embodiment, the judgment module 1208 is further configured to: determine that the link performance indicator is abnormal in response to the bandwidth not meeting the first threshold range; determine that the link performance indicator is normal in response to the bandwidth meeting the first threshold range; determine that the link performance indicator is abnormal in response to the rate not meeting the second threshold range; determine that the link performance indicator is normal in response to the rate meeting the second threshold range; determine that the link performance indicator is abnormal in response to the bit error rate not meeting the third threshold range within a preset detection time; and determine that the link performance indicator is normal in response to the bit error rate meeting the third threshold range within a preset detection time.

[0149] The description of the features in the embodiments corresponding to the above-mentioned link fault location device can be found in the relevant descriptions of the embodiments corresponding to the link fault location method, and will not be repeated here.

[0150] Example

[0151] Figure 13 A flowchart (II) illustrating the link fault location method provided in this application embodiment is shown below. Figure 13 As shown, this embodiment uses a high-speed bus topology in which two connectors and two devices are interconnected via external cables as an example.

[0152] When the detection program or monitoring mechanism detects abnormal signs at the physical layer of the high-speed link (including bandwidth, rate, and bit error rate), the system immediately initiates the fault location process. The automated nature of this process ensures a rapid and efficient response. For the receiver (Rx) and the corresponding transmitter (Tx) that first reports an error, the system initiates a small loopback detection in parallel. This is a preliminary health check designed to quickly define the scope of the fault.

[0153] If the small loopback test shows no obvious abnormalities at either end, the subsequent process escalates to the large loopback test stage. This test covers a wider range of links, including internal circuit boards, connectors, and external cables, allowing for a more in-depth inspection of the fault point. If the large loopback test result is abnormal, it often points to poor contact between the external cable and its connector, such as contamination or interference from foreign objects. In this case, a simple and effective solution is to unplug or replace the cable to restore normal communication.

[0154] Conversely, if the large loopback test is normal, it means the fault may originate from a low-probability event or a temporary fluctuation in the system's state, rather than a persistent problem with the link itself. In this case, the system takes a soft-fix approach, using a restart and extended testing cycle to more rigorously re-evaluate the fault. It's important to note that even if the more stringent re-evaluation fails to reproduce the fault, the maintenance process will not be triggered hastily. This ensures the machine can be put back into normal use without concrete evidence of physical damage, avoiding unnecessary downtime.

[0155] If a small loopback detection fails at either end, the system will further perform a self-loopback detection on that end. Self-loopback is a more in-depth diagnostic method that bypasses external connections and directly checks signal integrity within the device's chip. The result of this detection becomes crucial in determining the root cause of the fault—whether it's a defect in the chip itself, a soldering problem associated with the board, abnormal PCB routing, via defects, or even connector failure, it can all be clearly identified. For confirmed board faults, the system recommends replacing the board as the final solution, covering all hardware-level issues that may be associated with the board.

[0156] It should be noted that this embodiment illustrates a high-speed bus topology with two connectors and two devices interconnected via external cables. In practical applications, this topology can also be extended to interconnect more connectors and more devices. It can be dynamically adjusted according to the actual application scenario, and this invention does not impose any limitations on it.

[0157] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described embodiments of the link fault location method.

[0158] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the link fault location method when it is run.

[0159] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0160] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described embodiments of the link fault location method.

[0161] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described link fault location method embodiments.

[0162] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0163] The foregoing has provided a detailed description of the link fault location circuit, method, and apparatus provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A link fault location circuit, characterized in that, The device includes at least one first connector and a second connector, wherein the first and second connectors are disposed on a printed circuit board, and are connected via a first external cable and a second external cable. The first connector is connected to a first device via traces on a first board, and the second connector is connected to a second device via traces on a second board. The first switching unit of the first connector switches between the first connecting unit and the second connecting unit of the first connector, and the second switching unit of the first connector switches between the first connecting unit and the second connecting unit of the first connector. The first switching unit of the second connector switches between the first connecting unit and the second connecting unit of the second connector, and the second switching unit of the second connector switches between the first connecting unit and the second connecting unit of the second connector.

2. The circuit according to claim 1, characterized in that, The first connector includes first board inner pins, second board inner pins, a first switching unit, a first connecting unit, a second switching unit, first board outer pins, second board outer pins, a first external cable pin, a second external cable pin, and a second connecting unit. The first switching unit includes a first sub-switching unit and a second sub-switching unit; the first connection unit includes a first sub-connection unit and a second connection unit; and the second switching unit includes a third sub-switching unit and a fourth sub-switching unit. The first sub-connection unit includes a first connection end and a second connection end; the second sub-connection unit includes a third connection end and a fourth connection end; the second connection unit includes a fifth connection end and a sixth connection end. The first and second internal pins are disposed on the printed circuit board. The first internal pin is connected to the transmitting end of the first device through the internal traces of the first board, and the second internal pin is connected to the receiving end of the first device through the internal traces of the first board. The first sub-switching unit switches between the first connection terminal and the fifth connection terminal; the second sub-switching unit switches between the third connection terminal and the sixth connection terminal; the third sub-switching unit switches between the second connection terminal and the fifth connection terminal; and the fourth sub-switching unit switches between the fourth connection terminal and the sixth connection terminal. The first board external pin is connected to the first external cable pin, the second board external pin is connected to the second external cable pin, the first external cable pin is connected to the first external cable, and the second external cable pin is connected to the second external cable.

3. The circuit according to claim 1, characterized in that, The second connector includes first board inner pins, second board inner pins, a first switching unit, a first connecting unit, a second switching unit, first board outer pins, second board outer pins, a first external cable pin, a second external cable pin, and a second connecting unit. The first switching unit includes a first sub-switching unit and a second sub-switching unit; the first connection unit includes a first sub-connection unit and a second connection unit; and the second switching unit includes a third sub-switching unit and a fourth sub-switching unit. The first sub-connection unit includes a first connection end and a second connection end; the second sub-connection unit includes a third connection end and a fourth connection end; the second connection unit includes a fifth connection end and a sixth connection end. The first board internal pin and the second board internal pin are disposed on the printed circuit board. The first board internal pin is connected to the transmitting end of the second device through the second board internal trace, and the second board internal pin is connected to the receiving end of the second device through the second board internal trace. The first sub-switching unit switches between the first connection terminal and the fifth connection terminal; the second sub-switching unit switches between the third connection terminal and the sixth connection terminal; the third sub-switching unit switches between the second connection terminal and the fifth connection terminal; and the fourth sub-switching unit switches between the fourth connection terminal and the sixth connection terminal. The first board external pin is connected to the first external cable pin, the second board external pin is connected to the second external cable pin, the first external cable pin is connected to the first external cable, and the second external cable pin is connected to the second external cable.

4. The circuit according to claim 2 or 3, characterized in that, in, The first sub-switching unit is one of the following: electrical contact, DIP switch, or integrated circuit. The second sub-switching unit is one of the following: electrical contacts, DIP switches, or integrated circuits. The third sub-switching unit is one of the following: electrical contact, DIP switch, or integrated circuit. The fourth sub-switching unit is one of the following: an electrical contact, a DIP switch, or an integrated circuit. The first sub-connection unit is one of the following: an electrical contact, a DIP switch, or an integrated circuit. The second sub-connection unit is one of the following: electrical contact, DIP switch, or integrated circuit. The second connection unit is one of an electrical contact, a DIP switch, or an integrated circuit.

5. The circuit according to claim 2, characterized in that, When the first sub-switching unit is connected to the first connection terminal, the second sub-switching unit is connected to the third connection terminal, the third sub-switching unit is connected to the second connection terminal, and the fourth sub-switching unit is connected to the fourth connection terminal, the first connector is in the first connection state.

6. The circuit according to claim 2, characterized in that, When the first sub-switching unit is connected to the fifth connection terminal and the second sub-switching unit is connected to the sixth connection terminal, the first connector is in the second connection state; or... When the third sub-switching unit is connected to the fifth connection terminal and the fourth sub-switching unit is connected to the sixth connection terminal, the first connector is in the second connection state.

7. The circuit according to claim 3, characterized in that, When the first sub-switching unit is connected to the first connection terminal, the second sub-switching unit is connected to the third connection terminal, the third sub-switching unit is connected to the second connection terminal, and the fourth sub-switching unit is connected to the fourth connection terminal, the second connector is in the first connection state.

8. The circuit according to claim 3, characterized in that, When the first sub-switching unit is connected to the fifth connection terminal and the second sub-switching unit is connected to the sixth connection terminal, the second connector is in a second connection state; or... When the third sub-switching unit is connected to the fifth connection terminal and the fourth sub-switching unit is connected to the sixth connection terminal, the second connector is in the second connection state.

9. A link fault location method, characterized in that, The method, applied to the link fault location circuit according to any one of claims 1 to 8, comprises: In response to an anomaly in the link between the first device and the second device, the connection status of the first connector and the second connector is switched to set the corresponding connection status; The link fault is located based on the corresponding connection status.

10. The method according to claim 9, characterized in that, Switching the connection status of the first connector and the second connector to set the corresponding connection status includes: The first sub-switching unit of the first connector is switched to connect to the fifth connection end, and the second sub-switching unit is switched to connect to the sixth connection end, so as to set the first connector to a second connection state; The first sub-switching unit of the second connector is switched to connect to the fifth connection end, and the second sub-switching unit is switched to connect to the sixth connection end, so as to set the second connector to the second connection state.

11. The method according to claim 10, characterized in that, Locating link faults based on the corresponding connection status includes: In response to the fact that data sent by the transmitter of the first device fails to return to the receiver of the first device through the traces in the first board and the first connector, it is determined that the link failure occurs in at least one of the first device, the first connector, and the traces in the first board. In response to the fact that data sent by the transmitter of the second device fails to return to the receiver of the second device through the traces in the second board and the second connector, it is determined that the link failure occurs in at least one of the second device, the second connector, and the traces in the second board.

12. The method according to claim 11, characterized in that, The method further includes: In response to the fact that the sending end and receiving end of the first device are connected, and the data sent by the sending end of the first device does not return to the receiving end of the first device, it is determined that the link failure occurred in the first device; In response to the fact that the transmitting end and receiving end of the second device are connected, and the data sent by the transmitting end of the second device is not returned to the receiving end of the second device, it is determined that the link failure occurred in the second device.

13. The method according to claim 11, characterized in that, The method further includes: In response to the connection between the transmitting end and the receiving end of the first device, and the data sent by the transmitting end of the first device being returned to the receiving end of the first device, it is determined that the link failure occurs in at least one of the first connector and the traces in the first board; In response to the connection between the transmitter and receiver of the second device, and the data sent by the transmitter of the second device being returned to the receiver of the second device, it is determined that the link failure occurs in at least one of the second connector and the traces within the second board.

14. The method according to claim 10, characterized in that, The method further includes: In response to the data sent by the transmitting end of the first device being returned to the receiving end of the first device through the wiring in the first board and the first connector, the first sub-switching unit of the first connector is switched to be connected to the first connection end, the second sub-switching unit is switched to be connected to the third connection end, the third sub-switching unit is switched to be connected to the second connection end, and the fourth sub-switching unit is connected to the fourth connection end, so as to set the first connector to be in the first connection state. The third sub-switching unit of the second connector is switched to connect to the fifth connection end, and the fourth sub-switching unit is switched to connect to the sixth connection end, so as to set the second connector to the second connection state.

15. The method according to claim 14, characterized in that, Locating link faults based on the corresponding connection status includes: If the data sent by the transmitter of the first device fails to return to the receiver of the first device through the traces in the first board, the first connector, and the second connector, it is determined that the link failure occurred in the cable between the first connector and the second connector.

16. The method according to claim 14, characterized in that, Locating link faults based on the corresponding connection status includes: In response to the data sent by the transmitter of the first device being returned to the receiver of the first device through the traces in the first board, the first connector, and the second connector, it is determined that the link failure has not occurred, and the first device and the second device are restarted.

17. The method according to claim 10, characterized in that, The method further includes: In response to the data sent by the transmitting end of the second device being returned to the receiving end of the second device through the traces in the second board and the second connector, the first sub-switching unit of the second connector is switched to be connected to the first connection end, the second sub-switching unit is switched to be connected to the third connection end, the third sub-switching unit is switched to be connected to the second connection end, and the fourth sub-switching unit is connected to the fourth connection end, so as to set the second connector to be in the first connection state. The third sub-switching unit of the first connector is switched to connect to the fifth connection end, and the fourth sub-switching unit is switched to connect to the sixth connection end, so as to set the first connector to the second connection state.

18. The method according to claim 17, characterized in that, Locating link faults based on the corresponding connection status includes: If the data sent by the transmitter of the second device fails to return to the receiver of the second device through the traces in the second board, the second connector, and the first connector, it is determined that the link failure occurred in the cable between the first connector and the second connector.

19. The method according to claim 17, characterized in that, Locating link faults based on the corresponding connection status includes: In response to the data sent by the transmitter of the second device, the data is returned to the receiver of the second device through the traces in the second board, the second connector, and the first connector. If it is determined that the link failure has not occurred, the first device and the second device are restarted.

20. The method according to claim 9, characterized in that, Before switching the connection states of the first connector and the second connector to set the corresponding connection state, the following steps are included: Detect link performance metrics; Determine if the link performance metrics are abnormal.

21. The method according to claim 20, characterized in that, The link performance metrics include at least one of the following: bandwidth, rate, and bit error rate.

22. The method according to claim 21, characterized in that, Determine if the link performance metrics are abnormal, including at least one of the following: If the bandwidth does not meet the first threshold range, the link performance indicator is determined to be abnormal; if the bandwidth meets the first threshold range, the link performance indicator is determined to be normal. If the rate does not meet the second threshold range, the link performance indicator is determined to be abnormal; if the rate meets the second threshold range, the link performance indicator is determined to be normal. If the bit error rate does not meet the third threshold range within a preset detection time, the link performance indicator is determined to be abnormal; if the bit error rate meets the third threshold range within a preset detection time, the link performance indicator is determined to be normal.

23. A link fault location device, characterized in that, include: The switching module is used to switch the first switching unit and the second switching unit of the first connector and the second connector in response to an abnormality in the link between the first device and the second device, so as to set the corresponding connection status. The positioning module is used to locate link faults based on the corresponding connection status.

24. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the method as claimed in any one of claims 9 to 22.

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