Method and device for determining time delay, chip and communication system

Abstract

The invention provides a method and equipment for determining time delay, a chip and a communication system, and belongs to the technical field of communication. The method comprises the steps that a sending device sends a first test code stream and a second test code stream to a receiving device, the first test code stream is used for determining the time delay of serial processing, and the second test code stream is used for determining the time delay of deserializing processing, so that the two test code streams can be used for respectively determining the time delay of serial processing and the time delay of deserializing processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a method for determining time delay, device, chip and communication system. BACKGROUND

[0002] In some high-precision distance measurement or high-precision clock synchronization scenarios, uncertain time delay is a key bottleneck for precision improvement. For example, when measuring the precise distance between a first position point and a second position point, the first position point is deployed with a first device and the second position point is deployed with a second device. A serializer and a deserializer are used in the digital high-speed chip of the first device and the second device. There are functional components such as serial processing, deserial processing and clock recovery in the serializer and the deserializer, and it is difficult to avoid introducing uncertain time delay. For this type of time delay, the data time delay after each power-on, reset or establishment of an optical communication link is inconsistent, and needs to be effectively compensated according to the state of the digital high-speed chip each time the optical communication link is established.

[0003] In the related art, after the establishment of a communication link, a clock code stream is sent on the serializer of the digital high-speed chip of the first device. The clock code stream is transmitted to the deserializer of the digital high-speed chip of the second device all the time, and a phase comparison circuit is added at the outlet of the serializer and the inlet of the deserializer to measure the time delay after the serializer and the deserializer are stabilized. Although this method can better solve the problem of uncertain time delay, when applied to an optical communication system, the method of sending a clock code stream is only applicable to an intensity modulation with direct detection (IMDD) system, and for differential phase shift keying (DPSK) systems or other systems with better communication performance, since the clock code stream cannot be received by the deserializer, the time delay cannot be determined. SUMMARY

[0004] The present application provides a method for determining time delay, device, chip and communication system, which uses two test code streams to determine the time delay of serial processing and the time delay of deserial processing. The technical solutions adopted are as follows:

[0005] In a first aspect, the present application provides a method for determining a time delay, applied to a sending device, the method comprising: performing serial processing on a first test code stream to obtain first serial data and outputting the first serial data to a receiving device; determining a time delay of the serial processing based on a phase comparison result of a phase of the first serial data and a first phase (the first phase being a phase of a clock used by the first test code stream); performing the serial processing on a second test code stream to obtain second serial data and outputting the second serial data to the receiving device, wherein the second test code stream is used to determine a time delay of deserial processing in the receiving device after the sending device and the receiving device establish a communication connection, and a frequency of the first test code stream is lower than a frequency of the second test code stream.

[0006] In the scheme shown in the present application, the sending device uses the first test code stream to determine the time delay of the serial processing in the sending device. The sending device sends the second test code stream to the receiving device, and the second test code stream is used to determine the time delay of the deserial processing in the receiving device. In this way, two test code streams can be used to determine the time delays of the serial processing and the deserial processing, respectively.

[0007] In an optional manner, the second test code stream is used not only to determine the time delay of the deserial processing in the receiving device, but also to establish the communication connection between the receiving device and the sending device. In this way, when the communication connection is established, no separate data for establishing the communication connection needs to be sent, thereby saving communication resources.

[0008] In an optional manner, the first serial data is a low-frequency clock code stream, and in the case that a data baud rate of the sending device is X gigabit per second (Gbps), a frequency of the first serial data is X / 2N giga hertz (GHz), and N is an integer.

[0009] In an optional manner, the first serial data is a periodic data stream composed of continuous N-bit 0 and continuous N-bit 1, so that the sending device can measure the time delay of the serial processing.

[0010] In an optional manner, in order to make the serial data obtained after demodulation by the receiving device be balanced at 0 and 1 and be able to perform phase comparison, and in the case that the data baud rate of the sending device is X Gbps, the second serial data is a periodic data stream composed of continuous N-bit clock code stream and continuous N-bit direct current level, a frequency of the N-bit clock code stream is X / 2 GHz, and N is an integer.

[0011] In an optional manner, N is related to a parallelism used by the serial processing, for example, N is equal to one half of the parallelism. In this way, N is related to a system in which the sending device is located, and it is more convenient to measure the time delays of the serial processing and the deserial processing.

[0012] In an alternative way, the second test code stream is obtained by differentially encoding the first test code stream, so that only one test code stream needs to be provided when measuring the delay.

[0013] In an alternative way, after the communication connection between the sending device and the receiving device is interrupted, the sending device re-sends the second test code stream to the receiving device, so that the sending device and the receiving device re-establish the communication connection and re-measure the delay of the deserializing processing in the receiving device.

[0014] In an alternative way, after the sending device and the receiving device establish the communication connection, the sending device can also send normal communication data to the receiving device to communicate with the receiving device, and determine the transmission time between the sending device and the receiving device based on the delay of the deserializing processing and the delay of the serializing processing. In this way, since the delay of the deserializing processing and the delay of the serializing processing are compensated, the accurate transmission time can be determined.

[0015] In a second aspect, the application provides a method for determining a delay, applied to a receiving device, which comprises: receiving serial data sent by a sending device, before receiving the serial data, receiving data obtained by serializing and modulating a first test code stream, the serial data is obtained by serializing and modulating a second test code stream, sequentially demodulating and deserializing the serial data to obtain a target clock and parallel data, after establishing a communication connection with the sending device, determining the delay of the deserializing processing based on a phase comparison result of a phase of the target clock and a target phase, wherein the target phase is a phase of data obtained by demodulating the serial data.

[0016] In the scheme shown in the application, the sending device sends the second test code stream to the receiving device, and the second test code stream is used to determine the delay of the deserializing processing after being demodulated in the receiving device, so that the receiving device can determine the delay of the deserializing processing.

[0017] In an alternative way, the second test code stream is used to establish the communication connection between the receiving device and the sending device, in addition to being used to determine the delay of the deserializing processing in the receiving device, so that no special processing of data for establishing the communication connection is needed, thereby saving processing resources.

[0018] In an alternative way, in order to make the serial data obtained by the receiving device after demodulation balanced with 0 and 1 and capable of phase comparison, when the data baud rate of the sending device is X Gbps, the serial data is a periodic data stream composed of a continuous N-bit clock code stream and a continuous N-bit direct current level, the frequency of the N-bit clock code stream is X / 2 GHz, and N is an integer.

[0019] In a third aspect, the present application provides a sending device, comprising a processing module, a serializer, a phase comparator and a modulator, the processing module is configured to output a first test code stream and a second test code stream to the serializer, the first test code stream is output before the second test code stream, the frequency of the first test code stream is lower than the frequency of the second test code stream, and the second test code stream is used to detect the time delay of deserialization processing in a receiving device; the serializer is configured to perform serialization processing on the received data to obtain serialized data and output the serialized data to the modulator; the phase comparator is configured to determine the time delay of the serializer based on the phase comparison result of the phase of the serialized data corresponding to the first test code stream and a first phase, and the first phase is the phase of the clock used by the first test code stream; and the modulator is configured to output the modulated serialized data.

[0020] In the scheme shown in the present application, the sending device sends the first test code stream and the second test code stream to the receiving device, the first test code stream is used to determine the time delay of serialization processing, and the second test code stream is used to determine the time delay of deserialization processing, so that two kinds of test code streams can be used to determine the time delays of serialization processing and deserialization processing, respectively.

[0021] In an optional manner, the processing module comprises a multiplexer, which can transmit different data in different cases, so that a set of systems can be used for measuring time delay and normal communication, i.e., the first test code stream is output to the serializer when the time delay of the serializer is measured, the second test code stream is output to the serializer when the time delay of deserialization processing is measured, and the communication data is output to the serializer when the sending device sends the communication data.

[0022] In an optional manner, the second test code stream is obtained by differentially encoding the first test code stream, and the processing module comprises a differential encoding unit, which transmits the first test code stream when the time delay of the serializer is measured by the sending device, and obtains the second test code stream by differentially encoding the first test code stream when the time delay of deserialization processing is measured, so that the sending device only needs to provide one kind of test code stream.

[0023] In an optional manner, the processing module comprises a multiplexer, which can transmit different data in different cases, so that a set of systems can be used for measuring time delay and normal communication. For example, the multiplexer is configured to obtain the first test code stream when the time delay of the serializer or the time delay of deserialization processing is measured, output the first test code stream to the differential encoding unit, and output the communication data to the differential encoding unit when the sending device sends the communication data; the differential encoding unit is configured to output the communication data to the serializer after differentially encoding the communication data when the communication data is not differentially encoded data; or the multiplexer is configured to receive the data sent by the differential encoding unit when the time delay of the serializer or the time delay of deserialization processing is measured, output the received data to the serializer, and output the communication data to the serializer when the sending device sends the communication data.

[0024] In an optional mode, the serial data corresponding to the first test code stream is a low-frequency clock code stream, and in the case that the data baud rate of the sending device is X Gbps, the frequency of the low-frequency clock code stream is X / 2N GHz, N being an integer.

[0025] In an optional mode, the serial data corresponding to the first test code stream is a periodic data stream composed of continuous N-bit 0 and continuous N-bit 1, so that the sending device can measure the time delay of serial processing.

[0026] In an optional mode, in order to make the serial data obtained after demodulation by the receiving device be equalized to 0 and 1 and be able to perform phase comparison, and in the case that the data baud rate of the sending device is X Gbps, the serial data corresponding to the second test code stream is a periodic data stream composed of continuous N-bit clock code stream and continuous N-bit direct current level, the frequency of the N-bit clock code stream being X / 2 GHz, N being an integer.

[0027] In a fourth aspect, the present application provides a receiving device, comprising a demodulator, a deserializer and a target phase comparator; the demodulator is configured to perform demodulation processing on serial data received from a sending device to obtain and output data after demodulation processing to the deserializer, the receiving device receives data obtained by performing serial processing and modulation processing on a first test code stream before receiving the serial data, the frequency of the first test code stream being lower than the frequency of a second test code stream; the deserializer is configured to perform deserialization processing on the data after demodulation processing to obtain a target clock and parallel data; and the target phase comparator is configured to determine the time delay of the deserializer based on the phase comparison result of the phase of the target clock and a target phase, the target phase being the phase of the data after demodulation processing.

[0028] In the scheme shown in the present application, the sending device sends the second test code stream to the receiving device, and the second test code stream is used to determine the time delay of deserialization processing, so that the receiving device can determine the time delay of deserialization processing.

[0029] In an optional mode, the receiving device further comprises a target processing module, and the target processing module establishes a communication connection with the sending device in the case that the serial data is correctly received. In this way, the data for establishing a communication connection does not need to be processed specially, so that processing resources can be saved.

[0030] In a fifth aspect, the present application provides a chip, which is used to execute the method for determining a time delay in the first aspect or any of the optional modes of the first aspect.

[0031] In a sixth aspect, the present application provides a chip, which is used to execute the method for determining a time delay in the second aspect or any of the optional modes of the second aspect.

[0032] In a seventh aspect, the present application provides a communication system, the communication system comprising a transmitting device and a receiving device, the transmitting device being as described in the third aspect or any of the optional modes, and the receiving device being as described in the fourth aspect or any of the optional modes. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a schematic diagram of a clock stream transmission before and after provided in a conventional scheme;

[0034] Figure 2 is a schematic diagram of a system architecture of a communication system provided by an exemplary embodiment of the present application;

[0035] Figure 3 is another schematic diagram of a system architecture of a communication system provided by an exemplary embodiment of the present application;

[0036] Figure 4 is a schematic diagram of a structure of a transmitting device provided by an exemplary embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a structure of a receiving device provided by an exemplary embodiment of the present application;

[0038] Figure 6 is another schematic diagram of a structure of a transmitting device provided by an exemplary embodiment of the present application;

[0039] Figure 7 is yet another schematic diagram of a structure of a transmitting device provided by an exemplary embodiment of the present application;

[0040] Figure 8 is still another schematic diagram of a structure of a transmitting device provided by an exemplary embodiment of the present application;

[0041] Figure 9 is a schematic diagram of a first test stream provided by an exemplary embodiment of the present application;

[0042] Figure 10 is a schematic diagram of a second test stream provided by an exemplary embodiment of the present application;

[0043] Figure 11 is another schematic diagram of a second test stream provided by an exemplary embodiment of the present application;

[0044] Figure 12 is a schematic diagram of a method flow of determining a time delay provided by an exemplary embodiment of the present application.

[0045] BRIEF DESCRIPTION OF DRAWINGS

[0046] 1, transmitting device; 2, receiving device; 3, controller; 11, processing module; 12, serializer; 13, phase comparator; 14, modulator; 111, multiplexer; 112, differential encoding unit; 113, code stream providing unit; 21, demodulator; 22, deserializer; 23, target phase comparator; 24, target processing module. DETAILED DESCRIPTION

[0047] For the purpose, technical solutions and advantages of the present application to be more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0048] Some terms and concepts related to the embodiments of the present application are explained below.

[0049] 1, DPSK is a digital signal modulation method, which uses the relative carrier phase information value of the previous and next symbols to transmit digital information. When using the DPSK modulation method, the receiving device uses the balanced detection method, which can theoretically obtain a 3dB optical signal noise ratio (OSNR) performance benefit compared to the direct intensity detection method. Therefore, DPSK is more suitable for long-distance communication systems sensitive to transmission performance.

[0050] 2, uncertain delay on the communication link, in the digital high-speed physical layer (Physical Layer, PHY) chip, the serializer (Serializer) and deserializer (Deserializer) are commonly used, there is serial processing (parallel conversion processing) in the serializer, and there is deserialization processing (serial-parallel conversion processing and clock recovery) in the deserializer. It is difficult to avoid introducing uncertain delay in functions such as serial processing and deserialization processing. For such delays, the data delay is inconsistent after each power-on, reset or re-establishment of communication connection, and needs to be effectively compensated according to the state of each time the physical layer chip establishes a communication connection.

[0051] In some high-precision distance measurement or high-precision clock synchronization scenarios, uncertain delay is a key bottleneck for precision improvement. For example, when measuring the distance between satellites, multiplexing the inter-satellite laser communication link for inter-satellite distance measurement, the uncertain delay on the communication link is a key bottleneck for improving the precision of satellite communication and ranging integration.

[0052] In the IMDD system, after the optical communication link is established, the clock code stream is sent on the serializer of the sending device, and a phase comparison circuit is added at the outlet of the serializer to determine the time delay of the serializer. The clock code stream is transmitted to the deserializer of the digital high-speed PHY chip of the receiving device, and a phase comparison circuit is added at the inlet of the deserializer to determine the time delay of the deserializer. This method is suitable for determining the time delay in the IMDD system, but in the system using the DPSK modulation method or other systems with better communication performance, after the clock code stream is transmitted to the receiving device, it is phase-modulated by the sending device and becomes an unbalanced pulse signal of 0 and 1, which is difficult to use for phase comparison and does not meet the characteristics of balanced 0 and 1 input of the deserializer, as shown in Figure 1 Therefore, it cannot be received by the deserializer, so the time delay of the deserializer cannot be determined.

[0053] Based on this, the embodiment of the present application provides a method for determining the time delay, in which the sending device sends two different test code streams, the two different test code streams including a first test code stream and a second test code stream, the first test code stream being used to measure the time delay of the serialization processing, and the second test code stream being used to measure the time delay of the deserialization processing, which solves the requirement that one test code stream cannot measure the time delays on both sides of the transceiver physical layer chip.

[0054] Figure 2 A system architecture diagram of the communication system in the embodiment of the present application is provided. As shown in Figure 2 The communication system includes a sending device 1 and a receiving device 2, and the sending device 1 and the receiving device 2 are connected through an optical fiber or other transmission medium. The sending device 1 is used to send the test code stream to the receiving device 2 to determine the time delay of the serialization processing in the sending device 1, and to enable the receiving device 2 to determine the time delay of the deserialization processing. In addition, the sending device 1 is also used to send normal communication data to the receiving device 2.

[0055] Specifically, after establishing a physical communication link between transmitting device 1 and receiving device 2, transmitting device 1 first sends a first test code stream to receiving device 2 to determine the first delay in serial processing within transmitting device 1. The first test code stream is a code stream suitable for phase comparison after serial processing. Then, transmitting device 1 sends a second test code stream to receiving device 2 so that receiving device 2 can determine the second delay in deserialization processing. The second test code stream is a code stream suitable for phase comparison after transmission to receiving device 2, and the frequency of the first test code stream is lower than the frequency of the second test code stream. After determining these two time delays, transmitting device 1 sends normal communication data to receiving device 2 to establish normal communication. When transmitting normal communication data, transmitting device 1 carries a first timestamp, which is added before serial processing. After receiving the normal communication data, receiving device 2 records the second timestamp of the parallel data received. Then, it determines the difference between the two timestamps and subtracts the modulation delay in transmitting device 1 and the demodulation delay in receiving device 2 from this difference to obtain the actual transmission time of the normal communication data from transmitting device 1 to receiving device 2. Multiplying this actual transmission time by the transmission rate gives the distance between transmitting device 1 and receiving device 2. Here, the modulation delay in transmitting device 1 and the demodulation delay in receiving device 2 are both fixed values.

[0056] In one alternative approach, the transmitting device 1 and the receiving device 2 are connected by an optical fiber link. During modulation processing, the electrical signal is converted into an optical signal, and during demodulation processing, the optical signal is converted back into an electrical signal. The following text will use the example of an optical fiber link between the transmitting device 1 and the receiving device 2 for illustration.

[0057] Optionally, both transmitting device 1 and receiving device 2 are optical transport network (OTN) devices.

[0058] In an alternative way, such as Figure 3 As shown, the system architecture also includes a controller 3, which is connected to both the transmitting device 1 and the receiving device 2. The controller 3 can manage the transmitting device 1 and the receiving device 2.

[0059] Before starting the delay measurement, controller 3 sends a first measurement command to both transmitting device 1 and receiving device 2, and sends a communication connection establishment command to receiving device 2. Transmitting device 1 starts sending a first test code stream. After measuring and obtaining the serial processing delay, transmitting device 1 switches to sending a second test code stream. After receiving the modulated data corresponding to the second test code stream, receiving device 2 determines that it was sent by transmitting device 1 and detects that clock recovery and deserialization processing can be performed normally, indicating that receiving device 2 can normally receive the data sent by transmitting device 1. At this time, receiving device 2 and transmitting device 1 successfully establish a communication connection. Receiving device 2 uses the modulated data corresponding to the second test code stream to determine the deserialization processing delay and sends a delay measurement completion message to controller 3. Controller 3 receives the delay measurement completion message and sends a communication command to transmitting device 1 so that transmitting device 1 can send normal communication data to receiving device 2.

[0060] Subsequently, controller 3 can obtain a first timestamp from transmitting device 1 and a second timestamp from receiving device 2, and use the second timestamp and the first timestamp to calculate the distance between transmitting device 1 and receiving device 2. The calculation process is described above and will not be repeated here.

[0061] Optionally, after obtaining the delay in serial processing, transmitting device 1 sends a measurement completion message to controller 3, which may include the delay. Controller 3 receives the measurement completion message and sends a second measurement command to transmitting device 1, at which point transmitting device 1 switches to transmitting a second test stream.

[0062] Figure 4 A schematic diagram of the transmitting device is provided, such as Figure 4 As shown, the transmitting device 1 includes a processing module 11, a serializer 12, a phase comparator 13, and a modulator 14. The processing module 11 is electrically connected to the serializer 12, the serializer 12 is electrically connected to the phase comparator 13, and is also electrically connected to one end of the modulator 14. The other end of the modulator 14 is connected to the transmission medium. The processing module 11 is used to provide a first test code stream, a second test code stream, and normal communication data. The serializer 12 is used to perform serial processing. The phase comparator 13 is used to perform phase comparison and determine the delay of the serial processing (i.e., the serializer 12) based on the phase comparison result. The phase comparator 13 can be a phase comparison circuit. The modulator 14 is used to perform phase modulation processing on the serial data.

[0063] Figure 5 A schematic diagram of a receiving device is provided, such as... Figure 5As shown, the receiving device 2 includes a demodulator 21, a deserializer 22, and a target phase comparator 23. One end of the demodulator 21 is connected to the transmission medium, and the other end is electrically connected to the deserializer 22 and the target phase comparator 23. The deserializer 22 is also electrically connected to the target phase comparator 23. The demodulator 21 is used to demodulate the received data. The deserializer 22 is used to perform clock recovery processing and serial-to-parallel conversion processing on the demodulated data to obtain the target clock and parallel data. The target phase comparator 23 is used to perform phase comparison and determine the delay of the deserialization process (i.e., the deserializer 22) based on the phase comparison result. The target phase comparator 23 can be a phase comparison circuit.

[0064] Optionally, such as Figure 5 As shown, the receiving device 2 also includes a target processing module 24, which is connected to the deserializer 22. The target processing module 24 is used to establish a communication connection with the transmitting device 1 after determining that the correct data has been received from the transmitting device 1. The target processing module 24 also processes the parallel data output by the deserializer 22.

[0065] The following describes the process of measuring the delay of serializer 12, establishing a communication connection, and measuring the delay of deserializer 22.

[0066] 1. Measure the delay of serializer 12.

[0067] After the transmitting device 1 and receiving device 2 are deployed and put into operation, and after initializing the transmitting device 1 and receiving device 2, the delay of the serializer 12 and the delay of the deserializer 22 are measured.

[0068] When measuring the delay of the serializer 12, the processing module 11 outputs a first test code stream to the serializer 12. The processing module 11 uses a clock (which is the clock for parallel data, and therefore can be considered a parallel clock) to send the first test code stream to the serializer 12. The serializer 12 performs serial processing (i.e., parallel-to-serial conversion) on the first test code stream to obtain first serial data, and outputs the first serial data. During the transmission of the first serial data to the modulator 14, a driving unit is set at point B between the serializer 12 and the modulator 14, so that the first serial data transmitted between the serializer 12 and the modulator 14, in addition to being transmitted in the communication link, drives an additional channel of serial data to the phase comparator 13. The phase comparator 13 compares the second phase (the second phase being the phase of the first serializer data) with the first phase (the first phase being the phase used by the first test code stream) to obtain a phase comparison result, which is the phase difference. The delay corresponding to this phase difference is calculated, and this delay is determined as the delay of the serializer 12. Modulator 14 is a phase modulator. After modulating the received first serial data, modulator 14 obtains phase-modulated data and outputs the phase-modulated data to receiving device 2. Here, the phase of the parallel data is represented by the phase of the parallel clock, and the phase of the serial data output by serializer 12 is represented by the phase of the first serial data. The phase difference between the two is the relative delay of serializer 12.

[0069] After receiving the phase-modulated data, the demodulator 21 performs delayed coherent demodulation on the received data to obtain demodulated data, and outputs the demodulated data to the deserializer 22. A driving unit is provided between the demodulator 21 and the deserializer 22, so that the demodulated data transmitted between the demodulator 21 and the deserializer 22, in addition to being transmitted in the communication link, drives an additional path of demodulated data to the target phase comparator 23. Since the first test code stream is 0 and 1 balanced in the transmitting device 1, after phase modulation, it reaches the receiving device 2. After demodulation in the receiving device 2, the 0 and 1 are unbalanced, making it impossible for the deserializer 22 to process, thus preventing the establishment of a communication connection. Therefore, the first test code stream is used in the transmitting device 1 to determine the delay of the serializer 12.

[0070] 2. The receiving device 2 establishes a communication connection with the transmitting device 1 and determines the delay of the deserializer 22.

[0071] Before measuring the delay of the deserializer 22 in receiving device 2, transmitting device 1 establishes a communication connection with receiving device 2. One method is for transmitting device 1 to send connection establishment data to receiving device 2; this data can be called connection establishment data. After the connection establishment data passes through demodulator 21 in receiving device 2, it is equalized between 0s and 1s. Upon receiving the equalized 0s and 1s data from transmitting device 1, and confirming that it is the specified data, receiving device 2 indicates that it can normally receive data from transmitting device 1, thus confirming that the communication connection with transmitting device 1 has been successfully established. Then, transmitting device 1 switches to sending a second test stream to measure the delay of deserializer 22.

[0072] Alternatively, the second test code stream can also be used to indicate the establishment of a communication connection with transmitting device 1. In this case, when measuring the delay of deserializer 22 in receiving device 2, processing module 11 switches to outputting the second test code stream to serializer 12. Serializer 12 acquires a parallel clock, and processing module 11 uses the parallel clock to send the second test code stream to serializer 12. Serializer 12 performs serial processing on the second test code stream to obtain the second serial data, and outputs the second serial data. During the transmission of the second serial data to modulator 14, the second serial data is driven into two paths at point B: one path drives the phase comparator 13, and the other path drives the modulator 14. Due to the asymmetry between the physical layer chips of transmitting device 1 and receiving device 2, the second serial data is balanced in receiving device 2, but unbalanced in transmitting device 1, thus preventing phase comparator 13 from performing phase comparison. After phase modulation of the second serial data, modulator 14 obtains phase-modulated data and sends this phase-modulated data to receiving device 2.

[0073] After receiving the modulated data, the demodulator 21 performs delayed coherent demodulation on the received data to obtain demodulated data, and outputs the demodulated data to the deserializer 22. A driving unit is set at point D between the demodulator 21 and the deserializer 22. This driving unit causes the demodulated data transmitted between the demodulator 21 and the deserializer 22 to drive an additional path of demodulated data to the target phase comparator 23, in addition to the data transmitted in the communication link. Since the second test code stream is 0-1 equalized in the receiving device 2, the deserializer 22 can process the demodulated data. The deserializer 22 performs clock recovery processing on the demodulated data to obtain the target clock (this target clock is the clock for parallel data, therefore it can be considered a parallel clock), and performs serial-to-parallel conversion processing on the demodulated data to obtain parallel data. It then sends the target clock to the target phase comparator 23 and also outputs the parallel data and the target clock. The receiving device 2 determines that the parallel data is the specified parallel data and establishes a communication connection with the transmitting device 1. The target phase comparator 23 compares the phase of the target clock with the target phase to obtain a phase comparison result, which is the phase difference. The target phase is the phase of the demodulated data. The delay corresponding to this phase difference is calculated, and this delay is determined as the delay of the deserializer 22. Here, the purpose of outputting the target clock is that the target clock is the parallel clock of the parallel data, so that the parallel clock can be known when processing the parallel data later.

[0074] It should be noted that the driving units set at points B and D can be implemented in any way, and this application embodiment does not limit them. For example, the driving unit can be a driving circuit, etc. After sending normal communication data, the driving unit at point B can be turned off, and all the received data can be sent to the modulator 14. The driving unit at point D can be turned off, and all the received data can be sent to the deserializer 22.

[0075] In one alternative approach, the modulation scheme of modulator 14 can be DPSK modulation, or other modulation schemes that result in asymmetry between transmission and reception.

[0076] In one alternative approach, both the first and second test streams are stored in transmitting device 1, or both are generated by processing module 11, or the first test stream is either stored in transmitting device 1 or generated by processing module 11. Since transmitting device 1 and receiving device 2 perform data processing in reverse order, and the first test stream can measure serially processed data, differentially encoding the first test stream before transmitting it to receiving device 2 allows receiving device 2 to measure the deserialization delay. Therefore, the second test stream is obtained by differentially encoding the first test stream. When the sources of the first and second test streams are different, the structure of transmitting device 1 also differs, as explained below.

[0077] 1. Both the first test stream and the second test stream are stored in the transmitting device 1, or generated by the processing module 11.

[0078] like Figure 6 As shown, the processing module 11 includes a multiplexer (MUX) 111 and a stream providing unit 113. The multiplexer 111 is electrically connected to the stream providing unit 113 and is electrically connected to the serializer 12. The multiplexer 111 can also be called a multiplexer.

[0079] When measuring the delay of serializer 12, the bitstream providing unit 113 obtains a first test bitstream from the stored bitstream or generates a first test bitstream, and outputs the first test bitstream to multiplexer 111. Multiplexer 111 receives the first test bitstream and outputs the first test bitstream to serializer 12. When measuring the delay of deserializer 22, the bitstream providing unit 113 obtains a second test bitstream from the stored bitstream or generates a second test bitstream, and outputs the second test bitstream to multiplexer 111. Multiplexer 111 receives the second test bitstream and outputs the second test bitstream to serializer 12.

[0080] When sending normal communication data, the code stream providing unit 113 outputs the normal communication data to the multiplexer 111, so that the transmitting device 1 transmits the normal communication data to the receiving device 2. The normal communication data is generated or received by the code stream providing unit 113.

[0081] 2. The second test bitstream is obtained by differential encoding the first test bitstream.

[0082] Processing module 11 includes a multiplexer 111, a differential coding unit 112, and a bitstream providing unit 113. For example... Figure 7 As shown, the bitstream providing unit 113 is electrically connected to the differential coding unit 112, and the bitstream providing unit 113 is also electrically connected to the multiplexer 111, which is electrically connected to the serializer 12.

[0083] exist Figure 7 In the illustrated structure, when measuring the delay of the serializer 12, the bitstream providing unit 113 obtains a first test bitstream from the stored bitstream or generates a first test bitstream, outputs the first test bitstream to the differential coding unit 112, disables differential coding, transparently transmits the first test bitstream, and outputs the first test bitstream to the multiplexer 111. The multiplexer 111 receives the first test bitstream and outputs the first test bitstream to the serializer 12. When measuring the delay of the deserializer 22, the bitstream providing unit 113 obtains a first test bitstream from the stored bitstream or generates a first test bitstream, outputs the first test bitstream to the differential coding unit 112, enables differential coding, differentially codes the first test bitstream to obtain a second test bitstream, and outputs the second test bitstream to the multiplexer 111. The multiplexer 111 receives the second test bitstream and outputs the second test bitstream to the serializer 12.

[0084] When sending normal communication data, the normal communication data is communication data that has been differentially encoded. The code stream providing unit 113 outputs the normal communication data to the multiplexer 111. The multiplexer 111 receives the normal communication data and outputs the normal communication data to the serializer 12, so that the transmitting device 1 transmits the normal communication data to the receiving device 2.

[0085] Or, such as Figure 8 As shown, the stream providing unit 113 is electrically connected to the multiplexer 111, the multiplexer 111 is electrically connected to the differential coding unit 112, and the differential coding unit 112 is electrically connected to the serializer 12.

[0086] exist Figure 8 In the illustrated structure, when measuring the delay of the serializer 12, the bitstream providing unit 113 obtains a first test bitstream from the stored bitstream or generates a first test bitstream, and outputs the first test bitstream to the multiplexer 111. The multiplexer 111 outputs the first test bitstream to the differential coding unit 112, which disables differential coding, transparently transmits the first test bitstream, and outputs the first test bitstream to the serializer 12. When measuring the delay of the deserializer 22, the bitstream providing unit 113 obtains a first test bitstream from the stored bitstream or generates a first test bitstream, and outputs the first test bitstream to the multiplexer 111. The multiplexer 111 outputs the first test bitstream to the differential coding unit 112, which enables differential coding, differentially codes the first test bitstream to obtain a second test bitstream, and outputs the second test bitstream to the serializer 12.

[0087] When sending normal communication data, which is communication data that has already undergone differential coding, the code stream providing unit 113 outputs the normal communication data to the multiplexer 111. The multiplexer 111 receives the normal communication data and outputs it to the differential coding unit 112. The differential coding unit 112 disables differential coding and transmits the normal communication data transparently to the serializer 12. Alternatively, the normal communication data may be communication data that has not yet undergone differential coding. After receiving the normal communication data, the differential coding unit 112 enables differential coding, performs differential coding processing on the normal communication data, obtains differentially coded data, and outputs the differentially coded data to the serializer 12.

[0088] In one alternative approach, during the data transmission and reception process between transmitting device 1 and receiving device 2, a communication connection may be lost. After the communication connection is re-established, the delay of the deserializer 22 in receiving device 2 may be inaccurate, requiring recalibration of the delay of the deserializer 22. Transmitting device 1 first establishes a communication connection with receiving device 2, and then measures the delay of the deserializer 22 in receiving device 2. For example, transmitting device 1 resends a second test stream to receiving device 2, so that receiving device 2 first establishes a communication connection with transmitting device 1, and then determines the delay of the deserializer 22. The method for measuring the delay of the deserializer 22 is described above and will not be repeated here.

[0089] Optionally, the receiving device 2 detects that the data sent by the transmitting device 1 has been lost and / or the frame header has been lost, and determines that the communication connection needs to be re-established.

[0090] In one alternative approach, the first test bitstream is a low-frequency clock bitstream, the frequency of which must be matched with the phase comparator 13 to enable phase comparison. Optionally, the frequency of the low-frequency clock bitstream is related to the baud rate of the communication system and the parallelism of the serial processing. Assuming the data baud rate of transmitting device 1 is X Gbps, the first test bitstream, after passing through serializer 12, yields the first serial data, the frequency of which is X / 2N GHz, where N is an integer.

[0091] Optionally, N is equal to half the parallelism. For example, if the baud rate is 10Gbps and the parallelism of serial processing is 32, then the parallel clock frequency is 312.5MHz. In order to make the parallel clock frequency of the first test bitstream 312.5MHz, N=16, and 16 zeros and 16 ones constitute a 32-cycle clock.

[0092] Optionally, the first serial data is a periodic data stream consisting of N consecutive 0 bits and N consecutive 1 bits. For example, such as Figure 9As shown, it starts with N consecutive 1 bits, then N consecutive 0 bits, then another N consecutive 1 bits, and so on. Alternatively, it starts with N consecutive 0 bits, then N consecutive 1 bits, then another N consecutive 0 bits, and so on.

[0093] In one alternative approach, the second test bitstream is processed by serializer 12 to obtain second serial data. With the data baud rate of the transmitting device being X Gbps, the second serial data is a periodic data stream consisting of a continuous N-bit clock bitstream and a continuous N-bit DC level. The frequency of the N-bit clock bitstream is X / 2 GHz, and this N-bit clock bitstream is a 0-to-1 toggling clock bitstream comprising N / 2 high-frequency clocks. For example, as... Figure 10 As shown, N is an even number, and when the start bit of the second serial data is 1, the DC level is 0 for N consecutive bits. For example, as... Figure 11 As shown, N is an even number, and when the start bit of the second serial data is 0, the DC level of N consecutive bits is 1.

[0094] Optionally, N is equal to half the parallelism.

[0095] In one alternative approach, since the second test code stream is an unbalanced data stream of 0s and 1s on the transmitting device 1 side, in order for the second serial data (the second serial data is the code stream obtained by serial processing of the first test code stream) to be transmitted normally to the modulator 14, the link between the serializer 12 and the modulator 14 adopts direct current coupling (DC coupling). DC coupling refers to a coupling method that allows DC and AC components in the signal to pass through simultaneously.

[0096] In one alternative approach, transmitting device 1, as described above, possesses both the ability to transmit and receive data; that is, transmitting device 1 is a transceiver integrated device. The receiving component of transmitting device 1 is identical to the receiving component of receiving device 2, and will not be elaborated upon here. Similarly, receiving device 2 can also possess the ability to transmit data; that is, receiving device 2 is a transceiver integrated device.

[0097] This application also provides a method flow for determining the time delay in the embodiments, see [link to relevant documentation]. Figure 12 In steps 1201 to 1208, in Figure 12 In the process shown, the second test bitstream is used both to establish a communication connection with the transmitting device 1 and to determine the delay of the deserializer 22 in the receiving device 2.

[0098] Step 1201: Initialize the physical layer chips in transmitting device 1 and receiving device 2.

[0099] In this embodiment, after the sending device 1 and the receiving device 2 are deployed and put into operation, their physical layer chips undergo initialization processing, enabling the physical layer chips to perform data processing and transmission and reception.

[0100] Step 1202: Sending device 1 sends the first test bitstream.

[0101] In this embodiment, the controller 3 sends a first measurement command to the transmitting device 1, so that the transmitting device 1 sends a first test bitstream.

[0102] Step 1203: The transmitting device 1 uses the first test bitstream to determine the delay of the serializer 12.

[0103] In this embodiment, after determining the delay of the serializer 12, the transmitting device 1 sends a measurement completion message to the controller 3. Upon receiving the measurement completion message, the controller 3 sends a second measurement command to the transmitting device 1.

[0104] Step 1204: Sending device 1 sends the second test stream.

[0105] In this embodiment, the transmitting device 1 receives the second measurement command and switches to transmitting the second test code stream.

[0106] Step 1205: Receiving device 2 receives the serial data corresponding to the second test code stream and establishes a communication connection with transmitting device 1.

[0107] Step 1206: The receiving device 2 uses the serial data corresponding to the second test code stream to determine the delay of the deserializer 22.

[0108] In this embodiment, after determining the delay of the deserializer 22, the receiving device 2 sends a measurement completion message to the controller 3. Upon receiving the measurement completion message, the controller 3 sends a communication data transmission command to the sending device 1.

[0109] Step 1207: Sending device 1 sends normal communication data.

[0110] Step 1208: Determine whether the communication connection is disconnected. If the communication connection is disconnected, return to step 1204. If the communication connection is not disconnected, return to step 1208.

[0111] In this embodiment, the receiving device 2 determines whether the communication connection is broken based on the data received from the transmitting device 1. If broken, it sends a communication connection break message to the controller 3. The controller 3 receives the communication connection break message, sends a second measurement command to the transmitting device 1, and returns to step 1204.

[0112] The specific processes in steps 1201 to 1208 are described above and will not be repeated here.

[0113] In this embodiment of the application, a chip is also provided, which may be a PHY chip, including a processing module 11, a serializer 12 and a phase comparator 13.

[0114] In this embodiment of the application, a chip is also provided, which may be a PHY chip, including a deserializer 22, a target phase comparator 23 and a target processing module 24.

[0115] In this embodiment, when the physical layer chips for transmitting and receiving are asymmetrical, a first test code stream is used to determine the delay of the serializer 12 in transmitting device 1, and a second test code stream is used to determine the delay of the deserializer 22 in receiving device 2, enabling delay measurement for both receiving and transmitting. Furthermore, by first measuring the delay of the serializer 12 in transmitting device 1, then establishing a transmitting-receiving communication connection, and finally measuring the delay of the deserializer 22 in receiving device 2, only one communication connection is established. This ensures that the measurement processes performed by transmitting device 1 and receiving device 2 do not introduce a second communication connection establishment, thus guaranteeing the validity of the measured delay. Moreover, this delay measurement scheme eliminates uncertain delays in the communication link, allowing the communication system to be reused for picosecond (PS) level precise delay measurement and precise distance measurement.

[0116] In this application, the terms "first" and "second," etc., are used to distinguish identical or similar items that have substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first" and "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first test stream can be referred to as a second test stream, and similarly, a second test stream can be referred to as a first test stream. Both the first and second test streams can be test streams, and in some cases, they can be separate and distinct test streams.

[0117] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and such modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for determining time delay, characterized in that, Applied to a transmitting device, the method includes: The first test bitstream is processed serially to obtain the first serial data; Based on the phase comparison result between the phase of the first serial data and the first phase, the delay of the serial processing is determined, wherein the first phase is the phase of the clock used by the first test code stream; The second test code stream is subjected to the serial processing to obtain and output second serial data to the receiving device. The second test code stream is used to determine the deserialization processing delay in the receiving device after the sending device and the receiving device establish a communication connection. The frequency of the first test code stream is lower than the frequency of the second test code stream.

2. The method according to claim 1, characterized in that, The second test stream is also used to trigger the sending device to establish a communication connection with the receiving device.

3. The method according to claim 1 or 2, characterized in that, The data baud rate of the transmitting device is XGbps, and the frequency of the first serial data is X / 2NGHz, where N is an integer.

4. The method according to claim 3, characterized in that, The first serial data is a periodic data stream consisting of N consecutive 0 bits and N consecutive 1 bits.

5. The method according to any one of claims 1 to 4, characterized in that, The data baud rate of the transmitting device is XGbps, and the second serial data is a periodic data stream consisting of a continuous N-bit clock code stream and a continuous N-bit DC level. The frequency of the N-bit clock code stream is X / 2GHz, where N is an integer.

6. The method according to any one of claims 3 to 5, characterized in that, N is related to the degree of parallelism used in the serial processing.

7. The method according to any one of claims 1 to 6, characterized in that, The second test bitstream is obtained by differential encoding the first test bitstream.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: If the communication connection between the sending device and the receiving device is interrupted, the process of sending the second test stream to the receiving device will be returned.

9. The method according to any one of claims 1 to 8, characterized in that, The method further includes: After the transmitting device establishes a communication connection with the receiving device, it sends communication data to the receiving device. Based on the delay of the deserialization process and the delay of the serialization process, the transmission time of the communication data from the sending device to the receiving device is determined.

10. A method for determining time delay, characterized in that, Applied to a receiving device, the method includes: The device receives serial data sent by a transmitting device, wherein, before receiving the serial data, it receives data obtained by serial processing and modulation processing of a first test code stream, wherein the serial data is data obtained by serial processing and modulation processing of a second test code stream, and the frequency of the first test code stream is lower than the frequency of the second test code stream. The serial data is sequentially demodulated and deserialized to obtain and output the target clock. After establishing a communication connection with the transmitting device, the delay of the deserialization process is determined based on the phase comparison result between the phase of the target clock and the target phase, wherein the target phase is the phase of the data obtained by demodulating the serial data.

11. The method according to claim 10, characterized in that, The method further includes: A communication connection is established with the sending device based on the second test bitstream.

12. The method according to claim 10 or 11, characterized in that, The data baud rate of the transmitting device is XGbps, and the serial data is a periodic data stream consisting of a continuous N-bit clock code stream and a continuous N-bit DC level. The frequency of the N-bit clock code stream is X / 2GHz, where N is an integer.

13. A transmitting device, characterized in that, It includes a processing module (11), a serializer (12), a phase comparator (13), and a modulator (14); The processing module (11) is used to output a first test code stream and a second test code stream to the serializer (12), wherein the first test code stream is output before the second test code stream, the frequency of the first test code stream is lower than the frequency of the second test code stream, and the second test code stream is used to measure the delay of the deserialization process in the receiving device. The serializer (12) is used to perform serial processing on the received data to obtain and output serial data to the modulator (14); The phase comparator (13) is used to determine the delay of the serializer (12) based on the phase comparison result between the phase of the serial data corresponding to the first test code stream and the first phase, wherein the first phase is the phase of the clock used by the first test code stream; The modulator (14) is used to modulate the received serial data and then output it.

14. The transmitting device according to claim 13, characterized in that, The processing module (11) includes a multiplexer (111); The multiplexer (111) is used to receive the first test code stream and output the first test code stream to the serializer (12) when measuring the delay of the serializer (12); to receive the second test code stream and output the second test code stream to the serializer (12) when measuring the delay of the deserialization process; and to receive the communication data and output the communication data to the serializer (12) when sending communication data.

15. The transmitting device according to claim 13, characterized in that, The processing module (11) includes a differential coding unit (112); The differential coding unit (112) is used to acquire the first test code stream, transmit the first test code stream to the serializer (12) when measuring the delay of the serializer (12), perform differential coding on the first test code stream when measuring the delay of the deserialization process to obtain the second test code stream, and output the second test code stream to the serializer (12).

16. The transmitting device according to claim 15, characterized in that, The processing module (11) also includes a multiplexer (111); The multiplexer (111) is used to receive the first test code stream and output the first test code stream to the differential coding unit (112) when measuring the delay of the serializer (12) or the delay of the deserialization process; and to acquire the communication data and output the communication data to the differential coding unit (112) when the transmitting device transmits communication data. The differential coding unit (112) is further configured to, when the communication data is not differentially coded, differentially code the communication data and then output it to the serializer (12); or, The multiplexer (111) is used to receive data sent by the differential coding unit (112) when measuring the delay of the serializer (12) or the delay of the deserialization process, and to output the received data to the serializer (12). When the transmitting device sends communication data, the multiplexer receives the communication data and outputs the communication data to the serializer (12).

17. The transmitting device according to any one of claims 13 to 16, characterized in that, The data baud rate of the transmitting device is XGbps, and the frequency of the serial data corresponding to the first test code stream is X / 2NGHz, where N is an integer.

18. The transmitting device according to claim 17, characterized in that, The serial data corresponding to the first test code stream is a periodic data stream consisting of N consecutive 0 bits and N consecutive 1 bits.

19. The transmitting device according to any one of claims 13 to 18, characterized in that, The data baud rate of the transmitting device is XGbps, and the serial data corresponding to the second test code stream is a periodic data stream consisting of a continuous N-bit clock code stream and a continuous N-bit DC level. The frequency of the N-bit clock code stream is X / 2GHz, where N is an integer.

20. A receiving device, characterized in that, It includes a demodulator (21), a deserializer (22), and a target phase comparator (23); The demodulator (21) is used to demodulate the serial data from the transmitting device to obtain and output the demodulated data to the deserializer (22). The receiving device receives data obtained by serial processing and modulation of the first test code stream before receiving the serial data. The serial data is data obtained by serial processing and modulation of the second test code stream. The frequency of the first test code stream is lower than the frequency of the second test code stream. The deserializer (22) is used to deserialize the demodulated data to obtain and output the target clock. The target phase comparator (23) is used to determine the delay of the deserialization process based on the phase comparison result between the phase of the target clock and the target phase, wherein the target phase is the phase of the data after demodulation processing.

21. The receiving device according to claim 20, characterized in that, The receiving device further includes a target processing module (24); The target processing module (24) is used to establish a communication connection with the transmitting device when the serial data is correctly received.

22. A chip, characterized in that, The chip is used to perform the method according to any one of claims 1 to 9, or to perform the method according to any one of claims 10 to 12.

23. A communication system, characterized in that, The communication system includes a transmitting device and a receiving device; The transmitting device is the transmitting device as described in any one of claims 13 to 19; The receiving device is the receiving device as described in claim 20 or 21.

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