Multipath signal timestamp recording and transmitting device based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a multichannel signal timestamp recording and transmitting device based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of data acquisition and transmission. The device takes an FPGA (Field Programmable Gate Array) as a core processing unit, and integrates a gigabit Ethernet MAC (Media Access Control) module, a UDP (User Datagram Protocol) processing module, a control module and a timestamp acquisition and data encapsulation module; a 48-bit high-precision timestamp is generated through a 125MHz clock, independent detection and timestamp processing of rising edges / falling edges of eight paths of signals are achieved through a two-stage pipeline structure, timestamp real-time recording is completed through a first-stage pipeline, timestamp data load packaging is completed through a second-stage pipeline, and the recording period is 1 microsecond. Only when the change of the signal edge is detected, the packaged UDP data frame is sent through a GMII interface via a gigabit Ethernet; meanwhile, UDP command frame receiving and control word analyzing are supported, so that collection starting / stopping and edge detection type configuration are achieved. The system has the characteristics of strong real-time performance, high transmission rate and flexible configuration, and can be widely applied to scenes such as industrial automation, communication test, data acquisition of the Internet of Things and the like.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of data acquisition and network transmission, and particularly relates to a multi-channel signal timestamp recording and transmission device based on FPGA. BACKGROUND

[0002] In the fields of motion control, communication test and Internet of Things, high-precision time recording of edge changes of multi-channel external signals is often required, and data is transmitted to a back-end processing system in real time. Traditional signal timestamp acquisition devices are mostly implemented by using single-chip microcomputers or ARM processors, but the parallel processing capability of the processors is limited, and it is difficult to meet the real-time requirement of simultaneous detection of multi-channel signals, and the timestamp generation precision is low (usually above the microsecond level).

[0003] In the prior art, although some acquisition devices using FPGA can improve the parallel processing capability, the following defects exist: first, timestamp recording and data encapsulation are executed in series, which increases processing delay and makes it difficult to meet the short-period (such as 1 microsecond) acquisition requirement; second, the edge detection type configuration is fixed, and the rising edge / descending edge detection cannot be flexibly switched according to actual requirements; third, the data frame format used for transmitting timestamps is not reasonably designed, which leads to low data analysis efficiency and lacks standardized processing of control commands. In addition, the Ethernet transmission rate of traditional devices is mostly in the order of 100 Mbps, which is difficult to meet the high-speed transmission requirement of a large amount of high-precision timestamp data.

[0004] Therefore, there is an urgent need for a multi-channel signal timestamp acquisition and transmission device with high precision, high real-time performance, flexible configuration and high-speed transmission capability, and in particular, it is necessary to reduce the delay by optimizing the internal processing architecture to solve the problems of the prior art. SUMMARY

[0005] The application aims to provide a multi-channel signal timestamp recording and transmission device based on FPGA, which optimizes the timestamp processing flow through a two-stage pipeline structure, solves the problems of poor real-time performance, high processing delay, insufficient precision, inflexible configuration and low transmission rate of existing devices, and realizes high-precision time recording and efficient transmission of edge changes of multi-channel signals.

[0006] The technical scheme adopted by the application to achieve the above-mentioned purpose is as follows: a multi-channel signal timestamp recording and transmission device based on FPGA, comprising:

[0007] a phase-locked loop module, configured to generate an internal working clock of the FPGA according to a clock input, and provide the clock to a gigabit Ethernet MAC module, a control module, a UDP protocol processing module and a timestamp acquisition and data encapsulation module;

[0008] Gigabit Ethernet MAC module, for realizing data receiving and sending by connecting with external PHY chip, transmitting received MAC data load to the receiving unit of the UDP protocol processing module for processing, connecting with the sending unit of the UDP protocol processing module to obtain MAC data to be sent and sending to the external PHY chip;

[0009] The control module is configured to receive a control command of the UDP protocol processing module containing a sampling start command and edge detection configuration information, and generate an enable signal for enabling the timestamp acquisition and data encapsulation module.

[0010] The UDP protocol processing module is configured to receive MAC data load of the Gigabit Ethernet MAC module, process Ethernet data packets of UDP and ARP types, and send a control command to the control module for transmission, receive a UDP data packet containing timestamp information provided by the data encapsulation submodule of the timestamp acquisition and data encapsulation module, and complete UDP data frame encapsulation.

[0011] The timestamp acquisition and data encapsulation module is configured to complete timestamp acquisition and data encapsulation to ensure parallel execution of timestamp recording and data encapsulation.

[0012] The UDP protocol processing module comprises:

[0013] The receiving unit is configured to receive MAC data load transmitted by the Gigabit Ethernet MAC module, analyze IP header and UDP header, extract control commands in the UDP load, and transmit the control commands to the control module; for ARP data packets, the received ARP protocol load is sent to the protocol sequencer through an ARP receiving data signal line.

[0014] The protocol sequencer module is configured to process ARP data packets and complete connection establishment with the upper computer.

[0015] The sending unit is configured to receive ARP data packets of the protocol sequencer module, receive UDP data packets provided by the data encapsulation submodule of the timestamp acquisition and data encapsulation module, add UDP header, IP header and MAC header, complete UDP data frame encapsulation, and send the encapsulated data as MAC data to be sent to the Gigabit Ethernet MAC module.

[0016] The timestamp acquisition and data encapsulation module comprises:

[0017] The timestamp recording submodule is configured as a first-stage pipeline, for performing edge detection on an input signal and recording a timestamp, receiving a timestamp recording enable signal of the control module, and sending timestamp information to the data encapsulation submodule.

[0018] The data encapsulation sub-module, as a secondary pipeline, completes data encapsulation of 8-way timestamp information, and transmits the UDP data packet containing the timestamp information to the UDP protocol processing module.

[0019] The timestamp recording sub-module comprises:

[0020] The edge detection unit starts to work after receiving the enable signal generated by the control module, is used for secondary flip-flop synchronization de-bouncing of 8-way input signals, detects specified edges through an XOR gate, each signal is independently detected, and the detection result is output to the recording control unit.

[0021] The recording control unit starts to work after receiving the enable signal generated by the control module, is used for immediately latching the current 48-bit count value of the timer as a timestamp when the target edge is detected in the input signal corresponding thereto, simultaneously enabling the timestamp valid indication signal of the input signal, and sending the timestamp information containing the timestamp and the timestamp valid indication signal to the input end of the primary pipeline register.

[0022] The primary pipeline register is composed of 8 groups of 49-bit registers, each group of registers corresponding to 1-way input signal, is used for updating the output once every 1 microsecond, and simultaneously pushing the timestamp information output by the recording control unit into the secondary pipeline, and clearing the timestamp information so as to record new timestamp information in the next 1 microsecond interval.

[0023] The data encapsulation sub-module comprises:

[0024] The state control unit starts to work after receiving the enable signal generated by the control module, adopts a state machine design, and contains an idle state, a detection state, an encapsulation state and an output state; in the idle state, when the primary pipeline register is updated, the detection state is jumped into; in the detection state, whether the 8 groups of timestamp information contain valid timestamps is detected, that is, 8 groups of timestamp valid indication bits are not 0 at the same time, if the valid timestamps are contained, the encapsulation state is jumped into, otherwise the idle state is returned; in the encapsulation state, the frame format encapsulation unit completes conversion of the timestamp information to the UDP data load, and then the state jumps into the output state; the data output unit outputs the UDP load to the UDP protocol processing module, and after the UDP protocol processing module receives the data, the state returns to the idle state.

[0025] The frame format encapsulation unit is used for triggering encapsulation logic when the state machine of the state control unit is in the encapsulation state, assembling the UDP data frame load according to a preset format, and forming the UDP data packet containing the timestamp information.

[0026] The data output control unit is configured to transmit a UDP data packet containing timestamp information to the UDP protocol processing module when the state machine of the state control unit is in an output state, and release the corresponding interface signal after the output data is received.

[0027] A FPGA-based multi-channel signal timestamp recording and transmission method, comprising the following steps:

[0028] The phase-locked loop module generates an internal working clock of the FPGA according to a clock input, and provides the clock to a gigabit Ethernet MAC module, a control module, a UDP protocol processing module, and a timestamp acquisition and data encapsulation module.

[0029] The gigabit Ethernet MAC module realizes data transmission and reception through connection with an external PHY chip, delivers the received MAC data load to a receiving unit of the UDP protocol processing module for processing, and is connected with a sending unit of the UDP protocol processing module to obtain MAC data to be sent and send the MAC data to the external PHY chip.

[0030] The control module receives a control command containing a sampling start command and edge detection configuration information from the UDP protocol processing module, and generates an enable signal for enabling a data encapsulation submodule and a timestamp recording submodule of the timestamp acquisition and data encapsulation module.

[0031] The UDP protocol processing module receives the MAC data load of the gigabit Ethernet MAC module, processes UDP and ARP type Ethernet data packets, and sends a control command to the control module for transmission.

[0032] The timestamp acquisition and data encapsulation module is configured to complete timestamp acquisition and data encapsulation to ensure parallel execution of timestamp recording and data encapsulation.

[0033] The UDP protocol processing module is configured to perform the following steps:

[0034] The receiving unit receives the MAC data load transmitted by the gigabit Ethernet MAC module, analyzes the IP header and the UDP header, extracts the control command in the UDP load, and transmits the control command to the control module; for an ARP data packet, the received ARP protocol load is sent to the protocol sequence machine through an ARP receiving data signal line.

[0035] The protocol sequence machine module processes the ARP data packet and establishes connection with the upper computer.

[0036] The sending unit receives an ARP data packet of the protocol sequence machine module, receives a UDP data packet provided by a data encapsulation submodule of the time stamp acquisition and data encapsulation module, adds a UDP header, an IP header and a MAC header, completes encapsulation of a UDP data frame, and sends the UDP data frame as a MAC data to be sent to the gigabit Ethernet MAC module.

[0037] The time stamp acquisition and data encapsulation module is configured to perform the following steps:

[0038] The time stamp recording submodule is a first-stage pipeline, performs edge detection on the input signal and records a time stamp, receives a time stamp recording enable of the receiving control module, and sends time stamp information to the data encapsulation submodule.

[0039] The data encapsulation submodule is a second-stage pipeline, completes data encapsulation of 8-way time stamp information, and transmits a UDP data packet containing the time stamp information to the UDP protocol processing module.

[0040] The time stamp recording submodule is configured to perform the following steps:

[0041] The edge detection unit starts working after receiving an enable signal generated by the control module, performs second-stage flip-flop synchronization dithering on 8-way input signals, detects a specified edge through an XOR gate, and outputs a detection result to the recording control unit.

[0042] The recording control unit starts working after receiving an enable signal generated by the control module, latches a current 48-bit count value of a timer as a time stamp when a target edge of the input signal corresponding to the recording control unit is detected, enables a time stamp valid indication signal of the input signal, and sends time stamp information containing the time stamp and the time stamp valid indication signal to an input end of the first-stage pipeline register.

[0043] The first-stage pipeline register is composed of 8 groups of 49-bit registers, each group of registers corresponding to 1-way input signal; the output is updated every 1 microsecond, and the time stamp information is cleared at the same time as the time stamp information output by the recording control unit is pushed into the second-stage pipeline, so as to record new time stamp information in the next 1 microsecond interval.

[0044] The data encapsulation submodule is configured to perform the following steps:

[0045] The state control unit starts to work after receiving the enable signal generated by the control module, adopts a state machine design, and includes an idle state, a detection state, a packaging state and an output state; in the idle state, when the first flow register is updated, the detection state is entered; in the detection state, whether the 8 groups of timestamp information contain valid timestamps is detected, that is, the 8 groups of timestamp valid indication bits are not 0 at the same time, if the valid timestamp is contained, the packaging state is entered, otherwise the idle state is returned; in the packaging state, the frame format packaging unit completes the conversion of the timestamp information to the UDP data load, and then the state jumps to the output state; the data output unit outputs the UDP load to the UDP protocol processing module, and after the data is received by the UDP protocol processing module, the state returns to the idle state;

[0046] The frame format packaging unit triggers the packaging logic when the state machine of the state control unit is in the packaging state, assembles the UDP data frame load according to the preset format, and forms the UDP data packet containing the timestamp information;

[0047] The data output control unit transmits the UDP data packet containing the timestamp information to the UDP protocol processing module when the state machine of the state control unit is in the output state, and releases the corresponding interface signal after the output data is received.

[0048] Compared with the prior art, the beneficial effects of the present application are as follows:

[0049] 1. High precision and high real-time performance: 125MHz clock generates 48-bit timestamp, resolution reaches 8ns; two-stage flow structure makes timestamp recording and data packaging execute in parallel, eliminates serial processing delay, 1 microsecond acquisition cycle ensures that the edge change is recorded without omission, and the FPGA parallel processing architecture meets the simultaneous detection demand of multiple signals;

[0050] 2. High transmission efficiency: only when the signal change is detected, the data is sent, reducing the network bandwidth occupation; the combination of gigabit Ethernet and UDP protocol makes the transmission rate reach 1000Mbps, meeting the demand of high-speed real-time transmission of a large amount of data;

[0051] 3. Flexible configuration: supporting remote configuration of edge detection type and start-stop control through UDP command frame, adapting to the signal acquisition demand of different application scenarios;

[0052] 4. High integration: all functional modules are integrated in a single FPGA, small size, low power consumption, and convenient for embedded system integration;

[0053] 5. Non-blocking processing: the first flow register design ensures that the two-stage flow packaging process does not affect the real-time recording of the first flow, avoiding data loss or delay. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a whole architecture block diagram of the device of the present application;

[0055] Figure 2 is a two-stage pipeline structure block diagram of the timestamp acquisition and data encapsulation module of the present application;

[0056] Figure 3 is a load format schematic diagram of the UDP timestamp data frame and command control frame;

[0057] Figure 4 is a device working state flow chart. DETAILED DESCRIPTION

[0058] The present application will be further described in detail below in combination with the drawings and embodiments.

[0059] The present application discloses a multi-channel signal timestamp recording and transmission device based on FPGA, which takes FPGA as a core processing unit, integrates a gigabit Ethernet MAC module, a UDP protocol processing module, a control module and a timestamp acquisition and data encapsulation module; generates a 48-bit high-precision timestamp through a 125MHz clock, and realizes independent detection and timestamp processing of rising edges and falling edges of 8 channels through a two-stage pipeline structure; a first-stage pipeline completes real-time recording of the timestamp, and a second-stage pipeline completes timestamp data load encapsulation; the recording period is 1 microsecond, and only when a signal edge change is detected, the encapsulated UDP data frame is sent through a GMII interface through a gigabit Ethernet; and the device also supports receiving a UDP command frame, and analyzes a control word to realize acquisition start / stop and edge detection type configuration. The present application has the characteristics of strong real-time performance, high transmission rate and flexible configuration, and can be widely applied to industrial automation, communication testing, Internet of Things data acquisition and the like.

[0060] The present application adopts the following technical solutions:

[0061] 1. Whole architecture design: taking FPGA as a core, integrating four functional modules, and realizing high-speed transmission of data and control signals through internal bus interconnection; and externally connecting a PHY chip through a GMII interface and accessing a gigabit Ethernet.

[0062] 2. Timestamp generation and acquisition (two-stage pipeline architecture):

[0063] Timestamp generation: generating a 48-bit timestamp through a 125MHz clock source, and the time resolution is 8ns;

[0064] First-stage pipeline: taking 1 microsecond as an acquisition period, detecting specified edges of 8 channels in parallel, recording timestamps and channel identifiers in real time, and buffering to a first-stage pipeline register;

[0065] Secondary flow water: parallel with the first flow water, read the data in the first flow water register and encapsulate as data block, pass to UDP protocol processing module, avoid delay caused by serial processing.

[0066] 3. UDP protocol processing: receive and analyze command data frame, encapsulate and send time stamp load data frame; customize UDP data load format, ensure data integrity and analysis efficiency; control command frame and data frame use different ports to distinguish, realize parallel transmission of command and data.

[0067] 4. Control logic design: control module receives command control word, dynamically configures edge detection type, controls acquisition start and stop, realizes flexible adaptation of device.

[0068] (I) Hardware composition of device

[0069] The overall architecture of the device is shown in Figure 1 The core is FPGA chip (such as Xilinx Artix-7 series), and only PHY chip (such as RTL8211EG), clock source (25MHz crystal), power module and 8-way signal input interface need to be configured externally. FPGA and PHY chip are connected through GMII interface to realize Ethernet physical layer communication; 8-way input signal can be connected to FPGA I / O pin through level conversion circuit, and 25Mhz clock source is multiplied to 125MHz clock as reference clock of the device after phase-locked loop in FPGA.

[0070] (II) Internal modules of FPGA

[0071] Phase-locked loop

[0072] The function of phase-locked loop module is to generate working clock of each module in FPGA. The clock input is provided by external 25Mhz crystal through clock data signal CLKIN, and 125MHz clock is generated and connected to Gigabit Ethernet MAC module, control module, UDP protocol processing module and its internal sub-modules, and timestamp acquisition and data encapsulation module and its sub-modules.

[0073] Gigabit Ethernet MAC module

[0074] Gigabit Ethernet MAC module is realized by built-in Ethernet MAC IP core of FPGA, configured as GMII interface mode. The function of the module is to receive and send Ethernet data packet, specifically to add preamble, frame start symbol and CRC check code to MAC frame output by UDP protocol processing module, and send it to PHY chip through GMII interface; at the same time, receive Ethernet frame transmitted by PHY chip, and transmit it to UDP protocol processing module after stripping preamble and CRC.

[0075] The clock of the Gigabit Ethernet MAC module is provided by the clk signal output by the phase-locked loop module. The module is connected with the external PHY chip through the GMII interface to transmit and receive data. The MAC data receiving signal line is connected with the receiving unit of the UDP protocol processing module to transmit the received MAC data load to the receiving unit for processing. The MAC data sending signal line is connected with the sending unit of the UDP protocol processing module to obtain the MAC data to be sent.

[0076] UDP protocol processing module

[0077] The function of the UDP protocol processing module is to process the UDP and ARP type Ethernet data packets, which is composed of a receiving unit, a protocol sequencer module and a sending unit.

[0078] The function of the receiving unit is to unpack the Ethernet data packet, specifically to receive the Ethernet frame transmitted by the Gigabit Ethernet MAC module, analyze the IP header and the UDP header, extract the control command in the UDP load, and transmit it to the control module.

[0079] The connection relationship of the receiving unit: for the ARP data packet, the received ARP protocol load is sent to the protocol sequencer through the ARP receiving data signal line; for the UDP data packet, the control signal line (including the sampling start command and the edge detection configuration information) is transmitted to the control module.

[0080] The function of the protocol sequencer module is to process the ARP data packet and complete the connection establishment with the upper computer.

[0081] The module input is provided by the ARP receiving data signal line of the receiving unit, the module output is connected with the sending unit through the ARP sending data signal line, and the module output is connected with the control module through the connection establishment indication signal line.

[0082] The function of the sending unit is to pack the Ethernet data packet, specifically to receive the data block output by the timestamp collection and data packing module, add the UDP header (source port, destination port, length, checksum), IP header and MAC header, and complete the UDP data frame packing.

[0083] The connection relationship of the sending unit: for the ARP data packet, it is received by the ARP receiving data signal line of the protocol sequencer module; for the UDP data packet, it is provided by the UDP sending data line (including the received timestamp information) of the data packing sub-module of the timestamp collection and data packing module.

[0084] Control module

[0085] The function of the control module is to realize overall control, and the state machine design is adopted, including initialization state, standby state and collection state. The initialization state is that after the device is powered on, the initial default parameters of each module are configured (such as default MAC address and IP address, UDP default port, rising edge detection type, and stop collection), and the first-level flow register is initialized to empty state. The standby state is waiting for the UDP control command, and after receiving the “start collection” command, it is switched to the collection state, and the detection type of the 8-way signal is updated according to the “edge type” configured in the command. The collection state controls the timestamp collection module to start the second-level flow work, and returns to the standby state after receiving the “stop collection” command, and clears the first-level flow register.

[0086] The control module input is provided by the UDP control signal line (including sampling start command and edge detection configuration information) of the receiving unit of the UDP protocol processing module, the module generates data encapsulation enable signal line to enable the timestamp collection and data encapsulation module, and the module generates timestamp record enable and edge detection type configuration signal line and is connected with the timestamp record submodule of the timestamp collection and data encapsulation module.

[0087] Timestamp collection and data encapsulation module

[0088] The function of the timestamp collection and data encapsulation module is to complete timestamp collection and data encapsulation, and a two-level flow architecture is adopted, as shown in the figure, to ensure the parallel execution of timestamp recording and data encapsulation. The timestamp collection and data encapsulation module comprises a data encapsulation submodule, a timer submodule and a timestamp recording submodule. Figure 2

[0089] The function of the timer submodule is to provide a free count value of the timestamp time base, and the count value is connected with the timestamp recording submodule through a timing count value signal line. The timer submodule is driven by a 125MHz clock and a 48-bit counter, and the timing accuracy is 8ns, which can continuously time for about 625 hours (26 days), and provides a real-time time base for the first-level flow.

[0090] The function of the timestamp recording submodule (first-level flow) is to detect the edge of the input signal and record the timestamp, which is composed of eight parallel edge detection and recording control units and a first-level flow register. The module is composed of an edge detection unit, a recording control unit and a first-level flow register.

[0091] The edge detection unit: the eight-way input signal is synchronized and de-bounced by a two-level flip-flop, and the specified edge (rising edge: the current signal is 1 and the previous period is 0; falling edge: the current signal is 0 and the previous period is 1) is detected by an XOR gate, and each signal is detected independently, and the detection result is output to the recording control unit.

[0092] ​Record control unit: When the target edge of the corresponding input signal is detected, the current 48-bit count value of the timer is immediately latched as a time stamp, while enabling the time stamp valid indication signal of the input signal, and sending the time stamp and time stamp valid indication signal to the first stage pipeline register input terminal.

[0093] First stage pipeline register: composed of 8 groups of 49-bit registers (48-bit time stamp + 1-bit time stamp valid indication bit), each group of registers corresponds to 1 input signal. The register working clock is 125Mhz, and the output is updated every 1 microsecond (125 working periods). At the same time, the time stamp information output by the record control unit is pushed into the second stage pipeline, and the information is cleared to record new time stamp information in the next 1 microsecond interval.

[0094] Connection of time stamp recording sub-module: enable control is provided by the time stamp recording enable and edge detection type configuration signal line of the control module; module input is connected to the outside world by 8 input signals 0..7; the module is connected to the data packaging sub-module through the time stamp data signal line (transferring 8-way time stamp information corresponding to input signals 0..7).

[0095] The function of the data packaging sub-module (second stage pipeline) is to complete the data packaging function of 8-way time stamp information. The data packaging sub-module is composed of a state control unit, a frame format packaging unit and a data output control unit.

[0096] State control unit: designed with a state machine, including idle state, detection state, packaging state and output state; in idle state, the data packaging sub-module waits for the first stage pipeline register to update, and when the first stage pipeline register updates, it jumps into detection state; in detection state, the data packaging sub-module detects whether 8 groups of time stamp information contain valid time stamps, i.e. 8 groups of time stamp valid indication bits are not all 0, if they contain valid time stamps, it jumps into packaging state, otherwise it returns to idle state; in packaging state, the frame format packaging unit completes the conversion of time stamp information to UDP data load, and then the state jumps into output state; the data output unit outputs the UDP load to the UDP protocol processing module, and after the UDP protocol processing module receives the data, the state returns to idle state.

[0097] Frame format packaging unit: when the state machine of the state control unit is in packaging state, trigger the packaging logic to assemble the UDP data frame load according to the preset format.

[0098] Data output control unit: when the state machine of the state control unit is in output state, transmit the complete data block to the UDP protocol processing module, and after the output data is received, release the corresponding interface signal.

[0099] The data encapsulation module is enabled by a data encapsulation enable signal line of the control module, the module input is provided by a timestamp data signal line (transferring 8-way timestamp information corresponding to input signals 0..7) of the timestamp recording sub-module, and the module output is a UDP sending data line (containing received collected timestamp information) to a sending unit of the UDP protocol processing module.

[0100] (Three) UDP data load format definition

[0101] As shown in Figure 3 , the load formats of the UDP timestamp data frame and the command control frame are shown in Table 1 and Table 2, respectively.

[0102] Table 1. Timestamp data frame load format

[0103]

[0104] Table 2. Control command frame load format

[0105]

[0106] (Four) Device workflow

[0107] 1. Initialization stage: after the device is powered on, each module in the FPGA completes initialization, the control module sets default parameters (8-way signals are all rising edge detection, and the state is initialization); the UDP protocol processing module configures the UDP source port 5000, the destination port 5001, the IP address 192.168.2.10, and the MAC address 10:22:33:44:55:66; the timestamp acquisition and data encapsulation module clears the first-stage pipeline register; the gigabit Ethernet MAC module negotiates with the PHY chip to establish a gigabit Ethernet connection. As shown in Figure 4 .

[0108] 2. Command receiving and processing stage: the UDP protocol processing module establishes a connection with the upper computer through the ARP protocol, after the connection is established, it continuously listens to the specified port, receives the UDP control command frame, and analyzes the control word in the load; if the control word is the "start" operation, the control module updates the edge detection configuration of the 8-way signal, and switches to the acquisition state, starts the timestamp acquisition and data encapsulation module, and the second-stage pipeline starts parallel work; if the control word is the "stop" command, the control module switches to the standby state, stops the second-stage pipeline work, and clears the first-stage pipeline register;

[0109] 3. Time stamp collection and data sending stage (two-stage pipeline parallel execution): in the first stage pipeline, the edge detection unit of the time stamp recording submodule continuously detects the 8-way input signal, and when the target edge is detected, the relevant time stamp is latched by the recording control unit and the corresponding time stamp valid indication signal is enabled. When the pipeline is updated, all information is written into the first stage pipeline register; in the second stage pipeline, the data packaging submodule detects the valid time stamp information, which is assembled into a UDP data frame payload by the frame format packaging unit, and sent to the UDP protocol processing module through the data output control unit. After being packaged into a UDP data frame by the UDP protocol processing module, it is sent out through the MAC module through the gigabit Ethernet.

[0110] 4. Stop stage: after receiving the "stop" command, the control module stops the edge detection of the first stage pipeline and the packaging output of the second stage pipeline, and the device returns to the standby state, waiting for the next start command.

Claims

1. A multi-channel signal timestamp recording and transmission device based on FPGA, characterized in that, include: The phase-locked loop module is used to generate the internal working clock of the FPGA based on the clock input, and provides it to the gigabit Ethernet MAC module, control module, UDP protocol processing module, and timestamp acquisition and data encapsulation module. The Gigabit Ethernet MAC module is used to send and receive data through connection with an external PHY chip. It passes the received MAC data payload to the receiving unit of the UDP protocol processing module for processing, and obtains the MAC data to be sent through connection with the sending unit of the UDP protocol processing module, and sends it to the external PHY chip. The control module receives control commands from the UDP protocol processing module, including sampling start commands and edge detection configuration information, and generates enable signals to enable the data encapsulation submodule and timestamp recording submodule of the timestamp acquisition and data encapsulation module. The UDP protocol processing module is used to receive the MAC data payload from the Gigabit Ethernet MAC module, process Ethernet packets of UDP and ARP types, and send control commands to the control module. It also receives UDP packets containing timestamp information from the data encapsulation submodule of the timestamp acquisition and data encapsulation module and completes UDP data frame encapsulation. The timestamp acquisition and data encapsulation module is used to complete timestamp acquisition and data encapsulation to ensure the parallel execution of timestamp recording and data encapsulation.

2. The FPGA-based multi-channel signal timestamp recording and transmission device according to claim 1, characterized in that, The UDP protocol processing module includes: The receiving unit is used to receive MAC data payloads transmitted by the Gigabit Ethernet MAC module, parse the IP header and UDP header, extract control commands from the UDP payload, and transmit them to the control module; for ARP packets, it sends the received ARP protocol payload to the protocol sequencer through the ARP receive data signal line. The protocol sequencer module is used to process ARP packets and establish a connection with the host computer. The sending unit is used to receive ARP packets from the protocol sequencer module; receive UDP packets provided by the data encapsulation submodule of the timestamp acquisition and data encapsulation module, add UDP headers, IP headers and MAC headers, complete UDP data frame encapsulation, and send it as MAC data to be sent to the Gigabit Ethernet MAC module.

3. The FPGA-based multi-channel signal timestamp recording and transmission device according to claim 1, characterized in that, The timestamp acquisition and data encapsulation module includes: The timestamp recording submodule, as a first-level pipeline, is used to perform edge detection on the input signal and record the timestamp; it receives the timestamp recording enable from the control module and sends the timestamp information to the data encapsulation submodule. The data encapsulation submodule, as a secondary pipeline, completes the data encapsulation function for 8-channel timestamp information and transmits the UDP data packets containing timestamp information to the UDP protocol processing module.

4. The FPGA-based multi-channel signal timestamp recording and transmission device according to claim 1, characterized in that, The timestamp recording submodule includes: The edge detection unit starts working after receiving the enable signal generated by the control module. It is used to perform two-stage flip-flop synchronous debouncing on the eight input signals. It detects the specified edge through an XOR gate. Each signal is detected independently, and the detection result is output to the recording control unit. The record control unit starts working after receiving the enable signal generated by the control module. When the corresponding input signal detects the target edge, it immediately latches the current 48-bit count value of the timer as a timestamp, enables the timestamp validity indicator signal of the input signal, and sends the timestamp information containing the timestamp and the timestamp validity indicator signal to the input terminal of the first-level pipeline register. The first-level pipeline register consists of 8 groups of 49-bit registers, each group corresponding to one input signal; it is used to update the output every 1 microsecond. While pushing the timestamp information of the recording control unit output into the second-level pipeline, it also clears the timestamp information so that new timestamp information can be recorded in the next 1 microsecond interval.

5. The FPGA-based multi-channel signal timestamp recording and transmission device according to claim 1, characterized in that, The data encapsulation submodule includes: The state control unit starts working after receiving the enable signal generated by the control module. It adopts a state machine design and includes an idle state, a detection state, an encapsulation state, and an output state. In the idle state, when the first-level pipeline register is updated, it jumps to the detection state. In the detection state, it checks whether the eight sets of timestamp information contain a valid timestamp, i.e., the valid timestamp indicator bits of the eight sets are not all 0 at the same time. If a valid timestamp is contained, it jumps to the encapsulation state; otherwise, it returns to the idle state. In the encapsulation state, the frame format encapsulation unit completes the conversion of timestamp information into UDP data payload, and then the state jumps to the output state. The data output unit outputs the UDP payload to the UDP protocol processing module. After the UDP protocol processing module receives the data, the state returns to the idle state. The frame format encapsulation unit is used to trigger encapsulation logic when the state machine of the state control unit is in the encapsulation state, and to assemble the UDP data frame payload according to the preset format to form a UDP data packet containing timestamp information. The data output control unit is used to transmit UDP data packets containing timestamp information to the UDP protocol processing module when the state machine of the state control unit is in the output state. After the output data is received, the corresponding interface signal is released.

6. A method for recording and transmitting multi-channel signal timestamps based on FPGA, characterized in that, Includes the following steps: The phase-locked loop module generates the FPGA's internal operating clock based on the clock input, which is then provided to the Gigabit Ethernet MAC module, control module, UDP protocol processing module, and timestamp acquisition and data encapsulation module. The Gigabit Ethernet MAC module transmits and receives data by connecting to an external PHY chip. It passes the received MAC data payload to the receiving unit of the UDP protocol processing module for processing, and obtains the MAC data to be sent by connecting to the sending unit of the UDP protocol processing module, and sends it to the external PHY chip. The control module receives control commands from the UDP protocol processing module, including sampling start commands and edge detection configuration information, and generates enable signals to enable the data encapsulation submodule and timestamp recording submodule of the timestamp acquisition and data encapsulation module. The UDP protocol processing module receives the MAC data payload from the gigabit Ethernet MAC module, processes Ethernet packets of UDP and ARP types, and sends control commands to the control module. It also receives UDP packets containing timestamp information from the data encapsulation submodule of the timestamp acquisition and data encapsulation module and completes UDP data frame encapsulation. The timestamp acquisition and data encapsulation module is used to complete timestamp acquisition and data encapsulation to ensure the parallel execution of timestamp recording and data encapsulation.

7. The FPGA-based multi-channel signal timestamp recording and transmission method according to claim 6, characterized in that, The UDP protocol processing module is configured to perform the following steps: The receiving unit receives the MAC data payload transmitted by the Gigabit Ethernet MAC module, parses the IP header and UDP header, extracts the control commands in the UDP payload, and transmits them to the control module; for ARP packets, it sends the received ARP protocol payload to the protocol sequencer through the ARP receive data signal line. The protocol sequencer module processes ARP packets and establishes a connection with the host computer. The sending unit receives ARP packets from the protocol sequencer module; it also receives UDP packets from the data encapsulation submodule of the timestamp acquisition and data encapsulation module, adds UDP headers, IP headers, and MAC headers, completes UDP data frame encapsulation, and sends it as MAC data to the Gigabit Ethernet MAC module.

8. The FPGA-based multi-channel signal timestamp recording and transmission method according to claim 6, characterized in that, The timestamp acquisition and data encapsulation module is configured to perform the following steps: The timestamp recording submodule acts as a first-level pipeline, performing edge detection on the input signal and recording the timestamp; it receives the timestamp recording enable from the control module and sends the timestamp information to the data encapsulation submodule. The data encapsulation submodule, as a secondary pipeline, completes the data encapsulation function for 8-channel timestamp information and transmits the UDP data packets containing timestamp information to the UDP protocol processing module.

9. The FPGA-based multi-channel signal timestamp recording and transmission method according to claim 6, characterized in that, The timestamp recording submodule is configured to perform the following steps: The edge detection unit starts working after receiving the enable signal generated by the control module. It performs two-stage trigger synchronous debouncing on the eight input signals, detects the specified edge through an XOR gate, detects each signal independently, and outputs the detection result to the recording control unit. The record control unit starts working after receiving the enable signal generated by the control module. When the corresponding input signal detects the target edge, it immediately latches the current 48-bit count value of the timer as a timestamp, enables the timestamp validity indicator signal of the input signal, and sends the timestamp information containing the timestamp and the timestamp validity indicator signal to the input terminal of the first-level pipeline register. The first-stage pipeline register consists of 8 groups of 49-bit registers, each group corresponding to one input signal. The output is updated every 1 microsecond. While pushing the timestamp information of the recording control unit output into the second-stage pipeline, the timestamp information is cleared so that new timestamp information can be recorded in the next 1 microsecond interval.

10. A method for recording and transmitting multi-channel signal timestamps based on FPGA according to claim 6, characterized in that, The data encapsulation submodule is configured to perform the following steps: The state control unit starts working after receiving the enable signal generated by the control module. It adopts a state machine design and includes an idle state, a detection state, an encapsulation state, and an output state. In the idle state, when the first-level pipeline register is updated, it jumps into the detection state. In the detection state, it checks whether the 8 sets of timestamp information contain a valid timestamp, that is, the valid timestamp indicator bits of the 8 sets of timestamps are not all 0 at the same time. If a valid timestamp is contained, it jumps to the encapsulation state; otherwise, it returns to the idle state. In the encapsulation state, the frame format encapsulation unit completes the conversion of timestamp information into UDP data payload, and then the state jumps to the output state. The data output unit outputs the UDP payload to the UDP protocol processing module. After the UDP protocol processing module receives the data, the state returns to the idle state. When the state machine of the state control unit is in the encapsulation state, the frame format encapsulation unit triggers the encapsulation logic to assemble the UDP data frame payload according to the preset format, forming a UDP data packet containing timestamp information. When the state machine of the state control unit is in the output state, the data output control unit transmits UDP data packets containing timestamp information to the UDP protocol processing module. After the output data is received, the corresponding interface signal is released.

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