Thin film transistor, manufacturing method thereof, array substrate and display device

Abstract

The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display device. In one specific implementation mode, the thin film transistor comprises an active region, a gate insulating layer and a gate which are arranged in a stacked mode, the thin film transistor further comprises an active expansion region arranged on the periphery of the active region, the doping concentration of the active region is smaller than that of the active expansion region, and the doping concentration of the active expansion region is smaller than that of the gate insulating layer. The thickness of the active region in the stacking direction of the active region, the gate insulating layer and the gate is larger than the thickness of the active expansion region in the stacking direction. According to the thin film transistor, the off-state leakage current of the thin film transistor can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display. More particularly, it relates to a thin film transistor, a manufacturing method thereof, an array substrate and a display device. BACKGROUND

[0002] At present, various types of displays have been developed in the field of display technology. In view of the requirements of independent control of pixels, high-density integration and compatibility with panel substrate process for the circuit of the display, the driving circuit of the display includes a thin film transistor (TFT). When the thin film transistor is closed, there is a leakage current in the device, which reduces the stability of the driving circuit and affects the display effect. SUMMARY

[0003] The present disclosure aims to provide a display panel and a display device to solve at least one of the problems in the prior art.

[0004] To achieve the above-mentioned purpose, the present disclosure adopts the following technical solutions: The first aspect of the present disclosure provides a thin film transistor, comprising: an active region, a gate insulating layer and a gate which are stacked; the thin film transistor further comprises: an active extension region which is arranged at the periphery of the active region; The doping concentration of the active region is less than the doping concentration of the active extension region; The thickness of the active region in the stacking direction of the active region, the gate insulating layer and the gate is greater than the thickness of the active extension region in the stacking direction.

[0005] Optionally, the thin film transistor comprises: a buffer layer, an active layer, a gate insulating layer and a gate which are sequentially stacked on a substrate; The active layer comprises the active region and the active extension region; The buffer layer comprises a groove, and the active layer covers the groove and partially covers the surface of the buffer layer away from the substrate; The orthographic projection of the active region on the substrate covers the orthographic projection of the groove on the substrate.

[0006] Optionally, the depth of the groove is greater than the doping depth of the impurities in the active extension region.

[0007] Optionally, the thin film transistor comprises: The gate is formed on the substrate; The gate insulating layer is formed on the gate, and covers the gate and the substrate which is not covered by the gate; The active region is formed on the gate insulating layer.

[0008] Optionally, the distance from the surface of the active region away from the substrate to the substrate is greater than the distance from the surface of the active extension region away from the substrate to the substrate.

[0009] Optionally, a thickness of the active region in a stacking direction of the active region, the gate insulating layer and the gate is greater than 2 times of a thickness of the active extension region in the stacking direction.

[0010] Optionally, the thin film transistor further comprises: an active buffer region, the active buffer region is disposed between the active region and the active extension region, a doping concentration of the active buffer region is greater than a doping concentration of the active region and less than a doping concentration of the active extension region.

[0011] The second aspect of the present disclosure provides a manufacturing method of a thin film transistor as described above, comprising: forming the active region, the gate insulating layer and the gate in a stacked manner, the thin film transistor further comprises: the active extension region disposed at a periphery of the active region; a doping concentration of the active region is less than a doping concentration of the active extension region; a thickness of the active region in a stacking direction of the active region, the gate insulating layer and the gate is greater than 2 times of a thickness of the active extension region in the stacking direction.

[0012] Optionally, the manufacturing method of the thin film transistor comprises: providing a substrate; forming a buffer layer on the substrate, the buffer layer comprises a recess; forming a first semiconductor material layer covering the buffer layer; patterning the first semiconductor material layer to form a second semiconductor material layer, a surface of the second semiconductor material layer away from a surface of the substrate is a flat surface; patterning the second semiconductor material layer to form a third semiconductor material layer, the third semiconductor material layer has a pattern of the active region and the active extension region; forming the gate insulating layer and the gate on the third semiconductor layer; doping the third semiconductor material layer to form the active region and the active extension region.

[0013] The third aspect of the present disclosure provides an array substrate, comprising: a display area and a non-display area disposed at a periphery of the display area, the display area comprises a plurality of pixel driving circuits arranged in an array, the pixel driving circuit comprises a plurality of thin film transistors and at least one storage capacitor, at least one thin film transistor of the plurality of thin film transistors is electrically connected to the storage capacitor, and the thin film transistor is according to the thin film transistor as described above.

[0014] Optionally, the plurality of thin film transistors comprises a driving transistor and the at least one storage capacitor comprises a first capacitor; the driving transistor is electrically connected between a first power signal terminal and a second power signal terminal to generate a driving current for driving the light emitting unit to emit light, a first pole of the first capacitor is electrically connected to a control pole of the driving transistor, and a second pole is electrically connected to a first pole or a second pole of the driving transistor; At least the driving transistor in the pixel driving circuit is a thin-film transistor as described above.

[0015] A fourth aspect of this disclosure provides a display device including the array substrate described above.

[0016] The beneficial effects of this disclosure are as follows: This disclosure addresses existing problems by providing a thin-film transistor and its fabrication method, array substrate, and display device. It includes an active region and an active extension region surrounding the active region. The doping concentration of the active region is lower than that of the active extension region. By setting the thickness of the active region to be greater than that of the active extension region, the thickness difference physically isolates the active extension region from the active region when the thin-film transistor is off, thus avoiding off-state leakage current and demonstrating broad application prospects. Attached Figure Description

[0017] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0018] Figure 1 A schematic diagram of a thin-film transistor according to related technologies is shown; Figure 2 A schematic diagram of a thin-film transistor according to an embodiment of the present disclosure is shown; Figure 3 A schematic diagram of a thin-film transistor according to another embodiment of the present disclosure is shown; Figure 4 A schematic diagram of a thin-film transistor according to another embodiment of the present disclosure is shown; Figure 5 A schematic diagram of a thin-film transistor according to another embodiment of the present disclosure is shown; Figures 6 to 9 A flowchart illustrating a method for fabricating a thin-film transistor according to an embodiment of the present disclosure; Figure 10 A schematic diagram of an exemplary pixel driving circuit is shown. Detailed Implementation

[0019] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0020] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0021] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0022] Furthermore, the terms "having", "containing", and "including" used in this disclosure are all open-ended, meaning that when a module is described as "having", "containing", or "including" a first element, a second element, and / or a third element, it indicates that the module includes other elements in addition to the first element, the second element, and / or the third element.

[0023] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the described constituent elements. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0024] In this disclosure, unless otherwise stated, the term "co-layered arrangement" means a layer, component, or other structure formed by patterning two (or more) structures using the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple co-layered arrangements may be made of the same material, while the final materials may be the same or different.

[0025] In related technologies, refer to Figure 1The example shown includes a thin-film transistor comprising a semiconductor layer, an insulating layer, and a metal layer stacked together. The semiconductor layer includes a low-doped region with a lower doping concentration and a high-doped region with a higher doping concentration. The metal layer serves as the gate of the thin-film transistor. The low-doped region below the gate serves as the channel region, and the high-doped region is used for electrical connection with the source and drain electrodes.

[0026] The inventors discovered through research that, for example Figure 1 The P-type thin-film transistor shown is turned off. Because a turn-off voltage is applied to the gate, the electric field on the gate drives the channel semiconductor carriers to distribute in space perpendicular to the electric field direction. In typical applications, this turn-off voltage is positive. Positive charges are distributed in the metal layer serving as the gate, and holes are distributed in the highly doped region of the semiconductor layer. Due to the repulsion of like charges and the attraction of unlike charges, holes are distributed on the surface of the less doped region of the channel away from the metal layer, while electrons are distributed in the film layer closer to the metal layer. Therefore, in the off state, the carriers in the channel and the carriers in the highly doped regions corresponding to the source and drain electrodes can form conductive carrier paths, thus creating a leakage path and generating a leakage current I. 漏 N-type thin-film transistors also exhibit similar charge and carrier distributions, as well as leakage channels, in the off-state. The only difference is that, due to the opposite polarity of the off-state voltage, the charge and carrier distribution differs from... Figure 1 The opposite is true.

[0027] In view of the above, embodiments of the present disclosure provide a thin-film transistor, including: an active region, a gate insulating layer and a gate stacked thereon, and the thin-film transistor further includes: an active extension region disposed around the active region; The doping concentration in the active region is less than that in the active extension region; The thickness of the active region in the stacking direction of the active region, the gate insulating layer, and the gate is greater than the thickness of the active extension region in the stacking direction.

[0028] In this embodiment, an active region and an active extension region disposed around the active region are provided. The doping concentration of the active region is less than that of the active extension region. By setting the thickness of the active region to be greater than that of the active extension region, the possibility of the active extension region and the active region forming a leakage path is physically isolated by the thickness difference when the thin-film transistor is turned off, thereby avoiding off-state leakage current.

[0029] In a specific example, refer to Figure 2 As shown, the thin-film transistor includes an active region 201, a gate insulating layer 202, and a gate layer 203 stacked on a substrate 200.

[0030] The substrate 200 can be made of insulating materials such as glass, quartz, or polymers. Polymers may include, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherketone (PEK), polycarbonate (PC), polyarylate (PAK), polyethersulfone (PES), or polyimide (PI).

[0031] The active region 201 is a semiconductor material layer doped with N-type or P-type impurities. The semiconductor material layer can be one of the following: amorphous silicon, low-temperature polycrystalline silicon, oxide semiconductors, and compound semiconductors. Oxide semiconductors can be, for example, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), but are not limited to these. The specific doping type of the N-type impurity and the specific doping type of the P-type impurity vary depending on the material of the semiconductor material layer. For example, in silicon-based semiconductors such as amorphous silicon and low-temperature polycrystalline silicon, the N-type impurities can be, for example, phosphorus (P), arsenic (As), and antimony (Sb), and the P-type impurities can be, for example, boron (B), aluminum (Al), and gallium (Ga). In semiconductors such as oxide semiconductors, the N-type impurities can be, for example, tin (Sn), titanium (Ti), zirconium (Zr), and tungsten (W), and the P-type impurities can be, for example, copper (Cu), silver (Ag), lithium (Li), nickel (Ni), and oxide dopants (CuO, NiO, MgO). It can be understood that the active region 201 can also be referred to as the "channel" of the thin-film transistor.

[0032] The gate insulating layer 202 may be made of silicon oxide, silicon nitride, silicon carbide, or a combination thereof, and may have a single-layer structure or a multilayer structure including, for example, silicon nitride and / or silicon oxide. The gate 203 may be made of gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or alloys thereof. The gate 203 may have a single-layer structure or a multilayer structure including different metal layers. The gate insulating layer 202 serves to electrically isolate the gate 203 from the active region 201.

[0033] Continue to refer to Figure 2As shown, the thin-film transistor also includes an active extension region 201-1 disposed around the active region 201. The active extension region 201-1 can also be a semiconductor material layer doped with N-type or P-type impurities, and the doping type of the active extension region 201-1 is the same as that of the active region 201. Furthermore, the doping concentration of the active extension region 201-1 is greater than that of the active region 201, or in other words, the doping concentration of the active region 201 is less than that of the active extension region 201-1. Exemplarily, the active extension region 201-1 can be referred to as a "source / drain doped region" to directly contact the source or drain of the thin-film transistor, reducing ohmic contact resistance and improving current transport efficiency. (Refer to...) Figure 2 As shown, the end of the active extension region 201-1 in this example should be adjacent to the active region 201.

[0034] Optionally, from the perspective of simplifying the manufacturing process, the semiconductor material type of the active extension region 201-1 can be the same as that of the active region 201. It should be understood that the semiconductor material type applicable to the active region 201 also applies to the active extension region 201-1, and will not be elaborated here.

[0035] Continue to refer to Figure 2 As shown, the thickness h1 of the active region 201 in the stacking direction of the active region 201, the gate insulating layer 202, and the gate 203 is greater than the thickness h2 of the active extension region 201-1 in the same stacking direction. Figure 2 As shown, the stacking direction can also be represented as the direction perpendicular to the surface of the substrate 200.

[0036] With this setting, when the thin-film transistor is in the off state, a state-related voltage is applied to the gate 203, such as... Figure 2 As shown, for a P-type thin-film transistor, in typical applications, a positive voltage is applied to the gate 203 when it is off. This causes the electric field on the gate 203 to drive the active region 201, which serves as the channel, to have a layered distribution of holes (represented by "+") and electrons (represented by "-") in space perpendicular to the electric field direction. The electric field direction is the direction parallel to the surface of the substrate 200 formed between the source or drain and the gate 203. (Refer to...) Figure 2As shown, positive charges are distributed in the gate 203. Under the influence of like charges repelling and unlike charges attracting, electrons are distributed in the active region 201 near the gate 203, while holes are repelled to the side away from the gate 203. The charge carriers in the P-type doped active extension region 201-1 are holes. At this time, since the thickness h1 of the active region 201 is greater than the thickness h2 of the active extension region 201-1, that is, in the direction perpendicular to the electric field, the thickness h1 of the active region 201 is greater than the thickness h2 of the active extension region 201-1, thus the physical discontinuity formed between the active region 201 and the active extension region 201-1 isolates the pathway between the holes in the active extension region 201-1 and the holes in the active region 201.

[0037] Similarly, although Figure 2 Taking a P-type thin-film transistor as an example, it should be understood that if the thin-film transistor is an N-type thin-film transistor, then in the off state, a negative voltage is usually applied to the gate 203, so the gate 203 should be distributed with negative charge. Holes are located near the gate in the active region, and electrons are located away from the gate 203. The charge carriers in the active extension region 201-1 are electrons. It should also be understood that, referring to... Figure 2 The distribution principle is that since the thickness h1 of the active region 201 is greater than the thickness h2 of the active extension region 201-1, that is, in the direction perpendicular to the electric field, the thickness h1 of the active region 201 is greater than the thickness h2 of the active extension region. Thus, the physical discontinuity formed between the active region 201 and the active extension region 201-1 isolates the pathway between the electrons in the active extension region 201-1 and the electrons in the active region 201.

[0038] Therefore, when the thin-film transistor of this embodiment is in the off state and the active region 201 has the above-mentioned carrier distribution due to the applied voltage in the gate 203, it is also possible to avoid the formation of a leakage current path between the active extension region 201-1 and the active region 201.

[0039] Continue to refer to Figure 2 As shown, the active region 201, the gate insulating layer 202, and the gate 203 of the thin-film transistor are sequentially stacked on the substrate 200, that is, the thin-film transistor in this example is a top-gate structure.

[0040] Optionally, a buffer layer 205 is further included between the active region 201 and the substrate 200. The material of the buffer layer 205 can be one of silicon nitride, silicon oxide, aluminum oxide, or a stack thereof. The buffer layer 205 is used to provide a stable and high-quality growth or deposition environment for the active layer, ensuring the stability of the electrical performance of the thin-film transistor.

[0041] Continue to refer to Figure 2As shown, the active region 201 and the active extension region 201-1 are both disposed in the active layer. The buffer layer 205 includes a groove. The active layer covers the groove and partially covers the surface of the buffer layer 205 away from the substrate 200. The orthogonal projection of the active region on the substrate 200 covers the orthogonal projection of the groove on the substrate 200.

[0042] In other words, when the thin-film transistor is a top-gate structure, the groove formed in the buffer layer 205 is used to form a physical gap between the active region 201 and the active extension region 201-1, thereby forming a physical barrier to the leakage current in the device's off state.

[0043] Optionally, the thickness h1 of the active region 201 in the stacking direction of the active region 201, the gate insulating layer 202, and the gate 203 satisfies h1>2L with respect to the doping depth L of the impurities in the active extension region 201-1. When the thickness h1 and the doping depth L of the impurities in the active extension region 201-1 satisfy this relationship, the possibility of leakage current caused by charge layering in the active region 201 when the thin film transistor is in the off state can be effectively blocked.

[0044] Considering the characteristics of semiconductor processes, the active extension region 201-1 is usually formed by subsequent impurity doping on the basis of semiconductor material layer through ion implantation, etc. Therefore, the doping depth L must be less than or equal to the thickness h2 of the active extension region 201-1.

[0045] Optionally, refer to Figure 2 As shown, in the stacking direction of the active region 201, the gate insulating layer 202, and the gate 203, when the depth h3 of the groove in the buffer layer 205 is greater than or equal to the thickness h2 of the active extension region 201-1, it can ensure that the thickness h1 of the active region and the doping depth L of the impurities in the active extension region 201-1 satisfy the relationship h1>2L, thereby effectively isolating the possibility of leakage current caused by charge layering in the active region 201 when the thin film transistor is in the off state.

[0046] It should be noted that, although Figure 2 The source and drain of the thin-film transistor are not shown in the figure. Those skilled in the art should understand that in actual scenarios, the thin-film transistor should also include a source and drain disposed on the gate 203. The source and drain are electrically connected to the active extension regions 201-1 on both sides of the active region 201, respectively. The source and drain can be formed in the same metal layer. The source and drain are electrically isolated from the gate 203 through one side or multiple insulating layers. This will not be elaborated in this article.

[0047] In some alternative embodiments, refer to Figure 3 As shown, the thin-film transistor also includes an active buffer 201-2 disposed between the active region 201 and the active extended region 201-1.

[0048] The active buffer 201-2 is also a semiconductor material layer doped with N-type or P-type impurities. The doping type of the active buffer 202-1 is the same as that of the active region 201 and the active extension region 201-1. The doping concentration of the active buffer 201-2 is greater than that of the active region 201 and less than that of the active extension region 201-1.

[0049] By setting an active buffer 201-2, a gradually decreasing doping concentration gradient is formed from the source-drain expansion region 201-1 through the active expansion region 201-2 to the active region 201, which helps to prevent the generation of hot carriers and avoid leakage caused by the hot carrier effect.

[0050] It should be noted that in this embodiment, other structures and functions are similar to those in the embodiments described above, and will not be repeated here.

[0051] In some alternative embodiments, refer to Figure 4 As shown, the thin-film transistor includes: a gate 203', a gate insulating layer 202', and an active region 201' sequentially stacked on a substrate 200, i.e., the thin-film transistor in this embodiment is a bottom-gate structure. The gate insulating layer 202' covers the gate 203' and the substrate 200 not covered by the gate 203'; the active region 201' is formed on the gate insulating layer 202'.

[0052] In this embodiment, the thin-film transistor further includes an active extension region 201-1' disposed around the active region 201'. The thickness h1 of the active region 201' in the stacking direction of the active region 201', the gate insulating layer 202', and the gate 203' is greater than the thickness h2 of the active extension region 201-1' in the same stacking direction.

[0053] Additionally, refer to Figure 4 As shown, considering the characteristics of semiconductor manufacturing processes, in order to ensure that there is a physical discontinuity between the side of the active region 201' away from the gate 203' below it and the surface of the active extension region 201-1' away from the substrate 200 after multiple film layers on the substrate, in this embodiment, the distance a1 from the surface of the active region 201' away from the substrate 200 to the substrate 200 is greater than the distance a2 from the surface of the active extension region 201-1' away from the substrate 200 to the substrate 200.

[0054] With the above settings, when the thin-film transistor is in the off state, a state-related voltage is applied to the gate 203', such as... Figure 4As shown, for a P-type thin-film transistor, in typical applications, a positive voltage is applied to the gate 203' when it is off. This causes the electric field on the gate 203' to drive the active region 201', which serves as the channel, to have a layered distribution of holes (represented by "+") and electrons (represented by "-") in space perpendicular to the electric field direction. The electric field direction is the direction parallel to the surface of the substrate 200 formed between the source or drain and the gate 203'. (Refer to...) Figure 4 As shown, positive charges are distributed in the gate 203'. Under the effect of like charges repelling and unlike charges attracting, electrons are distributed in the active region 201' near the gate 203', while holes are repelled to the side away from the gate 203'. The charge carriers in the P-type doped active extension region 201-1' are holes.

[0055] At this time, since the thickness h1 of the active region 201' is greater than the thickness h2 of the active extension region 201-1', that is, in the direction perpendicular to the electric field, the thickness h1 of the active region 201' is greater than the thickness h2 of the active extension region 201-1', thus the physical discontinuity formed between the active region 201' and the active extension region 201-1' isolates the pathway between the holes in the active extension region 201-1' and the holes in the active region 201'.

[0056] Similarly, although Figure 4 Taking a P-type thin-film transistor as an example, it should be understood that if the thin-film transistor is an N-type thin-film transistor, then in the off state, a negative voltage is usually applied to the gate 203', so the gate 203' should be distributed with negative charge. In the active region, the side closer to the gate contains holes, and the side farther from the gate 203' contains electrons. The charge carriers in the active extension region 201-1' are electrons. It should also be understood that, referring to... Figure 2 The distribution principle is that since the thickness h1 of the active region 201' is greater than the thickness h2 of the active extension region 201-1', that is, in the direction perpendicular to the electric field, the thickness h1 of the active region 201' is greater than the thickness h2 of the active extension region. Thus, the physical discontinuity formed between the active region 201' and the active extension region 201-1' isolates the pathway between the electrons in the active extension region 201-1' and the electrons in the active region 201'.

[0057] Therefore, when the thin-film transistor of this embodiment is in the off state and the active region 201' has the above-mentioned carrier distribution due to the applied voltage, the formation of a leakage current path between the active extension region 201-1' and the active region 201' can also be avoided.

[0058] Considering the characteristics of semiconductor processes, when the active region 201' and the active extended region 201-1' are stacked sequentially from the substrate 200, since the active region 201' is far from the substrate 200 relative to the gate 203', when doping the semiconductor material layer, it is usually necessary to dop from the surface of the semiconductor material layer where the active region 201' and the active extended region 201-1' are located, which is far from the gate 203'. Therefore, in order to ensure that there is sufficient physical discontinuity between the surface of the active region 201' far from the gate 203' and the active extended region 201-1', the thickness h1 of the active region 201' in the stacking direction of the active region 201', the gate insulating layer 202' and the gate 203' is more than twice the thickness h2 of the active extended region 201-1' in the stacking direction.

[0059] This configuration ensures that the discontinuity distance between the surface of the active region away from the substrate 200 and the surface of the active extension region 201-1' away from the substrate 200 can reach a certain value. Figure 2 and Figure 3 The discontinuity distance between the doping depth of impurities in the active extension region 201-1' of the middle-top gate thin-film transistor and the surface of its active region 201' away from the gate 203' can effectively isolate the possibility of leakage current caused by charge stratification in the active region 201' of the thin-film transistor when it is off.

[0060] In addition, it should be noted that, Figure 4 The top-gate structure of the thin-film transistor in the image illustrates an ideal film layer state. However, in actual device fabrication, when the thickness of the gate insulating layer 202' is insufficient relative to the gate 203', the side of the gate insulating line 202' away from the substrate 200 will not form a flat surface, but rather exhibit a stepped shape following the gradient of the gate 203 and the buffer layer 205. It is understood that in this case, the active extension region 201-1' located thereon will also exhibit a stepped shape following this stepped shape.

[0061] However, it should be noted that the step-like change of the active extension region of the top-gate thin-film transistor does not affect whether leakage current is formed due to the carrier distribution in the off state of the thin-film transistor. As long as there is no thickness gradient at the contact position between the active extension region and the active region, there will be leakage current due to the carrier distribution in the off state. Furthermore, the physical isolation provided in the embodiments of this disclosure avoids leakage current path, which will not be elaborated further below.

[0062] In some alternative embodiments, refer to Figure 5 As shown, the thin-film transistor also includes an active buffer 201-2' disposed between the active region 201' and the active extended region 201-1'.

[0063] The active buffer 201-2' is also a semiconductor material layer doped with N-type or P-type impurities, and the doping type of the active buffer 202-1' is the same as that of the active region 201' and the active extension region 201-1'. The doping concentration of the active buffer 201-2' is greater than that of the active region 201' and less than that of the active extension region 201-1'.

[0064] By setting an active buffer 201-2', a gradually decreasing doping concentration gradient is formed from the source-drain extension region 201-1' through the active extension region 201-2' to the active region 201', which helps to prevent the generation of hot carriers and avoid leakage caused by the hot carrier effect.

[0065] It should be noted that in this embodiment, other structures and functions are similar to those in the embodiments described above, and will not be repeated here.

[0066] A second aspect of this disclosure provides a method for fabricating the thin-film transistor described above, comprising: The thin-film transistor forms an active region, a gate insulating layer, and a gate stacked together. It also includes an active extension region disposed around the active region, wherein the doping concentration of the active region is less than that of the active extension region. The thickness of the active region in the stacking direction of the active region, the gate insulating layer, and the gate is greater than the thickness of the active extension region in the stacking direction.

[0067] In this embodiment, the thin-film transistor fabricated according to this disclosure includes an active region and an active extension region disposed around the active region. The doping concentration of the active region is less than that of the active extension region. By setting the thickness of the active region to be greater than that of the active extension region, the possibility of the active extension region and the active region forming a leakage path is physically isolated by the thickness difference when the thin-film transistor is turned off, thereby avoiding off-state leakage current.

[0068] The following is combined with Figures 6-9 The process flow diagram shown describes Figure 2 The method for fabricating the thin-film transistor structure shown.

[0069] Reference Figure 6 As shown, in step S1, a substrate 200 is provided. The material of the substrate 200 may be an insulating material such as glass, quartz, or a polymer. The polymer may include, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherketone (PEK), polycarbonate (PC), polyarylate (PAK), polyethersulfone (PES), or polyimide (PI).

[0070] In step S2, a buffer layer 205 is formed on the substrate 200. The buffer layer 205 includes a groove 215. The material of the buffer layer 205 can be one of silicon nitride, silicon oxide, aluminum oxide, or a stack thereof. The groove 215 can be fabricated by patterning processes such as dry etching or wet etching.

[0071] The depth h3 of the groove 215 can be greater than or equal to the thickness h2 of the active extension region 201-1 to be formed, so as to ensure that the thickness h1 of the active region to be formed and the doping depth L of the impurities in the active extension region 201-1 satisfy the relationship h1>2L, thereby effectively isolating the possibility of leakage current caused by charge layering in the active region 201 of the thin film transistor in the off state.

[0072] Reference Figure 7 As shown, in step S3, a first semiconductor material layer 211 is formed over the buffer layer 205. Specifically, the first semiconductor material layer 211 can be formed by chemical vapor deposition (CVD). The material of the first semiconductor material layer 211 may include one of the following: amorphous silicon, low-temperature polycrystalline silicon, oxide semiconductor, and compound semiconductor. The oxide semiconductor may be, for example, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), but is not limited to these.

[0073] Reference Figure 8 As shown, in step S4, the first semiconductor material layer 211 is patterned to form a second semiconductor material layer 221, and the surface of the second semiconductor material layer 221 away from the substrate 200 is a flat surface. Specifically, the portion of the first semiconductor material layer 211 not covering the groove 21 can be etched through a patterning process to flatten the surface away from the substrate 200 corresponding to the groove 215, thereby forming the second semiconductor material layer 221. The thickness of the portion of the second semiconductor material layer 221 covering the groove 215 is h1, and the thickness of the portion of the buffer layer 205 covering the groove 215 is h2.

[0074] Next, refer to Figure 9 As shown, in step S5, a third semiconductor material layer 231 is formed by patterning the second semiconductor material layer 221. The third semiconductor material layer 231 has a pattern corresponding to the active region 201 and the active extension region 201-1. This step aims to form the lines required for the channel and the portion of the active extension region 201-1 for ohmic contact between the source and drain.

[0075] In step S6, a gate insulating layer 201 and a gate 203 are formed on the third semiconductor layer 231. Exemplarily, a gate insulating material layer and a gate material layer can be sequentially covered on the third semiconductor layer 231, and the gate insulating layer 201 and the gate 203 can be formed by patterning etching. The material of the gate insulating material layer may include silicon oxide, silicon nitride, silicon carbide, or combinations thereof, and the gate insulating material layer may be a single layer or a multilayer structure. The material of the gate material layer may be selected from: gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), or alloys thereof. The gate material layer may have a single-layer structure or a multilayer structure including different metal layers.

[0076] In step S7, the third semiconductor material layer 231 is doped to form an active extension region 201-1. Exemplarily, doping processes such as ion implantation can be performed on the exposed surface of the third semiconductor material layer 231, using the already formed gate insulating layer 201 and gate 203 as shielding layers, to form the active region 201 and the active extension region 201-1, thereby forming... Figure 2 The thin-film transistor structure shown.

[0077] Afterwards, an insulating layer, a source, and a drain can be formed on the gate 203. The source and drain are electrically connected to the active region 201-1, thereby completing the fabrication of the thin-film transistor.

[0078] Based on the same inventive concept, a third aspect of this disclosure also provides an array substrate, the array substrate comprising: a display area and a non-display area disposed around the display area, the display area comprising an array of pixel driving circuits, the pixel driving circuit comprising a plurality of thin film transistors and at least one storage capacitor, wherein at least one of the plurality of thin film transistors electrically connected to the storage capacitor is a thin film transistor according to the above description.

[0079] In particular, when a thin-film transistor is used in a pixel driving circuit and is electrically connected to the signal terminal or power supply terminal, it can continuously replenish the leakage current caused by the leakage current through the signal terminal. However, when a thin-film transistor is electrically connected to a storage capacitor, the leakage current in its off state cannot be replenished by the storage capacitor, thus forming a leakage current effect.

[0080] In this embodiment, by providing an array substrate including a pixel driving circuit of the thin-film transistor of the present disclosure, when the thin-film transistor is in the off state, the off-state voltage applied to the gate causes a carrier distribution at the gate of the thin-film transistor. The above structure can be used to avoid turn-off leakage current, thereby ensuring the output stability of the pixel driving circuit.

[0081] Optionally, the plurality of thin-film transistors include driving transistors and the at least one storage capacitor includes a first capacitor. The driving transistor is electrically connected between a first power signal terminal and a second power signal terminal to generate a driving current for driving the light-emitting unit to emit light. The first terminal of the first capacitor is electrically connected to the control terminal of the driving transistor, and the second terminal is electrically connected to either the first or second terminal of the driving transistor. At least the driving transistor in the pixel driving circuit is a thin-film transistor as described above.

[0082] This setting prevents leakage current from the driving transistor DTFT when it is off, thus ensuring the stability of the driving current of the driving transistor DTFT.

[0083] Figure 10 A circuit schematic of an exemplary pixel driving circuit and the light-emitting unit driven by it is shown. (Refer to...) Figure 10 As shown, the pixel driving circuit includes multiple thin-film transistors, including: a driving transistor DTFT, a first transistor T1 as a data writing transistor, a second transistor T2 as a light-emitting control transistor, and a third transistor T3 as a reset transistor.

[0084] In this example, the driving transistor DTFT is electrically connected between the first power supply signal terminal VDD and the second power supply signal terminal VSS to form the driving current for the light-emitting unit D to emit light. Specifically, in this example, the first electrode of the driving transistor DTFT is electrically connected to the first power supply signal terminal VDD, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first node N1.

[0085] The first transistor T1 has its first electrode electrically connected to the data signal terminal Data, its second electrode electrically connected to the second node N2, and its control electrode electrically connected to the second control terminal Gate2, so as to electrically connect the data signal terminal Data and the second node N2 based on the signal from the second control terminal Gate2. The second transistor T2 has its first electrode electrically connected to the second node N2, its second electrode electrically connected to the first electrode of the light-emitting unit D, and its control electrode electrically connected to the light-emitting control terminal EM, so as to electrically connect the second node N2 and the first electrode of the light-emitting unit D based on the signal from the light-emitting control terminal EM, thereby transmitting driving current to the light-emitting unit D to drive it to emit light. The third transistor T3 has its first electrode electrically connected to the reset signal terminal Vinit, its second electrode electrically connected to the first node N1, and its control electrode electrically connected to the first control terminal Gate1, so as to electrically connect the reset signal terminal Vinit and the first node N1 based on the signal from the first control terminal Gate1, thereby resetting the potential of the first node N1.

[0086] In addition, the pixel driving circuit also includes two storage capacitors, namely a first storage capacitor C1 and a second storage capacitor C2. The first terminal of the first storage capacitor C1 is electrically connected to the first node N1, and the second terminal is electrically connected to the second node N2. The first terminal of the second storage capacitor C2 is electrically connected to the first power signal terminal VDD, and the second terminal is electrically connected to the first node N1.

[0087] In this example, during the reset phase, based on the conduction of the third transistor T3, the reset signal Vinit from the reset signal terminal Vinit is transmitted to the first node N1. The first transistor T1 can also be turned on and used to discharge and reset the second node N2 to the reference voltage Vref using the data signal terminal. Then, based on the first transistor T1, the reference voltage Vref is transmitted using the data signal terminal Data, and transmitted via the coupling effect of the first capacitor C1 to the first node N1 corresponding to the control electrode of the driving transistor DTFT to perform threshold compensation on the driving transistor DTFT. During the light emission phase, based on the signal from the light emission control terminal EM, the second transistor T2 is turned on, thereby using the driving current generated by the driving transistor DTFT to drive the light emission unit D to emit light. The driving current is: Where K is the driving parameter representing the conductivity factor of the driving transistor, Vref is the reference voltage Vref, Vdata is the data signal, Cv1 represents the capacitance value of the first storage capacitor C1, and Cv2 represents the capacitance value of the second storage capacitor C2.

[0088] As can be seen in this example, when the driving transistor DTFT is electrically connected to the storage capacitor, voltage coupling and charge storage are required through the storage capacitor to generate the driving current. The value of the driving current determines the grayscale of the light-emitting unit as a pixel.

[0089] When the driving transistor DTFT is in the off state, a leakage current is formed between the active region and the active extended region when the turn-off voltage is applied to the driving transistor. Since the storage capacitor cannot compensate for the leakage current, the leakage current generated by the driving transistor DTFT will affect the grayscale of the driving current generated by the driving transistor DTFT, thereby affecting the display uniformity of pixels in the display panel driven by the array substrate.

[0090] In the embodiments of this disclosure, by setting the driving transistor DTFT connected to the storage capacitor as the thin film transistor described above, it is possible to ensure that when the driving transistor DTFT is in the off state and an off-state potential is applied to the gate to form a layered arrangement of holes and electrons in the active region, the leakage path is blocked by the physical isolation of the thickness difference between the active region 201 and the active extension region 201-1 in the thin film transistor. Even if it is connected to the storage capacitor, the grayscale of the driving current generated by the driving transistor DTFT can still be stabilized, thereby improving the display uniformity of pixels in the display panel driven by the array substrate.

[0091] It should be noted that, although the above text uses... Figure 10 The pixel driving circuit structure shown is illustrated as an example, but this disclosure is not intended to limit the specific structure of the pixel driving circuit for the array substrate applicable to the embodiments of this disclosure. As long as the driving transistor DTFT is electrically connected to at least one storage capacitor, when it is set as a thin-film transistor in the embodiments of this disclosure, the grayscale of the driving current can be stabilized.

[0092] Furthermore, it should be noted that the embodiments of this disclosure are not intended to be limited to a structure that only drives transistors. The transistors electrically connected to the storage capacitor in the pixel driving circuit can all be configured as thin-film transistors in the embodiments of this disclosure. In this way, when the transistor is in the off state, leakage current caused by the layered arrangement of hole carriers due to the application of the off-state voltage to the gate of the transistor can be avoided. The leakage damage caused by the connection of the storage capacitor can be avoided, thereby avoiding leakage paths in the pixel driving circuit that cause the nodes of the circuit to be unable to reach the desired potential. For example, it can also avoid misleading conduction of the corresponding path.

[0093] Furthermore, it should be noted that, considering the existence of parasitic capacitance in the circuit, when a transistor that is not directly electrically connected to the storage capacitor is set as a thin-film transistor, leakage current in its off state can also be avoided, thereby improving circuit stability.

[0094] It should also be noted that the pixel driving circuit of the array substrate in this embodiment can be used for various light-emitting devices. The light-emitting unit D can be an organic light-emitting diode (OLED) made of organic light-emitting materials; it can also be a light-emitting diode (LED) made of inorganic light-emitting materials, such as micro light-emitting diodes (Micro LED) and mini light-emitting diodes (Mini LED); it can also be a quantum dot light-emitting diode (QLED) and other devices.

[0095] Another embodiment of this disclosure provides a display device including the aforementioned array substrate. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment is not limited to this. By loading the array substrate, the display device can utilize the array substrate to provide uniform grayscale driving, thereby improving the product display effect.

[0096] Since the array substrate included in the display device provided in this embodiment is the same as the array substrate provided in the above embodiments, the previous embodiments are also applicable to the display device provided in this embodiment, and will not be described in detail in this embodiment.

[0097] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A thin-film transistor, characterized in that, include: The thin-film transistor comprises an active region, a gate insulating layer, and a gate layer stacked together. It further includes an active extension region disposed around the active region. The doping concentration of the active region is less than the doping concentration of the active extension region. The thickness of the active region in the stacking direction of the active region, the gate insulating layer, and the gate is greater than the thickness of the active extension region in the stacking direction.

2. The thin-film transistor according to claim 1, characterized in that, include: A buffer layer, an active layer, a gate insulating layer, and a gate are sequentially stacked on a substrate. The active layer includes the active region and the active extension region. The buffer layer includes a groove, and the active layer covers the groove and partially covers the surface of the buffer layer away from the substrate. The orthogonal projection of the active region onto the substrate covers the orthogonal projection of the groove onto the substrate.

3. The thin-film transistor according to claim 2, characterized in that, The depth of the groove is greater than the doping depth of the impurities in the active extension region.

4. The thin-film transistor according to claim 1, characterized in that, include: The gate formed on the substrate; A gate insulating layer is formed on the gate, the gate insulating layer covering the gate and the substrate not covered by the gate; The active region formed on the gate insulating layer.

5. The thin-film transistor according to claim 4, characterized in that, The distance from the surface of the active region away from the substrate to the substrate is greater than the distance from the surface of the active extended region away from the substrate to the substrate.

6. The thin-film transistor according to claim 4, characterized in that, The thickness of the active region in the stacking direction is greater than twice the thickness of the active extension region in the stacking direction.

7. The thin-film transistor according to claim 1, characterized in that, Also includes: An active buffer is provided, which is disposed between the active region and the active extended region. The doping concentration of the active buffer is greater than the doping concentration of the active region and less than the doping concentration of the active extension region.

8. A method for fabricating a thin-film transistor according to claims 1-7, characterized in that, include: The thin-film transistor comprises an active region, a gate insulating layer, and a gate layer stacked together. It further includes an active extension region disposed around the active region. The doping concentration of the active region is less than the doping concentration of the active extension region. The thickness of the active region in the stacking direction of the active region, the gate insulating layer, and the gate is greater than the thickness of the active extension region in the stacking direction.

9. The manufacturing method according to claim 8, characterized in that, The method includes: Provide substrate; A buffer layer is formed on the substrate, the buffer layer including grooves; A first semiconductor material layer is formed covering the buffer layer; The first semiconductor material layer is patterned to form a second semiconductor material layer, wherein the surface of the second semiconductor material layer away from the substrate is a flat surface; A third semiconductor material layer is formed by patterning the second semiconductor material layer, the third semiconductor material layer having the pattern of the active region and the active extended region; A gate insulating layer and a gate are formed on the third semiconductor layer; The third semiconductor material layer is doped to form the active region and the active extended region.

10. An array substrate, characterized in that, include: A display area and a non-display area disposed around the display area, the display area including an array of pixel driving circuits. The pixel driving circuit includes multiple thin-film transistors and at least one storage capacitor. At least one of the plurality of thin-film transistors electrically connected to the storage capacitor is a thin-film transistor according to any one of claims 1-7.

11. The array substrate according to claim 10, characterized in that, The plurality of thin-film transistors include driving transistors and the at least one storage capacitor includes a first capacitor. The driving transistor is electrically connected between the first power signal terminal and the second power signal terminal to generate a driving current for the light-emitting unit to emit light. The first terminal of the first capacitor is electrically connected to the control terminal of the driving transistor, and the second terminal is electrically connected to either the first or second terminal of the driving transistor. At least one of the driving transistors in the pixel driving circuit is a thin-film transistor according to any one of claims 1-7.

12. A display device, characterized in that, Includes the array substrate as described in claim 10 or 11.

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