Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a substrate, a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels, the gate lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction intersect and are both parallel to a plane where the substrate is located. The sub-pixel comprises a thin film transistor and a pixel electrode, the control end of the thin film transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the pixel electrode. Wherein the orthographic projection of at least part of the gate lines on the substrate is overlapped with the orthographic projection of the pixel electrodes on the substrate. According to the embodiment of the invention, at least part of the gate lines are adjusted to be arranged corresponding to the pixel electrodes, so that the gate lines are not limited between adjacent electrode rows any more, the distance between at least part of adjacent gate lines can be increased, stray capacitance between the adjacent gate lines can be reduced, the display cross grain problem of the display panel is improved, and the display reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display devices, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technologies such as liquid crystal display devices (LCD), organic light-emitting diode display devices (OLED), etc., display panels are widely used in various industries. However, abnormal phenomena such as display horizontal lines may still occur during the use of current display panels, affecting the use experience. SUMMARY

[0003] The embodiments of the present application provide a display panel and a display device, which can improve display reliability.

[0004] In a first aspect, the embodiments of the present application provide a display panel. The display panel includes a substrate, a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels. The gate lines extend along a first direction, and the data lines extend along a second direction. The first direction and the second direction intersect and are both parallel to a plane on which the substrate lies. The sub-pixel includes a thin film transistor and a pixel electrode. The control terminal of the thin film transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the pixel electrode. At least part of the gate lines overlaps the pixel electrode in the orthographic projection of the substrate.

[0005] In a second aspect, the embodiments of the present application provide a display device. The display device includes the display panel in any of the foregoing embodiments.

[0006] The embodiments of the present application provide a display panel and a display device. By changing the position of at least part of the gate lines, at least part of the gate lines are adjusted to be arranged corresponding to the pixel electrodes, thereby improving the layout flexibility of the plurality of gate lines. Moreover, this design makes the gate lines no longer limited between adjacent electrode rows, so that the distance between at least part of the adjacent gate lines can be increased, the parasitic capacitance between the adjacent gate lines can be reduced, and the display horizontal line problem of the display panel can be improved, thereby improving the display reliability. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments of the present application will be briefly introduced. For those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0008] Figure 1 is a structural diagram of a display panel in the prior art; Figure 2 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 3 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 4 is Figure 3 is a cross-sectional structural diagram of A-A in Figure 5 is Figure 3 is a partial enlarged view in Figure 6 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 7 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 8 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 9 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 10 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 11 is a cross-sectional structural diagram of a display panel provided by an embodiment of the present application; Figure 12 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 13 is a structural diagram of a display panel provided by an embodiment of the present application; Figure 14 is a structural diagram of a display device provided by an embodiment of the present application.

[0009] Label Description: 100, display panel; 200, display device; 10, substrate; 20, gate line; 21, first gate line; 22, second gate line; 23, third gate line; 24, fourth gate line; 30, data line; 31, first data line; 32, second data line; 40, sub-pixel; 50, pixel electrode; 51, first overlap part; 52, first pole part; 53, second pole part; 54, second overlap part; 55, third pole part; 56, fourth pole part; 57, first domain part; 58, second domain part; 59, connection area; 50a, first electrode; 50b, second electrode; 60, common electrode; 70, color filter substrate; 71, light shielding layer; 711, first light shielding part; 712, second light shielding part; 713, third light shielding part; 714, fourth light shielding part; 72, filter; 80, liquid crystal layer; L, pixel column; L1, first pixel column; L2, second pixel column; L3, third pixel column; L4, fourth pixel column; H, pixel row; H1, first pixel row; H2, second pixel row J1, first electrode; J2, second electrode; J3, control terminal; T, thin film transistor; K, recessed space; X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0010] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0011] It should be noted that, in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0012] As Figure 1 shown, in the liquid crystal display device, the liquid crystal display device will define a plurality of sub-pixel regions, and the sub-pixel region is usually provided with part of the structure in the common electrode, the pixel electrode, the liquid crystal capacitor C LC , the storage capacitor C st and the transistor structure as a switching device, the data line data and the scan line scan extend in different directions and are located on the side of the sub-pixel region. The liquid crystal capacitor CLC The pixel electrode and the common electrode jointly constitute a liquid crystal capacitor C st There are various forms, such as the storage capacitor C st It can be composed of a scan line scan and a pixel electrode, or a storage capacitor C st It can be composed of a common electrode line and a pixel electrode, wherein the common electrode line is used to provide a corresponding voltage signal to the common electrode. The storage capacitor C st It is used to maintain the charge of the liquid crystal capacitor C LC When the transistor structure has a leakage problem due to its own characteristics, the storage capacitor C st Can timely charge the liquid crystal capacitor C LC .

[0013] In the related art, the parasitic capacitance is easily generated in the liquid crystal display device due to the too close distance between some adjacent scan lines scan, thereby causing the display horizontal line phenomenon of the liquid crystal display device, and affecting the use and perception of the liquid crystal display device.

[0014] To solve the above problems, in a first aspect, please refer to Figures 2 to 4 The display panel 100 provided by the embodiment of the present application includes a substrate 10, a plurality of gate lines 20, a plurality of data lines 30, and a plurality of sub-pixels 40. The gate lines 20 extend along a first direction X, the data lines 30 extend along a second direction Y, and the first direction X and the second direction Y are perpendicular to each other and parallel to the plane on which the substrate 10 is located. The sub-pixel 40 includes a thin film transistor T and a pixel electrode 50. The control end J3 of the thin film transistor T is electrically connected to the gate line 20, the first pole J1 is electrically connected to the data line 30, and the second pole J2 is electrically connected to the pixel electrode 50. At least part of the gate lines 20 in the orthographic projection of the substrate 10 overlaps with the orthographic projection of the pixel electrode 50 on the substrate 10. In Figure 2 In the orthographic projection of the substrate 10, the area where the sub-pixel 40 is located is shown in the form of a thick dashed box.

[0015] The display panel 100 is used to form a display panel 100 subsequently. The display panel 100 provided by the embodiment of the present application does not emit light by itself, and depends on the cooperation of a backlight module. Specifically, the display panel 100 includes an array substrate, a liquid crystal layer 80, and a color film substrate 70. The array substrate includes structures such as the thin film transistor T, the gate line 20, the data line 30, and the pixel electrode 50, which are used to control the deflection of the liquid crystal molecules in the liquid crystal layer 80. The light source emitted by the backlight module propagates into the liquid crystal layer of the display panel 100, and the array substrate controls the deflection angle of the liquid crystal molecules, thereby changing the light transmittance to present different brightness. The color filter 72 in the color film substrate 70 can filter the light passing through the liquid crystal layer 80, thereby realizing the multi-color display effect.

[0016] The substrate 10 is a film layer structure that plays a supporting role in the display panel 100. Other film layer structures are stacked on the substrate 10. The thickness direction Z of the substrate 10 is often consistent with the thickness direction Z of other film layers and the overall thickness direction Z of the display panel 100. Therefore, for ease of understanding, this application will use the same direction Z to illustrate multiple thickness directions Z.

[0017] Gate lines 20, also called scan lines, are used to transmit scan signals. Gate lines 20 extend along a first direction X, and multiple gate lines 20 can be arranged side-by-side at intervals in a second direction Y. Optionally, the first direction X is perpendicular to the second direction Y. Further, the first direction X is the row direction of the display panel 100, and the second direction Y is the column direction of the display panel 100.

[0018] The data line 30 is used to transmit data signals. The data line 30 extends along the second direction Y, and multiple data lines 30 can be arranged side by side at intervals in the first direction X. The multiple data lines 30 and multiple gate lines 20 are spatially intersecting, that is, the extension directions of the two signal lines intersect and overlap in the orthographic projection of the substrate 10.

[0019] It should be noted that when we say the gate line 20 extends along the first direction X, it means that the gate line 20 has a tendency to extend along the first direction X. Depending on the actual layout requirements, the gate line 20 can be a straight line structure parallel to the first direction X, or the gate line 20 can intersect the first direction X at some locations, such as having a wavy or zigzag structure locally or overall, as long as the gate line 20 as a whole has a tendency to extend along the first direction X. Similarly, when we say the data line 30 extends along the second direction Y, it means that the data line 30 as a whole has a tendency to extend along the second direction Y.

[0020] In some optional embodiments, the display panel 100 further includes a driving chip and a gate driving circuit. The driving chip provides data signals to the data lines 30, and the gate driving circuit includes multiple shift register units and provides scan signals to the gate lines 20. Further optionally, the display panel 100 includes a display area and a border area surrounding the display area. Multiple sub-pixels 40 are located within the display area, and the driving chip and gate driving circuit are both located within the border area. The driving chip is located on one side of the display area along the second direction Y, while the gate driving circuit is located on at least one side of the display area along the first direction X.

[0021] Sub-pixels 40 are the smallest units in the display panel 100 used to form images. A sub-pixel 40 includes a portion of the liquid crystal layer, a portion of the common electrode 60, a pixel electrode 50, and a thin-film transistor T. The pixel electrode 50 and the common electrode 60 work together to generate a corresponding electric field to drive the liquid crystal molecules to deflect. When the display panel 100 is provided with a color filter substrate 70, the color filter substrate 70 includes filters 72 corresponding to the multiple sub-pixels 40. Optionally, the multiple filters 72 include red, green, and blue filters of different colors. The coordinated arrangement of the color filter substrate 70 and the display panel 100 can satisfy the multi-color display function, thereby improving the applicability and display effect of the display panel 100. Of course, in other embodiments, the multiple filters 72 include red, green, blue, and white filters of different colors.

[0022] There are multiple pixel electrodes 50, each corresponding to a multiple sub-pixels 40. The common electrode 60 can take various forms. For example, the common electrode 60 can be a full-surface structure, with its orthographic projection on the substrate 10 covering the orthographic projections of all pixel electrodes 50 on the substrate 10. Alternatively, the common electrode 60 can be a block structure, with multiple block structures arranged in an array along the first direction X and the second direction Y, and the orthographic projection of a single block structure on the substrate 10 overlapping the orthographic projections of multiple pixel electrodes 50 on the substrate 10. In this case, a single block structure can also be reused as a touch electrode to achieve touch functionality.

[0023] The pixel electrode 50, the common electrode 60, and the liquid crystal layer can have various positional relationships. For example, the pixel electrode 50 and the common electrode 60 can be located on different sides of the liquid crystal layer, or the pixel electrode 50 and the common electrode 60 can be located on the same side of the liquid crystal layer. In this case, the common electrode 60 can be sandwiched between the pixel electrode 50 and the liquid crystal layer, or the pixel electrode 50 can also be sandwiched between the common electrode 60 and the liquid crystal layer.

[0024] like Figure 4 As shown, the thin-film transistor T includes a first electrode J1, a second electrode J2, and a control terminal J3. One of the first electrode J1 and the second electrode J2 is the source, and the other is the drain. The control terminal J3 is used to control whether the first electrode J1 and the second electrode J2 are turned on or off. Further, the control terminal J3 of the thin-film transistor T is electrically connected to the gate line 20 to receive the scan signal, the first electrode J1 is electrically connected to the data line 30 to receive the data signal, and the second electrode J2 is electrically connected to the pixel electrode 50.

[0025] It should be noted that a portion of the gate line 20 is reused as the control terminal J3 of the thin-film transistor T to meet the electrical connection requirements between the two. Specifically, the portion of the gate line 20 that overlaps with the active structure in the thin-film transistor T is the control terminal J3 of the thin-film transistor T. The active structure includes a source region, a drain region, and a channel region, with the channel region located between the source and drain regions. The source and drain regions can be electrically connected to the first electrode J1 and the second electrode J2 of the thin-film transistor T respectively via vias, or the first electrode J1 and the second electrode J2 can be directly connected to the source and drain regions respectively, or the source and drain regions can be directly reused as the first electrode J1 and the second electrode J2 of the thin-film transistor T.

[0026] The active structure can be made of various materials. For example, the active structure may include one of low-temperature polycrystalline silicon, amorphous silicon, and metal oxide. When the active structure includes low-temperature polycrystalline silicon, the thin-film transistor T typically employs a top-gate structure, meaning the control terminal J3 is located on the side of the active structure away from the substrate 10. Furthermore, an insulating layer is provided between the active structure and the control terminal J3, and vias are provided in the insulating layer. In this case, the first electrode J1 and the second electrode J2 need to pass through the insulating layer vias to achieve electrical connection with the source and drain regions. Additionally, an inorganic layer is often provided on the side of the first electrode J1 and the second electrode J2 away from the substrate 10 to meet insulation requirements. When the active structure includes amorphous silicon, the thin-film transistor T typically employs a bottom-gate structure, meaning the control terminal J3 is located on the side of the active structure facing the substrate 10. Furthermore, there is no insulating layer between the first electrode J1 and the second electrode J2 relative to the active structure; in this case, the first electrode J1 and the second electrode J2 are directly connected to the source and drain regions, respectively. In addition, the first electrode J1 and the second electrode J2 often have an inorganic layer on the side away from the substrate 10 to meet the insulation requirements.

[0027] When the active structure includes metal oxide, the thin-film transistor T can adopt either a bottom-gate structure or a top-gate structure. Taking a bottom-gate structure with a metal oxide active structure as an example, the control terminal J3 is located on the side of the active structure facing the substrate 10. Furthermore, there is no insulating layer between the first electrode J1 and the second electrode J2 relative to the active structure; in this case, the first electrode J1 and the second electrode J2 are directly connected to the source and drain regions, respectively. Additionally, an inorganic layer is often provided on the side of the first electrode J1 and the second electrode J2 away from the substrate 10 to meet insulation requirements. Taking a top-gate structure with a metal oxide active structure as an example, the control terminal J3 is located on the side of the active structure away from the substrate 10. Furthermore, an insulating layer is also provided between the first electrode J1 and the second electrode J2 relative to the active structure, and vias are provided in the insulating layer. In this case, the first electrode J1 and the second electrode J2 need to pass through the insulating layer vias to achieve electrical connection with the source and drain regions. In addition, an inorganic layer is often provided on the side of the first electrode J1 and the second electrode J2 away from the substrate 10 to meet the insulation requirements.

[0028] It should be noted that the thin-film transistor T in the embodiments of this application can be a bottom-gate structure or a top-gate structure, and the active structure of both can include low-temperature polycrystalline silicon, amorphous silicon, or metal oxide; the embodiments of this application do not impose any limitations on these. Figure 3 The diagram illustrates an active structure comprising low-temperature polycrystalline silicon and a thin-film transistor T with a top-gate structure.

[0029] In existing designs, such as Figure 1 As shown, multiple pixel electrodes arranged side by side in the row direction can jointly form an electrode row D. The scan line is located between adjacent electrode rows, that is, the orthographic projection of the scan line is completely outside the orthographic projection of the pixel electrode. Adjacent electrode rows D often have a small distance between them. Therefore, if multiple scan lines are clustered between the same adjacent electrode rows D, it is easy to cause the distance between different scan lines to be too close, resulting in a large parasitic capacitance between them, which in turn causes abnormal phenomena such as horizontal stripes in the display.

[0030] Therefore, this embodiment of the application improves the layout flexibility of multiple gate lines 20 by changing the position of at least a portion of the gate lines 20, adjusting at least a portion of the gate lines 20 to correspond to the pixel electrode 50. Furthermore, this design allows the gate lines 20 to no longer be limited to adjacent electrode rows, thereby increasing the distance between at least a portion of adjacent gate lines 20, reducing parasitic capacitance between adjacent gate lines 20, and thus improving the horizontal stripe problem of the display panel 100 and enhancing display reliability.

[0031] In some embodiments, such as Figure 2 andFigure 3 As shown, a plurality of sub-pixels 40 include a pixel column L extending along the second direction Y. The pixel column L includes at least two sub-pixels 40. In a single pixel column L, one of two adjacent gate lines 20 overlaps with a pixel electrode 50 in the pixel column L, and the other is located between adjacent pixel electrodes 50.

[0032] The phrase "multiple sub-pixels 40 including a pixel column L extending along the second direction Y" mentioned here refers to the following: multiple sub-pixels 40 arranged side-by-side in the second direction Y together form a pixel column L, and in a single pixel column L, the center lines connecting different sub-pixels 40 are parallel to the second direction Y. The display panel 100 includes multiple pixel columns L, which are arranged in the first direction X.

[0033] Typically, two adjacent gate lines 20 are located between the same adjacent sub-pixels 40 in a single pixel column L. This results in a close proximity of the two gate lines 20 and a tendency to generate large parasitic capacitance. However, in this embodiment, by adjusting the position of one of the two adjacent gate lines 20 to overlap with the pixel electrode 50, one of the two adjacent gate lines 20 overlaps with the pixel electrode 50 in the single pixel column L, while the other is located between adjacent pixel electrodes 50. This helps increase the distance between two adjacent gate lines 20, reduces the parasitic capacitance between adjacent gate lines 20, improves the horizontal stripe problem, and enhances display reliability.

[0034] In some embodiments, a single data line 30 is electrically connected to a thin-film transistor T in two adjacent pixel columns L, and two adjacent gate lines 20 are electrically connected to thin-film transistors T in different pixel columns L.

[0035] The embodiments of this application can be applied to a Dual-Gate driving architecture, that is, every two columns of sub-pixels 40 share one data line 30, and every row of sub-pixels 40 shares two gate lines 20. Specifically, in conjunction with Figure 2 For example, the multiple pixel columns L include a first pixel column L1, a second pixel column L2, a third pixel column L3 and a fourth pixel column L4 arranged from left to right; the multiple data lines 30 include a first data line 31 and a second data line 32 located to the right of the first data line 31; and the multiple gate lines 20 include a first gate line 21, a second gate line 22, a third gate line 23 and a fourth gate line 24 arranged from top to bottom.

[0036] All thin-film transistors T in the first pixel column L1 and the second pixel column L2 are electrically connected to the first data line 31, and all thin-film transistors T in the third pixel column L3 and the fourth pixel column L4 are electrically connected to the second data line 32.

[0037] The first gate line 21 is electrically connected to the thin-film transistor T of the first row of sub-pixels 40 in the first pixel column L1 and the third pixel column L3; the second gate line 22 is electrically connected to the thin-film transistor T of the first row of sub-pixels 40 in the second pixel column L2 and the fourth pixel column L4; the third gate line 23 is electrically connected to the thin-film transistor T of the second row of sub-pixels 40 in the first pixel column L1 and the third pixel column L3; and the fourth gate line 24 is electrically connected to the thin-film transistor T of the second row of sub-pixels 40 in the second pixel column L2 and the fourth pixel column L4.

[0038] In this embodiment, the Dual-Gate driving architecture helps reduce the number of data lines 30 in the display panel 100, thereby reducing the difficulty of laying out multiple data lines 30. However, the Dual-Gate driving architecture doubles the number of gate lines 20. Typically, two gate lines 20 are provided between adjacent electrode rows in the second direction Y, and a large parasitic capacitance is generated between the two gate lines 20. In view of this, this embodiment changes the position of at least some of the gate lines 20, adjusting at least some of the gate lines 20 to correspond to the pixel electrode 50, thereby increasing the distance between at least some adjacent gate lines 20, reducing the parasitic capacitance between adjacent gate lines 20, and thus improving the display stripe problem of the display panel 100 and improving display reliability.

[0039] In some embodiments, such as Figure 2 and Figure 3 As shown, a plurality of sub-pixels 40 include a pixel row H extending along a first direction X. The pixel row H includes at least two sub-pixels 40. One of two adjacent gate lines 20 overlaps with a pixel electrode 50 in the pixel row H, and the other is located between pixel electrodes 50 in adjacent pixel rows H, or on the same side of all pixel electrodes 50 in the second direction Y.

[0040] The phrase "multiple sub-pixels 40 including pixel rows H extending along the first direction X" mentioned here refers to the following: multiple sub-pixels 40 arranged side-by-side along the first direction X together form a pixel row H, and in a single pixel row H, the center lines connecting different sub-pixels 40 are parallel to the first direction X. The display panel 100 includes multiple pixel rows H, which are arranged along the second direction Y.

[0041] At least two sub-pixels 40 are arranged side by side in the first direction X to form a pixel row H, and at least two sub-pixels 40 are arranged side by side in the second direction Y to form a pixel column L. Multiple sub-pixels 40 are arrayed and arranged in the first direction X and the second direction Y. Therefore, the arrangement of multiple sub-pixels 40 in this embodiment of the application is not adjusted, and the display panel 100 still adopts the conventional real-rgb pixel arrangement.

[0042] CombinationFigure 3 In this pixel arrangement, the first gate line 21 is located on the side of the pixel electrode 50 in the first row of pixels H1 that is away from the pixel electrodes 50 in other rows of pixels H. That is, the first gate line 21 is located on the same side of the pixel electrodes 50 in all the pixel rows H in the second direction Y. The second gate line 22 is correspondingly overlapped with the pixel electrode 50 in the first row of pixels H1. The third gate line 23 is located between the pixel electrode 50 in the first row of pixels H1 and the pixel electrode 50 in the second row of pixels H2. The fourth gate line 24 is correspondingly overlapped with the pixel electrode 50 in the second row of pixels H2.

[0043] In this embodiment, some gate lines 20 overlap with all pixel electrodes 50 in a single pixel row H, while the orthographic projection of the remaining gate lines 20 onto the substrate 10 can be completely outside the orthographic projection of all pixel electrodes 50 onto the substrate 10. This design increases the distance between adjacent gate lines 20 without adjusting the pixel arrangement, simplifying pixel layout while reducing parasitic capacitance between adjacent gate lines 20 and improving the display reliability of the display panel 100.

[0044] In some embodiments, please refer to Figure 3 and Figure 5 At least a portion of the pixel electrode 50 includes a first overlapping portion 51 and a first electrode portion 52 and a second electrode portion 53 located on both sides of the overlapping portion along the second direction Y. The orthographic projection of the first overlapping portion 51 onto the substrate 10 overlaps with the orthographic projections of the gate line 20 and the thin-film transistor T onto the substrate 10. The orthographic projections of the first electrode portion 52 and the second electrode portion 53 onto the substrate 10 are located outside the orthographic projections of the gate line 20 and the thin-film transistor T onto the substrate 10. The first electrode portion 52 and the second electrode portion 53 are both integrally formed and connected to the first overlapping portion 51.

[0045] The control terminal J3 of the thin-film transistor T is electrically connected to the gate line 20, and the second terminal J2 is electrically connected to the pixel electrode 50. For some gate lines 20, the gate lines 20 are located between the pixel electrodes 50 in adjacent pixel rows H, or on the same side of the pixel electrodes 50 in the second direction Y in all pixel rows H. Based on this, in order to meet the electrical connection requirements of the thin-film transistor T relative to the gate line 20 and the pixel electrode 50, the thin-film transistor T corresponding to this part of the gate line 20 is often disposed at the edge position of the pixel electrode 50 in the second direction Y.

[0046] As for the remaining gate lines 20, since the gate lines 20 overlap with the pixel electrodes 50 in the pixel row H, and there is a certain gap between the edge of the pixel electrode 50 in the second direction Y and the gate lines 20, if the thin film transistor T corresponding to the remaining gate lines 20 is still set at the edge position of the pixel electrode 50 in the second direction Y, then the active structure in the thin film transistor T needs to be set with a larger size in the second direction Y.

[0047] In view of this, the position of some thin-film transistors T in this embodiment is adjusted. Some thin-film transistors T are adjusted from the edge position of the pixel electrode 50 in the second direction Y to the middle position of the pixel electrode 50 in the second direction Y. This allows the electrical connection requirements between the thin-film transistors T and the gate line 20 to be met without adjusting the size of the active structure in the second direction Y.

[0048] Furthermore, the pixel electrode 50 may include a first overlapping portion 51 that overlaps with the gate line 20 and the thin-film transistor T, and a first electrode portion 52 and a second electrode portion 53 disposed on both sides of the first overlapping portion 51 along the second direction Y. The first electrode portion 52 and the second electrode portion 53 are both integrally connected to the first overlapping portion 51. This design allows the pixel electrode 50 to have the same structural shape as the pixel electrode in the prior art. Thus, the present application embodiment can improve the horizontal stripe problem of the display panel 100 without changing the pixel arrangement or the structural shape of the pixel electrode 50, thereby reducing the design and manufacturing difficulty of the display panel 100 and improving the display reliability of the display panel 100.

[0049] Furthermore, in this design, the projection of the thin-film transistor T in the first pixel column L1 onto the first direction X is outside the projection of the thin-film transistor T in the second pixel column L2 onto the first direction X. That is, the thin-film transistors T in adjacent pixel columns L are staggered in the second direction Y, thereby increasing the distance between the thin-film transistors T in the second direction Y and improving the interference between different thin-film transistors T.

[0050] In some alternative embodiments, the first electrode portion 52 and the second electrode portion 53 have the same size in the second direction Y, that is, a portion of the gate line 20 is located in the central region of the pixel electrode 50 in the second direction Y, thereby achieving a centered design of the gate line 20 relative to the pixel electrode 50, which helps to improve the display uniformity of the display panel 100.

[0051] In some embodiments, see [link to relevant documentation] Figure 6 and Figure 7The plurality of pixel columns L includes a first pixel column L1 and a second pixel column L2. The gap between two adjacent pixel electrodes 50 in the first pixel column L1 overlaps with the projection of the pixel electrodes 50 in the second pixel column L2 in the first direction X. One of two adjacent gate lines 20 overlaps with the pixel electrodes 50 in the first pixel column L1 and is located between adjacent pixel electrodes 50 in the second pixel column L2, and the other overlaps with the pixel electrodes 50 in the second pixel column L2 and is located between adjacent pixel electrodes 50 in the first pixel column L1.

[0052] Unlike the aforementioned embodiments, this application adjusts the pixel arrangement. Specifically, the gap between two adjacent pixel electrodes 50 in the first pixel column L1 overlaps with the pixel electrodes 50 in the second pixel column L2 in the first direction X, and the gap between two adjacent pixel electrodes 50 in the second pixel column L2 overlaps with the pixel electrodes 50 in the first pixel column L1 in the first direction X. In other words, the sub-pixels 40 in the same row of the first pixel column L1 and the second pixel column L2 are not arranged side by side in the first direction X, and the center line connecting the sub-pixels 40 in the same row of the first pixel column L1 and the second pixel column L2 intersects the first direction X.

[0053] For the multiple gate lines 20, the first gate line 21 overlaps with the pixel electrode 50 in the second pixel column L2 and is located between adjacent pixel electrodes 50 in the first pixel column L1. The second gate line 22 overlaps with the pixel electrode 50 in the first pixel column L1 and is located between adjacent pixel electrodes 50 in the second pixel column L2. Furthermore, the thin-film transistor T for electrically connecting to the pixel electrode 50 in the first pixel column L1 and the first gate line 21 is located at the edge of the pixel electrode 50 in the second direction Y. Similarly, the thin-film transistor T for electrically connecting to the pixel electrode 50 in the second pixel column L2 and the second gate line 22 is also located at the edge of the pixel electrode 50 in the second direction Y.

[0054] In summary, in this embodiment, in addition to adjusting the position of some gate lines 20, the pixel arrangement is also adjusted. Based on this, adjacent gate lines 20 overlap with pixel electrodes 50, and pixel electrodes 50 in adjacent pixel columns L overlap with different gate lines 20. Furthermore, in this design, each thin-film transistor T is located at the edge of the pixel electrode 50 in the second direction Y. Therefore, different pixel electrodes 50 and their corresponding thin-film transistors T can have similar relative positional relationships. This reduces design complexity and helps improve the display differences between different sub-pixels 40, thereby increasing the display accuracy of the display panel 100.

[0055] Furthermore, under this design, the thin-film transistors T in adjacent pixel columns L can also be staggered in the second direction Y, thereby increasing the distance between the thin-film transistors T in the pixel column L in the second direction Y and improving the interference effect between different thin-film transistors T.

[0056] It should be noted that the thin-film transistors T corresponding to the first pixel column L1 and the second pixel column L2 are electrically connected to the same data line 30. Therefore, the data line 30 can transmit data signals to both the pixel electrodes 50 in the first pixel column L1 and the pixel electrodes 50 in the second pixel column L2. Furthermore, the thin-film transistors T corresponding to the first pixel column L1 and the second pixel column L2 are located on different sides of the single data line 30 in the first direction X.

[0057] The positional relationship between the pixel electrode 50 and the thin-film transistor T is not limited in the embodiments of this application. Optionally, as... Figure 3 As shown, the thin-film transistor T electrically connected to the pixel electrode 50 in the second pixel column L2 is not completely located within the orthogonal projection of the pixel electrode 50 onto the substrate 10, but is overlapped relative to two adjacent pixel electrodes 50 in the second pixel column L2. This helps to increase the distance between the thin-film transistor T corresponding to the first pixel column L1 and the thin-film transistor T corresponding to the second pixel column L2 in the second direction Y, thereby reducing the interference between different thin-film transistors T.

[0058] In some embodiments, please refer to Figure 8 The plurality of pixel electrodes 50 include a first electrode 50a and a second electrode 50b located adjacent to each other in the second pixel column L2. The second electrode 50b is provided with a recessed space K. The orthographic projection of the thin film transistor T electrically connected to the first electrode 50a on the substrate 10 overlaps with the orthographic projection of the recessed space K on the substrate 10.

[0059] The recessed space K is located on the side of the second electrode 50b close to the first electrode 50a, and the opening of the recessed space K in the second direction Y faces the first electrode 50a, and the opening of the recessed space K in the first direction X faces the data line 30 located between the first pixel column L1 and the second pixel column L2.

[0060] In this embodiment, by overlapping the orthographic projection of the thin-film transistor T electrically connected to the first electrode 50a onto the substrate 10 with the orthographic projection of the recessed space K onto the substrate 10, it helps to increase the distance between the thin-film transistor T corresponding to the first pixel column L1 and the thin-film transistor T corresponding to the second pixel column L2 in the second direction Y, thereby reducing the interference between different thin-film transistors T. On the other hand, it helps to reduce the interference of the thin-film transistor T electrically connected to the first electrode 50a on the second electrode 50b, thereby improving the display reliability of the display panel 100.

[0061] In some embodiments, such as Figure 8 As shown, the pixel electrode 50 in the first pixel column L1 includes a second overlapping portion 54 and a third electrode portion 55 and a fourth electrode portion 56 located on both sides of the second overlapping portion 54 along the second direction Y. The orthographic projection of the second overlapping portion 54 on the substrate 10 overlaps with the orthographic projection of the gate line 20 on the substrate 10. The projections of the third electrode portion 55 and the fourth electrode portion 56 on the first direction X overlap with the projections of the adjacent pixel electrode 50 in the second pixel column L2 on the first direction X, respectively.

[0062] The second overlapping portion 54 is the part of the structure where the pixel electrode 50 and the gate line 20 overlap in the first pixel column L1. Since the gate line 20 and the corresponding overlapping pixel electrode 50 are not electrically connected to the same thin-film transistor T, the orthographic projection of the second overlapping portion 54 onto the substrate 10 is located outside the orthographic projection of the thin-film transistor T onto the substrate 10. The third electrode portion 55 and the fourth electrode portion 56 are respectively located on both sides of the overlapping portion in the second direction Y, and the orthographic projections of both onto the substrate 10 are located outside the orthographic projection of the gate line 20 onto the substrate 10. Optionally, the third electrode portion 55 and the fourth electrode portion 56 are both integrally connected to the second overlapping portion 54.

[0063] Furthermore, in this embodiment, the third electrode portion 55 and the fourth electrode portion 56 are respectively overlapped with different pixel electrodes 50 in the second pixel column L2 in the first direction X, thereby realizing the staggered distribution of sub-pixels 40 in adjacent pixel columns L in the second direction Y, thereby increasing the equivalent visual performance of pixel density, reducing moiré patterns and jagged effects, and making it smoother, especially when displaying fine patterns or text.

[0064] In some alternative embodiments, the third pole portion 55 has the same size in the second direction Y as the fourth pole portion 56 in the second direction Y, which helps to make the pixel arrangement design of the multiple sub-pixels 40 more uniform, thereby further improving the display effect.

[0065] In some embodiments, please refer to Figure 9 and Figure 10 At least a portion of the pixel electrode 50 includes a first domain portion 57 and a second domain portion 58 connected and disposed in the second direction Y, wherein the extending directions of the first domain portion 57 and the second domain portion 58 intersect. The orthographic projection of the gate line 20 onto the substrate 10 overlaps with the orthographic projection of the connection region 59 of the first domain portion 57 and the second domain portion 58 onto the substrate 10.

[0066] The pixel electrode 50 includes a first domain portion 57 and a second domain portion 58 that are connected and intersect in their extending directions. That is, the display panel 100 of this application embodiment has a dual-domain pixel structure. By setting the extending directions of the first domain portion 57 and the second domain portion 58 in the pixel electrode 50 to intersect at a certain angle, two domain regions can be formed within a sub-pixel 40 area. In different viewing angle directions, the viewing angles of the two domain regions where the first domain portion 57 and the second domain portion 58 are located in a single pixel electrode 50 can be complementary, thereby solving the problem of viewing angle in the horizontal or vertical direction during display, improving the viewing angle of the display panel 100, and improving the display quality.

[0067] Research revealed that the connection region 59 between the first domain 57 and the second domain 58 often corresponds to a dark area, meaning the light transmittance of the display panel 100 is significantly reduced at the connection region 59. Therefore, in this embodiment, the gate line 20 overlapping with the pixel electrode 50 is configured to overlap with the connection region 59, thereby reducing the adverse effects on the display effect caused by the overlap of the gate line 20 and the pixel electrode 50. Optical simulation showed that setting the gate line 20 to overlap with the connection region 59 resulted in a light effect simulation difference of approximately 0.6%, indicating that the display deviation caused by this design is negligible.

[0068] Next, the positional relationship between the gate line 20 and the pixel electrode 50 will be described in detail with reference to the accompanying drawings, such as... Figure 9 As shown, in this case, the orthographic projections of the first gate line 21 and the third gate line 23 on the substrate 10 are both located outside the orthographic projections of all pixel electrodes 50 on the substrate 10, while the orthographic projections of the second gate line 22 and the fourth gate line 24 on the substrate 10 overlap with the orthographic projections of the connection regions 59 of all pixel electrodes 50 located in the same row on the substrate 10.

[0069] like Figure 10 As shown, in this case, the orthographic projections of the first gate line 21 and the third gate line 23 onto the substrate 10 both overlap with the orthographic projections of the connection regions 59 of the pixel electrodes 50 in the second pixel column L2 onto the substrate 10, and both are located outside the orthographic projections of the connection regions 59 of the pixel electrodes 50 in the first pixel column L1 onto the substrate 10. Similarly, the orthographic projections of the second gate line 22 and the fourth gate line 24 onto the substrate 10 both overlap with the orthographic projections of the connection regions 59 of the pixel electrodes 50 in the first pixel column L1 onto the substrate 10, and both are located outside the orthographic projections of the connection regions 59 of the pixel electrodes 50 in the second pixel column L2 onto the substrate 10.

[0070] It should be noted that the liquid crystal layer often has a light-shielding layer 71 on the side facing away from the substrate 10 to block the metal traces such as the data line 30 and the gate line 20. Since the connection region 59 is itself a dark display area, the presence of this dark display area can itself block part of the structure in the gate line 20. Therefore, in some optional embodiments, the orthographic projection of the part of the structure in the gate line 20 that overlaps with the connection region 59 onto the substrate 10 is outside the orthographic projection of the light-shielding layer 71 onto the substrate 10. In other words, by setting at least a portion of the gate line 20 and the pixel electrode 50 to overlap at the connection region 59, this application can ensure that the orthographic projection of at least a portion of the structure in the gate line 20 onto the substrate 10 is outside the light-shielding layer 71.

[0071] Please see Figure 4 and Figure 11 In some embodiments, the display panel 100 includes a liquid crystal layer 80 and a color filter substrate 70. The liquid crystal layer 80 is located on the side of the pixel electrode 50 away from the substrate 10, and the color filter substrate 70 is disposed on the side of the liquid crystal layer 80 away from the substrate 10.

[0072] It should be noted that the color filter substrate 70 and the pixel electrode 50 are disposed on different sides of the liquid crystal layer 80. However, the common electrode 60 and the color filter substrate 70 can be located on the same side of the liquid crystal layer 80, or the common electrode 60 can be located on the same side of the liquid crystal layer 80 as the pixel electrode 50; this embodiment does not impose any limitations. Furthermore, when the common electrode 60 and the pixel electrode 50 are located on the same side of the liquid crystal layer 80, such as... Figure 4 As shown, the common electrode 60 can be located on the side of the pixel electrode 50 facing away from the substrate 10, or as... Figure 11 As shown, the common electrode 60 can be located on the side of the pixel electrode 50 facing the substrate 10.

[0073] In some embodiments, please refer to Figure 2 , Figure 3 and Figure 12 The color filter substrate 70 includes a light-shielding layer 71, which includes a first light-shielding portion 711 extending along a first direction X. The orthographic projection of the first light-shielding portion 711 onto the substrate 10 overlaps with the orthographic projection of at least a portion of the gate line 20 onto the substrate 10. The width of the first light-shielding portion 711 in the second direction Y is W, where W ≤ 25 μm. Optionally, W is one of 19 μm, 20 μm, 21 μm, 22 μm, 24 μm, and 25 μm.

[0074] The light-shielding layer 71 includes a light-shielding material. On the one hand, the light-shielding layer 71 can block the metal traces to improve the reflection problem. On the other hand, the light-shielding layer 71 can separate the filters in different sub-pixels 40, thereby reducing the risk of crosstalk between different colors of light and improving the display effect of the display panel 100.

[0075] The first light-shielding portion 711 is a part of the light-shielding layer 71 used to block the gate line 20. Similar to the gate line 20, the first light-shielding portion 711 also needs to extend along the first direction X, and multiple first light-shielding portions 711 need to be spaced apart in the second direction Y. Based on this, the width W of the first light-shielding portion 711 is the size of the first light-shielding portion 711 in the second direction Y. Depending on the actual needs, each gate line 20 can overlap with the first light-shielding portion 711 to be blocked, or some gate lines 20 can not overlap with the first light-shielding portion 711. This application embodiment does not limit this.

[0076] In existing designs, multiple scan lines converge between adjacent electrode rows. As a result, the light-shielding material located between adjacent electrode rows needs to cover multiple scan lines simultaneously, leading to a large width of the light-shielding material.

[0077] However, in this embodiment, by adjusting the position of at least some of the gate lines 20, a larger distance is achieved between adjacent gate lines 20, and only a single gate line 20 exists between two adjacent pixel electrodes 50 in the second direction Y. Based on this, a single first light-shielding portion 711 only needs to cover a single gate line 20, thereby helping to reduce the width W of the first light-shielding portion 711, ensuring that the width W is no greater than 25 μm, thus helping to improve the aperture ratio of the display panel 100. Experimental verification shows that this design can increase the aperture ratio of the display panel 100 by approximately 1%.

[0078] In some embodiments, please refer to Figure 8 , Figure 10 and Figure 13 At least a portion of the gate line 20 includes a trace overlap portion that overlaps with the pixel electrode 50, and the orthogonal projection of the at least portion of the trace overlap portion on the substrate 10 is located outside the orthogonal projection of the light-shielding layer 71 on the substrate 10.

[0079] At least a portion of the gate lines 20 overlap with pixels, and the portion of the gate lines 20 that overlaps with the pixel electrode 50 is the trace overlap section. As can be seen from the foregoing, by providing the display panel 100 with a dual-domain pixel structure and setting the trace overlap section to overlap with the connection area 59, the display effect will not be significantly affected even if the trace overlap section is not obstructed.

[0080] In view of this, in the embodiments of this application, at least a portion of the overlapping portion of the traces is positioned outside the orthogonal projection of the light-shielding layer 71 on the substrate 10, thereby reducing the overlapping area between the light-shielding layer 71 and the sub-pixel 40, reducing the shading of the sub-pixel 40 by the light-shielding layer 71, and improving the aperture ratio and display effect of the display panel 100.

[0081] It should be noted that, depending on the actual needs, the orthographic projection of each overlapping trace on the substrate 10 can be all located outside the orthographic projection of the light-shielding layer 71 on the substrate 10, or the orthographic projection of some overlapping traces on the substrate 10 can be located within the orthographic projection of the light-shielding layer 71 on the substrate 10. This embodiment of the present application does not impose any limitations on this. Optionally, the orthographic projection of the overlapping traces that overlap with the thin-film transistor T on the substrate 10 can be located within the orthographic projection of the light-shielding layer 71 on the substrate 10. This helps to improve the shielding effect of the light-shielding layer 71 on the thin-film transistor T.

[0082] In some embodiments, the color filter substrate 70 includes a light-shielding layer 71, which includes a second light-shielding portion 712, a third light-shielding portion 713, and a fourth light-shielding portion 714. The second light-shielding portion 712 extends along the second direction Y and overlaps with the data line 30. The third light-shielding portion 713 and the fourth light-shielding portion 714 are connected to the two sides of the second light-shielding portion 712 along the first direction X and are respectively overlapped with different thin-film transistors T. The projection of the third light-shielding portion 713 in the first direction X is outside the projection of the fourth light-shielding portion 714 in the first direction X.

[0083] In addition to the first light-shielding portion 711, the light-shielding layer 71 may also include a second light-shielding portion 712, a third light-shielding portion 713, and a fourth light-shielding portion 714. The second light-shielding portion 712 is used to block the data cable 30. Similar to the data cable 30, the second light-shielding portion 712 also extends along the second direction Y, and multiple second light-shielding portions 712 are spaced apart in the first direction X. The first light-shielding portion 711 and the second light-shielding portion 712 are intersecting and distributed to form multiple opening structures, so as to... Figure 1 and Figure 8 Taking the structure shown as an example, a single opening structure can be set to correspond to two sub-pixels 40.

[0084] Both the third light-shielding portion 713 and the fourth light-shielding portion 714 are used to block the thin-film transistor T, and they are connected to different sides of the second light-shielding portion 712 in the first direction X, so as to meet the blocking requirements of the thin-film transistor T in different pixel columns L. For example, the third light-shielding portion 713 is used to block the thin-film transistor T in the first pixel column L1, and the fourth light-shielding portion 714 is used to block the thin-film transistor T in the second pixel column L2.

[0085] Based on the foregoing, it can be seen that, whether Figure 2 and Figure 12 The structure shown is stillFigure 8 and Figure 13 In the structure shown, the thin-film transistors T in adjacent pixel columns L are all staggered in the second direction Y. On this basis, the third light-shielding part 713 and the fourth light-shielding part 714, which correspond to the thin-film transistors T in adjacent pixel columns L, are also staggered in the second direction Y. In this way, the third light-shielding part 713 and the fourth light-shielding part 714 are no longer clustered in the same area. This can reduce the problem of local dark spots appearing in the display panel 100 due to excessive accumulation of light-shielding material and improve the display uniformity of the display panel 100.

[0086] Secondly, please refer to Figure 14 This application provides a display device 200, which includes a display panel 100 as described in any of the foregoing embodiments.

[0087] The display device 200 provided in this application embodiment has the beneficial effects of the display panel 100 in any of the foregoing embodiments. For details, please refer to the foregoing description of the beneficial effects of the display panel 100. This application embodiment will not repeat the details.

[0088] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit the invention. Any person skilled in the art to which this application pertains may make any modifications and changes in form and detail of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

[0089] The above description is merely a specific embodiment of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, substitutions for other connection methods described above can be made by referring to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: Substrate; Multiple gate lines extend along a first direction; Multiple data lines extend along a second direction, where the first direction intersects the second direction and are both parallel to the plane of the substrate. Multiple sub-pixels, each sub-pixel including a thin-film transistor and a pixel electrode, wherein the control terminal of the thin-film transistor is electrically connected to the gate line, the first electrode is electrically connected to the data line, and the second electrode is electrically connected to the pixel electrode; Wherein, at least a portion of the gate line's orthogonal projection on the substrate overlaps with the pixel electrode's orthogonal projection on the substrate.

2. The display panel according to claim 1, characterized in that, The plurality of sub-pixels include a pixel column extending along the second direction, the pixel column including at least two of the sub-pixels, wherein in a single pixel column, one of two adjacent gate lines overlaps with a pixel electrode in the pixel column, and the other is located between adjacent pixel electrodes in the pixel column.

3. The display panel according to claim 2, characterized in that, A single data line is electrically connected to the thin-film transistors in two adjacent pixel columns, and two adjacent gate lines are electrically connected to the thin-film transistors in different pixel columns.

4. The display panel according to claim 2, characterized in that, The plurality of sub-pixels include pixel rows extending along the first direction, each pixel row including at least two of the sub-pixels, one of two adjacent gate lines overlapping with a pixel electrode in the pixel row, and the other located between pixel electrodes in adjacent pixel rows, or located on the same side of the pixel electrodes in all the pixel rows in the second direction.

5. The display panel according to claim 4, characterized in that, At least a portion of the pixel electrode includes a first overlapping portion and a first electrode portion and a second electrode portion located on both sides of the overlapping portion along the second direction. The orthographic projection of the first overlapping portion onto the substrate overlaps with the orthographic projection of the gate line and the thin film transistor onto the substrate. The orthographic projections of the first electrode portion and the second electrode portion onto the substrate are located outside the orthographic projections of the gate line and the thin film transistor onto the substrate. Both the first pole portion and the second pole portion are integrally connected to the first overlapping portion.

6. The display panel according to claim 2, characterized in that, The plurality of pixel columns include a first pixel column and a second pixel column, wherein the gap between two adjacent pixel electrodes in the first pixel column overlaps with the projection of the pixel electrodes in the second pixel column in the first direction; One of the two adjacent gate lines overlaps with the pixel electrode in the first pixel column and is located between adjacent pixel electrodes in the second pixel column; the other overlaps with the pixel electrode in the second pixel column and is located between adjacent pixel electrodes in the first pixel column.

7. The display panel according to claim 6, characterized in that, The plurality of pixel electrodes include a first electrode and a second electrode located within and adjacent to each other in the second pixel column. The second electrode has a recessed space. The orthographic projection of the thin-film transistor electrically connected to the first electrode on the substrate overlaps with the orthographic projection of the recessed space on the substrate.

8. The display panel according to claim 6, characterized in that, The pixel electrode in the first pixel column includes a second overlapping portion and a third electrode portion and a fourth electrode portion located on both sides of the second overlapping portion along the second direction. The orthographic projection of the second overlapping portion on the substrate overlaps with the orthographic projection of the gate line on the substrate. The projections of the third electrode portion and the fourth electrode portion in the first direction overlap with the projections of the adjacent pixel electrode in the second pixel column in the first direction, respectively.

9. The display panel according to claim 1, characterized in that, At least a portion of the pixel electrode includes a first domain and a second domain connected and disposed in the second direction, the first domain intersecting the extending direction of the second domain; Wherein, the orthographic projection of the gate line on the substrate overlaps with the connection region of the first domain and the second domain on the orthographic projection of the substrate.

10. The display panel according to claim 1, characterized in that, It also includes a liquid crystal layer and a color filter substrate, wherein the liquid crystal layer is located on the side of the pixel electrode opposite to the substrate, and the color filter substrate is disposed on the side of the liquid crystal layer opposite to the substrate.

11. The display panel according to claim 10, characterized in that, The color filter substrate includes a light-shielding layer, the light-shielding layer includes a first light-shielding portion extending along the first direction, and the orthographic projection of the first light-shielding portion on the substrate overlaps with the orthographic projection of at least a portion of the gate line on the substrate. Wherein, the width dimension of the first light-shielding part in the second direction is W, and W satisfies: W≤25μm.

12. The display panel according to claim 11, characterized in that, At least a portion of the gate line includes a trace overlap portion that overlaps with the pixel electrode, and the orthogonal projection of at least a portion of the trace overlap portion onto the substrate is located outside the orthogonal projection of the light-shielding layer onto the substrate.

13. The display panel according to claim 10, characterized in that, The color filter substrate includes a light-shielding layer, which includes a second light-shielding portion, a third light-shielding portion, and a fourth light-shielding portion. The second light-shielding portion extends along the second direction and overlaps with the data line. The third light-shielding portion and the fourth light-shielding portion are connected to both sides of the second light-shielding portion along the first direction and are respectively overlapped with different thin-film transistors. Wherein, the projection of the third light-shielding part in the first direction is located outside the projection of the fourth light-shielding part in the first direction.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

Images