Display device, method of manufacturing the same, and electronic device including the same

Abstract

The invention discloses a display device, a method of manufacturing the same, and an electronic device including the same. The display device includes a substrate including a display area and a non-display area adjacent to the display area. A first dam is disposed in the non-display area. The second dam is disposed in the non-display area. An alignment mark is provided between the first dam and the second dam, and is provided as an opening in the metal layer. A planarization layer is disposed on the first dam, the second dam, and the alignment mark. The optical functional layer is disposed on the planarization layer. The entire upper surface of the planarization layer overlapping the alignment mark is adhered to the entire lower surface of the optical functional layer disposed on the planarization layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0135973, filed with the Korean Intellectual Property Office on October 7, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to display devices including alignment marks located between dams, methods of manufacturing the display devices, and electronic devices including the display devices. Background Technology

[0003] Display devices are used to visually present data, and their size can vary depending on their application. For example, display devices can be integrated into small products such as mobile phones or larger products such as televisions.

[0004] The display device includes a plurality of pixels that receive electrical signals and emit light to display an image to a user. Each of the pixels includes a display element, and for example, an organic light-emitting diode (OLED) display device includes an organic light-emitting diode (OLED) as the display element. Typically, in an OLED display device, thin-film transistors and OLEDs are formed on a substrate, and the OLEDs operate by emitting light.

[0005] Recently, as the uses of display devices have become more diversified, various designs have been tried to improve the quality of display devices. Summary of the Invention

[0006] One or more embodiments include a display device with improved reliability and quality, a method of manufacturing the display device, and an electronic device including the display device. The embodiments set forth herein are examples, and the scope of this disclosure is not limited thereto.

[0007] The display device includes a substrate comprising a display area and a non-display area adjacent to the display area. A first dam is disposed in the non-display area. A second dam is disposed in the non-display area. An alignment mark is disposed between the first dam and the second dam and is provided as an opening in a metal layer. A planarization layer is disposed on the first dam, the second dam, and the alignment mark. An optical functional layer is disposed on the planarization layer. The entire upper surface of the planarization layer, overlapping the alignment mark, adheres to the entire lower surface of the optical functional layer disposed on the planarization layer.

[0008] The entire upper surface of the planarization layer that overlaps with the alignment mark can be flat.

[0009] The display device may further include shaders installed on the first and second dams.

[0010] The light shield can have an opening that overlaps with the alignment mark.

[0011] The light shield can have an opening that overlaps with the opening of the metal layer.

[0012] The shading device can be installed on the upper surface of the first dam.

[0013] The shading device can be installed on the upper surface of the second dam.

[0014] The first and second dams may each include organic insulating materials and / or inorganic insulating materials.

[0015] The display device may further include: a thin-film transistor disposed in the display area, and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

[0016] The metal layer may include the same material as the source electrode or drain electrode.

[0017] A method for manufacturing a display device includes: forming a metal layer on a substrate; forming an alignment mark by forming an opening in the metal layer; the alignment mark being formed between a first dam and a second dam; a light shield being formed on the first dam and the second dam; an opening being formed in the light shield, the opening overlapping the alignment mark; a first planarization layer being formed on the alignment mark and the light shield; and a second planarization layer being formed on the first planarization layer, the second planarization layer overlapping the alignment mark.

[0018] At least a portion of the upper surface of the first planarization layer that overlaps with the alignment mark may be concave.

[0019] The upper surface of the second planarization layer that overlaps with the alignment mark can be flat.

[0020] The method may further include forming an optical functional layer on the second planarization layer.

[0021] The entire upper surface of the second planarization layer can adhere to the entire lower surface of the optical functional layer.

[0022] The shading device can be installed on the upper surface of the first dam.

[0023] The shading device can be installed on the upper surface of the second dam.

[0024] The method may further include forming a thin-film transistor disposed on a substrate and including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode.

[0025] The metal layer may include the same material as the source electrode or drain electrode.

[0026] The opening of the light shield can overlap with the opening of the metal layer.

[0027] An electronic device includes a substrate comprising a display area and a non-display area adjacent to the display area. A first dam is disposed in the non-display area. A second dam is disposed in the non-display area. An alignment mark is disposed between the first dam and the second dam and is provided as an opening in a metal layer. A planarization layer is disposed on the first dam, the second dam, and the alignment mark. An optical functional layer is disposed on the planarization layer. The entire upper surface of the planarization layer, overlapping the alignment mark, adheres to the entire lower surface of the optical functional layer disposed on the planarization layer. Attached Figure Description

[0028] The above and other aspects and features of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a plan view of the display device according to an embodiment;

[0030] Figure 2 It is along Figure 1 A schematic cross-sectional view of the display device taken by line I-I';

[0031] Figure 3 yes Figure 1 A schematic enlarged plan view of region A;

[0032] Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device taken from line II-II';

[0033] Figures 5 to 11 It is a schematic cross-sectional view illustrating a method for manufacturing a display device;

[0034] Figure 12 This is a block diagram of an electronic device according to an embodiment; and

[0035] Figure 13 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0036] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals may refer to the same elements throughout the specification and drawings. In this respect, the present embodiments may take different forms and should not necessarily be construed as limited to the description set forth herein. Accordingly, the following embodiments are described with reference to the accompanying drawings to illustrate aspects of the present description. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b, and c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0037] Because this disclosure allows for various modifications and numerous embodiments, specific embodiments will be illustrated in the accompanying drawings and described in detail in the written description. Reference is made to the accompanying drawings, which illustrate one or more embodiments, to obtain a sufficient understanding of their advantages and the objectives achieved through implementation. However, embodiments may take different forms and should not necessarily be construed as limited to the description set forth herein.

[0038] If an element is not described in detail with respect to this figure, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0039] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various components, these components should not necessarily be limited by these terms. These terms are used to distinguish one component from another.

[0040] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0041] It will be further understood that the terms “comprising,” “having,” and / or variations thereof, as used herein, indicate the presence of a stated feature or component, but do not preclude the presence or addition of one or more other features or components.

[0042] It will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be formed directly or indirectly on that other layer, region, or component. For example, an intermediary layer, region, or component may exist.

[0043] Although each figure may represent one or more specific embodiments of the present disclosure and is drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them, it will be understood that the invention is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be varied within the spirit and scope of the present disclosure, for example, to account for manufacturing limitations, etc.

[0044] When an embodiment can be implemented differently, the specific process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0045] In this specification, expressions such as "A and / or B" mean A, B, or A and B. Additionally, expressions such as "at least one of A and B" mean A, B, or A and B.

[0046] In the following embodiments, when layers, regions, or components are connected to each other, these layers, regions, or components may be directly connected to each other, or another layer, another region, or another component may be located between these layers, regions, or components, and therefore, these layers, regions, or components may be indirectly connected to each other. For example, in the following embodiments, when layers, regions, or components are electrically connected to each other, these layers, regions, or components may be directly electrically connected to each other, or another layer, another region, or another component may be located between these layers, regions, or components, and therefore, these layers, regions, or components may be indirectly electrically connected to each other.

[0047] The x-axis, y-axis, and z-axis are not limited to the three axes of the Cartesian coordinate system and can be interpreted in a general sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0048] Exemplary embodiments of the present invention relate to an improved structural design and manufacturing process for a display device to enhance reliability and optical performance. The display device includes a planarization layer and an optical functional layer, both of which are finely constructed to prevent defects such as bubbles that could degrade display quality.

[0049] A key innovation is the introduction of alignment marks in the non-display areas of the display device. These alignment marks, formed as openings in the metal layer, play a crucial role in the manufacturing precision of the display device. To maintain the visibility and effectiveness of these alignment marks, the design includes a planarization layer with a flat surface that ensures complete adhesion to the optical functional layers. This prevents the formation of bubbles or voids, which could otherwise affect the quality and reliability of the display device.

[0050] In addition, a multi-layered dam structure can be used around the alignment marks. This structure provides several functions, such as preventing the organic encapsulation layer from overflowing and supporting the manufacturing mask used during processing. A light shield is also introduced to enhance contrast and visibility by reducing external light interference.

[0051] The manufacturing method includes a double-layer planarization process, in which an initial planarization layer is applied, which may have surface irregularities, and then a second planarization layer is used to correct these irregularities. This ensures that optical functional layers, such as polarizers, are properly adhered without defects. The display device can also be embodied as an electronic device.

[0052] Accordingly, embodiments of this disclosure can provide structural and manufacturing improvements aimed at enhancing the optical clarity, alignment accuracy, and reliability of modern display devices, particularly those using organic light-emitting diodes and thin-film transistors.

[0053] Figure 1 This is a plan view of the display device 10 according to an embodiment.

[0054] refer to Figure 1 The display device 10 may include a substrate 100. The substrate 100 may include a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image. The non-display area NDA may surround at least a portion of the display area DA. For example, the non-display area NDA may be adjacent to one or more sides of the display area DA. The non-display area NDA may be an area where no image is displayed.

[0055] Pixel PX can be entirely disposed within the display area DA. Pixel PX can emit light to display an image. Additionally, wiring connected to and configured to transmit signals to pixel PX can be disposed within the display area DA. For example, the wiring may include data lines DL configured to transmit data signals and gate lines GL configured to transmit gate signals.

[0056] At least one dam can be disposed on the substrate 100 in the non-display area NDA. For example, a first dam DAM1 and a second dam DAM2 can be disposed in the non-display area NDA.

[0057] The first dam DAM1 can be positioned around the periphery of the display area DA. The first dam DAM1 can surround the display area DA. The first dam DAM1 can limit the organic encapsulation layer (e.g., ...) positioned within the display area DA. Figure 2 (Organic encapsulation layer 320 in the image). For example, the first dam DAM1 can prevent the organic encapsulation layer from overflowing to the periphery of the non-display area NDA.

[0058] The second dam DAM2 can be disposed around the periphery of the display area DA. The second dam DAM2 can surround the first dam DAM1. During the manufacturing process of the display device 10, the second dam DAM2 can support the mask located on the display device 10. The mask can pass through the second dam DAM2 without directly contacting the display panel included in the display device 10. However, this disclosure is not limited to this.

[0059] Alignment marks AM can be set in the non-display area NDA. Alignment marks AM can be used during the manufacturing process. For example, alignment marks AM can indicate the location of components required for the manufacturing process of display device 10. Although in Figure 1 The diagram shows 12 alignment marks AM, but this is just an example, and the alignment marks AM can be set on the substrate 100 in various ways within the range where the parts can be precisely positioned.

[0060] For example, alignment marks AM may be provided only on the side of substrate 100. Alternatively, alignment marks AM may be provided only at each corner of the upper surface of substrate 100. However, this disclosure is not limited to this.

[0061] Figure 2It is along Figure 1 A schematic cross-sectional view of the display device 10 taken by line I-I'.

[0062] refer to Figure 1 and Figure 2 The display device 10 may include a display panel DP, a touch layer 400, a light shield BM, a color filter CF, and a planarization layer 500. In the display area DA, the display panel DP may include a substrate 100, a buffer layer 111, insulating layers 112, 113, 114, 115, 116, and 118, a thin-film transistor (TFT), a data line DL, a connection electrode CM, an organic light-emitting diode (OLED), and an encapsulation layer 300.

[0063] A buffer layer 111 can be disposed on the substrate 100. The buffer layer 111 can be disposed in the display area DA and the non-display area NDA. The buffer layer 111 can prevent metal atoms or other impurities from diffusing from the substrate 100 to the semiconductor layer ACT.

[0064] A thin-film transistor (TFT) can be disposed on the substrate 100 in the display area DA. The TFT may include an oxide layer (i.e., a semiconductor layer ACT), a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0065] In the display area DA, the semiconductor layer ACT can be disposed on the buffer layer 111. The semiconductor layer ACT can be divided into source and drain regions, each doped with impurities, and a channel region located between the source and drain regions.

[0066] The first insulating layer 112 may be disposed on the buffer layer 111. In the display area DA, the first insulating layer 112 may cover the semiconductor layer ACT and may be continuously disposed on the substrate 100 (e.g., configured as a continuous structure without breaks or interruptions). However, embodiments according to this disclosure are not limited thereto. In embodiments, the first insulating layer 112 may comprise an inorganic material.

[0067] In the display area DA, the gate electrode GE can be disposed on the first insulating layer 112. The gate electrode GE can overlap with the channel region of the semiconductor layer ACT.

[0068] The second insulating layer 113 may be disposed on the first insulating layer 112. Alternatively, the second insulating layer 113 may be continuously disposed on the substrate 100 to cover the gate electrode GE. However, embodiments according to this disclosure are not limited to this. In embodiments, the second insulating layer 113 may comprise an inorganic material.

[0069] In the display area DA, the upper electrode CE2 can be disposed on the second insulating layer 113. The upper electrode CE2 can be a capacitor electrode. The lower electrode CE1 can be integrally disposed below the upper electrode CE2 with the gate electrode GE. The upper electrode CE2 and the lower electrode CE1 can form a capacitor Cst.

[0070] The third insulating layer 114 may be disposed on the second insulating layer 113. Furthermore, the third insulating layer 114 may cover the upper electrode CE2 and may be continuously disposed on the substrate 100. However, this disclosure is not limited thereto. In embodiments, the third insulating layer 114 may comprise an inorganic material.

[0071] In the display area DA, the source electrode SE, drain electrode DE, data line DL, etc. can be disposed on the third insulating layer 114.

[0072] The source electrode SE can be connected to the source region of the semiconductor layer ACT through contact holes formed in the first to third insulating layers 112, 113 and 114. The drain electrode DE can be connected to the drain region of the semiconductor layer ACT through contact holes formed in the first to third insulating layers 112, 113 and 114.

[0073] In the display area DA, a fourth insulating layer 115 may be disposed on the third insulating layer 114. Alternatively, the fourth insulating layer 115 may be continuously disposed on the substrate 100 to cover the source electrode SE and the drain electrode DE. However, this disclosure is not limited thereto. In embodiments, the fourth insulating layer 115 may comprise an organic material.

[0074] In the display area DA, the connection electrode CM can be disposed on the fourth insulating layer 115. The connection electrode CM can be connected to the drain electrode DE or the source electrode SE through contact holes formed in the fourth insulating layer 115.

[0075] In the display area DA, a fifth insulating layer 116 may be disposed on the fourth insulating layer 115. The fifth insulating layer 116 may cover the connection electrode CM and may be continuously disposed on the substrate 100. However, this disclosure is not limited thereto. In embodiments, the fifth insulating layer 116 may include an organic material.

[0076] In the display area DA, an organic light-emitting diode (OLED) can be disposed on a fifth insulating layer 116. The OLED may include a pixel electrode 211, an emitting layer 212, and a counter electrode 213. The pixel electrode 211 may reflect or transmit light. For example, the pixel electrode 211 may include metal.

[0077] The pixel electrode 211 can be connected to the connection electrode CM through a contact hole formed in the fifth insulating layer 116. Thus, the pixel electrode 211 can be connected to the thin-film transistor TFT.

[0078] In the display area DA, a sixth insulating layer 118 may be disposed on the fifth insulating layer 116. An opening exposing at least a portion of the upper surface of the pixel electrode 211 may be defined in the sixth insulating layer 118. For example, the sixth insulating layer 118 may comprise an organic material.

[0079] In the display area DA, spacer 119 may be disposed on the sixth insulating layer 118. For example, spacer 119 may comprise an organic material. Spacer 119 may maintain the gap between encapsulation layer 300 and substrate 100.

[0080] The emitting layer 212 may be disposed on the pixel electrode 211. The emitting layer 212 may be disposed in an opening formed in the sixth insulating layer 118. In an embodiment, the emitting layer 212 may have a multilayer structure including a hole injection layer, a hole transport layer, an organic emitting layer, an electron transport layer, and an electron injection layer. The organic emitting layer may include a light-emitting material.

[0081] The counter electrode 213 may cover the emitting layer 212 and may be disposed on the sixth insulating layer 118. In embodiments, the counter electrode 213 may have light-transmitting or reflective properties. For example, the counter electrode 213 may comprise a metal. The counter electrode 213 may be continuously disposed on the substrate 100.

[0082] The encapsulation layer 300 can prevent moisture and oxygen from penetrating into the organic light-emitting diode (OLED) from the surrounding environment. For example, the encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0083] A first inorganic encapsulation layer 310 may be disposed on the counter electrode 213. An organic encapsulation layer 320 may be disposed on the first inorganic encapsulation layer 310 and may have a substantially flat upper surface without creating steps around the first inorganic encapsulation layer 310. A second inorganic encapsulation layer 330 may be disposed on the organic encapsulation layer 320.

[0084] The organic encapsulation layer 320 can be disposed in a portion of the non-display area NDA and the display area DA. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can extend from the display area DA to the non-display area NDA.

[0085] The touch layer 400 can be disposed on the display panel DP. The touch layer 400 may include a first touch electrode 430, a second touch electrode 440, a first touch insulating layer 410, and a second touch insulating layer 420.

[0086] A first touch insulating layer 410 may be disposed on the encapsulation layer 300. The first touch insulating layer 410 may include silicon oxide, silicon nitride, silicon oxynitride, etc. These materials may be used individually or in combination with each other. The first touch insulating layer 410 may extend from the display area DA to the non-display area NDA.

[0087] The first touch electrode 430 may be disposed on the first touch insulating layer 410. In an embodiment, the first touch electrode 430 may be disposed in a non-emitting area. For example, the first touch electrode 430 may overlap with the sixth insulating layer 118. The first touch electrode 430 may include metal, alloy, conductive metal oxide, transparent conductive material, etc.

[0088] The second touch insulating layer 420 may cover the first touch electrode 430. The second touch insulating layer 420 may include an inorganic insulating material. The second touch insulating layer 420 may include silicon oxide, silicon nitride, silicon oxynitride, etc. These materials may be used alone or in combination with each other. A contact hole exposing a portion of the first touch electrode 430 may be defined in the second touch insulating layer 420.

[0089] The second touch electrode 440 may be disposed on the second touch insulating layer 420 and may overlap with the first touch electrode 430. For example, the second touch electrode 440 may be disposed in the non-emission area of ​​the display device 10. The second touch electrode 440 may be electrically connected to the first touch electrode 430 through a contact hole that exposes a portion of the first touch electrode 430. The second touch electrode 440 may include metal, alloy, conductive metal oxide, transparent conductive material, etc.

[0090] The first touch electrode 430 and the second touch electrode 440 can form a touch electrode. In an embodiment, the touch electrode may have a grid structure in a plan view. However, this disclosure is not limited to this, and the structure of the touch electrode can vary.

[0091] A light-shielding element BM can be disposed on the second touch insulating layer 420. In an embodiment, the light-shielding element BM can cover the entire non-emitting area and can have a grid shape in a plan view. For example, the light-shielding element BM can overlap with the sixth insulating layer 118 and the touch electrode. In an embodiment, the light-shielding element BM can cover the second touch electrode 440.

[0092] The light shield BM can absorb external light. Accordingly, the light shield BM can reduce the external light reflectivity of the display device 10. The light shield BM may include at least one of carbon black, black pigment, and black dye. These materials may be used alone or in combination with each other.

[0093] In an embodiment, the light-shielding device BM may define multiple openings, each exposing a portion of the second touch insulating layer 420. For example, the light-shielding device BM may define an opening corresponding to an organic light-emitting diode (OLED). For example, the opening may overlap with the OLED.

[0094] In one embodiment, a touch protective layer may be additionally disposed between the second touch insulating layer 420 and the light shield BM. In this case, the second touch electrode 440 may be covered by the touch protective layer. The light shield BM may overlap the touch electrode on the touch protective layer. Examples of materials that can be used as the touch protective layer include silicon oxide, silicon nitride, silicon oxynitride, etc. These materials may be used alone or in combination with each other.

[0095] The color filter CF can be disposed on the second touch insulating layer 420. When a separate touch protective layer is provided, the color filter CF can be disposed on the touch protective layer.

[0096] A color filter CF can be disposed within an opening defined by a light-shielding device BM. In an embodiment, the color filter CF may partially overlap with the light-shielding device BM. The color of light emitted from an organic light-emitting diode (OLED) can be more clearly discerned as the light passes through the color filter CF.

[0097] In an embodiment, the color filter CF can transmit light of a specific color and block light of a color other than that specific color. For example, the color filter CF may include dyes and / or pigments that absorb light of a color different from that specific color.

[0098] A planarization layer 500 may be disposed on the light-shielding BM and the color filter CF. The planarization layer 500 may cover the light-shielding BM and the color filter CF. Accordingly, the reliability of the light-shielding BM and the color filter CF can be improved. In an embodiment, the planarization layer 500 may have a substantially flat upper surface. Accordingly, the planarization layer 500 may compensate for step differences on its lower surface. In an embodiment, the planarization layer 500 may include an organic material. Examples of organic materials that can be used as the planarization layer 500 may include photoresist, polyacrylic resin, polyimide resin, acrylic resin, epoxy resin, acrylate resin, etc. These materials may be used alone or in combination with each other.

[0099] Figure 3 yes Figure 1 A schematic enlarged plan view of region A. Figure 4 It is along Figure 3 A schematic cross-sectional view of the display device 10 taken from line II-II'.

[0100] refer to Figure 3 and Figure 4The first dam DAM1 and the second dam DAM2 may be located in the non-display area NDA. The first dam DAM1 and the second dam DAM2 may each include at least a portion of insulating layers 112, 113, 114, 115, 116, and 118. For example, the first dam DAM1 and the second dam DAM2 may each include inorganic insulating material and / or organic insulating material.

[0101] Alignment mark AM can be disposed between the first dam DAM1 and the second dam DAM2. Alignment mark AM can be provided as an opening 20_OP in metal layer 20. For example, alignment mark AM can be an engraved pattern provided in metal layer 20. Specifically, metal layer 20 may include a first metal layer 21 and a second metal layer 22. Furthermore, opening 20_OP in metal layer 20 may include openings in the first metal layer 21 and the second metal layer 22.

[0102] For reference Figure 2 As described, a thin-film transistor (TFT) comprising a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE can be disposed in the display area DA. The metal layer 20 may comprise the same material as the source electrode SE or drain electrode DE of the thin-film transistor TFT.

[0103] A light-blocking device BM can be disposed on the first dam DAM1 and the second dam DAM2. The light-blocking device BM can have an opening BM_OP that overlaps with the alignment mark AM. For example, the light-blocking device BM can have an opening BM_OP that overlaps with the opening 20_OP of the metal layer 20. The light-blocking device BM can be disposed on the upper surface of the first dam DAM1 and the upper surface of the second dam DAM2. Because the light-blocking device BM includes an opening BM_OP that overlaps with the alignment mark AM and is disposed on the upper surface of the first dam DAM1 and the upper surface of the second dam DAM2, the visibility of the alignment mark AM can be improved.

[0104] The planarization layer 500 can be disposed on the first dam DAM1, the second dam DAM2, and the alignment mark AM. The entire upper surface of the planarization layer 500 overlapping with the alignment mark AM can be flat.

[0105] The optical functional layer 600 may be disposed on the planarization layer 500. The optical functional layer 600 may be a polarizer. However, this disclosure is not limited thereto.

[0106] In this embodiment, because the entire upper surface of the planarization layer 500 overlapping with the alignment mark AM is flat, the entire upper surface of the planarization layer 500 overlapping with the alignment mark AM and the entire lower surface of the optical functional layer 600 can adhere to each other. For example, the entire upper surface of the planarization layer 500 overlapping with the alignment mark AM and the entire lower surface of the optical functional layer 600 can adhere to each other without any gaps between them.

[0107] As a comparative example, to reduce the area of ​​the non-display region, alignment marks can be provided as openings in a metal layer between the first and second dams. When alignment marks are provided as openings in the metal layer (e.g., engraved patterns), the upper surface of the planarization layer may be concave in the area where the alignment marks are located due to the step between the alignment marks and the dams. When the upper surface of the planarization layer on the alignment marks is concave, the planarization layer and the optical functional layer disposed thereon may not bond to each other, and therefore, bubbles may form between the planarization layer and the optical functional layer. When bubbles form, the alignment marks may not be visible from the outside, and therefore, the quality and reliability of the display device may deteriorate.

[0108] In this embodiment, the entire upper surface of the planarization layer 500 overlapping the alignment mark AM can be flat, and therefore, the entire upper surface of the planarization layer 500 overlapping the alignment mark AM and the entire lower surface of the optical functional layer 600 disposed on the planarization layer 500 can adhere to each other without any gaps between them. The adhesion of the planarization layer 500 and the optical functional layer 600 to each other prevents air bubbles from forming between the planarization layer 500 and the optical functional layer 600, improves the external visibility of the engraved alignment mark AM, and thus enhances the quality and reliability of the display device 10.

[0109] The adhesive OCA can be disposed on the optical functional layer 600, and the cover window 700 can be disposed on the adhesive OCA.

[0110] Figures 5 to 11 This is a schematic cross-sectional view illustrating a method for manufacturing a display device.

[0111] refer to Figure 5 and Figure 6 Metal layer 20 can be formed on substrate 100. Metal layer 20 may include a first metal layer 21 and a second metal layer 22. The first metal layer 21 may include a thin-film transistor (TFT) formed in display area DA (see...). Figure 2 The source electrode SE included in ) (see Figure 2 ) or drain electrode DE (see Figure 2 The same material as the material.

[0112] In an embodiment, an opening 20_OP may be formed in the metal layer 20. The opening 20_OP in the metal layer 20 may include an opening in the first metal layer 21 and an opening in the second metal layer 22. An alignment mark AM can be formed by forming the opening 20_OP in the metal layer 20. For example, the alignment mark AM may be provided as an opening 20_OP in the metal layer 20.

[0113] refer to Figure 7 A first dam DAM1 and a second dam DAM2 can be formed, wherein the alignment mark AM is between the first dam DAM1 and the second dam DAM2. The first dam DAM1 and the second dam DAM2 may each comprise organic insulating material and / or inorganic insulating material.

[0114] refer to Figure 7 and Figure 8 A light-shielding device BM can be formed on the first dam DAM1 and the second dam DAM2. An opening BM_OP overlapping with the alignment mark AM can be formed in the light-shielding device BM. For example, an opening BM_OP overlapping with an opening 20_OP of the metal layer 20 can be formed in the light-shielding device BM. The light-shielding device BM can be disposed on the upper surface of the first dam DAM1 and the upper surface of the second dam DAM2. Since the light-shielding device BM includes an opening BM_OP overlapping with the alignment mark AM and is disposed on the upper surface of the first dam DAM1 and the upper surface of the second dam DAM2, the alignment mark AM can be identified from the outside, thereby improving the quality and reliability of the display device.

[0115] refer to Figure 9 and Figure 10 The first planarization layer 500a can be formed on the alignment mark AM and the light shield BM. Due to the steps of the alignment mark AM with the first dam DAM1 and the second dam DAM2, the upper surface of the first planarization layer 500a may be concave.

[0116] A second planarization layer 500b overlapping the alignment mark AM can be formed on the first planarization layer 500a. The second planarization layer 500b can be formed on the first planarization layer 500a overlapping the alignment mark AM by a photoresist process or an inkjet process.

[0117] Because the planarization layer 500 disposed in the area overlapping with the alignment mark AM is formed by a total of two processes (e.g., a process for forming the first planarization layer 500a and a process for forming the second planarization layer 500b), the upper surface of the second planarization layer 500b overlapping with the alignment mark AM can be flat.

[0118] refer to Figure 11 The optical functional layer 600 can be disposed on the first planarization layer 500a and the second planarization layer 500b. Since the upper surface of the second planarization layer 500b, which overlaps with the alignment mark AM, is flat, the entire upper surface of the second planarization layer 500b and the entire lower surface of the optical functional layer 600 can adhere to each other. Because the second planarization layer 500b and the optical functional layer 600 adhere to each other, bubbles will not form between them, and therefore, the alignment mark AM of the engraved pattern can be identified from the outside, thus improving the quality and reliability of the display device.

[0119] The adhesive OCA can be disposed on the optical functional layer 600, and the cover window 700 can be disposed on the adhesive OCA.

[0120] Figure 12 This is a block diagram of electronic device 1 according to an embodiment.

[0121] refer to Figure 12 The electronic device 1 according to the embodiment may include a display module 1001, a processor 1002, a memory 1003, and a power module 1004.

[0122] The processor 1002 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0123] The data information required for the operation of the processor 1002 or the display module 1001 can be stored in the memory 1003. When the processor 1002 executes the application stored in the memory 1003, image data signals and / or input control signals are transmitted to the display module 1001, and the display module 1001 can process the received signals and output image information on the display screen.

[0124] The power module 1004 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0125] At least one of the components of electronic device 1 may be included in the display device according to the embodiment. Furthermore, some of the modules described above may be included within the display device, while other modules may be provided separately from the display device. For example, the display device may include display module 1001, and processor 1002, memory 1003, and power module 1004 may be provided as other devices within electronic device 1 besides the display device.

[0126] Figure 13 These are schematic diagrams of electronic devices according to various embodiments.

[0127] refer to Figure 13The various electronic devices to which the display device according to the embodiment is applied include not only image display electronic devices such as smartphones 1_1a, tablet PCs 1_1b, laptop computers 1_1c, TVs 1_1d, and desktop monitors 1_1e, but also wearable electronic devices including display modules such as smart glasses 1_2a, head-mounted displays 1_2b, and smartwatches 1_2c, as well as vehicle electronic devices 1_3 including display modules such as in-vehicle mirror displays and central information displays (CIDs) arranged on dashboards, central instrument panels, and vehicle instrument panels.

[0128] According to one or more of the above embodiments, a display device with improved reliability and improved quality, as well as a method for manufacturing the display device, can be realized. However, the scope of this disclosure is not necessarily limited to this effect.

[0129] It should be understood that the embodiments described herein are to be considered in a descriptive sense and not necessarily for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A display device, comprising: A substrate, comprising a display area and a non-display area adjacent to the display area; The first dam is located in the non-display area; The second dam is located in the non-display area; Alignment marks are provided between the first dam and the second dam, and are provided as openings in the metal layer; A planarization layer is disposed on each of the first dam, the second dam, and the alignment mark; as well as An optical functional layer is disposed on the planarization layer. The entire upper surface of the planarization layer, which overlaps with the alignment mark, adheres to the entire lower surface of the optical functional layer disposed on the planarization layer.

2. The display device according to claim 1, wherein, The entire upper surface of the planarization layer that overlaps with the alignment mark is flat.

3. The display device according to claim 1, further comprising: Light-blocking devices are installed on the first dam and the second dam.

4. The display device according to claim 3, wherein, The light shield includes an opening that overlaps with the alignment mark.

5. The display device according to claim 3, wherein, The light-blocking device is disposed on the upper surface of the first dam.

6. The display device according to claim 3, wherein, The light-blocking device is disposed on the upper surface of the second dam.

7. The display device according to claim 1, wherein, The first dam and the second dam each comprise organic insulating materials and / or inorganic insulating materials.

8. The display device according to claim 1, further comprising: A thin-film transistor, disposed in the display area, includes a semiconductor layer, a gate electrode, a source electrode, and a drain electrode. The metal layer comprises the same material as the source electrode or the drain electrode.

9. A method for manufacturing a display device, the method comprising: A metal layer is formed on the substrate; An opening is formed in the metal layer to form alignment marks; A first dam and a second dam are formed, with the alignment mark arranged between the first dam and the second dam; Shade structures are formed on the first and second dams; An opening overlapping the alignment mark is formed in the light shield; A first planarization layer is formed on the alignment mark and the light shield; as well as A second planarization layer is formed on the first planarization layer, overlapping the alignment mark.

10. An electronic device comprising a display device according to any one of claims 1 to 8.

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