Display device and method of manufacturing same

Abstract

The invention relates to a display device, a method of manufacturing the display device, and an electronic device. The display device includes: a substrate; a thin film transistor disposed on the substrate; and a light emitting element electrically connected to the thin film transistor, in which the thin film transistor includes a semiconductor layer and a gate electrode with a first insulating layer therebetween, and the gate electrode includes an opening exposing a portion of the first insulating layer at a position where the gate electrode overlaps the semiconductor layer.

Description

[0001] Cross Reference to Related Applications.

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0137468, filed on October 10, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Embodiments relate to a display device and a method of manufacturing a display device. BACKGROUND

[0004] Recently, various types of flat panel display devices of light weight and small size are being developed. Examples of flat panel display devices include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting displays (OLEDs).

[0005] Among flat panel display devices, organic light emitting displays (OLEDs) display images using organic light emitting diodes that emit light by recombination of electrons and holes. These OLEDs are attracting attention as next-generation displays because they have a fast response speed and operate with low power consumption. SUMMARY

[0006] Embodiments provide a display device having improved luminance accuracy.

[0007] However, embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent by reference to the following detailed description of the present disclosure given by referring to the accompanying drawings.

[0008] According to embodiments of the present disclosure, a display device is provided, including: a substrate; a thin film transistor disposed on the substrate; and a light emitting element electrically connected to the thin film transistor, wherein the thin film transistor includes a semiconductor layer and a gate electrode, has a first insulating layer between the semiconductor layer and the gate electrode, and the gate electrode includes an opening exposing a portion of the first insulating layer at a position where the gate electrode overlaps the semiconductor layer.

[0009] In embodiments, a first width of the opening in a direction perpendicular to a longitudinal direction of the semiconductor layer can be greater than or equal to a width of the semiconductor layer.

[0010] In this embodiment, the opening is in a central region of the gate electrode.

[0011] In embodiments, a second width of the opening in a longitudinal direction of the semiconductor layer can be about 2 µm to about 4 µm.

[0012] In an embodiment, a first width of the opening in a direction perpendicular to a longitudinal direction of the semiconductor layer can be less than a width of the semiconductor layer.

[0013] In an embodiment, a difference between the width of the semiconductor layer and the first width of the opening can be about 1 μm to about 2 μm.

[0014] In an embodiment, the display device can further include a second insulating layer covering the thin film transistor, and the thin film transistor can further include a source and a drain on the second insulating layer and electrically connected to the source region and the drain region of the semiconductor layer, respectively.

[0015] In an embodiment, the opening can be located between the central region of the semiconductor layer and the source region or the drain region.

[0016] In an embodiment, the display device can further include a third insulating layer on the source electrode and the drain electrode, wherein the third insulating layer fills the opening.

[0017] In an embodiment, the thin film transistor can include a driving transistor.

[0018] According to another embodiment, a method of manufacturing a display device is disclosed, the method including: a first operation of sequentially forming a semiconductor layer, a first insulating layer, and a gate electrode on a substrate; a second operation of forming a second insulating layer on the gate electrode; a third operation of exposing a portion of the gate electrode by patterning the second insulating layer; and a fourth operation of forming an opening in the gate electrode by removing the exposed portion of the gate electrode, wherein the opening is formed at a position overlapping the semiconductor layer.

[0019] In an embodiment, the method can further include, between the first operation and the second operation, forming a source region and a drain region by doping an impurity to the semiconductor layer using the gate electrode as a mask.

[0020] In an embodiment, the source region and the drain region are exposed together in a case where the second insulating layer is patterned.

[0021] In an embodiment, the method can further include, after the third operation, forming a source and a drain on the second insulating layer and electrically connected to the source region and the drain region, respectively.

[0022] In an embodiment, the method can further include, after the fourth operation, forming a third insulating layer on the source and the drain, wherein the third insulating layer fills the opening.

[0023] In an embodiment, the opening can be located between the central region of the semiconductor layer and the source region or the drain region.

[0024] In an embodiment, a first width of the opening in a direction perpendicular to a longitudinal direction of the semiconductor layer can be greater than or equal to a width of the semiconductor layer.

[0025] In an embodiment, a first width of the opening in a direction perpendicular to a longitudinal direction of the semiconductor layer can be less than a width of the semiconductor layer.

[0026] In an embodiment, a difference between the width of the semiconductor layer and the first width can be about 1 µm to about 2 µm.

[0027] According to one or more embodiments, there is provided an electronic device, including a display device, wherein the display device includes: a substrate, a thin film transistor on the substrate, and a light emitting element electrically connected to the thin film transistor, wherein the thin film transistor includes a semiconductor layer and a gate electrode, a first insulating layer between the semiconductor layer and the gate electrode, and the gate electrode includes an opening exposing a portion of the first insulating layer at a position where the gate electrode overlaps the semiconductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0028] The following drawings attached to the specification illustrate preferred embodiments of the present disclosure and, together with the detailed description of the present disclosure given below, serve to further understand the technical idea of the present disclosure; therefore, the present disclosure should not be construed as being limited to the contents described in the drawings.

[0029] Figure 1 is a schematic plan view of an example of a display device according to an embodiment; Figure 2 is a schematic block diagram of a structure of the display device of Figure 1 ; and Figure 3 is a schematic view of an equivalent circuit of one sub-pixel of the display device of Figure 1 ; and Figure 4 is a schematic plan view of an example of a first transistor arranged in a sub-pixel included in the display device of Figure 1 ; and Figure 5 is a schematic cross-sectional view of the example of the first transistor taken along line A-A' of Figure 4 ; and Figure 6 is a graph showing a driving current with respect to a voltage applied to a gate electrode of the first transistor of Figure 4 ; and Figures 7 to 10 is a schematic cross-sectional view of an example of a method of manufacturing the first transistor of Figure 4 ; and Figure 11 is a schematic cross-sectional view of another example of the first transistor arranged in a sub-pixel included in the display device of Figure 1 ; and Figure 12 is a schematic plan view of another example of a first transistor disposed in a sub-pixel included in a display device of Figure 1 Figure 13 is a schematic view of an example in which an electronic device including a display device according to an embodiment is implemented as a head-mounted display. DETAILED DESCRIPTION

[0030] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words that are non-limiting examples of the apparatus or method disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. Herein, various embodiments are not necessarily mutually exclusive, and / or do not limit the disclosure. For example, a particular shape, configuration, and characteristic can be used or implemented in another embodiment.

[0031] Unless otherwise indicated, the illustrated embodiments are to be understood as providing features that can be widely applied to the invention. Thus, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged, and / or rearranged, unless otherwise indicated, without departing from the scope of the invention.

[0032] The use of cross-hatching and / or shading in the drawings is generally provided to illustrate the boundaries of regions or areas in a drawing. As the scope of the invention is not limited by the size, shape, relative and / or absolute positions of the elements, unless otherwise indicated, the presence or absence of cross-hatching or shading in a drawing is not intended to convey or indicate any preference or requirement for any particular material, material property, size, proportion, commonality of elements between illustrations, and / or any other characteristic, attribute, property, etc. of the elements. In addition, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When an embodiment can be implemented differently, a specific process sequence can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously, or in an order opposite to the described order. Also, like reference numerals denote like elements.

[0033] ​When an element or layer is referred to as being "on," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" on, directly connected to, or directly attached to another element or layer, there is no intervening element or layer. Therefore, the term "connection" may refer to a physical, electrical, and / or fluid connection with or without an intervening element. Furthermore, the axis of the first direction X, the axis of the second direction Y, and the axis of the third direction Z are not limited to the three axes of a Cartesian coordinate system, such as the X-axis, Y-axis, and Z-axis, and may be interpreted in a broader sense. For the purposes of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "selected from at least one of X, Y, and Z" may be understood to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0034] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0035] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “upper,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to also include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “below” to other elements or features will subsequently be oriented “above” to other elements or features. Thus, the term “below” can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or "contains" or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It is also to be noted that, as used herein, the terms "substantially," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, unless otherwise indicated, and therefore, such terms should be construed to admit some variations. For example, "about" can mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of a stated value.

[0037] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures of embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments disclosed herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. In this manner, the regions illustrated in the figures can not have a shape that is identical to the shape of a region as illustrated in the figures, and such regions are not intended to be limited to the particular shapes illustrated herein, but are to include shapes that are very similar, as well as alternative shapes. In this fashion, the regions shown in the figures are intended to be illustrative and not limiting.

[0038] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings for functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electrical (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connectors, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Furthermore, it is contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmable microprocessors and associated circuitry) for performing other functions. Moreover, without departing from the scope of the invention, each block, unit, and / or module in some embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the invention, some implementation blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0039] In the following description, embodiments will be described in detail with reference to the accompanying drawings, in which the same reference numerals denote the same elements.

[0040] Figure 1 This is a schematic plan view of an example of a display device according to an embodiment. Figure 2 yes Figure 1 A block diagram of the structure of the display device, and Figure 3 yes Figure 1 A schematic diagram of the equivalent circuit of a sub-pixel of a display device.

[0041] First, refer to Figure 1 and Figure 2 According to the embodiment, the display device 10 may include a substrate 100, which includes a display area DA for displaying an image and a peripheral area PA located outside the display area DA.

[0042] The display area DA may include scan lines SL1 to SLn extending in the first direction X, data lines DL1 to DLm extending in the second direction Y perpendicular to the first direction X, and sub-pixels PX. Here, m and n can each be natural numbers greater than 1. The third direction Z is perpendicular to the plane defined by the first direction X and the second direction Y.

[0043] The wiring that applies electrical signals to sub-pixel PX may include scan lines SL1 to SLn, data lines DL1 to DLm, etc. Scan lines SL1 to SLn are arranged, for example, in rows extending in a first direction X to transmit scan signals to sub-pixel PX, and data lines DL1 to DLm are arranged, for example, in columns extending in a second direction Y to transmit data signals to sub-pixel PX, and sub-pixel PX may be located at the intersection of scan lines SL1 to SLn and data lines DL1 to DLm.

[0044] Each sub-pixel PX may include a light-emitting element that emits red, green, blue, or white light. For example, each sub-pixel PX may include an organic light-emitting diode (OLED) as the light-emitting element. However, the implementation is not limited to this.

[0045] Data driver 130, scan driver 150, voltage controller 170, and controller 190 can be located in the peripheral area PA. Data driver 130 provides data signals to display area DA, scan driver 150 provides scan signals to display area DA, voltage controller 170 controls the voltage supplied to display area DA, and controller 190 controls data driver 130, scan driver 150, and voltage controller 170.

[0046] The voltage controller 170 can generate and control the first voltage ELVDD, the second voltage ELVSS, and the initialization voltage VINT supplied to the display area DA.

[0047] A first voltage ELVDD, a second voltage ELVSS, and an initialization voltage VINT can be applied to the sub-pixel PX. For example, the first voltage ELVDD can be a positive voltage, and the second voltage ELVSS can be a negative voltage or ground. For example, the second voltage ELVSS can have a lower level than the first voltage ELVDD.

[0048] Controller 190 can receive image signals RGB and control signals CS from an external source (e.g., a system board). Controller 190 can generate image data by converting the data format of the image signals RGB to match the interface specification of data driver 130. Controller 190 can then provide the image data with the converted data format to data driver 130.

[0049] The controller 190 can generate and output a first control signal CS1, a second control signal CS2, and a third control signal CS3 in response to a control signal CS provided from an external source. The first control signal CS1 can be defined as a scan control signal, and the second control signal CS2 can be defined as a data control signal. The first control signal CS1 can be provided to the scan driver 150. The second control signal CS2 can be provided to the data driver 130. The third control signal CS3 can be applied to the voltage controller 170.

[0050] The scan driver 150 can generate a scan signal in response to the first control signal CS1. The scan signal can be applied to the sub-pixel PX via scan lines SL1 to SLn.

[0051] The data driver 130 can generate a data voltage corresponding to image data in response to the second control signal CS2. The data voltage can be applied to the sub-pixel PX via data lines DL1 to DLm. The data driver 130 can simultaneously provide the data voltage generated by the cells of the sub-pixel row to data lines DL1 to DLm, thereby simultaneously providing the data voltage to the sub-pixel PX.

[0052] Subpixels (PXs) can receive data voltages in response to a scan signal. Subpixels (PXs) can display images by emitting light with a brightness corresponding to the data voltage. Subpixels (PXs) can display images by emitting light sequentially or simultaneously.

[0053] refer to Figures 1 to 3 A sub-pixel PX may include pixel circuitry PXC and a light-emitting element LD. For example, a sub-pixel PX may be connected to a scan line SL (or gate line) and a data line DL. The scan line SL may be... Figure 2 One of the scan lines SL1 to SLn, and the data line DL can be Figure 2 One of the data lines DL1 to DLm. The scan line SL may include a first scan line SL1, a second scan line SL2, a third scan line SL3, a first transmit control line ECL, and a second transmit control line EBL.

[0054] Drive signals can be applied to scan line SL and data line DL. A first scan signal GW can be applied to the first scan line SL1, a second scan signal GR can be applied to the second scan line SL2, and a third scan signal GI can be applied to the third scan line SL3. A first transmit control signal EM can be applied to the first transmit control line ECL, a second transmit control signal EMB can be applied to the second transmit control line EBL, and a data signal Vdata (or data voltage) can be applied to data line DL.

[0055] For example, sub-pixel PX can also be connected to a first voltage line PL1, a second voltage line PL2, a third voltage line PL3, a reference voltage line RFL, and an initialization voltage line INL. Voltages can be applied to the first voltage line PL1, the second voltage line PL2, the third voltage line PL3, the reference voltage line RFL, and the initialization voltage line INL. A first voltage ELVDD can be applied to the first voltage line PL1, a second voltage ELVSS can be applied to the second voltage line PL2, a first voltage ELVDD or a reference voltage VREF can be applied to the third voltage line PL3, a reference voltage VREF can be applied to the reference voltage line RFL, and an initialization voltage VINT can be applied to the initialization voltage line INL.

[0056] The voltage level of the first voltage ELVDD can be higher than the voltage level of the second voltage ELVSS. The voltage level of the reference voltage VREF can be equal to or different from the voltage level of the first voltage ELVDD. The voltage level of the initialization voltage VINT can be lower than the voltage level of the first voltage ELVDD and higher than the voltage level of the second voltage ELVSS. However, the voltages are not limited to these, and the voltage levels can vary according to product specifications.

[0057] The pixel circuit PXC may include a first transistor T1 (or driving transistor), a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor Cst (or storage capacitor), and a second capacitor Chold (or holding capacitor).

[0058] The first transistor T1 can be electrically connected between the first voltage line PL1 and the second node N2. For example, the first electrode of the first transistor T1 can be connected to the first voltage line PL1 via a fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the second node N2. For example, the first electrode can be the source electrode, and the second electrode can be the drain electrode. However, this disclosure is not limited thereto, and the first electrode can be the drain electrode and the second electrode can be the source electrode.

[0059] The gate electrode of the first transistor T1 may be connected to the first node N1. For example, the first transistor T1 may also include a bottom electrode (or a second gate electrode) corresponding to the gate electrode. The first transistor T1 may be configured to provide a drive current to the light-emitting element LD or control the amplitude of the drive current flowing from the first voltage line PL1 to the light-emitting element LD. For example, the first transistor T1 may provide a drive current corresponding to the voltage of the first node N1 to the light-emitting element LD.

[0060] The second transistor T2 can be electrically connected between the data line DL and the first node N1. The gate electrode of the second transistor T2 can be connected to the first scan line SL1. The second transistor T2 can be turned on in response to the first scan signal GW of the first scan line SL1. When the second transistor T2 is turned on, the data signal Vdata of the data line DL can be transmitted to the first node N1.

[0061] The third transistor T3 can be electrically connected between the reference voltage line RFL and the first node N1. The gate electrode of the third transistor T3 can be connected to the second scan line SL2. The third transistor T3 can be turned on in response to the second scan signal GR of the second scan line SL2. When the third transistor T3 is turned on, the reference voltage VREF can be transmitted to the first node N1.

[0062] The fourth transistor T4 can be electrically connected between the anode electrode of the light-emitting element LD and the initialization voltage line INL. The gate electrode of the fourth transistor T4 can be connected to the third scan line SL3. The fourth transistor T4 can be turned on in response to the third scan signal GI of the third scan line SL3. When the fourth transistor T4 is turned on, the initialization voltage VINT can be transmitted to the anode electrode of the light-emitting element LD.

[0063] The fifth transistor T5 can be electrically connected between the first voltage line PL1 and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the first emitter control line ECL. The fifth transistor T5 can be turned on in response to the first emitter control signal EM of the first emitter control line ECL.

[0064] The sixth transistor T6 can be electrically connected between the second node N2 and the anode electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the second emitter control line EBL. The sixth transistor T6 can be turned on in response to the second emitter control signal EMB on the second emitter control line EBL.

[0065] When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path can be formed, through which the driving current can flow from the first voltage line PL1 through the first transistor T1 and the light-emitting element LD to the second voltage line PL2.

[0066] The first capacitor Cst can be formed or electrically connected between the first node N1 and the second node N2. The voltage corresponding to the data voltage Vdata can be stored in the first capacitor Cst.

[0067] The second capacitor Chold can be formed or electrically connected between the third voltage line PL3 and the second node N2. The second capacitor Chold can stabilize the voltage of the second node N2. A first voltage ELVDD or a reference voltage VREF can be applied to the third voltage line PL3. For example, when the first voltage ELVDD is applied to the third voltage line PL3, the third voltage line PL3 can be electrically connected to the first voltage line PL1 or formed integrally with (or become integral with) the first voltage line PL1. However, the third voltage line PL3 is not limited to this.

[0068] The light-emitting element LD can be electrically connected between the sixth transistor T6 and the second voltage line PL2. For example, the light-emitting element LD can be forward biased and connected between the second node N2 and the second voltage line PL2. When a drive current is provided from the first transistor T1, the light-emitting element LD can emit light with a brightness corresponding to the drive current.

[0069] In one embodiment, the light-emitting element (LD) may include an OLED. In another embodiment, the light-emitting element (LD) may include at least one inorganic light-emitting diode. The type, size, and / or number of light-emitting elements (LDs) may vary depending on the embodiment.

[0070] The first transistor T1 through the sixth transistor T6 can be N-type transistors. However, the implementation is not limited to this. For example, at least one of the first transistor T1 through the sixth transistor T6 can be changed to a P-type transistor. For example, the voltage level of the drive signal used to control the operation of the transistors can be set according to the type of each transistor.

[0071] The first transistor T1 through the sixth transistor T6 may comprise oxide semiconductor and / or low-temperature polycrystalline silicon (LTPS). For example, at least one transistor including the first transistor T1 may be an oxide semiconductor transistor comprising oxide semiconductor.

[0072] Figure 4 It is arranged in the area included Figure 1 A schematic plan view of an example of the first transistor in a sub-pixel of a display device. Figure 5 It is along Figure 4 A schematic cross-sectional view of an example of the first transistor cut off by line A-A', and Figure 6 It shows relative to what is applied to Figure 4 The graph shows the voltage of the gate electrode of the first transistor versus the driving current.

[0073] refer to Figure 4 and Figure 5According to the embodiments, the sub-pixel PX may include a substrate 100, a first transistor 400 on the substrate 100, and a light-emitting element electrically connected to the first transistor 400. The first transistor 400 may include a thin-film transistor, and further, the first transistor 400 may include a drive transistor for controlling the current flowing to the light-emitting element.

[0074] For example, substrate 100 may include a transparent glass material containing SiO2 as a main component. However, this disclosure is not limited thereto, and substrate 100 may include a transparent plastic material. The plastic material may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide, polycarbonate (PC), cellulose triacetate (TAC), cellulose acetate propionate (CAP), etc.

[0075] Semiconductor layer 410 may be formed on substrate 100. Semiconductor layer 410 may include source region 411, drain region 412 and channel region 413 located between source region 411 and drain region 412.

[0076] For example, semiconductor layer 410 may include a source region 411 and a drain region 412 formed by doping impurities on both sides of channel region 413. For example, the impurities vary depending on the type of first transistor 400 and may include N-type impurities or P-type impurities. For example, channel region 413, source region 411 located on one side of channel region 413, and drain region 412 located on the other side of channel region 413 may be referred to as semiconductor layer 410.

[0077] When the source region 411 and drain region 412 are doped with impurities, a self-aligned method in which the gate electrode 430, which will be described later, is used as a mask can be applied. However, this disclosure is not limited thereto, and a separate mask can be used to dope the semiconductor layer 410 with impurities without using the gate electrode 430 as a mask.

[0078] The source region 411 and drain region 412 can be electrically connected to the source electrode 451 and drain electrode 452, respectively, and the source region 411 or drain region 412 formed by doping can be interpreted as the source electrode 451 or drain electrode 452 of the first transistor 400, depending on the circumstances. The implementation is not limited thereto. For example, the positions of the source region 411 and drain region 412 can be interchanged depending on the impurities doped into the semiconductor layer 410.

[0079] Semiconductor layer 410 may be a layer comprising an oxide semiconductor. For example, semiconductor layer 410 may comprise indium gallium zinc oxide (IGZO). However, this disclosure is not limited thereto, and semiconductor layer 410 may comprise polysilicon.

[0080] As an alternative implementation, a buffer layer may be formed between the substrate 100 and the semiconductor layer 410. The buffer layer can block impurities during the crystallization process to form polycrystalline silicon, thereby improving the properties of the polycrystalline silicon and providing a flat surface on the buffer layer.

[0081] A first insulating layer 420 can be formed covering the semiconductor layer 410. A conductive layer including a gate electrode 430 can be formed on the first insulating layer 420. The gate electrode 430 can be formed together with the semiconductor layer 410 to form a first transistor 400.

[0082] For example, the gate electrode 430 may include an opening OP that exposes a portion of the first insulating layer 420 at a location where the gate electrode 430 overlaps with the semiconductor layer 410. The opening OP may be located in the central region of the gate electrode 430.

[0083] When the voltage applied to the gate electrode 430 is relatively small (e.g., the drive current can be about 10), -12 Ann to about 10 -9 The current flowing through the channel (from about 1 picoampere to about 1 nanoampere) may not be properly formed in the channel region 413 that overlaps with the opening OP. For example, when the voltage applied to the gate electrode 430 is relatively small (hereinafter referred to as a low electric field), the channel region 413 that overlaps with the opening OP can be used as a resistor.

[0084] When the drive current applied to the gate electrode 430 according to the voltage exceeds about 1 nanoamp, the current can flow appropriately in the channel region 413 despite the presence of the opening OP, due to the electric field applied to the channel region 413 through the gate electrode 430.

[0085] For example, the first width W1 of the opening OP can be formed to be greater than or equal to the width W2 of the semiconductor layer 410, thereby improving the accuracy of brightness under low electric field. For example, the first width W1 of the opening OP can refer to the length along a direction perpendicular to a second direction Y, which is the longitudinal direction of the semiconductor layer 410.

[0086] refer to Figure 6 The x-axis represents the voltage V applied to the gate electrode 430. GS And the y-axis represents the drive current I. DS The LTPS plot lines illustrate the effect of using LTPS as the semiconductor layer for the driving transistor, in response to a voltage V applied to the gate electrode 430.GS To measure the drive current I DS As a result, the Oxide-Normal plot shows the effect of using IGZO as the semiconductor layer for the driving transistor, for a voltage V applied to the gate electrode 430. GS To measure the drive current I DS As a result, and with the Oxide-Offset plotted lines showing the semiconductor layer where IGZO is used as the driving transistor, and the gate electrode 430 including an opening OP that exposes a portion of the first insulating layer 420 at the location where the gate electrode 430 overlaps with the semiconductor layer 410, the voltage V applied to the gate electrode 430 is... GS To measure the drive current I DS The result.

[0087] When the semiconductor layer 410 of the first transistor 400 is IGZO, compared to the case where the semiconductor layer 410 is low-temperature polycrystalline silicon (LTPS), the electron mobility is increased, enabling low-power operation and improving resolution. However, as... Figure 6 As shown, when the semiconductor layer 410 is IGZO, in response to the voltage V applied to the gate electrode 430 under a low electric field... GS Changes in driving current I DS Large fluctuations exist. As a result, even when a voltage V is applied to the gate electrode 430 under a low electric field... GS The tiny change in the light-emitting element drives the current I. DS The increase is significant, which reduces the accuracy of the brightness of the light-emitting element.

[0088] However, in the embodiment where the gate electrode 430 includes an opening OP that exposes a portion of the first insulating layer 420 at a location overlapping with the semiconductor layer 410, the channel region 413 overlapping the opening OP can act as a resistor under a low electric field, thereby reducing the voltage V applied to the gate electrode 430. GS The driving current I DS The fluctuation range. As a result, it can be determined by the voltage V applied to the gate electrode 430 under a low electric field. GS The increase is used to gently control the drive current I. DS The increase in [amount] is used to improve the accuracy of the brightness of the light-emitting element.

[0089] refer to Figure 6 As can be seen from the above description, under low electric field conditions, the slope l1 of the Oxide-Offset plot is less than the slope l2 of the Oxide-Normal plot. Therefore, as described above, for the Oxide-Offset plot under low electric field conditions, the light-emitting element responds to voltage V... GSThe sensitivity may decrease. It was confirmed that when the drive current exceeds about 1 nanoamp, the slope of the Oxide-Offset plot shows a similar trend to that of the Oxide-Normal plot.

[0090] For example, the second width d2 of the opening OP in the second direction Y (i.e., the longitudinal direction of the semiconductor layer 410) can be from about 2 μm to about 4 μm. When the second width d2 is less than about 2 μm, a channel can be well formed even in the channel region 413 overlapping the opening OP under low electric fields, and therefore, due to the voltage V applied to the gate electrode 430... GS There is a concern that the increase in drive current caused by the increase in width d2 may be significant. On the other hand, when the second width d2 exceeds about 4 μm, the resistance of the channel region 413 overlapping with the opening OP under a low electric field may increase significantly, and therefore the drive current may decrease, thus there is a concern that the brightness of the light-emitting element may decrease.

[0091] Figures 7 to 10 It is manufacturing Figure 4 A schematic cross-sectional view of an example of a method for using the first transistor.

[0092] refer to Figures 7 to 10 as well as Figure 5 The method of manufacturing the display device 10 according to the embodiment may include: a first operation of sequentially forming a semiconductor layer 410, a first insulating layer 420 and a gate electrode 430 on a substrate 100; a second operation of forming a second insulating layer 440 on the gate electrode 430; a third operation of exposing a portion of the gate electrode 430 by patterning the second insulating layer 440; and a fourth operation of forming an opening OP in the gate electrode 430 by removing the exposed portion of the gate electrode 430.

[0093] refer to Figure 7 In the first operation of sequentially forming a semiconductor layer 410, a first insulating layer 420, and a gate electrode 430 on a substrate 100, a semiconductor material can be coated on the entire surface of the substrate 100. Subsequently, the semiconductor layer 410 can be formed by patterning the semiconductor material using a mask process.

[0094] As an optional implementation, a light-shielding layer may be formed on the substrate 100 before the semiconductor layer 410 is formed to protect the semiconductor layer 410 from external light. For example, a buffer layer covering the entire surface of the substrate 100 may be formed on the light-shielding layer.

[0095] Silicon nitride (SiN) can be deposited on the entire surface of the substrate 100 on which the semiconductor layer 410 is formed. x ) or silicon oxide (SiO) xThe first insulating layer 420 may be formed using an insulating material. The first insulating layer 420 may include a monolayer of silicon nitride (SiN). x ) or silicon oxide (SiO) x (or its multiple layers)

[0096] Subsequently, a metal material can be deposited on the first insulating layer 420, and the metal material can be patterned using a mask process to form a gate electrode 430. The gate electrode 430 can be arranged to overlap with the semiconductor layer 410. The gate electrode 430 can be formed as a single layer or multiple layers, including at least one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0097] Between the first operation of sequentially forming a semiconductor layer 410, a first insulating layer 420, and a gate electrode 430 on the substrate 100 and the second operation of forming a second insulating layer 440 on the gate electrode 430, an operation can be added to dope impurities into the semiconductor layer 410 to form a source region 411 and a drain region 412 by using the gate electrode 430 as a mask.

[0098] refer to Figure 8 Silicon nitride (SiN) can be deposited on the entire surface of the substrate 100 on which the first insulating layer 420 and the gate electrode 430 are formed. x ) or silicon oxide (SiO) x The second insulating layer 440 may be formed using an insulating material. The second insulating layer 440 may include a monolayer of silicon nitride (SiN). x ) or silicon oxide (SiO) x (or its multiple layers)

[0099] refer to Figure 9 The second insulating layer 440 can be patterned using a mask process to form contact holes that expose portions of the gate electrode 430, the source region 411, and the drain region 412.

[0100] Subsequently, refer to Figure 10 The process may further include forming a source electrode 451 and a drain electrode 452 located on the second insulating layer 440 and electrically connected to the source region 411 and the drain region 412, respectively. The source electrode 451 and the drain electrode 452 may be formed as a single layer or multiple layers, including at least one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd).

[0101] Subsequently, a fourth operation can be performed to remove the exposed gate electrode 430 by a process such as etching, thereby forming an opening OP in the gate electrode 430. However, this disclosure is not limited to the order described above, and the fourth operation of forming the opening OP in the gate electrode 430 can be performed first, followed by the operation of forming the source electrode 451 and the drain electrode 452.

[0102] Subsequently, a third insulating layer 460 can be formed on the source electrode 451 and the drain electrode 452, and the third insulating layer 460 can fill the opening OP formed in the gate electrode 430.

[0103] For example, the methods and sequences for manufacturing the display device 10 for forming an opening OP in the gate electrode 430 are not limited to those described above, and various methods are possible as long as a portion of the first insulating layer 420 can be exposed at a location overlapping with the semiconductor layer 410 to form the opening OP in the gate electrode 430.

[0104] Figure 11 It is arranged in the area included Figure 1 A schematic cross-sectional view of another example of the first transistor in a sub-pixel of a display device.

[0105] refer to Figure 11 According to another embodiment, the sub-pixel PX may include a substrate 100, a first transistor 1100 on the substrate 100, and a light-emitting element electrically connected to the first transistor 1100. The first transistor 1100 may include a thin-film transistor, and further, the first transistor 1100 may include a drive transistor for controlling the current flowing to the light-emitting element.

[0106] The first transistor 1100 may include a semiconductor layer 1110 having a first insulating layer 1120 therebetween and a gate electrode 1130. The semiconductor layer 1110 may include a source region 1111 and a drain region 1112 doped with impurities, and a channel region 1113 located between the source region 1111 and the drain region 1112.

[0107] The gate electrode 1130 may include an opening OP2 that exposes a portion of the first insulating layer 1120 at the location where the gate electrode 1130 overlaps with the semiconductor layer 1110. For example, as Figure 11 As shown, the opening OP2 can be located at the end of the gate electrode 1130 in the cross-sectional view.

[0108] When the opening OP2 is located at the end of the gate electrode 1130 in the cross-sectional view, the channel region 1113 overlapping with the opening OP2 can be used as a resistor, as described above. For example, the electric field applied to the channel region 1113 by the gate electrode 1130 can be applied in a single direction of the channel region 1113 instead of in both directions, and therefore, the resistance of the channel region 1113 overlapping with the opening OP2 can be increased. As a result, the sensitivity of the light-emitting element to voltage under low electric fields can be reduced, thereby improving the accuracy of the brightness of the light-emitting element.

[0109] For example, the location of the opening OP2 is not limited to this, and the location of the opening OP2 can be in any region where the gate electrode 1130 and the semiconductor layer 1110 overlap, provided that the voltage sensitivity of the light-emitting element is reduced by the resistance of the channel region 1113 that overlaps with the opening OP2 under a low electric field. For example, the opening OP2 can be located between the central region of the semiconductor layer 1110 and the source region 1111 or the drain region 1112.

[0110] Figure 12 It is arranged in the area included Figure 1 A schematic plan view of another example of the first transistor in a sub-pixel of a display device.

[0111] refer to Figure 12 According to another embodiment, the sub-pixel PX may include a first transistor 1200. The first transistor 1200 may include a semiconductor layer 1210 having a first insulating layer therebetween and a gate electrode 1230. The semiconductor layer 1210 may include a source region 1211 and a drain region 1212 doped with impurities, and a channel region 1213 located between the source region 1211 and the drain region 1212.

[0112] The gate electrode 1230 may include an opening OP3 that exposes a portion of the first insulating layer at the location where the gate electrode 1230 overlaps with the semiconductor layer 1210. The opening OP3 may be located between the central region of the semiconductor layer 1210 and the source region 1211 or the drain region 1212. For example, the first width W3 of the opening OP3 in a direction perpendicular to the longitudinal direction of the semiconductor layer 1210 may be smaller than the width W2 of the semiconductor layer 1210. For example, as... Figure 12 As shown, the opening OP3 can be located in the region where the gate electrode 1230 and the channel region 1213 overlap.

[0113] For example, the first region P1 and the second region P2 can be formed on the side (e.g., opposite side) (the side perpendicular to the longitudinal direction of the semiconductor layer 1210) of the opening OP3 where the gate electrode 1230 and the channel region 1213 overlap. When a voltage is applied to the gate electrode 1230, a path for current to flow through the first region P1 and the second region P2 can be formed. Figure 12 As shown, the width of the first region P1 can be W4, and the width of the second region P2 can be W5. For example, the width W2 of the semiconductor layer 1210 can be substantially equal to the sum of the width W4 of the first region P1, the width W5 of the second region P2, and the first width W3 of the opening OP3.

[0114] Therefore, the opening OP3 can be formed as an island in the region where the gate electrode 1230 overlaps with the channel region 1213. When the opening OP3 is formed as an island, the region where the opening OP3 and the channel region 1213 overlap can act as a resistor as described above, and thus the brightness accuracy of the light-emitting element can be improved under low electric field.

[0115] For example, even under a low electric field, current can flow through the first region P1 and the second region P2, thereby reducing resistance and improving the power efficiency of the display device. For example, the first width W3 of the opening OP3 can be designed by comparing and evaluating the effect of improving the accuracy of the brightness of the light-emitting element due to the increased resistance with the effect of improving the power efficiency of the display device by forming the first region P1 and the second region P2.

[0116] Therefore, the difference between the width W2 of the semiconductor layer 1210 and the first width W3 of the opening OP3 can be from about 1 μm to about 2 μm. When the difference between the width W2 of the semiconductor layer 1210 and the first width W3 of the opening OP3 is about 1 μm or greater, the resistance can be reduced and the power consumption efficiency can be improved. However, when the difference between the width W2 of the semiconductor layer 1210 and the first width W3 of the opening OP3 exceeds about 2 μm, the overlap area between the opening OP3 and the channel region 1213 can be reduced, thereby reducing the effect on improving the accuracy of the brightness of the light-emitting element.

[0117] Figure 13 This is a schematic diagram illustrating an example in which an electronic device, including a display device according to an embodiment, is implemented as a head-mounted display.

[0118] refer to Figure 13 The electronic device including the display device 10 can be implemented as a head-mounted display (HMD) 800. The HMD 800 may include a display unit 810, a main unit 820, and a wearing unit 830.

[0119] For example, the display unit 810 may include according toFigures 1 to 12 The display device 10, implemented in this manner, serves as a screen. The main unit 820 may include a controller that applies scanning signals and data signals to the display unit 810, a touch sensor, or an acoustic sensor. A user may wear the HMD 800 using the wearing unit 830.

[0120] However, this is just an example, and the electronic device is not limited to HDM 800. For example, the electronic device can be any electronic device including display devices such as virtual reality (VR) devices, mobile phones, smartphones, tablet computers, digital televisions (TV), three-dimensional (3D) TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigators, etc.

[0121] According to an embodiment, the gate electrode of the driving transistor, which includes a semiconductor layer, an insulating layer, and a gate electrode, includes an opening that exposes a portion of the insulating layer, thereby allowing the increase in driving current based on the increase in voltage applied to the gate electrode under a low electric field to be controlled gradually, thereby improving the accuracy of the brightness of the display device.

[0122] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A display device, comprising: Substrate; Thin-film transistors are disposed on the substrate; as well as The light-emitting element is electrically connected to the thin-film transistor. The thin-film transistor includes a semiconductor layer and a gate electrode, with a first insulating layer between the semiconductor layer and the gate electrode. The gate electrode includes an opening that exposes a portion of the first insulating layer at a location where the gate electrode overlaps with the semiconductor layer.

2. The display device according to claim 1, wherein, The first width of the opening in a direction perpendicular to the longitudinal direction of the semiconductor layer is greater than or equal to the width of the semiconductor layer.

3. The display device according to claim 1, wherein, The opening is located in the central region of the gate electrode.

4. The display device according to claim 1, wherein, The second width of the opening in the longitudinal direction of the semiconductor layer is 2 μm to 4 μm.

5. The display device according to claim 1, wherein, The first width of the opening in a direction perpendicular to the longitudinal direction of the semiconductor layer is smaller than the width of the semiconductor layer.

6. The display device according to claim 5, wherein, The difference between the width of the semiconductor layer and the first width of the opening is 1 μm to 2 μm.

7. The display device according to claim 1, further comprising: A second insulating layer covers the thin-film transistor; as well as The thin-film transistor further includes: The source electrode and drain electrode are located on the second insulating layer and are electrically connected to the source region and drain region of the semiconductor layer, respectively.

8. The display device according to claim 7, wherein, The opening is located between the central region of the semiconductor layer and the source region or the drain region.

9. The display device according to claim 7, further comprising: A third insulating layer is located on the source electrode and the drain electrode. The third insulating layer fills the opening.

10. The display device according to claim 1, wherein, The thin-film transistor includes a driving transistor.

11. A method for manufacturing a display device, the method comprising: The first operation involves sequentially forming a semiconductor layer, a first insulating layer, and a gate electrode on a substrate; The second operation involves forming a second insulating layer on the gate electrode; The third operation involves exposing a portion of the gate electrode by patterning the second insulating layer; as well as The fourth operation involves forming an opening in the gate electrode by removing the exposed portion of the gate electrode. The opening is formed at a location overlapping the semiconductor layer.

12. The method of claim 11, further comprising: Between the first operation and the second operation, source and drain regions are formed by doping the semiconductor layer with impurities using the gate electrode as a mask.

13. The method according to claim 12, wherein, When the second insulating layer is patterned, the source region and the drain region are exposed together.

14. The method of claim 13, further comprising: After the third operation, a source electrode and a drain electrode are formed on the second insulating layer and electrically connected to the source region and the drain region, respectively.

15. The method of claim 14, further comprising: Following the fourth operation, a third insulating layer is formed on the source electrode and the drain electrode. The third insulating layer fills the opening.

16. The method according to claim 12, wherein, The opening is located between the central region of the semiconductor layer and the source region or the drain region.

17. The method according to claim 11, wherein, The first width of the opening in a direction perpendicular to the longitudinal direction of the semiconductor layer is greater than or equal to the width of the semiconductor layer.

18. The method according to claim 11, wherein, The second width of the opening in the longitudinal direction of the semiconductor layer is 2 μm to 4 μm.

19. The method according to claim 11, wherein, The first width of the opening in a direction perpendicular to the longitudinal direction of the semiconductor layer is smaller than the width of the semiconductor layer.

20. Electronic devices, including: The display device includes: Substrate; Thin-film transistors, on the substrate; and The light-emitting element is electrically connected to the thin-film transistor. The thin-film transistor includes a semiconductor layer and a gate electrode, with a first insulating layer between the semiconductor layer and the gate electrode. The gate electrode includes an opening that exposes a portion of the first insulating layer at a location where the gate electrode overlaps with the semiconductor layer.

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