Display apparatus and electronic apparatus

Abstract

A display apparatus includes a substrate, a first thin film transistor including a first active layer including an oxide and disposed over the substrate, and a second thin film transistor including a second active layer including an oxide and disposed over the substrate, and the first thin film transistor is disposed between the substrate and the second thin film transistor in a thickness direction of the substrate such that a distance between the substrate and the first thin film transistor has a smaller value than a distance between the substrate and the second thin film transistor.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0137438, filed on October 10, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosed embodiments relate to a display device. Background Technology

[0003] Recently, the use of display devices has become more diversified. As display devices have become thinner and lighter, their application range has gradually expanded.

[0004] As the use of display devices expands and technologies for utilizing them advance, the image quality and high resolution required by display devices are increasing.

[0005] At the same time, as display devices become thinner in a tablet-like form, the number of steps in the manufacturing process increases, and the complexity of the manufacturing process also rises.

[0006] Therefore, there are limitations in achieving high-resolution and high-quality display devices through stable manufacturing processes. Summary of the Invention

[0007] The disclosed embodiments relate to providing a display device with high resolution and high image quality.

[0008] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosed embodiments.

[0009] According to the disclosed aspects, a display device is provided, the display device including a substrate, a first thin-film transistor and a second thin-film transistor, wherein the first thin-film transistor includes a first active layer comprising oxide and is disposed above the substrate, the second thin-film transistor includes a second active layer comprising oxide and is disposed above the substrate, and the first thin-film transistor is disposed between the substrate and the second thin-film transistor in the thickness direction of the substrate, such that the distance between the substrate and the first thin-film transistor has a smaller value than the distance between the substrate and the second thin-film transistor.

[0010] In an embodiment, the display device may further include one or more interlayer insulating layers disposed between the first thin-film transistor and the second thin-film transistor.

[0011] In an embodiment, the first thin-film transistor and the second thin-film transistor may be stacked in at least one region in the thickness direction of the substrate.

[0012] In an embodiment, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may be stacked in at least one region in the thickness direction of the substrate.

[0013] In the embodiments, the first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor may have different properties.

[0014] In an embodiment, the display device may further include a conductive pattern portion superimposed on the first active layer of the first thin-film transistor or the second active layer of the second thin-film transistor.

[0015] In an embodiment, the conductive pattern portion can be electrically connected to the region of the first thin-film transistor or the region of the second thin-film transistor through one or more contact holes.

[0016] In an embodiment, the first thin-film transistor may include one or more connection electrodes electrically connected to the first active layer, and the conductive pattern portion may be electrically connected to at least one region of one or more connection electrodes.

[0017] In an embodiment, the display device may further include an intermediate conductive layer disposed between the first thin-film transistor and the second thin-film transistor.

[0018] In an embodiment, the intermediate conductive layer may be formed to correspond in one direction at least to the width of the first active layer or the second active layer.

[0019] In this embodiment, through the region where there is no intermediate conductive layer, the first thin-film transistor or one or more conductive patterns disposed on the same or different layers as the first thin-film transistor can be electrically connected to the second thin-film transistor or one or more conductive patterns disposed on the same or different layers as the second thin-film transistor.

[0020] In an embodiment, the display device may further include a display area on a substrate and a peripheral area disposed on at least one side of the display area, wherein one or more pixels may be disposed in the display area, and a driving circuit portion region for generating or controlling one or more signals for the operation of one or more pixels may be disposed in the peripheral area.

[0021] In an embodiment, the first thin-film transistor and the second thin-film transistor may be configured to correspond to one of one or more pixels.

[0022] In an embodiment, in a pixel, one or more thin-film transistors, each comprising an oxide layer and being an active layer required to drive the pixel, may be configured to be adjacent to a first thin-film transistor, and one or more thin-film transistors, each comprising an oxide layer and being an active layer required to drive the pixel, may be configured to be adjacent to a second thin-film transistor.

[0023] In an embodiment, a first thin-film transistor and one or more thin-film transistors adjacent to the first thin-film transistor may be disposed on the same layer, and a second thin-film transistor and one or more thin-film transistors adjacent to the second thin-film transistor may be disposed on the same layer.

[0024] In an embodiment, the first thin-film transistor and the second thin-film transistor may be configured to correspond to the driving circuit region.

[0025] In an embodiment, the first thin-film transistor and the second thin-film transistor may correspond to two different types of drive circuit sections disposed in the drive circuit section region, respectively.

[0026] In an embodiment, in the driving circuit section region, multiple driving circuit sections may be disposed in each of the upper and lower layers with an interlayer insulating film located therebetween, and multiple thin-film transistors, each including an active layer containing oxide, may be disposed on the same layer as the first thin-film transistor to be adjacent to the first thin-film transistor, and multiple thin-film transistors, each including an active layer containing oxide, may be disposed on the same layer as the second thin-film transistor to be adjacent to the second thin-film transistor, wherein the multiple thin-film transistors may be configured to correspond to the multiple driving circuit sections respectively.

[0027] In an embodiment, the driving circuit sections disposed in the upper and lower layers can be of different types, with an interlayer insulating film located between them.

[0028] According to another aspect of the disclosure, an electronic device including a display device is provided, and the display device includes a substrate, a first thin-film transistor and a second thin-film transistor, wherein the first thin-film transistor includes a first active layer comprising oxide and is disposed above the substrate, the second thin-film transistor includes a second active layer comprising oxide and is disposed above the substrate, and the first thin-film transistor is disposed between the substrate and the second thin-film transistor in the thickness direction of the substrate, such that the distance between the substrate and the first thin-film transistor has a smaller value than the distance between the substrate and the second thin-film transistor.

[0029] In an embodiment, the display device may further include one or more interlayer insulating layers disposed between the first thin-film transistor and the second thin-film transistor.

[0030] Other aspects, features, and advantages, in addition to those described above, will become apparent from the accompanying drawings, claims, and detailed description. Attached Figure Description

[0031] The above and other aspects, features, and advantages of certain embodiments disclosed will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic cross-sectional view showing a display device according to a disclosed embodiment; Figure 2 This is a schematic cross-sectional view showing a display device according to another embodiment of the disclosure; Figure 3 This is a schematic cross-sectional view showing a display device according to another embodiment of the disclosure; Figure 4 This is a schematic cross-sectional view illustrating a display device according to another embodiment of the disclosure; Figure 5 This is a schematic cross-sectional view showing a display device according to another embodiment of the disclosure; Figure 6 This is a schematic cross-sectional view showing a display device according to another embodiment of the disclosure; Figure 7 This is a schematic plan view of a display device according to another embodiment of the disclosure; Figure 8 It is along Figure 7 A sectional view taken by line VIII-VIII'; Figure 9 This is a schematic cross-sectional view showing a display device according to another embodiment of the disclosure; Figure 10 This is a schematic plan view of a display device according to another embodiment of the disclosure; Figure 11 It is used to describe Figure 10 A schematic cross-sectional view of region K; Figure 12 It shows Figure 11 A schematic diagram illustrating an example of the structure; Figure 13 It shows Figure 11 A schematic diagram of a modified example; Figure 14 This is a schematic plan view of a display device according to another embodiment of the disclosure; Figure 15 It is used to describe Figure 14 A schematic cross-sectional view of region K; Figure 16 It shows Figure 15 A schematic diagram illustrating an example of the structure; Figure 17 This is a schematic diagram of the equivalent circuit of a pixel of a display device according to a disclosed embodiment; Figure 18 It is used for driving Figure 17 A schematic waveform diagram of the driving signal for the pixel shown; and Figure 19This is a schematic block diagram illustrating a display system according to a disclosed embodiment. Detailed Implementation

[0032] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the various embodiments or implementations disclosed. As used herein, "embodiment" and "implementation" are interchangeable terms as non-limiting examples of the apparatus or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. These various embodiments are not necessarily exclusive, nor are they intended to limit the disclosure. For example, the specific shape, construction, and characteristics of an embodiment may be used or implemented in another embodiment.

[0033] Unless otherwise stated, the illustrated embodiments are to be understood as providing the features disclosed. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects (hereinafter individually or collectively referred to as “elements”) of various embodiments may be combined, separated, interchanged and / or rearranged in other ways without departing from the scope of the disclosure.

[0034] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, or any other characteristics, properties, etc. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the specific process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals and / or symbols denote the same elements.

[0035] When an element or layer is referred to as being "on" another element or layer, "connected to," or "bonded to" another element or layer, it can be directly on, directly connected to, or directly bonded to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly bonded to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection with or without an intermediary element. The first-direction axis, the second-direction axis, and the third-direction axis are not limited to the three axes of a Cartesian coordinate system (such as the X-axis, Y-axis, and Z-axis) and can be interpreted in a broader sense. For example, the first-direction axis, the second-direction axis, and the third-direction axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0036] While the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0037] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes to describe the relationship of one element to another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. Furthermore, when the terms “comprising,” “including,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are thus used to interpret the inherent deviations in measured, calculated, and / or provided values ​​that will be recognized by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±20%, ±10%, or ±5% of the stated value.

[0039] Various embodiments are described herein with reference to cross-sectional and / or exploded views as schematic diagrams of examples and / or intermediate structures. Thus, variations in the illustrated shapes will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown for a particular region, but will include shape deviations caused, for example, by manufacturing. In this way, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are thus not necessarily intended to be limiting.

[0040] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, units, parts, and / or modules. Those skilled in the art will understand that these blocks, units, parts, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, parts, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) that performs the various functions discussed herein, and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, part, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the disclosure, each block, unit, part, and / or module of some embodiments may be physically divided into two or more interactive and discrete blocks, units, parts, and / or modules. Without departing from the scope of the disclosure, blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules.

[0041] Figure 1 This is a schematic cross-sectional view showing a display device according to a disclosed embodiment.

[0042] Reference Figure 1 The display device 100 may include a substrate 101, a first thin-film transistor 110, and a second thin-film transistor 120.

[0043] Each of the first thin-film transistor 110 and the second thin-film transistor 120 may be configured to generate one or more signals for the display device 100. For example, the display device 100 may include one or more pixels, and each of the first thin-film transistor 110 and the second thin-film transistor 120 may be disposed in a pixel and may generate the same or different signals required for pixel operation.

[0044] For example, the display device 100 may include a non-display area, for instance, surrounding a display area comprising one or more pixels. The display device 100 may include a driving circuitry region within the non-display area, and this driving circuitry region may include one or more driving circuitry units that can generate one or more signals required for pixel operation and transmit those signals to the pixels. Each of the first thin-film transistor 110 and the second thin-film transistor 120 may be disposed within the driving circuitry region of the non-display area, and may be in the same or different driving circuitry units.

[0045] The first thin-film transistor 110 may include a first active layer 113 comprising at least an oxide layer, and the second thin-film transistor 120 may include a second active layer 123 comprising at least an oxide layer. The distance between the substrate 101 and the first thin-film transistor 110 may be smaller than the distance between the substrate 101 and the second thin-film transistor 120. Based on the thickness direction of the substrate 101 (e.g., ...), Figure 1 (in the Z-axis direction), the first thin-film transistor 110 can be disposed between the substrate 101 and the second thin-film transistor 120.

[0046] The display device 100 will be described in more detail below.

[0047] The substrate 101 may include various materials. In particular, the substrate 101 may be formed of glass, metal or other organic materials.

[0048] In another embodiment, the substrate 101 may be formed of a flexible material. For example, the substrate 101 may be formed to be easily flexed, bent, folded, or rolled.

[0049] The substrate 101 can be made of ultrathin glass, metal, or plastic. For example, when using plastic, the substrate 101 can contain polyimide (PI). For instance, the substrate 101 can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0050] The substrate 101 may have a structure having one or more layers, such as a multilayer structure. For example, the substrate 101 may include an organic layer (e.g., a resin-based material) and an inorganic layer, or, as a more specific example, may have a structure in which an inorganic layer is disposed between two organic layers.

[0051] In another embodiment, one or more buffer layers 102 may be disposed between the substrate 101 and the first thin-film transistor 110.

[0052] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may reduce or prevent impurities from diffusing into the first thin-film transistor 110.

[0053] The buffer layer 102 may comprise various materials such as inorganic materials. For example, the buffer layer 102 may comprise a silicon-based material. In another embodiment, the buffer layer 102 may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ) and silicon oxynitride (SiO) x N y At least one of the following.

[0054] As another example, buffer layer 102 may contain oxides, and may include, for example, at least one of metal oxides (such as aluminum oxide (Al₂O₃)). x )).

[0055] In another embodiment, the buffer layer 102 may include at least two layers of multiple layers.

[0056] The first thin-film transistor 110 may include a first active layer 113 and a first gate electrode 115.

[0057] The first thin-film transistor 110 may further include a first connecting electrode 116 and a second connecting electrode 117.

[0058] The first active layer 113 can be set on the buffer layer 102.

[0059] The first active layer 113 may include an oxide semiconductor. For example, the first active layer 113 may include zinc oxide (ZnO). x Gallium oxide (GaO) x Titanium oxide (TiO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr) x O y Indium gallium zinc oxide (IGZO) or indium gallium hafnium oxide (IGHO), and these oxides can be used alone or in combination with each other.

[0060] For example, the first active layer 113 may include indium tin gallium zinc oxide (ITGZO).

[0061] The first active layer 113 may include a first connection region 113a, a second connection region 113b, and a first channel region 113c disposed between the first connection region 113a and the second connection region 113b.

[0062] Based on the thickness direction of the substrate 101, the first gate electrode 115 can be stacked with the first active layer 113, for example, on top of the first active layer 113.

[0063] The first gate insulating film 114 can be configured to insulate between the first active layer 113 and the first gate electrode 115 (or configured between the first active layer 113 and the first gate electrode 115).

[0064] For example, a first gate insulating film 114 may be disposed on the first active layer 113. In another embodiment, the first gate insulating film 114 may be stacked with the first active layer 113. For example, the first gate insulating film 114 may be in contact with the first active layer 113.

[0065] In another embodiment, the first gate insulating film 114 may be stacked with the first channel region 113c of the first active layer 113, while being separated from the first connection region 113a and the second connection region 113b of the first active layer 113. Therefore, the first interlayer insulating layer ILD1 can be in direct contact with the first connection region 113a and the second connection region 113b. With this structure, hydrogen can diffuse from the first interlayer insulating layer ILD1, which is positioned adjacent to the first connection region 113a and the second connection region 113b, thereby increasing the conductivity of the first connection region 113a and the second connection region 113b; for example, the first connection region 113a and the second connection region 113b may become conductive.

[0066] The first gate insulating film 114 may include an insulating material. For example, the first gate insulating film 114 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and these may be used alone or in combination with each other.

[0067] The first gate electrode 115 may be disposed on the first gate insulating film 114. The first gate electrode 115 may be stacked with the first active layer 113, for example, to contact the first gate insulating film 114.

[0068] The first gate electrode 115 may include a conductive material, and may be formed of, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0069] For example, the first gate electrode 115 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), silver (Ag), tungsten (W), tungsten nitride (WN), nickel (Ni), chromium (Cr), chromium nitride (CrN), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc., and may also include alloys of conductive materials. The first gate electrode 115 may include a single layer or multiple layers comprising the above-mentioned materials.

[0070] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 115 and the first connection electrode 116 and the second connection electrode 117 (or be configured between the first gate electrode 115 and the first connection electrode 116 and the second connection electrode 117). For example, the first interlayer insulating layer ILD1 can be formed on top of the first gate electrode 115 and the first active layer 113 to cover the first gate electrode 115 and the first active layer 113.

[0071] The first interlayer insulation layer ILD1 can be disposed on the buffer layer 102. The first interlayer insulation layer ILD1 may include insulating material.

[0072] For example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, etc. Multiple contact holes may be defined within the first interlayer insulating layer ILD1.

[0073] The first connecting electrode 116 and the second connecting electrode 117 can be disposed on the first interlayer insulating layer ILD1. The first connecting electrode 116 and the second connecting electrode 117 can contact the first active layer 113 through contact holes in the first interlayer insulating layer ILD1. For example, the first connecting electrode 116 can contact the first connecting region 113a of the first active layer 113, and the second connecting electrode 117 can contact the second connecting region 113b of the first active layer 113.

[0074] Based on the signal applied to the first gate electrode 115, the first connection electrode 116 and the second connection electrode 117 can be electrically connected to each other.

[0075] Each of the first connecting electrode 116 and the second connecting electrode 117 may include one or more of a variety of conductive materials such as metals, alloys, conductive metal oxides, or transparent conductive materials. For example, each of the first connecting electrode 116 and the second connecting electrode 117 may include materials such as silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0076] The second thin-film transistor 120 may be disposed above the first thin-film transistor 110. For example, the second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 120 may be formed on the second interlayer insulating layer ILD2.

[0077] For example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 110.

[0078] The second interlayer insulating layer (ILD2) can be formed from various insulating materials. For example, the second interlayer insulating layer (ILD2) can contain inorganic materials, such as silicon oxide, silicon nitride, and silicon oxynitride. The second interlayer insulating layer (ILD2) can also contain organic materials, such as polyacrylic resin, polyimide resin, and acrylic resin.

[0079] In another embodiment, an intermediate insulating layer (not shown) may also be disposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0080] The second thin-film transistor 120 may include a second active layer 123 and a second gate electrode 125.

[0081] The second thin-film transistor 120 may also include a third connection electrode 126 and a fourth connection electrode 127.

[0082] The second active layer 123 can be disposed on the second interlayer insulating layer ILD2.

[0083] The second active layer 123 may include an oxide semiconductor. For example, the second active layer 123 may include zinc oxide (ZnO). x Gallium oxide (GaO) x Titanium oxide (TiO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr) x O y Indium gallium zinc oxide (IGZO) or indium gallium hafnium oxide (IGHO), and these oxides can be used alone or in combination with each other.

[0084] For example, the second active layer 123 may include indium tin gallium zinc oxide (ITGZO).

[0085] The second active layer 123 may include a first connection region 123a, a second connection region 123b, and a second channel region 123c disposed between the first connection region 123a and the second connection region 123b.

[0086] The second active layer 123 may contain the same oxide material as the first active layer 113. For example, the second active layer 123 and the first active layer 113 may be formed of the same material.

[0087] The second active layer 123 may be at least partially stacked with the first active layer 113, for example, the second active layer 123 may be completely stacked with the first active layer 113.

[0088] By configuring the second active layer 123 to at least partially overlap with the first active layer 113, the increased integration and reduced non-display area of ​​the display device 100 can be easily achieved.

[0089] The second gate electrode 125 may be stacked with the second active layer 123, and for example, may be disposed above the second active layer 123 in the thickness direction of the substrate 101.

[0090] The second gate insulating film 124 can be configured to insulate between the second active layer 123 and the second gate electrode 125 (or configured between the second active layer 123 and the second gate electrode 125).

[0091] For example, the second gate insulating film 124 may be disposed on the second active layer 123. In another embodiment, the second gate insulating film 124 may be stacked with the second active layer 123. For example, the second gate insulating film 124 may be configured to contact the second active layer 123.

[0092] In another embodiment, the second gate insulating film 124 may be stacked with the second channel region 123c of the second active layer 123 and may be separated from the first connection region 123a and the second connection region 123b of the second active layer 123. Therefore, the third interlayer insulating layer ILD3 may be in direct contact with the first connection region 123a and the second connection region 123b. With this structure, hydrogen can diffuse from the third interlayer insulating layer ILD3, which is positioned adjacent to the first connection region 123a and the second connection region 123b, thereby increasing the conductivity of the first connection region 123a and the second connection region 123b; for example, the first connection region 123a and the second connection region 123b may become conductive.

[0093] The second gate insulating film 124 may include an insulating material. For example, the second gate insulating film 124 may include silicon oxide, silicon nitride, silicon oxynitride, etc., and these may be used alone or in combination with each other.

[0094] The second gate electrode 125 may be disposed on the second gate insulating film 124. The second gate electrode 125 may be stacked with the second active layer 123, for example, to contact the second gate insulating film 124.

[0095] The second gate electrode 125 may include a conductive material, and may be formed of, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc.

[0096] For example, the second gate electrode 125 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), silver (Ag), tungsten (W), tungsten nitride (WN), nickel (Ni), chromium (Cr), chromium nitride (CrN), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc., and may also include alloys of conductive materials. The second gate electrode 125 may include a single layer or multiple layers comprising the above-mentioned materials.

[0097] The third interlayer insulating layer (ILD3) can be configured to insulate between the second gate electrode 125 and the third connection electrode 126 and the fourth connection electrode 127 (or be configured between the second gate electrode 125 and the third connection electrode 126 and the fourth connection electrode 127). For example, the third interlayer insulating layer (ILD3) can be formed on top of the second gate electrode 125 and the second active layer 123 to cover the second gate electrode 125 and the second active layer 123.

[0098] The third interlayer insulation layer ILD3 can be disposed on the second interlayer insulation layer ILD2.

[0099] The third interlayer insulating layer (ILD3) may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. Multiple contact holes may be defined within the third interlayer insulating layer (ILD3).

[0100] The third connecting electrode 126 and the fourth connecting electrode 127 can be disposed on the third interlayer insulating layer ILD3. The third connecting electrode 126 and the fourth connecting electrode 127 can contact the second active layer 123 through contact holes in the third interlayer insulating layer ILD3. For example, the third connecting electrode 126 can contact the first connecting region 123a of the second active layer 123, and the fourth connecting electrode 127 can contact the second connecting region 123b of the second active layer 123.

[0101] Based on the signal applied to the second gate electrode 125, the third connection electrode 126 and the fourth connection electrode 127 can be electrically connected to each other.

[0102] Each of the third connecting electrode 126 and the fourth connecting electrode 127 may include one or more of a variety of conductive materials such as metals, alloys, conductive metal oxides, or transparent conductive materials. For example, each of the third connecting electrode 126 and the fourth connecting electrode 127 may include materials such as silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0103] The first thin-film transistor 110 and the second thin-film transistor 120 can be configured to be aligned in the thickness direction of the substrate 101 (e.g., Figure 1 The first active layer 113 of the first thin-film transistor 110 may be stacked with the second active layer 123 of the second thin-film transistor 120, and the first gate electrode 115 may be stacked with the second gate electrode 125.

[0104] In the display device 100 of the embodiment, a first thin-film transistor 110 may be disposed on a substrate 101, and a second thin-film transistor 120 may be disposed above the first thin-film transistor 110. The second active layer 123 of the second thin-film transistor 120, which includes oxide, may be disposed on the first active layer 113 of the first thin-film transistor 110, which includes oxide.

[0105] With this structure, by forming the first active layer 113 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 110 disposed at a lower position in the thickness direction of the substrate 101, and similarly without using a high-energy process (e.g., laser crystallization) when forming the second active layer 123 disposed at a higher position, thermal damage to the first thin-film transistor 110 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 113 and the second active layer 123 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0106] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 120 is disposed above the first thin-film transistor 110 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and high resolution of the display device 100 can be easily achieved.

[0107] Figure 2 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0108] Reference Figure 2 The display device 200 may include a substrate 201, a first thin-film transistor 210, and a second thin-film transistor 220.

[0109] For ease of description, the main differences from the embodiments described above will be described.

[0110] The first thin-film transistor 210 may include a first active layer 213 comprising at least an oxide layer, and the second thin-film transistor 220 may include a second active layer 223 comprising at least an oxide layer. The distance between the substrate 201 and the first thin-film transistor 210 may be smaller than the distance between the substrate 201 and the second thin-film transistor 220. This is based on the thickness direction of the substrate 201 (e.g., Figure 2(In the Z-axis direction), the first thin-film transistor 210 can be disposed between the substrate 201 and the second thin-film transistor 220. The first active layer 213 may include a first connection region 213a, a second connection region 213b, and a first channel region 213c disposed between the first connection region 213a and the second connection region 213b. The second active layer 223 may include a first connection region 223a, a second connection region 223b, and a second channel region 223c disposed between the first connection region 223a and the second connection region 223b.

[0111] The display device 200 will be described in more detail below.

[0112] The substrate 201 may include various materials, and other details of the materials comprising the substrate 201 are substantially the same as those of the substrate 101 in the above embodiments, and therefore their detailed description will be omitted.

[0113] In another embodiment, one or more buffer layers 202 may be disposed between the substrate 201 and the first thin-film transistor 210. Since the further details of the buffer layer 202 are substantially the same as those of the buffer layer 102 in the above embodiment, their detailed description will be omitted.

[0114] The first thin-film transistor 210 may include a first active layer 213 and a first gate electrode 215.

[0115] The first thin-film transistor 210 may further include a first connecting electrode 216 and a second connecting electrode 217.

[0116] The first active layer 213 may be disposed on the buffer layer 202. The first active layer 213 may include an oxide semiconductor. Further details of the material comprising the first active layer 213 are substantially the same as those of the first active layer 113 in the above embodiments, and therefore their detailed description will be omitted.

[0117] Based on the thickness direction of the substrate 201, the first gate electrode 215 can be stacked with the first active layer 213, for example, on top of the first active layer 213.

[0118] The first gate insulating film 214 can be configured to insulate between the first active layer 213 and the first gate electrode 215 (or configured between the first active layer 213 and the first gate electrode 215).

[0119] Since the further details of the first gate insulating film 214 are substantially the same as those of the first gate insulating film 114 in the above embodiments, their detailed description will be omitted.

[0120] The first gate electrode 215 may be disposed on the first gate insulating film 214. The first gate electrode 215 may be stacked with the first active layer 213, for example, to contact the first gate insulating film 214.

[0121] Since the further details of the first gate electrode 215 are substantially the same as those of the first gate electrode 115 in the above embodiments, their detailed description will be omitted.

[0122] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 215 and the first connecting electrode 216 and the second connecting electrode 217 (or configured between the first gate electrode 215 and the first connecting electrode 216 and the second connecting electrode 217). Further details of the first interlayer insulating layer ILD1 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0123] The first connecting electrode 216 and the second connecting electrode 217 may be disposed on the first interlayer insulating layer ILD1. Further details of the first connecting electrode 216 and the second connecting electrode 217 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the above embodiments, and therefore their detailed description will be omitted.

[0124] The second thin-film transistor 220 may be disposed above the first thin-film transistor 210. For example, the second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 220 may be formed on the second interlayer insulating layer ILD2.

[0125] For example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 210. Further details of the second interlayer insulating layer ILD2 are substantially the same as those described in the above embodiments, and therefore their detailed description will be omitted.

[0126] The second thin-film transistor 220 may include a second active layer 223 and a second gate electrode 225.

[0127] The second thin-film transistor 220 may also include a third connection electrode 226 and a fourth connection electrode 227.

[0128] The second active layer 223 can be disposed on the second interlayer insulating layer ILD2.

[0129] The second active layer 223 may include an oxide semiconductor.

[0130] Further details regarding the material of the second active layer 223 are substantially the same as those of the second active layer 123 in the above embodiments, and therefore, a detailed description thereof will be omitted.

[0131] The second active layer 223 may contain the same oxide material as the first active layer 213. For example, the second active layer 223 and the first active layer 213 may be formed of the same material.

[0132] The second active layer 223 may be at least partially superimposed on the first active layer 213. For example, the superimposed region ORA, which is a portion of the second active layer 223, may be superimposed on the first active layer 213. A non-superimposed region NRA1, which is adjacent to the superimposed region ORA, which is a portion of the second active layer 223, may not be superimposed on the first active layer 213. Similarly, a non-superimposed region NRA2, which is a portion of the first active layer 213, may not be superimposed on the second active layer 223.

[0133] By configuring the second active layer 223 to at least partially overlap with the first active layer 213, the increased integration and reduced non-display area of ​​the display device 200 can be easily achieved.

[0134] By having a second active layer 223 that is partially superimposed and not partially superimposed with the first active layer 213, when designing circuit regions by stacking them up and down in the thickness direction of the substrate 201, the design of reducing mutual signal interference can be precisely achieved by selectively controlling the regions that reduce interference and the regions that do not reduce interference.

[0135] The second gate electrode 225 may be stacked with the second active layer 223, and for example, it may be disposed above the second active layer 223 in the thickness direction of the substrate 201.

[0136] The second gate insulating film 224 can be configured to insulate between the second active layer 223 and the second gate electrode 225 (or be configured between the second active layer 223 and the second gate electrode 225).

[0137] Further details of the second gate insulating film 224 are substantially the same as those of the second gate insulating film 124 in the above embodiments, and therefore their detailed description will be omitted.

[0138] The second gate electrode 225 may be disposed on the second gate insulating film 224. The second gate electrode 225 may be stacked with the second active layer 223, for example, to contact the second gate insulating film 224.

[0139] Further details of the second gate electrode 225 are substantially the same as those of the second gate electrode 125 in the above embodiments, and therefore their detailed description will be omitted.

[0140] The third interlayer insulating layer ILD3 can be configured to insulate between the second gate electrode 225 and the third connection electrode 226 and the fourth connection electrode 227 (or be configured between the second gate electrode 225 and the third connection electrode 226 and the fourth connection electrode 227). For example, the third interlayer insulating layer ILD3 can be formed on top of the second gate electrode 225 and the second active layer 223 to cover the second gate electrode 225 and the second active layer 223. Further details of the third interlayer insulating layer ILD3 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0141] The third connecting electrode 226 and the fourth connecting electrode 227 may be disposed on the third interlayer insulating layer ILD3. Further details of the third connecting electrode 226 and the fourth connecting electrode 227 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the above embodiments, and therefore their detailed description will be omitted.

[0142] The first thin-film transistor 210 and the second thin-film transistor 220 can be configured such that a region is in the thickness direction of the substrate 201 (e.g., Figure 2 The first thin-film transistor 210 has a stacked region ORA in the Z-axis direction, and is configured to have non-stacked regions NRA1 and NRA2 in another region adjacent to the stacked region ORA. For example, the first active layer 213 of the first thin-film transistor 210 may be stacked with the second active layer 223 of the second thin-film transistor 220 in at least one region, and may not be stacked with the second active layer 223 in another region.

[0143] In the display device 200 of this embodiment, a first thin-film transistor 210 may be disposed on a substrate 201, and a second thin-film transistor 220 may be disposed above the first thin-film transistor 210. A second active layer 223 comprising oxide of the second thin-film transistor 220 may be disposed above the first active layer 213 comprising oxide of the first thin-film transistor 210.

[0144] With this structure, by forming the first active layer 213 without using high-energy processes (e.g., laser crystallization) when forming the first thin-film transistor 210 disposed at a lower position in the thickness direction of the substrate 201, and similarly without using high-energy processes (e.g., laser crystallization) when forming the second active layer 223 disposed at a higher position, thermal damage to the first thin-film transistor 210 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 213 and the second active layer 223 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0145] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 220 is disposed above the first thin-film transistor 210 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and high resolution of the display device 200 can be easily achieved.

[0146] By partially stacking and partially not stacking the second active layer 223 with the first active layer 213, and constructing the circuit region by stacking the second active layer 223 with the first active layer 213 in the thickness direction of the substrate 201, the design of reducing mutual signal interference can be precisely achieved by selectively controlling the regions that reduce interference and the regions that do not reduce interference.

[0147] Figure 3 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0148] Reference Figure 3 The display device 300 may include a substrate 301, a first thin-film transistor 310, and a second thin-film transistor 320.

[0149] For ease of description, the main differences from the embodiments described above will be described.

[0150] The first thin-film transistor 310 may include a first active layer 313 comprising at least an oxide layer, and the second thin-film transistor 320 may include a second active layer 323 comprising at least an oxide layer. The distance between the substrate 301 and the first thin-film transistor 310 may be smaller than the distance between the substrate 301 and the second thin-film transistor 320. This is based on the thickness direction of the substrate 301 (e.g., Figure 3 (In the Z-axis direction), the first thin-film transistor 310 can be disposed between the substrate 301 and the second thin-film transistor 320. The first active layer 313 may include a first connection region 313a, a second connection region 313b, and a first channel region 313c disposed between the first connection region 313a and the second connection region 313b. The second active layer 323 may include a first connection region 323a, a second connection region 323b, and a second channel region 323c disposed between the first connection region 323a and the second connection region 323b.

[0151] The display device 300 will be described in more detail below.

[0152] The substrate 301 may include various materials, and other details of the materials comprising the substrate 301 are substantially the same as those of the substrate 101 in the above embodiments, and therefore their detailed description will be omitted.

[0153] In another embodiment, one or more buffer layers 302 may be disposed between the substrate 301 and the first thin-film transistor 310. Since the further details of the buffer layer 302 are substantially the same as those of the buffer layer 102 in the above embodiment, their detailed description will be omitted.

[0154] The first thin-film transistor 310 may include a first active layer 313 and a first gate electrode 315.

[0155] The first thin-film transistor 310 may further include a first connecting electrode 316 and a second connecting electrode 317.

[0156] The first active layer 313 may be disposed on the buffer layer 302. The first active layer 313 may include an oxide semiconductor. Further details of the material comprising the first active layer 313 are substantially the same as those of the first active layer 113 in the above embodiments, and therefore their detailed description will be omitted.

[0157] Based on the thickness direction of the substrate 301, the first gate electrode 315 can be stacked with the first active layer 313, for example, on top of the first active layer 313.

[0158] The first gate insulating film 314 can be configured to insulate between the first active layer 313 and the first gate electrode 315 (or configured between the first active layer 313 and the first gate electrode 315).

[0159] Since the further details of the first gate insulating film 314 are substantially the same as those of the first gate insulating film 114 in the above embodiments, their detailed description will be omitted.

[0160] The first gate electrode 315 may be disposed on the first gate insulating film 314. The first gate electrode 315 may be stacked with the first active layer 313, for example, to contact the first gate insulating film 314.

[0161] Since the further details of the first gate electrode 315 are substantially the same as those of the first gate electrode 115 in the above embodiments, their detailed description will be omitted.

[0162] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 315 and the first connecting electrode 316 and the second connecting electrode 317 (or configured between the first gate electrode 315 and the first connecting electrode 316 and the second connecting electrode 317). Further details of the first interlayer insulating layer ILD1 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0163] The first connecting electrode 316 and the second connecting electrode 317 may be disposed on the first interlayer insulating layer ILD1. Further details of the first connecting electrode 316 and the second connecting electrode 317 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the above embodiments, and therefore their detailed description will be omitted.

[0164] The second thin-film transistor 320 may be disposed above the first thin-film transistor 310. For example, the second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 320 may be formed on the second interlayer insulating layer ILD2.

[0165] For example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 310. Further details of the second interlayer insulating layer ILD2 are substantially the same as those described in the above embodiments, and therefore their detailed description will be omitted.

[0166] The second thin-film transistor 320 may include a second active layer 323 and a second gate electrode 325.

[0167] The second thin-film transistor 320 may also include a third connection electrode 326 and a fourth connection electrode 327.

[0168] The second active layer 323 can be disposed on the second interlayer insulating layer ILD2.

[0169] The second active layer 323 may include an oxide semiconductor.

[0170] Further details regarding the material of the second active layer 323 are substantially the same as those of the second active layer 123 in the above embodiments, and therefore, their detailed description will be omitted.

[0171] The second active layer 323 may contain the same oxide material as the first active layer 313. For example, the second active layer 323 and the first active layer 313 may be formed of the same material.

[0172] The second active layer 323 can be configured not to be stacked with the first active layer 313. For example, the second active layer 323 can be located in the thickness direction of the substrate 301 ( Figure 3 It is not superimposed on the first active layer 313 in the Z-axis direction.

[0173] For example, the extension line of the side surface of the first active layer 313 can be configured to have a separation gap LO with the extension line of the side surface of the second active layer 323.

[0174] In another embodiment, when viewed in the thickness direction of the substrate 301 (or in a plan view), the first active layer 313 and the second active layer 323 can be configured to be separated from each other. This allows for easy implementation of a vertically stacked structure of the first thin-film transistor 310 and the second thin-film transistor 320 in the thickness direction of the substrate 301, while reducing mutual signal interference between the first thin-film transistor 310 and the second thin-film transistor 320.

[0175] The second gate electrode 325 may be stacked with the second active layer 323, and for example, it may be disposed above the second active layer 323 in the thickness direction of the substrate 301.

[0176] The second gate insulating film 324 can be configured to insulate between the second active layer 323 and the second gate electrode 325 (or be configured between the second active layer 323 and the second gate electrode 325).

[0177] Further details of the second gate insulating film 324 are substantially the same as those of the second gate insulating film 124 in the above embodiments, and therefore their detailed description will be omitted.

[0178] The second gate electrode 325 may be disposed on the second gate insulating film 324. The second gate electrode 325 may be stacked with the second active layer 323, for example, to contact the second gate insulating film 324.

[0179] Further details of the second gate electrode 325 are substantially the same as those of the second gate electrode 125 in the above embodiments, and therefore their detailed description will be omitted.

[0180] The third interlayer insulating layer ILD3 can be configured to insulate between the second gate electrode 325 and the third connection electrode 326 and the fourth connection electrode 327 (or be configured between the second gate electrode 325 and the third connection electrode 326 and the fourth connection electrode 327). For example, the third interlayer insulating layer ILD3 can be formed on top of the second gate electrode 325 and the second active layer 323 to cover the second gate electrode 325 and the second active layer 323. Further details of the third interlayer insulating layer ILD3 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0181] The third connecting electrode 326 and the fourth connecting electrode 327 may be disposed on the third interlayer insulating layer ILD3. Further details of the third connecting electrode 326 and the fourth connecting electrode 327 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the above embodiments, and therefore their detailed description will be omitted.

[0182] The second active layer 323 can be configured not to be stacked with the first active layer 313. For example, the second active layer 323 can be located in the thickness direction of the substrate 301 ( Figure 3 It is not superimposed on the first active layer 313 in the Z-axis direction.

[0183] In the display device 300 of this embodiment, a first thin-film transistor 310 may be disposed on a substrate 301, and a second thin-film transistor 320 may be disposed above the first thin-film transistor 310. A second active layer 323 comprising oxide of the second thin-film transistor 320 may be disposed above a first active layer 313 comprising oxide of the first thin-film transistor 310.

[0184] With this structure, by forming the first active layer 313 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 310 disposed at a lower position in the thickness direction of the substrate 301, and similarly without using a high-energy process (e.g., laser crystallization) when forming the second active layer 323 disposed at a higher position, thermal damage to the first thin-film transistor 310 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 313 and the second active layer 323 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0185] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 320 is disposed above the first thin-film transistor 310 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and high resolution of the display device 300 can be easily achieved.

[0186] By arranging the first active layer 313 and the second active layer 323 to be separated from each other in the thickness direction of the substrate 301, the vertical stacking structure of the first thin film transistor 310 and the second thin film transistor 320 in the thickness direction of the substrate 301 can be easily realized, while reducing mutual signal interference between the first thin film transistor 310 and the second thin film transistor 320.

[0187] Figure 4 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0188] Reference Figure 4 The display device 400 may include a substrate 401, a first thin-film transistor 410, and a second thin-film transistor 420.

[0189] It may also include a first conductive pattern portion BML1 or a second conductive pattern portion BML2. Figure 4The image shows both the first conductive pattern portion BML1 and the second conductive pattern portion BML2, but this is another embodiment, and the display device 400 may include only one of the first conductive pattern portion BML1 and the second conductive pattern portion BML2.

[0190] For ease of description, the main differences from the embodiments described above will be described.

[0191] The first thin-film transistor 410 may include a first active layer 413 comprising at least an oxide layer, and the second thin-film transistor 420 may include a second active layer 423 comprising at least an oxide layer. The distance between the substrate 401 and the first thin-film transistor 410 may be smaller than the distance between the substrate 401 and the second thin-film transistor 420. This is based on the thickness direction of the substrate 401 (e.g., Figure 4 (In the Z-axis direction), the first thin-film transistor 410 can be disposed between the substrate 401 and the second thin-film transistor 420. The first active layer 413 may include a first connection region 413a, a second connection region 413b, and a first channel region 413c disposed between the first connection region 413a and the second connection region 413b. The second active layer 423 may include a first connection region 423a, a second connection region 423b, and a second channel region 423c disposed between the first connection region 423a and the second connection region 423b.

[0192] The display device 400 will be described in more detail below.

[0193] The substrate 401 may include various materials, and other details of the materials comprising the substrate 401 are substantially the same as those of the substrate 101 in the above embodiments, and therefore their detailed description will be omitted.

[0194] In another embodiment, one or more buffer layers 402 may be disposed between the substrate 401 and the first thin-film transistor 410. Since the further details of the buffer layer 402 are substantially the same as those of the buffer layer 102 in the above embodiment, their detailed description will be omitted.

[0195] The first thin-film transistor 410 may include a first active layer 413 and a first gate electrode 415.

[0196] The first thin-film transistor 410 may further include a first connecting electrode 416 and a second connecting electrode 417.

[0197] The first conductive pattern portion BML1 can be disposed between the first active layer 413 and the substrate 401.

[0198] For example, the first conductive pattern portion BML1 may have a region superimposed on the first active layer 413 and may be disposed between the substrate 401 and the buffer layer 402.

[0199] The first conductive pattern portion BML1 can be used as a light-blocking component to protect the first active layer 413 or the first thin-film transistor 410 by reducing or blocking light that may enter the substrate 401. For this purpose, the first conductive pattern portion BML1 can include a light-blocking material and / or a light-absorbing material. For example, the first conductive pattern portion BML1 may include an opaque metal layer.

[0200] In another embodiment, the first conductive pattern portion BML1 can be electrically connected to the first connection electrode 416 or the second connection electrode 417 through contact holes that sequentially pass through the first interlayer insulating layer ILD1 and the buffer layer 402. This expands the driving range of the predetermined voltage supplied to the first gate electrode 415 of the first thin-film transistor 410, and as another example, stabilizes the first channel region 413c of the first active layer 413.

[0201] In another embodiment, the first conductive pattern portion BML1 may include various metals and may be formed as a single layer, either alone or as a mixture, of a suitable (or selected) material from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. In another embodiment, to reduce wiring resistance, the first conductive pattern portion BML1 may be formed as a double-layer or multi-layer structure using a low-resistance material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0202] The first active layer 413 may be disposed on the buffer layer 402. The first active layer 413 may include an oxide semiconductor. Further details of the material comprising the first active layer 413 are substantially the same as those of the first active layer 113 in the above embodiments, and therefore their detailed description will be omitted.

[0203] Based on the thickness direction of the substrate 401, the first gate electrode 415 can be stacked with the first active layer 413, for example, on top of the first active layer 413.

[0204] The first gate insulating film 414 can be configured to insulate between the first active layer 413 and the first gate electrode 415 (or configured between the first active layer 413 and the first gate electrode 415).

[0205] Since the further details of the first gate insulating film 414 are substantially the same as those of the first gate insulating film 114 in the above embodiments, their detailed description will be omitted.

[0206] The first gate electrode 415 may be disposed on the first gate insulating film 414. The first gate electrode 415 may be stacked with the first active layer 413, for example, to contact the first gate insulating film 414.

[0207] Since the further details of the first gate electrode 415 are substantially the same as those of the first gate electrode 115 in the above embodiments, their detailed description will be omitted.

[0208] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 415 and the first connecting electrode 416 and the second connecting electrode 417 (or configured between the first gate electrode 415 and the first connecting electrode 416 and the second connecting electrode 417). Further details of the first interlayer insulating layer ILD1 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0209] The first connecting electrode 416 and the second connecting electrode 417 may be disposed on the first interlayer insulating layer ILD1. Further details of the first connecting electrode 416 and the second connecting electrode 417 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the above embodiments, and therefore their detailed description will be omitted.

[0210] The second thin-film transistor 420 may be disposed above the first thin-film transistor 410. For example, the second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 420 may be formed on the second interlayer insulating layer ILD2.

[0211] For example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 410. Further details of the second interlayer insulating layer ILD2 are substantially the same as those described in the above embodiments, and therefore their detailed description will be omitted.

[0212] The second thin-film transistor 420 may include a second active layer 423 and a second gate electrode 425.

[0213] The second thin-film transistor 420 may also include a third connection electrode 426 and a fourth connection electrode 427.

[0214] The second conductive pattern portion BML2 can be disposed between the second active layer 423 and the second interlayer insulating layer ILD2.

[0215] For example, the second conductive pattern portion BML2 may have a region superimposed on the second active layer 423, and may be disposed between the second active layer 423 and the second interlayer insulating layer ILD2.

[0216] The second conductive pattern portion BML2 can be used as a light-blocking component to protect the second active layer 423 or the second thin-film transistor 420 by reducing or blocking light that may enter the substrate 401. For this purpose, the second conductive pattern portion BML2 can include light-blocking materials and / or light-absorbing materials. For example, the second conductive pattern portion BML2 may include an opaque metal layer.

[0217] In another embodiment, the second conductive pattern portion BML2 can be electrically connected to the third connection electrode 426 or the fourth connection electrode 427 through contact holes sequentially passing through the third interlayer insulating layer ILD3 and the upper buffer layer 403. This expands the driving range of the predetermined voltage supplied to the second gate electrode 425 of the second thin-film transistor 420, and as another example, stabilizes the second channel region 423c of the second active layer 423.

[0218] In another embodiment, the second conductive pattern portion BML2 may include various metals and may be formed as a single layer, either alone or as a mixture, of a suitable (or selected) material from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. In another embodiment, to reduce wiring resistance, the second conductive pattern portion BML2 may be formed as a double-layer or multi-layer structure using a low-resistance material such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag).

[0219] One or more upper buffer layers 403 may be disposed between the second conductive pattern portion BML2 and the second active layer 423, and the upper buffer layer 403 may include one or more of the materials contained in the buffer layer 402, and for example, may be formed of the same material as the buffer layer 402.

[0220] The second active layer 423 can be disposed on the second interlayer insulating layer ILD2.

[0221] The second active layer 423 may include an oxide semiconductor.

[0222] Further details regarding the material of the second active layer 423 are substantially the same as those of the second active layer 123 in the above embodiments, and therefore, their detailed description will be omitted.

[0223] The second active layer 423 may contain the same oxide material as the first active layer 413. For example, the second active layer 423 and the first active layer 413 may be formed of the same material.

[0224] The second active layer 423 may be at least partially stacked with the first active layer 413, or in another embodiment, such as Figure 3 As shown, it may not be superimposed with the first active layer 413.

[0225] The second gate electrode 425 may be stacked with the second active layer 423, and for example, it may be disposed above the second active layer 423 in the thickness direction of the substrate 401.

[0226] The second gate insulating film 424 can be configured to insulate between the second active layer 423 and the second gate electrode 425 (or be configured between the second active layer 423 and the second gate electrode 425).

[0227] Further details of the second gate insulating film 424 are substantially the same as those of the second gate insulating film 124 in the above embodiments, and therefore their detailed description will be omitted.

[0228] The second gate electrode 425 may be disposed on the second gate insulating film 424. The second gate electrode 425 may be stacked with the second active layer 423, for example, to contact the second gate insulating film 424.

[0229] Further details of the second gate electrode 425 are substantially the same as those of the second gate electrode 125 in the above embodiments, and therefore their detailed description will be omitted.

[0230] The third interlayer insulating layer ILD3 can be configured to insulate between the second gate electrode 425 and the third connection electrode 426 and the fourth connection electrode 427 (or be configured between the second gate electrode 425 and the third connection electrode 426 and the fourth connection electrode 427). For example, the third interlayer insulating layer ILD3 can be formed on top of the second gate electrode 425 and the second active layer 423 to cover the second gate electrode 425 and the second active layer 423. Further details of the third interlayer insulating layer ILD3 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0231] The third connecting electrode 426 and the fourth connecting electrode 427 may be disposed on the third interlayer insulating layer ILD3. Further details of the third connecting electrode 426 and the fourth connecting electrode 427 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the above embodiments, and therefore their detailed description will be omitted.

[0232] In the display device 400 of this embodiment, a first thin-film transistor 410 may be disposed on a substrate 401, and a second thin-film transistor 420 may be disposed above the first thin-film transistor 410. A second active layer 423 comprising oxide of the second thin-film transistor 420 may be disposed above a first active layer 413 comprising oxide of the first thin-film transistor 410.

[0233] With this structure, by forming the first active layer 413 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 410 disposed at a lower position in the thickness direction of the substrate 401, and similarly without using a high-energy process (e.g., laser crystallization) when forming the second active layer 423 disposed at a higher position, thermal damage to the first thin-film transistor 410 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 413 and the second active layer 423 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0234] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 420 is disposed above the first thin-film transistor 410 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and high resolution of the display device 400 can be easily achieved.

[0235] By including a first conductive pattern portion BML1 or a second conductive pattern portion BML2, the display device 400 can reduce or prevent changes in the physical or electrical properties of the first active layer 413 or the second active layer 423 containing oxide due to light. By arranging the first conductive pattern portion BML1 or the second conductive pattern portion BML2 to be electrically connected to the conductive layer of the first thin-film transistor 410 or the second thin-film transistor 420 (e.g., to one of the connecting electrodes), the first thin-film transistor 410 or the second thin-film transistor 420 can have improved electrical properties and its precision control properties can also be enhanced. This improves the precision driving characteristics of the display device 400, thereby facilitating the easier achievement of high resolution.

[0236] Figure 5 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0237] Reference Figure 5 The display device 500 may include a substrate 501, a first thin-film transistor 510, and a second thin-film transistor 520.

[0238] The display device 500 may also include an intermediate conductive layer BBM between the first thin-film transistor 510 and the second thin-film transistor 520.

[0239] For ease of description, the main differences from the embodiments described above will be described.

[0240] The first thin-film transistor 510 may include a first active layer 513 comprising at least an oxide layer, and the second thin-film transistor 520 may include a second active layer 523 comprising at least an oxide layer. The distance between the substrate 501 and the first thin-film transistor 510 may be smaller than the distance between the substrate 501 and the second thin-film transistor 520. This is based on the thickness direction of the substrate 501 (e.g., Figure 5 (In the Z-axis direction), the first thin-film transistor 510 can be disposed between the substrate 501 and the second thin-film transistor 520. The first active layer 513 may include a first connection region 513a, a second connection region 513b, and a first channel region 513c disposed between the first connection region 513a and the second connection region 513b. The second active layer 523 may include a first connection region 523a, a second connection region 523b, and a second channel region 523c disposed between the first connection region 523a and the second connection region 523b.

[0241] The display device 500 will be described in more detail below.

[0242] The substrate 501 may include various materials, and other details of the materials comprising the substrate 501 are substantially the same as those of the substrate 101 in the above embodiments, and therefore their detailed description will be omitted.

[0243] In another embodiment, one or more buffer layers 502 may be disposed between the substrate 501 and the first thin-film transistor 510. Since the further details of the buffer layer 502 are substantially the same as those of the buffer layer 102 in the above embodiment, their detailed description will be omitted.

[0244] The first thin-film transistor 510 may include a first active layer 513 and a first gate electrode 515.

[0245] The first thin-film transistor 510 may further include a first connecting electrode 516 and a second connecting electrode 517.

[0246] In another embodiment, the first conductive pattern portion BML1 may be disposed between the first active layer 513 and the substrate 501. Since the further details of the first conductive pattern portion BML1 are substantially the same as those in the above embodiments, a detailed description will be omitted.

[0247] The first active layer 513 may be disposed on the buffer layer 502. The first active layer 513 may include an oxide semiconductor. Further details of the material comprising the first active layer 513 are substantially the same as those of the first active layer 113 in the above embodiments, and therefore their detailed description will be omitted.

[0248] Based on the thickness direction of the substrate 501, the first gate electrode 515 can be stacked with the first active layer 513, for example, on top of the first active layer 513.

[0249] The first gate insulating film 514 can be configured to insulate between the first active layer 513 and the first gate electrode 515 (or configured between the first active layer 513 and the first gate electrode 515).

[0250] Since the further details of the first gate insulating film 514 are substantially the same as those of the first gate insulating film 114 in the above embodiments, their detailed description will be omitted.

[0251] The first gate electrode 515 may be disposed on the first gate insulating film 514. The first gate electrode 515 may be stacked with the first active layer 513, for example, to contact the first gate insulating film 514.

[0252] Since the further details of the first gate electrode 515 are substantially the same as those of the first gate electrode 115 in the above embodiments, their detailed description will be omitted.

[0253] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 515 and the first connecting electrode 516 and the second connecting electrode 517 (or configured between the first gate electrode 515 and the first connecting electrode 516 and the second connecting electrode 517). Further details of the first interlayer insulating layer ILD1 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0254] The first connecting electrode 516 and the second connecting electrode 517 may be disposed on the first interlayer insulating layer ILD1. Further details of the first connecting electrode 516 and the second connecting electrode 517 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the above embodiments, and therefore their detailed description will be omitted.

[0255] The second thin-film transistor 520 can be disposed above the first thin-film transistor 510.

[0256] For example, the intermediate conductive layer BBM can be disposed between the first thin film transistor 510 and the second thin film transistor 520.

[0257] The intermediate conductive layer BBM may include conductive materials and may include one of various metals.

[0258] The intermediate conductive layer BBM can be disposed between the first thin film transistor 510 and the second thin film transistor 520 to reduce electrical signal interference that may occur between the first thin film transistor 510 and the second thin film transistor 520.

[0259] The intermediate conductive layer BBM can be formed to be stacked with at least one region of each of the first thin film transistor 510 and the second thin film transistor 520.

[0260] In another embodiment, the intermediate conductive layer BBM can be electrically connected via contact holes to a conductive layer in the same layer as the intermediate conductive layer BBM or above the intermediate conductive layer BBM. For example, it can be electrically connected to a conductive layer in the same layer as one of the components of the second thin film transistor 520 or above one of the components of the second thin film transistor 520.

[0261] In another embodiment, the intermediate conductive layer BBM can be electrically connected via contact holes to a conductive layer in the same layer as the intermediate conductive layer BBM or below the intermediate conductive layer BBM. For example, it can be electrically connected to a conductive layer in the same layer as one of the components of the first thin film transistor 510 or above one of the components of the first thin film transistor 510.

[0262] To successfully implement the above structure, the intermediate conductive layer BBM can have a width corresponding to or larger than the width of each of the first thin-film transistor 510 and the second thin-film transistor 520 in one direction. In another embodiment, the intermediate conductive layer BBM can be formed to overlap with each of the first active layer 513 and the second active layer 523, while at least corresponding to the width of each of the first active layer 513 and the second active layer 523 in one direction, and can be formed to have a width extending beyond the aforementioned width.

[0263] The intermediate conductive layer BBM can be disposed between insulating layers, such as between the lower ILD21 and the upper ILD22 of the second interlayer insulating layer.

[0264] The second thin-film transistor 520 may include a second active layer 523 and a second gate electrode 525.

[0265] The second thin-film transistor 520 may also include a third connection electrode 526 and a fourth connection electrode 527.

[0266] In another embodiment, the second conductive pattern portion BML2 may be disposed between the second active layer 523 and the upper ILD22 of the second interlayer insulating layer. Further details of the second conductive pattern portion BML2 are substantially the same as those in the above embodiments, and therefore a detailed description thereof will be omitted.

[0267] In another embodiment, one or more upper buffer layers 503 may be disposed between the second conductive pattern portion BML2 and the second active layer 523.

[0268] The second active layer 523 can be disposed on the upper layer ILD22 of the second interlayer insulating layer.

[0269] The second active layer 523 may include an oxide semiconductor.

[0270] Further details of the material including the second active layer 523 are substantially the same as those of the second active layer 123 in the above embodiments, therefore, their detailed description will be omitted.

[0271] The second active layer 523 may contain the same oxide material as the first active layer 513. For example, the second active layer 523 and the first active layer 513 may be formed of the same material.

[0272] The second active layer 523 may be at least partially stacked with the first active layer 513, or in another embodiment, such as Figure 3 As shown, it may not be superimposed with the first active layer 513.

[0273] The second gate electrode 525 may be stacked with the second active layer 523, and for example, it may be disposed above the second active layer 523 in the thickness direction of the substrate 501.

[0274] The second gate insulating film 524 can be configured to insulate between the second active layer 523 and the second gate electrode 525 (or configured between the second active layer 523 and the second gate electrode 525).

[0275] Further details of the second gate insulating film 524 are substantially the same as those of the second gate insulating film 124 in the above embodiments, and therefore their detailed description will be omitted.

[0276] The second gate electrode 525 may be disposed on the second gate insulating film 524. The second gate electrode 525 may be stacked with the second active layer 523, for example, to contact the second gate insulating film 524.

[0277] Further details of the second gate electrode 525 are substantially the same as those of the second gate electrode 125 in the above embodiments, and therefore their detailed description will be omitted.

[0278] The third interlayer insulating layer ILD3 can be configured to insulate between the second gate electrode 525 and the third connection electrode 526 and the fourth connection electrode 527 (or be configured between the second gate electrode 525 and the third connection electrode 526 and the fourth connection electrode 527). For example, the third interlayer insulating layer ILD3 can be formed on top of the second gate electrode 525 and the second active layer 523 to cover the second gate electrode 525 and the second active layer 523. Further details of the third interlayer insulating layer ILD3 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0279] The third connecting electrode 526 and the fourth connecting electrode 527 may be disposed on the third interlayer insulating layer ILD3. Further details of the third connecting electrode 526 and the fourth connecting electrode 527 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the above embodiments, and therefore their detailed description will be omitted.

[0280] In the display device 500 of this embodiment, a first thin-film transistor 510 may be disposed on a substrate 501, and a second thin-film transistor 520 may be disposed above the first thin-film transistor 510. A second active layer 523 comprising oxide of the second thin-film transistor 520 may be disposed above a first active layer 513 comprising oxide of the first thin-film transistor 510.

[0281] With this structure, by forming the first active layer 513 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 510 disposed at a lower position in the thickness direction of the substrate 501, and similarly by forming the second active layer 523 without using a high-energy process (e.g., laser crystallization) when forming the second thin-film transistor 520 disposed at a higher position, thermal damage to the first thin-film transistor 510 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 513 and the second active layer 523 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0282] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 520 is disposed above the first thin-film transistor 510 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and high resolution of the display device 500 can be easily achieved.

[0283] In the display device 500, an intermediate conductive layer BBM can be disposed between the first thin-film transistor 510 and the second thin-film transistor 520. This structure can reduce or prevent electrical signal interference between the first thin-film transistor 510 and the second thin-film transistor 520.

[0284] By electrically connecting the intermediate conductive layer BBM (e.g., through one or more contact holes) to conductive layers in different regions on the upper and lower sides of the substrate 501 in the thickness direction, various electrical signals can be realized.

[0285] By electrically connecting the conductive layers in different regions on the upper and lower sides of the substrate 501 in the thickness direction via the intermediate conductive layer BBM, the portions of the conductive layers on the upper and lower sides that need to be electrically connected can be connected.

[0286] Therefore, various circuit structures of the display device 500 can be easily implemented.

[0287] Figure 6 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0288] Reference Figure 6 The display device 600 may include a substrate 601, a first thin-film transistor 610, and a second thin-film transistor 620.

[0289] For ease of description, the main differences from the embodiments described above will be described.

[0290] The first active layer 613 of the first thin-film transistor 610 and the second active layer 623 of the second thin-film transistor 620 in the embodiment can be formed to have at least one different characteristic.

[0291] This will be described in detail below.

[0292] The first thin-film transistor 610 may include a first active layer 613 comprising at least an oxide layer, and the second thin-film transistor 620 may include a second active layer 623 comprising at least an oxide layer. The distance between the substrate 601 and the first thin-film transistor 610 may be smaller than the distance between the substrate 601 and the second thin-film transistor 620. This is based on the thickness direction of the substrate 601 (e.g., Figure 6 (In the Z-axis direction), the first thin-film transistor 610 can be disposed between the substrate 601 and the second thin-film transistor 620. The first active layer 613 may include a first connection region 613a, a second connection region 613b, and a first channel region 613c disposed between the first connection region 613a and the second connection region 613b. The second active layer 623 may include a first connection region 623a, a second connection region 623b, and a second channel region 623c disposed between the first connection region 623a and the second connection region 623b.

[0293] The display device 600 will be described in more detail below.

[0294] The substrate 601 may include various materials, and other details of the materials comprising the substrate 601 are substantially the same as those of the substrate 101 in the above embodiments, and therefore their detailed description will be omitted.

[0295] In another embodiment, one or more buffer layers 602 may be disposed between the substrate 601 and the first thin-film transistor 610. Since the further details of the buffer layer 602 are substantially the same as those of the buffer layer 102 in the above embodiment, their detailed description will be omitted.

[0296] The first thin-film transistor 610 may include a first active layer 613 and a first gate electrode 615.

[0297] The first thin-film transistor 610 may further include a first connecting electrode 616 and a second connecting electrode 617.

[0298] The first active layer 613 can be set on the buffer layer 602.

[0299] The first active layer 613 may include an oxide semiconductor. For example, the first active layer 613 may include zinc oxide (ZnO). x Gallium oxide (GaO) x Titanium oxide (TiO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr) x O y Indium gallium zinc oxide (IGZO) or indium gallium hafnium oxide (IGHO), and these oxides can be used alone or in combination with each other.

[0300] For example, the first active layer 613 may include indium tin gallium zinc oxide (ITGZO).

[0301] Based on the thickness direction of the substrate 601, the first gate electrode 615 can be stacked with the first active layer 613, for example, on top of the first active layer 613.

[0302] The first gate insulating film 614 can be configured to insulate between the first active layer 613 and the first gate electrode 615 (or configured between the first active layer 613 and the first gate electrode 615).

[0303] Since the further details of the first gate insulating film 614 are substantially the same as those of the first gate insulating film 114 in the above embodiments, their detailed description will be omitted.

[0304] The first gate electrode 615 may be disposed on the first gate insulating film 614. The first gate electrode 615 may be stacked with the first active layer 613, for example, to contact the first gate insulating film 614.

[0305] Since the further details of the first gate electrode 615 are substantially the same as those of the first gate electrode 115 in the above embodiments, their detailed description will be omitted.

[0306] The first interlayer insulating layer ILD1 can be configured to insulate between the first gate electrode 615 and the first connecting electrode 616 and the second connecting electrode 617 (or configured between the first gate electrode 615 and the first connecting electrode 616 and the second connecting electrode 617). Further details of the first interlayer insulating layer ILD1 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0307] The first connecting electrode 616 and the second connecting electrode 617 may be disposed on the first interlayer insulating layer ILD1. Further details of the first connecting electrode 616 and the second connecting electrode 617 are substantially the same as those of the first connecting electrode 116 and the second connecting electrode 117 in the above embodiments, and therefore their detailed description will be omitted.

[0308] The second thin-film transistor 620 may be disposed above the first thin-film transistor 610. For example, the second interlayer insulating layer ILD2 may be formed on the first interlayer insulating layer ILD1, and the second thin-film transistor 620 may be formed on the second interlayer insulating layer ILD2.

[0309] For example, the second interlayer insulating layer ILD2 can be formed to cover the first thin-film transistor 610. Further details of the second interlayer insulating layer ILD2 are substantially the same as those described in the above embodiments, and therefore their detailed description will be omitted.

[0310] The second thin-film transistor 620 may include a second active layer 623 and a second gate electrode 625.

[0311] The second thin-film transistor 620 may also include a third connection electrode 626 and a fourth connection electrode 627.

[0312] The second active layer 623 can be disposed on the second interlayer insulating layer ILD2.

[0313] The second active layer 623 may include an oxide semiconductor.

[0314] For example, the second active layer 623 may include zinc oxide (ZnO). x Gallium oxide (GaO) x Titanium oxide (TiO) x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), gallium zinc oxide (GZO), zinc magnesium oxide (ZMO), zinc zirconium oxide (ZnZr) x O y Indium gallium zinc oxide (IGZO) and indium gallium hafnium oxide (IGHO) are used, and these oxides can be used alone or in combination with each other.

[0315] For example, the second active layer 623 may include indium tin gallium zinc oxide (ITGZO).

[0316] In an embodiment, the second active layer 623 may be configured to have properties different from those of the first active layer 613. For example, the electrical properties of the second active layer 623 may differ from those of the first active layer 613.

[0317] For example, the first active layer 613 and the second active layer 623 can differ from each other in electron mobility. For instance, the electron mobility of the first active layer 613 can be higher than that of the second active layer 623. Various methods can be used to achieve these shared properties, and the oxide material of the first active layer 613 can differ from that of the second active layer 623. For example, the first active layer 613 may comprise indium tin gallium zinc oxide (ITGZO), and the second active layer 623 may comprise indium gallium zinc oxide (IGZO). In another embodiment, the materials of the first active layer 613 and the second active layer 623 can be selected through various combinations of oxides to produce a difference in electron mobility.

[0318] As another example of various methods to achieve these shared properties, the oxide material of the first active layer 613 and the oxide material of the second active layer 623 can be the same. For example, the first active layer 613 and the second active layer 623 can include indium gallium zinc oxide (IGZO), and the electron mobilities of the first active layer 613 and the second active layer 623 can be made different by adjusting the amount of hydrogen diffusion or by using dopants. For example, the electron mobility of the first active layer 613 can be made higher than that of the second active layer 623.

[0319] Therefore, the efficient arrangement of the first thin-film transistor 610 and the second thin-film transistor 620, which are regions used for signal generation in the pixel region or the driving circuit region, can be easily achieved. For example, in the driving circuit region, the first thin-film transistor 610 can be used to form a driving circuit section (e.g., a buffer circuit section) that requires a relatively large area or generates a large number of signals. The first thin-film transistor 610 includes a first active layer 613 with high electron mobility. On top of the driving circuit region, the second thin-film transistor 620 can be used to form a driving circuit section occupying a relatively small area (e.g., a light-emitting signal control circuit section). The second thin-film transistor 620 includes a second active layer 623 with low electron mobility. The design efficiency of each region can be enhanced by the vertical stacking structure of the thin-film transistors. As a result, high integration and high resolution of the display device 600 can be easily achieved.

[0320] Meanwhile, in another embodiment, the opposite structure can be applied, wherein the first active layer 613 and the second active layer 623 can be different from each other in terms of electron mobility. For example, the electron mobility of the first active layer 613 can be lower than that of the second active layer 623, and each of the characteristics of the first active layer 613 and the second active layer 623 can be selected based on the design conditions of the display device 600.

[0321] The second active layer 623 may be at least partially stacked with the first active layer 613; for example, the second active layer 623 may be entirely stacked with the first active layer 613. As another example, refer to the embodiments described above. Figure 3 As shown, the second active layer 623 may not be superimposed on the first active layer 613.

[0322] The second gate electrode 625 may be stacked with the second active layer 623, and for example, it may be disposed above the second active layer 623 in the thickness direction of the substrate 601.

[0323] The second gate insulating film 624 can be configured to insulate between the second active layer 623 and the second gate electrode 625 (or configured between the second active layer 623 and the second gate electrode 625).

[0324] Further details of the second gate insulating film 624 are substantially the same as those of the second gate insulating film 124 in the above embodiments, and therefore their detailed description will be omitted.

[0325] The second gate electrode 625 may be disposed on the second gate insulating film 624. The second gate electrode 625 may be stacked with the second active layer 623, for example, to contact the second gate insulating film 624.

[0326] Further details of the second gate electrode 625 are substantially the same as those of the second gate electrode 125 in the above embodiments, and therefore their detailed description will be omitted.

[0327] The third interlayer insulating layer ILD3 can be configured to insulate between the second gate electrode 625 and the third connection electrode 626 and the fourth connection electrode 627 (or be configured between the second gate electrode 625 and the third connection electrode 626 and the fourth connection electrode 627). For example, the third interlayer insulating layer ILD3 can be formed on top of the second gate electrode 625 and the second active layer 623 to cover the second gate electrode 625 and the second active layer 623. Further details of the third interlayer insulating layer ILD3 are substantially the same as those in the above embodiments, and therefore their detailed description will be omitted.

[0328] The third connecting electrode 626 and the fourth connecting electrode 627 may be disposed on the third interlayer insulating layer ILD3. Further details of the third connecting electrode 626 and the fourth connecting electrode 627 are substantially the same as those of the third connecting electrode 126 and the fourth connecting electrode 127 in the above embodiments, and therefore their detailed description will be omitted.

[0329] In the display device 600 of this embodiment, a first thin-film transistor 610 may be disposed on a substrate 601, and a second thin-film transistor 620 may be disposed above the first thin-film transistor 610. A second active layer 623 comprising oxide of the second thin-film transistor 620 may be disposed above a first active layer 613 comprising oxide of the first thin-film transistor 610.

[0330] With this structure, by forming the first active layer 613 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 610 disposed at a lower position in the thickness direction of the substrate 601, and similarly without using a high-energy process (e.g., laser crystallization) when forming the second active layer 623 disposed at a higher position, thermal damage to the first thin-film transistor 610 located at the lower position can be reduced or prevented. Stains on the first active layer 613 and the second active layer 623 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0331] This process allows for the easy and safe fabrication of a structure in which the second thin-film transistor 620 is disposed above the first thin-film transistor 610 (i.e., a structure in which multiple thin-film transistors are stacked). As a result, one or more circuits can be highly integrated and configured, and a high resolution of the display device 600 can be easily achieved.

[0332] In an embodiment, the second active layer 623 may be formed to have properties different from those of the first active layer 613. For example, the electrical properties of the second active layer 623 may differ from those of the first active layer 613. For example, the first active layer 613 and the second active layer 623 may differ from each other in electron mobility. For example, the electron mobility of the first active layer 613 may be higher than that of the second active layer 623.

[0333] Therefore, the vertically stacked structure of the first thin-film transistor 610 and the second thin-film transistor 620 can be easily and effectively arranged in the pixel region or the driving circuit region. For example, by arranging thin-film transistors (e.g., the first thin-film transistor 610) that can achieve high electron mobility in regions where relatively more circuit placement or signal generation is required, and arranging thin-film transistors (e.g., the second thin-film transistor 620) that can achieve low electron mobility in regions where relatively less circuit placement or signal generation is required, the layout design characteristics between the upper and lower layers of each region of the display device 600 can be precisely and easily controlled as needed.

[0334] In the various descriptions of these layers provided above, the construction of the second active layer 623 and the first active layer 613 of the embodiments having different properties (such as different electrical properties) can be selectively applied to the reference. Figures 1 to 5 The embodiments described herein may also be selectively applied to embodiments described later in this specification.

[0335] Figure 7 This is a schematic plan view showing a display device according to another embodiment of the disclosure. Figure 8 It is along Figure 7 A schematic cross-sectional view taken from line VIII-VIII'.

[0336] The display device 800 may include a display area DA and a peripheral area PA.

[0337] One or more display elements (not shown), such as organic light-emitting devices (OLEDs), can be disposed in the display area DA to display an image. For example, the display elements may include quantum dot light-emitting elements or liquid crystal display elements. As another example, the display elements may include one of a variety of other types, such as light-emitting diodes (LEDs), micro LEDs, mini LEDs, or nano LEDs.

[0338] Multiple pixels (not shown) may be set in the display area DA, and one or more display elements (not shown) may be set in the pixels (not shown).

[0339] A peripheral region PA may be formed around a display region DA. The peripheral region PA may include a non-display region (not shown), for example, the non-display region may be formed to surround the display region DA. In another embodiment, the peripheral region PA or the non-display region of the peripheral region PA may be formed to be adjacent only to one or both side surfaces of the display region DA.

[0340] The driving circuit section region that generates various signals for the operation of pixels in the display area DA can be set in the peripheral area PA, and the driving circuit section region can have one or more driving circuit sections.

[0341] Reference Figure 7 and Figure 8 The display device 800 may include a substrate 801, a first thin-film transistor 810, and a second thin-film transistor 820.

[0342] Figure 8 At least one area of ​​a pixel of the display device 800 may be schematically shown. For example, a pixel of the display device 800 may include a first thin-film transistor 810 and a second thin-film transistor 820.

[0343] Each of the first thin-film transistor 810 and the second thin-film transistor 820 can generate the same or different signals required for pixel operation.

[0344] The structure of the substrate 801, buffer layer 802, and the first active layer 813, first gate electrode 815, first gate insulating film 814, first connection electrode 816, and second connection electrode 817 of the first thin-film transistor 810 is the same as the structure of the above embodiments (such as...). Figure 1 The substrate 101, buffer layer 102, and the first active layer 113, first gate electrode 115, first gate insulating film 114, first connection electrode 116, and second connection electrode 117 of the first thin-film transistor 110 described herein are substantially the same, therefore their detailed description will be omitted. The first active layer 813 may include a first connection region 813a, a second connection region 813b, and a first channel region 813c disposed between the first connection region 813a and the second connection region 813b.

[0345] The first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 are substantially the same as the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, and the third interlayer insulating layer ILD3 described in the above embodiments, so their detailed description will be omitted.

[0346] The second active layer 823, second gate electrode 825, second gate insulating film 824, third connection electrode 826, and fourth connection electrode 827 of the second thin-film transistor 820 are constructed in the same manner as in the above embodiments (such as...). Figure 1 The second active layer 123, second gate electrode 125, second gate insulating film 124, third connection electrode 126, and fourth connection electrode 127 of the second thin-film transistor 120 described herein are substantially the same, and therefore their detailed description will be omitted. The second active layer 823 may include a first connection region 823a, a second connection region 823b, and a second channel region 823c disposed between the first connection region 823a and the second connection region 823b.

[0347] In another embodiment, the above reference can be further configured. Figure 4 The upper buffer layer 403, the first conductive pattern portion BML1 and the second conductive pattern portion BML2 in the described embodiment are substantially the same as the upper buffer layer 803, the first conductive pattern portion BML1 and the second conductive pattern portion BML2, so their detailed description will be omitted.

[0348] Although not shown in the accompanying drawings, it can be understood that... Figures 1 to 6 At least one of the structures is applied to the display device 800 in the embodiment.

[0349] The protective insulating layer PVX can be disposed on top of the second thin-film transistor 820, and can be configured to, for example, cover the second thin-film transistor 820.

[0350] The protective insulating layer PVX may contain insulating material to protect the second thin-film transistor 820 and to insulate the second thin-film transistor 820.

[0351] In another embodiment, the protective insulating layer PVX can eliminate the steps caused by the second thin-film transistor 820 and provide a flat surface above the second thin-film transistor 820, thereby reducing or preventing defects in the display element 850 caused by the underlying non-uniformity.

[0352] The protective insulating layer PVX can be formed from various materials and can be formed using organic or inorganic materials alone or in combination. The protective insulating layer PVX can comprise a single layer or multiple layers containing organic materials. For example, the protective insulating layer PVX can comprise a composite laminate of inorganic and organic insulating films.

[0353] The display element 850 can be disposed on top of the protective insulating layer PVX. As mentioned above, the display element 850 can be one of various types, such as an organic light-emitting element, which will be used as an example in the description below.

[0354] Although not shown in the accompanying drawings, the display element 850 may be electrically connected to a lower-level circuit such as the first thin-film transistor 810 or the second thin-film transistor 820.

[0355] The display element 850 may include a first electrode 851, a second electrode 852, and an intermediate layer 853 disposed between the first electrode 851 and the second electrode 852.

[0356] The first electrode 851 can be electrically connected to a lower-level circuit, such as a first thin-film transistor 810 or a second thin-film transistor 820.

[0357] The first electrode 851 can have various shapes, and can be patterned, for example, into an island shape.

[0358] The first electrode 851 may comprise various conductive materials. For example, the first electrode 851 may comprise at least one selected from the group consisting of transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). The first electrode 851 may comprise a highly reflective metal such as silver (Ag).

[0359] The intermediate layer 853 may include an organic light-emitting layer, and the organic light-emitting layer may be made of a low molecular weight organic material or a high molecular weight organic material. In another embodiment, in addition to the organic light-emitting layer, the intermediate layer 853 may also include at least one selected from the group consisting of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

[0360] Simultaneously, the organic light-emitting layer can be formed individually for each organic light-emitting element. For example, each of the organic light-emitting elements can emit red, green, and blue light. However, the disclosure is not limited to this, and the organic light-emitting layers can be formed together on the entire organic light-emitting element. For example, multiple organic light-emitting layers emitting red, green, and blue light can be vertically stacked or mixed to produce white light. Of course, the combination of colors used to emit white light is not limited to the combinations described above. Furthermore, for example, a color conversion layer or color filter that converts the emitted white light into a predetermined color can be provided separately.

[0361] The second electrode 852 can be formed of various conductive materials. For example, the second electrode 852 can contain lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg) or silver (Ag), and can be formed as a single layer or multiple layers using at least one of the above materials, and may also include an alloy material containing at least two of the above materials.

[0362] The pixel defining film (PDL) can be disposed on the protective insulating layer (PVX) so as not to cover a predetermined area of ​​the first electrode 851. Subsequently, an intermediate layer 853 can be disposed in the area of ​​the first electrode 851 not covered by the pixel defining film (PDL), and a second electrode 852 can be disposed on the intermediate layer 853.

[0363] Pixel-defined films (PDLs) can be formed from various insulating materials. For example, a pixel-defined film (PDL) can contain organic materials and can be formed, for example, by a method such as spin coating, using one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenolic resin.

[0364] In another embodiment, one or more functional layers (not shown) may also be disposed on the second electrode 852. For example, at least one of the functional layers may reduce contamination of the second electrode 852 during subsequent processes, and another functional layer may improve the efficiency of extracting visible light from the intermediate layer 853.

[0365] The encapsulation portion 890 can be configured to protect the display element 850. For example, the encapsulation portion 890 having one or more encapsulation layers can be provided on the second electrode 852 to block or reduce the penetration of moisture or other foreign matter into the display element 850.

[0366] For example, the encapsulation portion 890 may have two or more, or four or more encapsulation layers. In another embodiment, the encapsulation portion 890 may include one or more inorganic layers or one or more organic layers. For example, the encapsulation portion 890 may have a structure in which inorganic and organic layers are alternately stacked at least once, or, for example, stacked multiple times.

[0367] In the display device 800 of this embodiment, a first thin-film transistor 810 may be disposed on a substrate 801, and a second thin-film transistor 820 may be disposed above the first thin-film transistor 810. A second active layer 823 comprising oxide of the second thin-film transistor 820 may be disposed above a first active layer 813 comprising oxide of the first thin-film transistor 810.

[0368] With this structure, by forming the first active layer 813 without using a high-energy process (e.g., laser crystallization) when forming the first thin-film transistor 810 disposed at a lower position in the thickness direction of the substrate 801, and similarly without using a high-energy process (e.g., laser crystallization) when forming the second active layer 823 disposed at a higher position, thermal damage to the first thin-film transistor 810 located at the lower position can be reduced or prevented. The appearance of contaminants on the first active layer 813 and the second active layer 823 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0369] Multiple thin-film transistors included in a pixel of the display device 800 may include an active layer comprising oxide, and these thin-film transistors may be vertically arranged relative to the substrate 801. This configuration makes it easy to densely integrate circuitry within the pixel, thereby contributing to achieving high resolution in the display device 800.

[0370] Figure 9 This is a schematic cross-sectional view showing a display device according to another disclosed embodiment.

[0371] For ease of description, the main description will be... Figure 8 The differences between the display devices of the 800 and others.

[0372] The display device 900 may include a substrate 901, a first thin-film transistor 910, a second thin-film transistor 920, a third thin-film transistor 930, and a fourth thin-film transistor 940.

[0373] Figure 9 It may be a diagram schematically showing at least one region of a pixel of the display device 900. For example, a pixel of the display device 900 may include a first thin-film transistor 910, a second thin-film transistor 920, a third thin-film transistor 930, and a fourth thin-film transistor 940.

[0374] Each of the first thin-film transistor 910, the second thin-film transistor 920, the third thin-film transistor 930, and the fourth thin-film transistor 940 can generate the same or different signals required for pixel operation.

[0375] Each of the first thin-film transistor 910, the second thin-film transistor 920, the third thin-film transistor 930, and the fourth thin-film transistor 940 may include an active layer comprising oxide, and may respectively include, for example, a first active layer 913, a second active layer 923, a third active layer 933, and a fourth active layer 943, all comprising oxide.

[0376] The distance between the substrate 901 and the first thin-film transistor 910 can be smaller than the distance between the substrate 901 and the second thin-film transistor 920. This is based on the thickness direction of the substrate 901 (e.g., Figure 9 (in the Z-axis direction), the first thin-film transistor 910 can be disposed between the substrate 901 and the second thin-film transistor 920.

[0377] The distance between the substrate 901 and the third thin-film transistor 930 can be smaller than the distance between the substrate 901 and the fourth thin-film transistor 940. This is based on the thickness direction of the substrate 901 (e.g., Figure 9 (in the Z-axis direction), the third thin-film transistor 930 can be disposed between the substrate 901 and the fourth thin-film transistor 940.

[0378] In another embodiment, the first active layer 913 of the first thin-film transistor 910 and the third active layer 933 of the third thin-film transistor 930 may be formed in the same layer (e.g., on the buffer layer 902). For example, the first active layer 913 and the third active layer 933 may be formed simultaneously using the same oxide material.

[0379] In another embodiment, the second active layer 923 of the second thin-film transistor 920 and the fourth active layer 943 of the fourth thin-film transistor 940 may be formed in the same layer (e.g., on the upper buffer layer 903). For example, the second active layer 923 and the fourth active layer 943 may be formed simultaneously using the same oxide material.

[0380] The substrate 901 may include a variety of shapes and materials. For example, the substrate 901 may include multiple layers and may include one or more organic layers (e.g., resin-based materials) and one or more inorganic layers. For example, the substrate 901 may include two organic layers (e.g., a first organic layer 901a and a second organic layer 901b) and an inorganic layer 901c disposed between the two organic layers.

[0381] In another embodiment, one or more barrier layers BRL1, BRL2 may be disposed between the substrate 901 and the buffer layer 902. The one or more barrier layers BRL1, BRL2 may include a first barrier layer BRL1 and a second barrier layer BRL2.

[0382] Barrier layers BRL1 and BRL2 can reduce or prevent foreign matter from flowing in from the outside and can contain insulating materials, and can include, for example, a single layer or stacked structure of inorganic materials such as silicon oxide and silicon nitride layers.

[0383] In another embodiment, the first conductive pattern portion BML1 and the third conductive pattern portion BML3 may be disposed between the first barrier layer BRL1 and the second barrier layer BRL2.

[0384] The intermediate conductive layer BBM can be disposed between the first thin-film transistor 910 and the third thin-film transistor 930 and the second thin-film transistor 920 and the fourth thin-film transistor 940. The intermediate conductive layer BBM can be disposed between insulating layers, for example, between the lower ILD21 and the upper ILD22 of the second interlayer insulating layer.

[0385] The structure of the first active layer 913, the first gate electrode 915 and the first gate insulating film 914 of the first thin film transistor 910 can be modified and applied within a range that is substantially the same as or similar to the structure of one of the above embodiments. Optionally, a first connection electrode (not shown) or a second connection electrode (not shown) can also be provided.

[0386] The construction of the second active layer 923, the second gate electrode 925, and the second gate insulating film 924 of the second thin film transistor 920 can be modified and applied within a range that is substantially the same as or similar to the construction of one of the above embodiments. Optionally, a first connection electrode or a second connection electrode (not shown) may also be provided.

[0387] The structure of the third active layer 933, the third gate electrode 935 and the third gate insulating film 934 of the third thin film transistor 930 can be modified and applied within the same or similar range as the structure of one of the first thin film transistors described in the above embodiments. Optionally, a first connection electrode (not shown) or a second connection electrode (not shown) can also be provided.

[0388] The construction of the fourth active layer 943, the fourth gate electrode 945 and the fourth gate insulating film 944 of the fourth thin film transistor 940 can be modified and applied within the same or similar range as the construction of one of the second thin film transistors described in the above embodiments. Optionally, a first connection electrode (not shown) or a second connection electrode (not shown) can also be provided.

[0389] The accompanying drawings show a first conductive pattern portion BML1, a third conductive pattern portion BML3, and a fourth conductive pattern portion BML4, but these are examples and may also include a second conductive pattern portion (not shown) corresponding to the second thin-film transistor 920.

[0390] For example, at least one or all of the first conductive pattern portion BML1, the third conductive pattern portion BML3, and the fourth conductive pattern portion BML4 may be omitted.

[0391] The buffer layer 902, upper buffer layer 903, first interlayer insulation layer ILD1, second interlayer insulation layer (lower ILD21 and upper ILD22), and third interlayer insulation layer ILD3 are basically the same as those described in the above embodiments, so their detailed descriptions will be omitted.

[0392] In another embodiment, one or more lower conductive connection patterns GT11, GT12, GT13, GT14, GT15 may be disposed above the first thin-film transistor 910 and the third thin-film transistor 930. The lower conductive connection patterns GT11, GT12, GT13, GT14, and GT15 may be electrically connected to a region of each of the first conductive pattern portions BML1 and BML3 located below the first and third thin-film transistors 910 and 930, respectively, and for example, may be electrically connected to a region of each of the first and third thin-film transistors 910 and 930 and the first conductive pattern portions BML1 and BML3 located below the first and third thin-film transistors 910 and 930 through contact holes passing through at least one of the buffer layer 902, the second barrier layer BRL2, and the first interlayer insulating layer ILD1.

[0393] In another embodiment, one or more upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 may be disposed above the second thin-film transistor 920 and the fourth thin-film transistor 940. The upper conductive connection patterns CN11, CN12, CN13, CN14, CN15, and CN16 may be electrically connected to a region of each of the second thin-film transistor 920, the fourth thin-film transistor 940, and the fourth conductive pattern portion BML4 located below the fourth thin-film transistor 940, for example, through contact holes passing through at least one of the upper buffer layer 903 and the third interlayer insulating layer ILD3.

[0394] In another embodiment, one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15 and CN16 (e.g., upper conductive connection pattern CN11) may be electrically connected to one of the lower conductive connection patterns GT11, GT12, GT13, GT14 and GT15 (e.g., lower conductive connection pattern GT11).

[0395] In another embodiment, one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15 and CN16 (e.g., upper conductive connection pattern CN16) may be electrically connected to the intermediate conductive layer BBM.

[0396] The first protective insulating layer PVX1 may be disposed above the second thin-film transistor 920 and the fourth thin-film transistor 940, for example, to cover the second thin-film transistor 920 and the fourth thin-film transistor 940.

[0397] The first protective insulating layer PVX1 may contain insulating material to protect the second thin-film transistor 920 and the fourth thin-film transistor 940 and to insulate the second thin-film transistor 920 and the fourth thin-film transistor 940.

[0398] In another embodiment, the second protective insulating layer PVX2 may be formed on the first protective insulating layer PVX1.

[0399] In another embodiment, the second upper conductive connection pattern CN2 may be disposed on the first protective insulating layer PVX1. In this case, the second upper conductive connection pattern CN2 may be electrically connected to one or more of the upper conductive connection patterns CN11, CN12, CN13, CN14, CN15 and CN16 (e.g., upper conductive connection pattern CN13), and may be electrically connected to the first electrode 951 of the display element 950.

[0400] Display element 950 may be disposed on top of the second protective insulating layer PVX2. For example, display element 950 may include an organic light-emitting element and may be electrically connected to an underlying circuit, such as one of the first to fourth thin-film transistors 910, 920, 930 and 940 (e.g., the second thin-film transistor 920).

[0401] The display element 950 may include a first electrode 951, a second electrode 952, and an intermediate layer 953 disposed between the first electrode 951 and the second electrode 952, and its details are substantially the same as those described in the display element 850 in the above embodiments, so its detailed description will be omitted.

[0402] The pixel defining film (PDL) can be disposed on the second protective insulating layer (PVX2) so as not to cover a predetermined area of ​​the first electrode 951. Subsequently, an intermediate layer 953 can be disposed in the area of ​​the first electrode 951 not covered by the pixel defining film (PDL), and the second electrode 952 can be disposed on the intermediate layer 953.

[0403] The encapsulation part 990 can be configured to protect the display element 950, and is substantially the same as that described in the above embodiments, so its detailed description will be omitted.

[0404] In the display device 900 of the embodiment, the first thin-film transistor 910 and the third thin-film transistor 930 may be disposed above the substrate 901, and the second thin-film transistor 920 and the fourth thin-film transistor 940 may be disposed above the first thin-film transistor 910 and the third thin-film transistor 930.

[0405] Each of the first thin-film transistor 910, the third thin-film transistor 930, the second thin-film transistor 920, and the fourth thin-film transistor 940 may have an active layer including an oxide layer.

[0406] Although not shown in the accompanying drawings, a single pixel may include five or more (e.g., six or seven or more) thin-film transistors that may be stacked in a lower and upper region in the thickness direction of the substrate.

[0407] With this structure, by forming the first active layer 913 and the third active layer 933 without using high-energy processes (e.g., laser crystallization) when the first thin-film transistor 910 and the third thin-film transistor 930 are formed at a lower position in the thickness direction of the substrate 901, and similarly without using high-energy processes (e.g., laser crystallization) to form the second active layer 923 and the fourth active layer 943 when the second thin-film transistor 920 and the fourth thin-film transistor 940 are formed at a higher position, thermal damage to the underlying first thin-film transistor 910 and the third thin-film transistor 930 can be reduced or prevented. The formation of contaminants on the first active layer 913, the second active layer 923, the third active layer 933, and the fourth active layer 943 during high-energy processes (e.g., laser crystallization) can be reduced or prevented.

[0408] Each of the plurality of thin-film transistors included in a pixel of the display device 900 may include an active layer comprising oxide, and at least two of these thin-film transistors may be disposed on the same layer relative to the substrate 901. The plurality of thin-film transistors may be arranged in the form of a two-layer vertically stacked structure. Even when the circuitry included in the pixel becomes more complex, for example, with an increase in the number of thin-film transistors, this configuration can reduce the expansion of the pixel area, thereby contributing to achieving high resolution in the display device 900.

[0409] Figure 10 This is a schematic plan view showing a display device according to another embodiment of the disclosure. Figure 11 It is used to describe Figure 10 A schematic cross-sectional view of region K. Figure 12 It shows Figure 11 A schematic diagram illustrating an example of the structure.

[0410] The display device 1000 may include a display area DA and a peripheral area PA.

[0411] One or more display elements (not shown), such as organic light-emitting devices (OLEDs), can be disposed in the display area DA to display an image. For example, the display elements may include quantum dot light-emitting elements or liquid crystal display elements. As another example, the display elements may include one of a variety of other types, such as light-emitting diodes (LEDs), micro LEDs, mini LEDs, or nano LEDs.

[0412] Display elements can include one of several other types.

[0413] Multiple pixels (not shown) may be set in the display area DA, and one or more display elements (not shown) may be set in the pixels (not shown).

[0414] A peripheral region PA may be formed around a display region DA. The peripheral region PA may include a non-display region (not shown), which, as an example, may be formed to surround the display region DA. In another embodiment, the peripheral region PA or the non-display region of the peripheral region PA may be formed to be adjacent only to one or both side surfaces of the display region DA.

[0415] The driving circuit section region that generates various signals for the operation of pixels in the display area DA can be set in the peripheral area PA, and the driving circuit section region can have one or more driving circuit sections.

[0416] For example, multiple drive circuit sections (i.e., multiple drive circuit sections of different types) can be provided in the peripheral area PA.

[0417] Reference Figure 11 Two different types of drive circuit sections, BFR and ELG, can be disposed on the substrate 1001, and can be disposed on the upper and lower layers in the thickness direction of the substrate 1001, respectively. For example, the drive circuit sections BFR and ELG can be disposed on the lower and upper parts, respectively, with the interlayer insulating film (ILD) placed between them.

[0418] In another embodiment, the buffer circuit section BFR and the light-emitting control circuit section ELG can be respectively disposed on the lower and upper layers, with the interlayer insulating film ILD placed between them. This is for illustrative purposes only, and various types of drive circuit sections can be selectively provided.

[0419] The buffer circuit section (BFR) can be configured to perform various functions, and for example, it can be included in a shift register that sequentially shifts the scan output signal based on a clock signal.

[0420] Reference Figure 12 The image shows a first thin-film transistor 1010 and a second thin-film transistor 1020 disposed on a substrate 1001.

[0421] The buffer circuit section BFR may include a first thin-film transistor 1010. For example, the buffer circuit section BFR may include a first thin-film transistor 1010, which includes a first active layer 1013 comprising oxide. In another embodiment, the buffer circuit section BFR may include a plurality of first thin-film transistors 1010 (which may be a plurality of first thin-film transistors 1010 disposed side by side on the same layer).

[0422] The light-emitting control circuit section ELG may include a second thin-film transistor 1020. For example, the light-emitting control circuit section ELG may include a second thin-film transistor 1020, which includes a second active layer 1023 comprising oxide. In another embodiment, the light-emitting control circuit section ELG may include a plurality of second thin-film transistors 1020 (which may be a plurality of second thin-film transistors 1020 disposed side by side on the same layer). The first active layer 1013 may include a first connection region 1013a, a second connection region 1013b, and a first channel region 1013c disposed between the first connection region 1013a and the second connection region 1013b. The second active layer 1023 may include a first connection region 1023a, a second connection region 1023b, and a second channel region 1023c disposed between the first connection region 1023a and the second connection region 1023b.

[0423] The structures of the first conductive pattern portion BML1, the second conductive pattern portion BML2, the upper buffer layer 1003, the buffer layer 1002, the first gate electrode 1015, the first gate insulating film 1014, the first connecting electrode 1016 and the second connecting electrode 1017, the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2, the third interlayer insulating layer ILD3, the second gate electrode 1025, the second gate insulating film 1024, the third connecting electrode 1026, and the fourth connecting electrode 1027 can be modified and applied within the range that are substantially the same as or similar to the structures described in the above embodiments, and therefore their detailed description will be omitted.

[0424] Figure 13 It shows Figure 11 A schematic diagram of a modified example.

[0425] Reference Figure 13 Two or more drive circuit sections of different types, such as BFR, ELG1, ELG2, GCL, GRL and GWL, can be disposed on the substrate 1001 and can be disposed on the upper and lower layers based on the thickness direction of the substrate 1001. For example, multiple sections are disposed on the lower layer and multiple sections are disposed on the upper layer, and the interlayer insulating film ILD is placed between the upper and lower layers.

[0426] In another embodiment, multiple buffer circuit sections (BFRs) can be disposed on the lower layer, and other types of circuit sections (such as the first light emission control circuit section ELG1, the second light emission control circuit section ELG2, the first scan control circuit section GCL, the second scan control circuit section GRL, and the third scan control circuit section GWL) can be disposed on the upper layer, with the interlayer insulating film (ILD) placed between the upper and lower layers. Each of the first scan control circuit section GCL, the second scan control circuit section GRL, and the third scan control circuit section GWL can output or control different scan signals, and may include a start scan signal control section, a reference scan signal control section, and a write scan signal control section, and may also include a compensation scan signal control section or an initialization scan signal control section.

[0427] This is for illustrative purposes only, and various types of drive circuit sections can be selectively configured.

[0428] Figure 12 The specific structure can also be applied to Figure 13 Examples of implementations.

[0429] For example, a plurality of first thin-film transistors 1010 may be configured to correspond to a plurality of buffer circuit sections BFR.

[0430] After the interlayer insulating film (ILD) is disposed on top of the plurality of first thin-film transistors 1010, a plurality of second thin-film transistors 1020 corresponding to the first light-emitting control circuit section ELG1, the second light-emitting control circuit section ELG2, the first scan control circuit section GCL, the second scan control circuit section GRL, and the third scan control circuit section GWL can be disposed.

[0431] One or more types of driving circuit sections can be disposed on the upper and lower layers of the substrate 1001 to correspond to one or more driving circuit sections disposed in the peripheral region PA of the display device 1000 in the embodiment. For example, one or more types of driving circuit sections can be disposed on the upper part, and one or more different types of driving circuit sections can be disposed on the lower part with an interlayer insulating film (ILD) placed between the upper and lower parts. The first thin-film transistor 1010 and the second thin-film transistor 1020 can be configured to correspond to the driving circuit sections.

[0432] By arranging one or more first thin-film transistors and one or more second thin-film transistors to be stacked in at least one region in the thickness direction of the substrate, a plurality of driving circuit sections can be readily arranged to be stacked in the thickness direction of the substrate accordingly.

[0433] This reduces the area of ​​the peripheral PA, makes it easier to achieve high integration of the drive circuit section, and improves the manufacturability of the high-resolution display device 1000.

[0434] Meanwhile, in another embodiment, in the case of a buffer circuit occupying a relatively large area in the driving circuit section, the circuit section formation area can be reduced by arranging a first active layer 1013 on the first thin-film transistor 1010. The first active layer 1013 has a higher electron mobility than the second active layer 1023 of the second thin-film transistor 1020. This further enhances the effect of reducing the PA in the peripheral region. Whether to use the same active layer or an active layer with different electrical properties (such as varying electron mobility) can be determined based on the characteristics of different types of driving circuit sections and the required quantity or area.

[0435] In the case of stacking these various types of drive circuit sections, all the thin-film transistors in the drive circuit section include an active layer containing oxide. This ensures thermal stability during manufacturing and reduces or prevents active layer streaks, thereby improving uniformity among multiple thin-film transistors.

[0436] Figure 14 This is a schematic plan view showing a display device according to another embodiment of the disclosure. Figure 15 It is used to describe Figure 14 A schematic cross-sectional view of region K.

[0437] Figure 16 It shows Figure 15 A schematic diagram illustrating an example of the structure. For ease of description, the differences from the embodiments described above will be primarily described.

[0438] The display device 2000 may include a display area DA and a peripheral area PA.

[0439] The peripheral area PA can be formed around the display area DA.

[0440] The driving circuit section region that generates various signals for the operation of pixels in the display area DA can be set in the peripheral area PA, and the driving circuit section region can include one or more driving circuit sections.

[0441] For example, multiple drive circuit sections (i.e., multiple drive circuit sections of different types) can be provided in the peripheral area PA.

[0442] Reference Figure 15 Two or more driving circuit regions DB1, DB2, DB3, DB4 and DB5 of different types can be disposed on the substrate 2001, and can be disposed on the upper and lower layers based on the thickness direction of the substrate 2001. For example, multiple regions are disposed on the lower part and multiple regions are disposed on the upper part, and the interlayer insulating film ILD is placed between the upper and lower parts.

[0443] In another embodiment, the first driving circuit region DB1 and the third driving circuit region DB3 may be disposed on the lower layer, and the second driving circuit region DB2, the fourth driving circuit region DB4 and the fifth driving circuit region DB5 may be disposed on the upper layer, with the interlayer insulating film ILD placed between the upper and lower layers.

[0444] As shown in the attached figures, the first drive circuit region DB1 and the third drive circuit region DB3 in the lower layer can be superimposed on the second drive circuit region DB2, the fourth drive circuit region DB4 and the fifth drive circuit region DB5 in the upper layer in at least one region.

[0445] Each of the two or more drive circuit regions DB1, DB2, DB3, DB4 and DB5 may include multiple drive circuits of one or more types.

[0446] For example, the first driving circuit region DB1 may include one or more buffer circuits and a first scan control circuit; the second driving circuit region DB2 may include one or more buffer circuits and a first light emission control circuit; the third driving circuit region DB3 may include one or more buffer circuits and a third scan control circuit; the fourth driving circuit region DB4 may include one or more buffer circuits and a second light emission control circuit; and the fifth driving circuit region DB5 may include one or more buffer circuits and a second scan control circuit.

[0447] Here, each of the first scan control circuit section, the second scan control circuit section, and the third scan control circuit section can output or control different scan signals, and may include a start scan signal control section, a reference scan signal control section, and a write scan signal control section, and may also include a compensation scan signal control section or an initialization scan signal control section.

[0448] Reference Figure 16 The image shows the first thin-film transistor 2010 to the eighth thin-film transistor 2080 disposed on the substrate 2001.

[0449] The first driving circuit region DB1 may include a first thin-film transistor 2010 and a third thin-film transistor 2030. For example, the first driving circuit region DB1 may include the first thin-film transistor 2010 and may also include the third thin-film transistor 2030. The first thin-film transistor 2010 includes a first active layer 2013 comprising oxide, and the first thin-film transistor 2010 includes a third active layer comprising oxide. In another embodiment, the first thin-film transistor 2010 and the third thin-film transistor 2030 may be disposed side by side on the same layer.

[0450] The second driving circuit region DB2 may include a second thin-film transistor 2020 and a fourth thin-film transistor 2040. For example, the second driving circuit region DB2 may include the second thin-film transistor 2020 and may also include the fourth thin-film transistor 2040, wherein the second thin-film transistor 2020 includes a second active layer comprising oxide, and the fourth thin-film transistor 2040 includes a fourth active layer comprising oxide. In another embodiment, the second thin-film transistor 2020 and the fourth thin-film transistor 2040 may be disposed side by side on the same layer.

[0451] The second thin-film transistor 2020 and the fourth thin-film transistor 2040 may be stacked with the first thin-film transistor 2010 and the third thin-film transistor 2030 in at least one region. For example, each of the active layers of the upper and lower thin-film transistors may be stacked with each other.

[0452] The third driving circuit region DB3 may include a fifth thin-film transistor 2050 and a seventh thin-film transistor 2070. For example, the third driving circuit region DB3 may include the fifth thin-film transistor 2050 and may also include the seventh thin-film transistor 2070, wherein the fifth thin-film transistor 2050 includes a fifth active layer comprising oxide, and the seventh thin-film transistor 2070 includes a seventh active layer comprising oxide. In another embodiment, the fifth thin-film transistor 2050 and the seventh thin-film transistor 2070 may be disposed side by side on the same layer.

[0453] The fourth driving circuit region DB4 may include a sixth thin-film transistor 2060 and an eighth thin-film transistor 2080. For example, the fourth driving circuit region DB4 may include the sixth thin-film transistor 2060 and may also include the eighth thin-film transistor 2080, wherein the sixth thin-film transistor 2060 includes a sixth active layer comprising oxide, and the eighth thin-film transistor 2080 includes an eighth active layer comprising oxide. In another embodiment, the sixth thin-film transistor 2060 and the eighth thin-film transistor 2080 may be disposed side by side on the same layer.

[0454] The sixth thin-film transistor 2060 and the eighth thin-film transistor 2080 may be stacked with the fifth thin-film transistor 2050 and the seventh thin-film transistor 2070 in at least one region. For example, each of the active layers of the upper and lower thin-film transistors may be stacked with each other.

[0455] Although not shown in the accompanying drawings, the fifth driving circuit region DB5 may include a plurality of thin-film transistors, each of which has an active layer including an oxide layer.

[0456] The construction of the buffer layer, the first gate electrode to the eighth gate electrode (shown only as "2015"), the first gate insulating film to the eighth gate insulating film (shown only as "2014"), the connection electrode (shown only as "2016") and the connection electrode (shown only as "2017"), the first interlayer insulating layer ILD1, the second interlayer insulating layer ILD2 and the third interlayer insulating layer ILD3 can be modified and applied within the range that is substantially the same as or similar to the construction described in the above embodiments, and therefore their detailed description will be omitted.

[0457] One or more types of driving circuit regions can be disposed on the upper and lower layers of the substrate 2001 to correspond to one or more driving circuit regions disposed in the peripheral region PA of the display device 2000 in the embodiment. For example, one or more types of driving circuits can be disposed on the upper part, and one or more different types of driving circuits can be disposed on the lower part, with an interlayer insulating film (ILD) placed between the upper and lower parts. Multiple thin-film transistors can be configured to correspond to the driving circuit regions respectively.

[0458] In this configuration, to efficiently arrange multiple drive circuit sections, multiple regions can be defined in the upper layer and multiple regions can be defined in the lower layer, with an interlayer insulating film between the upper and lower layers. Furthermore, one or more drive circuit sections of one or more types can be disposed in each region. This improves the efficiency of arranging drive circuit sections in a vertically stacked structure.

[0459] For example, circuit sections that occupy a relatively large area or include a large number of circuits (such as buffer circuit sections) can be arranged across both upper and lower layers, while the remaining drive circuit sections can be arranged in either the upper or lower layer. For example, drive circuit sections that are related to each other in terms of their drive circuitry can be arranged to be adjacent to or on the same layer, thereby facilitating precise control in circuit layout design.

[0460] Therefore, the reduction in the peripheral area PA helps to easily achieve a high-density and high-resolution display device 2000.

[0461] Meanwhile, in another embodiment, the driving circuit region having a relatively large area or high signal processing requirements may include a thin-film transistor having an active layer different from the active layers in other regions. The active layer may include an oxide semiconductor having relatively higher electrical properties (specifically, electron mobility) than those in other regions.

[0462] Figure 17 This is a schematic diagram of the equivalent circuit of a pixel of a display device according to a disclosed embodiment.

[0463] Figure 18 It is used for driving Figure 17 The diagram shows a schematic waveform of the driving signal for the pixel.

[0464] In one embodiment, the pixel circuit may include seven pixel transistors (hereinafter referred to as first pixel transistors T1 to seventh pixel transistors T7) and three capacitors. However, this is only an example and may include a smaller number of transistors and capacitors.

[0465] Furthermore, the pixel transistors included in the pixel circuit may include at least some or all of the structures described in the foregoing embodiments, and may, for example, include thin-film transistors having an active layer comprising an oxide layer. Therefore, a detailed description of the thin-film transistor's structure (such as the active layer, gate electrode, and connection electrode) will be omitted.

[0466] A gate of the first pixel transistor T1 can be electrically connected to the source of the first pixel transistor T1.

[0467] In an embodiment, for example, the first pixel transistor T1 may be a driving transistor. The second pixel transistor T2 may be referred to as a switching transistor.

[0468] The organic light-emitting element (see the embodiments described above) may have a first electrode connected to a power line that receives a first power supply voltage ELVSS.

[0469] The first pixel transistor T1 may be electrically connected to a power line that receives a second power supply voltage ELVDD. In another embodiment, the first pixel transistor T1 may include multiple gates, such as an upper gate and a lower gate.

[0470] The second pixel transistor T2 can be electrically connected to the data line.

[0471] The third pixel transistor T3 can be electrically connected to the voltage line that receives the reference voltage VREF. The third pixel transistor T3 can be connected to the reference scan line GR, and for example, the gate of the third pixel transistor T3 can be electrically connected to the reference scan line GR.

[0472] The fourth pixel transistor T4 can be electrically connected to the voltage line that receives the initialization voltage Vint. The fourth pixel transistor T4 can also be electrically connected to the initialization scan line; for example, the gate of the fourth pixel transistor T4 can be electrically connected to the initialization scan line.

[0473] The fifth pixel transistor T5 can be electrically connected to the power line that receives the second power supply voltage ELVDD, and can also be electrically connected to the light-emitting signal line. For example, the gate of the fifth pixel transistor T5 can be electrically connected to the light-emitting signal line.

[0474] The sixth pixel transistor T6 can be electrically connected to the light-emitting element.

[0475] The seventh pixel transistor T7 can be electrically connected to the voltage line that receives the initialization voltage Vaint. As a disclosed example, the initialization voltage Vaint can have a different level than the initialization voltage Vint.

[0476] Reference Figure 17 and Figure 18 During the initialization period IP, a pixel transistor (e.g., the fourth pixel transistor T4) can be turned on, and the first electrode of the light-emitting element can be initialized to the initialization voltage Vint through the turned-on fourth pixel transistor T4. At this time, a capacitor can be initialized to the difference between the first power supply voltage ELVSS and the initialization voltage Vint.

[0477] Subsequently, during the light-emitting period, the sixth pixel transistor T6 can be turned on simultaneously with the fifth pixel transistor T5. The current output through the first pixel transistor T1 can be supplied to the light-emitting element through the turned-on sixth pixel transistor T6.

[0478] More specifically, the display device displays an image during each frame period, and each of the scan lines, reference scan lines, initialization scan lines, and light emission signal lines sequentially receives a scan signal or a light emission control signal during the frame period. Figure 18 A portion of the frame period can be shown. Each of the scan signals GR, GW, and GI, or the emission control signals EM and EMB, can have a high voltage (or high level) during one period and a low voltage (or low level) during another period. For example, when the corresponding scan signal has a high voltage, the first pixel transistor T1 through the fifth pixel transistor T5 can be turned on.

[0479] During the initialization period (IP), the third pixel transistor T3 and the fourth pixel transistor T4 can be turned on. During IP, the initialization process can be performed using either the reference voltage VREF or the initialization voltage Vint. The capacitor Cst between the third pixel transistor T3 and the fourth pixel transistor T4 is initialized to the difference between the reference voltage VREF and the initialization voltage Vint. Another capacitor Chold is initialized to the difference between the second power supply voltage ELVDD and the initialization voltage Vint.

[0480] During the compensation period CP, the third pixel transistor T3 and the fifth pixel transistor T5 can be turned on. The threshold voltage of the first pixel transistor T1 can be compensated through capacitor coupling.

[0481] During the write period WP, ​​the second pixel transistor T2 can be turned on. The second pixel transistor T2 outputs a voltage corresponding to the data signal Vdata. As a result, the capacitor is charged with a voltage value corresponding to the data signal Vdata. In addition, regardless of the deviation of the threshold voltage of the first pixel transistor T1 of the pixel, a current proportional to the data signal Vdata can be supplied to the light-emitting element.

[0482] Subsequently, during the light-emitting period, the fifth pixel transistor T5 can be turned on and the first pixel transistor T1 provides a current corresponding to the voltage value stored in the capacitor to the light-emitting element, and the light-emitting element can emit light with a brightness corresponding to the data signal Vdata.

[0483] In an embodiment, the circuitry included in a pixel may include seven pixel transistors. These seven pixel transistors may include at least one of a first thin-film transistor and a second thin-film transistor from the above embodiments. For example, thin-film transistors, each including an active layer comprising an oxide layer, may be disposed in different layers in the thickness direction of the substrate, for example, in a lower and upper layer with an interlayer insulating film located therebetween.

[0484] For example, the first pixel transistor T1 and the second pixel transistor T2 may respectively include or correspond to (or directly correspond to) the first thin-film transistor and the second thin-film transistor in the above embodiments.

[0485] As another example, all seven pixel transistors, including thin-film transistors comprising oxide, can be configured such that multiple transistors are disposed in each of the lower and upper layers, with an interlayer insulating film positioned between the lower and upper layers in the thickness direction of the substrate. For example, two to five pixel transistors can be disposed in the lower layer, and two to five pixel transistors can be disposed in the upper layer.

[0486] This arrangement allows for high integration of circuitry within a single pixel.

[0487] A driving circuit section configured to control or generate signals for driving pixels can be disposed in a non-display area. For example, a driving circuit section for generating or controlling one or more light emission control signals EM, EMB, and one or more scan control signals GR, GI, GW can be disposed in a non-display area. These driving circuit sections can be disposed on the upper and lower layers of the substrate, with an interlayer insulating film placed between the upper and lower layers. For example, the driving circuit section can use those from the embodiments described above. Figures 10 to 16 The configuration shown is used to set it up. This allows for a reduction in the non-display area or bezel of the display device, thereby facilitating the achievement of high integration and high resolution.

[0488] Figure 19 This is a schematic block diagram illustrating a display system according to a disclosed embodiment.

[0489] Reference Figure 19 The display system 10000 may include a processor 11000 and a display device 12000.

[0490] Processor 11000 can perform various tasks and calculations. Processor 11000 may include application processor, graphics processor, microprocessor, central processing unit (CPU), etc. Processor 11000 can be electrically connected to other components of display system 10000 via bus system to control other components.

[0491] The processor 11000 can transmit image data IMG and control signal CTRL to the display device 12000. The display device 12000 can display an image based on the image data IMG and control signal CTRL. The display device 12000 can be used with a reference... Figure 1 The described display device 100 is similarly constructed.

[0492] Display system 10000 may include computing systems that provide image display capabilities, such as smartwatches, mobile phones, smartphones, portable computers, tablet PCs, watch phones, car displays, smart glasses, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs). Display system 10000 may include at least one of head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and augmented reality (AR) devices.

[0493] While the disclosure has been described with reference to one embodiment illustrated in the accompanying drawings, this is merely an example, and those skilled in the art will understand that various modifications and variations of this embodiment are possible. Therefore, the true scope of protection of the disclosure should be determined by the technical concept of the appended claims.

[0494] In the display device of the disclosed embodiments, high resolution and high image quality characteristics can be easily achieved.

[0495] It should be understood that the embodiments described herein are to be considered descriptive only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims.

Claims

1. A display device, the display device comprising: Base; First thin-film transistor; as well as Second thin-film transistor, The first thin-film transistor includes a first active layer comprising an oxide layer disposed above the substrate. The second thin-film transistor includes a second active layer comprising oxide and disposed above the substrate, and The first thin-film transistor is disposed between the substrate and the second thin-film transistor in the thickness direction of the substrate, such that the distance between the substrate and the first thin-film transistor has a smaller value than the distance between the substrate and the second thin-film transistor.

2. The display device according to claim 1, further comprising: One or more interlayer insulating layers are disposed between the first thin-film transistor and the second thin-film transistor.

3. The display device according to claim 1, wherein, The first thin-film transistor and the second thin-film transistor are stacked in at least one region along the thickness direction of the substrate, and The first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor are stacked in at least one region in the thickness direction of the substrate.

4. The display device according to claim 1, wherein, The first active layer of the first thin-film transistor and the second active layer of the second thin-film transistor have different properties.

5. The display device according to claim 1, further comprising: The conductive pattern portion is stacked with the first active layer of the first thin-film transistor or the second active layer of the second thin-film transistor.

6. The display device according to claim 5, wherein, The conductive pattern portion is electrically connected to the region of the first thin-film transistor or the region of the second thin-film transistor through one or more contact holes.

7. The display device according to claim 6, wherein, The first thin-film transistor includes one or more connection electrodes electrically connected to the first active layer, and The conductive pattern portion is electrically connected to at least one region of the one or more connecting electrodes.

8. The display device according to claim 1, further comprising: An intermediate conductive layer is disposed between the first thin-film transistor and the second thin-film transistor.

9. The display device according to claim 8, wherein, The intermediate conductive layer is formed such that it corresponds in one direction to at least the width of the first active layer or the second active layer.

10. The display device according to claim 8, wherein, Through the region where the intermediate conductive layer is absent, the first thin-film transistor or one or more conductive patterns disposed in the same or different layers as the first thin-film transistor are electrically connected to the second thin-film transistor or one or more conductive patterns disposed in the same or different layers as the second thin-film transistor.

11. The display device according to claim 1, further comprising: A display area and a peripheral area are defined on the substrate, with the peripheral area disposed on at least one side of the display area. One or more pixels are disposed in the display area, and A drive circuit region that generates or controls one or more signals for the operation of the one or more pixels is disposed in the peripheral region.

12. The display device according to claim 11, wherein, The first thin-film transistor and the second thin-film transistor are configured to correspond to one of the one or more pixels.

13. The display device according to claim 12, wherein, In the aforementioned pixel, Each includes one or more thin-film transistors containing oxide and being the active layer required to drive the pixel, positioned adjacent to the first thin-film transistor. Each includes one or more thin-film transistors containing oxide and being the active layer required to drive the pixel, positioned adjacent to the second thin-film transistor.

14. The display device according to claim 13, wherein, The first thin-film transistor and one or more thin-film transistors adjacent to the first thin-film transistor are disposed on the same layer, and The second thin-film transistor and the one or more thin-film transistors adjacent to the second thin-film transistor are disposed on the same layer.

15. The display device according to claim 11, wherein, The first thin-film transistor and the second thin-film transistor are configured to correspond to the region of the driving circuit section.

16. The display device according to claim 15, wherein, The first thin-film transistor and the second thin-film transistor correspond to two different types of drive circuit sections disposed in the drive circuit section region, respectively.

17. The display device according to claim 15, wherein, In the driving circuit region, multiple driving circuit sections are disposed in each of the upper and lower layers, with an interlayer insulating film located between them. Each includes multiple thin-film transistors comprising an active layer containing an oxide layer, disposed on the same layer as the first thin-film transistor, and positioned adjacent to the first thin-film transistor. Each includes multiple thin-film transistors comprising an active layer containing an oxide layer, disposed on the same layer as the second thin-film transistor, and positioned adjacent to the second thin-film transistor. The plurality of thin-film transistors are configured to correspond to the plurality of driving circuit sections respectively.

18. The display device according to claim 17, wherein, The drive circuits disposed in the upper and lower layers are of different types, and the interlayer insulating film is located therebetween.

19. An electronic device, the electronic device comprising: Display devices The display device includes: a substrate; a first thin-film transistor; and a second thin-film transistor. The first thin-film transistor includes a first active layer comprising an oxide layer disposed over the substrate. The second thin-film transistor includes a second active layer comprising oxide and disposed above the substrate, and The first thin-film transistor is disposed between the substrate and the second thin-film transistor in the thickness direction of the substrate, such that the distance between the substrate and the first thin-film transistor has a smaller value than the distance between the substrate and the second thin-film transistor.

20. The electronic device of claim 19, further comprising: One or more interlayer insulating layers are disposed between the first thin-film transistor and the second thin-film transistor.

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