Display device, manufacturing method thereof and electronic device

Abstract

The invention relates to a display device, a method of manufacturing the display device, and an electronic device. A display device includes: a substrate; a first electrode disposed on the substrate; a pixel defining layer including an opening exposing at least a portion of the first electrode; a light emitting layer disposed on the first electrode in the opening; and a second electrode disposed on the light emitting layer and the pixel defining layer, in which the first electrode includes a first conductive layer including silver (Ag), palladium (Pd), and copper (Cu), and in the first conductive layer, a content of silver (Ag) is about 97 wt% to about 99 wt%, a content of palladium (Pd) is about 0.1 wt% to about 2.9 wt%, and a content of copper (Cu) is about 0.1 wt% to about 2.9 wt%.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a display device and a method of manufacturing a display device. BACKGROUND

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light emitting display device. The light emitting display device can include an organic light emitting display device including an organic light emitting element, an inorganic light emitting display device including an inorganic light emitting element such as an inorganic semiconductor, and a micro light emitting display device or a nano light emitting display device including a micro light emitting element or a nano light emitting element. SUMMARY

[0003] Aspects of the present disclosure provide a display device capable of preventing or minimizing a decrease in reflectance of a display panel while preventing voids from being generated in a light emitting layer that emits light by increasing a silver content of an APC alloy.

[0004] However, embodiments are not limited to those set forth herein. The above and other embodiments will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0005] According to aspects of the present disclosure, a display device includes a substrate, a first electrode disposed on the substrate, a pixel definition layer including an opening exposing at least a portion of the first electrode, a light emitting layer disposed on the first electrode in the opening, and a second electrode disposed on the light emitting layer and the pixel definition layer, wherein the first electrode can include a first conductive layer including silver (Ag), palladium (Pd), and copper (Cu), and in the first conductive layer, a content of silver (Ag) is in a range of about 97 wt% to about 99 wt%, a content of palladium (Pd) is in a range of about 0.1 wt% to about 2.9 wt%, and a content of copper (Cu) is in a range of about 0.1 wt% to about 2.9 wt%.

[0006] The first electrode further includes a second conductive layer disposed under the first conductive layer and including a conductive oxide, and a third conductive layer disposed on the first conductive layer and including the conductive oxide.

[0007] The conductive oxide can include at least one of indium tin oxide (ITO), zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0008] The pixel-defining layer can include at least one halogen element among Cl, Br, and I.

[0009] The content of the at least one halogen element in the pixel-defining layer can be in a range of about 1 wt% to about 30 wt%.

[0010] The pixel-defining layer can include a light-blocking material.

[0011] The display device can further include a transistor including a semiconductor layer disposed between the substrate and the first electrode and electrically connected to the first electrode, wherein the semiconductor layer can include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf).

[0012] The semiconductor layer can include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), and indium-tin-gallium-zinc oxide (ITGZO).

[0013] According to another aspect of the disclosure, a method of manufacturing a display device includes forming a transistor including a semiconductor layer on a substrate, forming a first electrode on the transistor, forming a pixel-defining layer including an opening exposing at least a portion of the first electrode, forming a light-emitting layer on the first electrode in the opening, and forming a second electrode on the light-emitting layer and the pixel-defining layer, wherein forming the first electrode can include forming a first conductive layer at an oxygen (O2) concentration of about 3% or less, and the first conductive layer includes silver (Ag), palladium (Pd), and copper (Cu).

[0014] The first conductive layer can include about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu).

[0015] Forming the first electrode can further include forming a second conductive layer including a conductive oxide before forming the first conductive layer, and forming a third conductive layer including a conductive oxide on the first conductive layer, and the first conductive layer can be disposed on the second conductive layer.

[0016] The conductive oxide can include at least one of indium tin oxide (ITO), zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0017] The pixel-defining layer can include at least one halogen element among Cl, Br, and I.

[0018] The content of the at least one halogen element in the pixel-defining layer can be in a range of about 1 wt% to about 30 wt%.

[0019] The pixel-defining layer can include a light-blocking material.

[0020] The semiconductor layer can include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO).

[0021] According to another aspect of the disclosure, an electronic device includes a display device providing an image, and a processor transmitting an image data signal to the display device, wherein the display device includes a substrate, a first electrode disposed on the substrate, a pixel-defining layer including an opening exposing at least a portion of the first electrode, a light-emitting layer disposed on the first electrode in the opening, and a second electrode disposed on the light-emitting layer and the pixel-defining layer, wherein the first electrode includes a first conductive layer including silver (Ag), palladium (Pd), and copper (Cu), and in the first conductive layer, a content of silver (Ag) is in a range of about 97 wt% to about 99 wt%, a content of palladium (Pd) is in a range of about 0.1 wt% to about 2.9 wt%, and a content of copper (Cu) is in a range of about 0.1 wt% to about 2.9 wt%.

[0022] According to the display device according to the embodiment, by applying a conductive layer having a controlled content ratio of silver, palladium, and copper to the electrode, an ionization phenomenon of silver (Ag) is improved, and a reaction with a halogen element included in the pixel-defining layer is inhibited, so that a salt generated by a reaction with silver (Ag) can be prevented, and defects such as voids and dark spots can be inhibited.

[0023] Effects according to the embodiments are not limited to the above-illustrated content, and include more various effects in the specification. BRIEF DESCRIPTION OF DRAWINGS

[0024] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings in which: Figure 1 is a schematic perspective view of a display device according to an embodiment; Figure 2 is a schematic layout view of a display panel according to an embodiment; Figure 3A is a schematic cross-sectional view of a display panel according to an embodiment; Figure 3B is an enlarged schematic cross-sectional view of a region A of a display panel according to an embodiment; Figure 3C is an enlarged schematic cross-sectional view of a region B of a display panel according to an embodiment; Figure 4A and Figure 4B are scanning electron microscope (SEM) images of the surface of Example 1 and Comparative Example 1, respectively, measured after heat treatment at a temperature of 450°C for 1 hour; Figure 5 is a schematic graph showing the transmittance of the display panels of Example 1 and Comparative Example 1 with respect to the wavelength region; Figure 6 is a schematic graph showing the reflectance of the display panels of Example 1 and Comparative Example 1 with respect to the wavelength region; Figure 7 is a schematic graph showing the absorbance of the display panels of Example 1 and Comparative Example 1 with respect to the wavelength region; Figure 8 is a surface image of a display panel manufactured according to Example 1; Figure 9 is a surface image of a display panel manufactured according to Comparative Example 1; Figure 10 is a surface image of a display panel manufactured according to Comparative Example 2; Figure 11 is a surface image of a display panel manufactured according to Comparative Example 3; Figure 12 is a schematic graph showing the transmittance of the display panels of Example 1 and Comparative Examples 2 and 3 with respect to the wavelength region; Figure 13 is a schematic graph showing the reflectance of the display panels of Example 1 and Comparative Examples 2 and 3 with respect to the wavelength region; Figure 14 is a schematic graph showing the absorbance of the display panels of Example 1 and Comparative Examples 2 and 3 with respect to the wavelength region; Figure 15is a graph showing the reflectance of the display panel of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, and Comparative Example 5 with respect to a wavelength region; Figure 16 is a graph showing the reflectance of the display panel of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, and Comparative Example 5 with respect to a wavelength region; Figure 17 is a graph showing the change in the sheet resistance of the display panel of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, Comparative Example 5, and Comparative Example 6 with respect to time; Figure 18 is a schematic perspective view of an electronic device to which a display device according to an embodiment is applied; Figure 19 is a block diagram of an electronic device according to one embodiment of the disclosure; and Figure 20 is a schematic view of an electronic device according to various embodiments of the disclosure. DETAILED DESCRIPTION

[0025] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, the terms "embodiment" and "implementation" are interchangeable, and are non-limiting examples of the apparatus or methods disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details, or with one or more equivalent arrangements. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the various embodiments.

[0026] Unless otherwise indicated, the illustrated embodiments are to be understood as providing features that can be monitarily combined, separated, interchanged, and / or rearranged without departing from the scope of the present invention. Accordingly, unless otherwise indicated, features, components, modules, layers, films, panels, regions, and / or aspects of the various embodiments (hereinafter referred to as "elements") can be combined, separated, interchanged, and / or rearranged without departing from the scope of the present invention.

[0027] The use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. As such, the absence of cross-hatching or shading does not mean that a particular material, material property, dimension, ratio, commonality between elements, and / or any other characteristic, attribute, property, etc. is either preferred or required, unless specifically indicated otherwise. Moreover, in the drawings, the size and relative sizes of elements can be exaggerated for clarity and / or descriptive purposes. When embodiments can be practiced differently, a particular sequence of processing steps can be performed other than as described. For example, two consecutively described processing steps can be executed substantially concurrently or in the reverse order described. Also, the same reference numerals are carried forward to denote the same elements throughout the specification.

[0028] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. To that end, the term “connected” can refer to physical, electrical, and / or fluidic connections with or without intervening elements. Moreover, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 are not limited to the three axes of a Cartesian coordinate system, such as the X-axis, the Y-axis, and the Z-axis, and can be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, “at least one of A and B” can be understood to mean only A, only B, or any combination of A and B. Moreover, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0029] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0030] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein to describe the relationship between one element and another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will consequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” designate the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and therefore to explain the inherent deviations of the measured, calculated, and / or provided values ​​that will be recognized by those skilled in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of said value.

[0032] Various embodiments are described herein with reference to cross-sectional views and / or exploded views that serve as schematic diagrams of implementations and / or intermediate structures. Therefore, variations in the illustrated shapes should be anticipated, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein should not necessarily be construed as limited to the shapes of the specifically shown areas, but should include, for example, deviations in shape due to manufacturing processes. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas do not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0033] As is customary in the art, some of the example embodiments are described and shown in the drawings with reference to functional blocks, units and / or modules. A person skilled in the art will understand that these blocks, units and / or modules are physically implemented by an electrical circuit (or optical circuit), such as a logic circuit, a discrete component, a microprocessor, a hard-wired circuit, a memory element, a wiring connector and the like, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In cases where the blocks, units and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled by software (e.g., microcode) to perform various functions discussed herein and can be driven selectively by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. In addition, each block, unit and / or module of some embodiments can be physically separated into two or more interacting and discrete blocks, units and / or modules without departing from the scope of the present application. Moreover, blocks, units and / or modules of some embodiments can be physically combined into more complex blocks, units and / or modules without departing from the scope of the present application.

[0034] Figure 1 FIG. 1 is a schematic perspective view of a display device 10 according to an embodiment.

[0035] Referring to Figure 1 The display device 10 can be a device for displaying a moving image or a still image. The display device 10 can be used as a display screen in a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra-mobile PC (UMPC), and various products such as a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IoT) device.

[0036] The display device 10 can be a light emitting display device such as an organic light emitting display device using an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a micro light emitting display device or a nano light emitting display device using a micro light emitting diode or a nano light emitting diode. Hereinafter, a case where the display device 10 is an organic light emitting display device will be described, but embodiments are not limited thereto.

[0037] The display device 10 can include a display panel 100, a plurality of source driving circuits 200, a plurality of flexible circuit boards 300, a timing control circuit 400, a power supply circuit 500, and a circuit board 600.

[0038] The display panel 100 can be shaped as a rectangular plane in a plan view, having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. Each corner where the long side extending in the first direction DR1 intersects the short side extending in the second direction DR2 can be rounded to have a selected curvature, or can be a right angle. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and can be other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 can be flat, but embodiments are not limited thereto. For example, the display panel 100 can include curved portions formed at left and right ends and having a constant or varying curvature. For example, the display panel 100 can be formed to be flexible, such that the display panel 100 can be curved, bent, folded, or rolled.

[0039] The display panel 100 can include a display area DA displaying an image and a non-display area NDA disposed around the display area DA. A substrate SUB (see Figure 3A ) of the display panel 100 can include the display area DA and the non-display area NDA.

[0040] The display area DA can occupy a large portion of the area of the display panel 100. The display area DA can be disposed in a central portion of the display panel 100. Pixels PX can be disposed in the display area DA to display an image. The display area DA can be an area that displays an image by including the pixels PX. For example, the display area DA can include a pixel area in which the pixels PX are disposed.

[0041] The non-display area NDA can be an area that does not display an image. The non-display area NDA can be an edge area of the display panel 100. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can surround the display area DA.

[0042] Display pads PD (see Figure 2 ) can be disposed in the non-display area NDA so as to be connected to the flexible circuit boards 300. The display pads PD (see Figure 2 ) can be disposed at an edge portion of the display panel 100.

[0043] Each of the source driving circuits 200 can be formed as an integrated circuit and attached to a corresponding flexible circuit board 300, but embodiments are not limited thereto. Each of the source driving circuits 200 can be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method.

[0044] Each of the flexible circuit boards 300 can be disposed on display pads PD (see Figure 2 ) provided at an edge portion of the display panel 100. Each of the flexible circuit boards 300 can be attached to the display pads PD (see Figure 2 ) using a conductive adhesive member such as an anisotropic conductive film. Accordingly, the flexible circuit boards 300 can be electrically connected to the signal lines of the display panel 100. Each of the flexible circuit boards 300 can be a flexible printed circuit board or a flexible film such as a chip on film.

[0045] The timing control circuit 400 can generate timing control signals that control timing of the scan driving circuits GDC1 and GDC2 (see Figure 2 ), the emission driving circuits EDC1 and EDC2 (see Figure 2 ), and the source driving circuit 200. The power supply circuit 500 can generate a power voltage that drives the display panel 100 according to a power input from the outside. Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit and attached to the circuit board 600.

[0046] The circuit board 600 can be connected to one side of each of the flexible circuit boards 300. The circuit board 600 can be a rigid printed circuit board.

[0047] Figure 2 is a schematic layout diagram of the display panel 100 according to an embodiment.

[0048] Referring to Figure 2 , the display panel 100 can include display pads PD, a first scan driving circuit GDC1, a first emission driving circuit EDC1, a second scan driving circuit GDC2, a second emission driving circuit EDC2, and a dam region DMA.

[0049] The display pads PD can be provided at an edge portion of the display panel 100. The display pads PD can be divided into a plurality of groups. In a case where the display device 10 includes five flexible circuit boards 300 as shown in Figure 1 , the display pads PD can be divided into five groups. The display pads PD of each of the groups can correspond one-to-one to protrusions of the corresponding flexible circuit boards 300. Accordingly, the display pads PD of each of the groups can be electrically connected to the corresponding flexible circuit boards 300.

[0050] Some of the display pads PD can be electrically connected to data lines disposed in the display area DA. Some of the other display pads PD can be electrically connected to the first scan driving circuit GDC1, the second scan driving circuit GDC2, the first emission driving circuit EDC1, and the second emission driving circuit EDC2. Some of the other display pads PD can be connected to power lines that apply a first power voltage.

[0051] The first scan driving circuit GDC1 and the second scan driving circuit GDC2 can be electrically connected to scan lines in the display area DA. The first scan driving circuit GDC1 can be disposed in the non-display area NDA on the first side (e.g., the left side) of the display panel 100. The second scan driving circuit GDC2 can be disposed in the non-display area NDA on the second side (e.g., the right side) of the display panel 100.

[0052] The first emission driving circuit EDC1 and the second emission driving circuit EDC2 can be electrically connected to emission control lines in the display area DA. The first emission driving circuit EDC1 can be disposed in the non-display area NDA on the first side (e.g., the left side) of the display panel 100. The second emission driving circuit EDC2 can be disposed in the non-display area NDA on the second side (e.g., the right side) of the display panel 100.

[0053] The first scan driving circuit GDC1 can be disposed between the display area DA and the first emission driving circuit EDC1. The first scan driving circuit GDC1 can be disposed closer to the display area DA than the first emission driving circuit EDC1. For example, the first emission driving circuit EDC1 can be disposed closer to an edge portion of the display panel 100 on the first side than the first scan driving circuit GDC1.

[0054] The second scan driving circuit GDC2 can be disposed between the display area DA and the second emission driving circuit EDC2. The second scan driving circuit GDC2 can be disposed closer to the display area DA than the second emission driving circuit EDC2. For example, the second emission driving circuit EDC2 can be disposed closer to an edge portion of the display panel 100 on the second side than the second scan driving circuit GDC2.

[0055] The dam area DMA can include at least one dam for preventing the encapsulation organic layer from overflowing to the display pads PD. The dam area DMA can surround the display area DA.

[0056] The dam region DMA can be disposed outside the first emission driving circuit EDC1 and outside the second emission driving circuit EDC2. The dam region DMA can be disposed closer to the edge portion of the display panel 100 on the first side than the first emission driving circuit EDC1. For example, the dam region DMA can be disposed closer to the edge portion of the display panel 100 on the second side than the second emission driving circuit EDC2.

[0057] Figure 3A is a schematic cross-sectional view of a display panel 100 according to an embodiment. For example, Figure 3A A portion of a display region DA of a display panel 100 is illustrated. As an example of a display panel 100 to which an embodiment is applied, Figure 3A A light-emitting display panel including light-emitting elements ED (e.g., organic light-emitting diodes) is illustrated.

[0058] Referring to Figure 3A The display panel 100 can include a substrate SUB (or base layer), a thin-film transistor layer TFT, a light-emitting element layer LEL, and an encapsulation layer ENL. The thin-film transistor layer TFT, the light-emitting element layer LEL, and the encapsulation layer ENL can be disposed on the substrate SUB to overlap with each other. For example, in the display region DA, the thin-film transistor layer TFT, the light-emitting element layer LEL, and the encapsulation layer ENL can be disposed on the substrate SUB in this order along the third direction DR3.

[0059] In an embodiment, the display panel 100 can further include additional elements disposed on and / or under the encapsulation layer ENL. For example, the display panel 100 can further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and the protective layer can be disposed on the encapsulation layer ENL, or can be disposed between the light-emitting element layer LEL and the encapsulation layer ENL.

[0060] The substrate SUB can be a base member for forming the display panel 100, and can be rigid or flexible. In an embodiment, the substrate SUB can be a substrate including an insulating material such as glass and having a rigid characteristic, and can not be bent. In another example, the substrate SUB can be a flexible substrate including polyimide or other insulating material, and can be bent, folded, rolled, etc., and can or can not be bent.

[0061] A thin film transistor layer TFT (e.g., a backplane circuit layer or a thin film transistor layer) can be provided on the substrate SUB. The thin film transistor layer TFT can include circuit elements (including pixel transistors and capacitors) of the pixels PX and lines (e.g., signal lines and power supply lines). In an embodiment, the thin film transistor layer TFT can also include circuit elements of at least one of the first scan driver circuit GDC1, the second scan driver circuit GDC2, the first emission driver circuit EDC1, and the second emission driver circuit EDC2, e.g., can also include circuit transistors and / or capacitors.

[0062] As an example of the circuit elements provided in the thin film transistor layer TFT, Figure 3A A transistor TR provided in a pixel region PXA in which one pixel PX is provided and included in a pixel circuit of the pixel PX is illustrated. The transistor TR can be a switching transistor or a driving transistor.

[0063] In an embodiment, the pixel transistors can be formed simultaneously using the same material and can have substantially the same or similar cross-sectional structures. For example, the transistors TR of the pixels PX can be formed simultaneously using the same oxide semiconductor and can have substantially the same or similar cross-sectional structures. For example, the active layers ACT of the transistors TR can be provided at the same layer within the thin film transistor layer TFT (e.g., on the buffer layer BFL) and can include the same oxide semiconductor.

[0064] The thin film transistor layer TFT can include a plurality of conductive layers and at least one semiconductor layer provided on the substrate SUB (or the barrier layer BR). For example, the thin film transistor layer TFT can also include a plurality of insulating layers and / or insulating patterns provided on the substrate SUB (or the barrier layer BR).

[0065] The patterns included in the conductive layers of the thin film transistor layer TFT can include electrodes that constitute the circuit elements of the thin film transistor layer TFT, conductive patterns and / or lines connected to the circuit elements, and / or the like. The patterns included in each of the conductive layers of the thin film transistor layer TFT (e.g., the electrodes, the conductive patterns, and / or the lines of each of the conductive layers) can include at least one conductive material. For example, the patterns included in each of the conductive layers of the thin film transistor layer TFT can include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials. In an embodiment, the patterns included in the same conductive layer can be formed simultaneously using the same conductive material.

[0066] The pattern included in the semiconductor layer of the thin film transistor layer TFT can include active layers ACT of transistors TR (e.g., pixel transistors and circuit transistors) disposed within the thin film transistor layer TFT. In an embodiment, the active layers ACT of the pixel transistors and the circuit transistors can be formed simultaneously using the same semiconductor material (e.g., the same oxide semiconductor). Thus, the active layers ACT of the pixel transistors and the circuit transistors can be disposed at the same layer and can include the same semiconductor material.

[0067] The insulating layer and / or the insulating pattern of the thin film transistor layer TFT can include a barrier layer BR, a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a planarization layer VIA disposed in sequence on the substrate SUB along the third direction DR3. Each of the insulating layer and the insulating pattern of the thin film transistor layer TFT can include an inorganic insulating material or an organic insulating material, and can consist of a single layer or multiple layers.

[0068] In an embodiment, at least one of the insulating layers of the thin film transistor layer TFT can be disposed throughout the entire display area DA. For example, the barrier layer BR, the buffer layer BFL, the interlayer insulating layer ILD, and the planarization layer VIA can be disposed throughout the entire display area DA.

[0069] The structure of the thin film transistor layer TFT will be described layer by layer. First, the barrier layer BR can be disposed on the substrate SUB. The barrier layer BR can include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), titanium oxide (TiO x ), aluminum oxide (Al x O y ), or other inorganic insulating materials). The barrier layer BR can protect the pixels PX from moisture introduced through the substrate SUB susceptible to moisture penetration. In another example, the barrier layer BR can also be omitted.

[0070] A first conductive layer (e.g., a lower conductive layer) including a bottom electrode BE (or a light-blocking layer) of at least one transistor TR can be disposed on the barrier layer BR (or the substrate SUB). For example, the bottom electrode BE (or the light-blocking layer) of the driving transistor can be disposed on the barrier layer BR. The bottom electrode BE can be disposed under the active layer ACT to overlap the channel region CH of the driving transistor. In an embodiment, the bottom electrode BE can also overlap at least a portion of each of the source region SR and the drain region DR of the transistor TR, but embodiments are not limited thereto. Each of the patterns of the first conductive layer including the bottom electrode BE can include at least one conductive material and can consist of a single layer or multiple layers.

[0071] In an embodiment, the bottom electrode BE can be electrically connected to an electrode (e.g., a source electrode SE) of the transistor TR and can function as an electrode for adjusting a characteristic of the transistor TR. For example, the bottom electrode BE can be electrically connected to the source electrode SE of the transistor TR. In the case where the bottom electrode BE is electrically connected to an electrode of the transistor TR, it can be regarded as a component included in the transistor TR. The bottom electrode BE disposed under the active layer ACT of the transistor TR can block external light from being incident on the channel region CH of the transistor TR. In an embodiment, in the case where the transistor TR of the thin film transistor layer TFT does not include a bottom electrode BE or a light-blocking layer, the first conductive layer can be omitted.

[0072] A buffer layer BFL can be disposed on the barrier layer BR and the bottom electrode BE. The buffer layer BFL can include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), titanium oxide (TiO x ), aluminum oxide (Al x O y ), or other inorganic insulating materials).

[0073] The buffer layer BFL can include an insulating material suitable as a barrier material for preventing diffusion of oxygen, hydrogen, etc. In addition to a silicon nitride layer including silicon nitride (SiN x ) and a silicon oxide layer including silicon oxide (SiO x ), the buffer layer BFL can also include an insulating material that appropriately blocks oxygen, hydrogen, and / or moisture.

[0074] Each of the pixel transistors can include an active layer ACT provided over the buffer layer BFL and a gate electrode GE overlapping with a portion of the active layer ACT. A gate insulating layer GI can be provided between the active layer ACT and the gate electrode GE of each of the pixel transistors. In an embodiment, each of the pixel transistors can further include at least one of a drain electrode DE electrically connected to a drain region DR of the active layer ACT and a source electrode SE electrically connected to a source region SR of the active layer ACT. In another example, at least one of the pixel transistors can not include the drain electrode DE and the source electrode SE, and the drain region DR and the source region SR of the active layer ACT can function as the drain electrode and the source electrode.

[0075] The active layer ACT of the pixel transistor can be provided over the buffer layer BFL. For example, a semiconductor layer including the active layer ACT can be provided over the buffer layer BFL. The semiconductor layer can be covered with the gate insulating layer GI and the interlayer insulating layer ILD.

[0076] Each of the active layers ACT can include a channel region CH, a source region SR, and a drain region DR. The channel region CH can overlap with the gate electrode GE in a plan view in the third direction DR3, and can be provided between the source region SR and the drain region DR. The source region SR and the drain region DR can be provided on both sides (e.g., opposite sides) of the channel region CH, and can be spaced apart from each other with the channel region CH therebetween. The source region SR and the drain region DR (or a portion of each of the source region SR and the drain region DR) can not overlap with the gate electrode GE in a plan view. The carrier concentration (e.g., electron concentration) of the source region SR and the drain region DR can be higher than the carrier concentration of the channel region CH.

[0077] In an embodiment, the active layer ACT of the pixel transistor can include an oxide semiconductor. For example, the active layer ACT of the pixel transistor can include an oxide semiconductor including at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), or other oxide semiconductor. For example, the active layer ACT of the pixel transistor can include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium oxide (InO or In2O3), titanium oxide (TiO or TiO2), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin gallium zinc oxide (ITGZO), or other oxide semiconductor.

[0078] In an embodiment, the active layers ACT of some of the transistors TR provided within the thin film transistor layer TFT, including the pixel transistors, can be provided over the buffer layer BFL.

[0079] In an embodiment, at least one transistor TR can be provided in each pixel region PXA. Accordingly, a plurality of transistors TR can be provided in the display region DA.

[0080] The gate insulating layer GI can be provided on the active layer ACT of the pixel transistor. For example, the gate insulating layer GI can be provided on a portion of each of the active layers ACT including the channel region CH.

[0081] The gate insulating layer GI can include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), titanium oxide (TiO x ), aluminum oxide (Al x O y , or other inorganic insulating material).

[0082] In an embodiment, in each transistor region in which the transistor TR is provided, the gate insulating layer GI can be etched to cover a portion of the active layer ACT included in the transistor TR and to expose another portion of the active layer ACT. For example, in the region in which the transistor TR is provided, the gate insulating layer GI can cover the channel region CH of the active layer ACT included in the transistor TR and expose the source region SR and the drain region DR of the active layer ACT.

[0083] Since the gate insulating layer GI exposes the source region SR and the drain region DR, the conductivity of the source region SR and the drain region DR can be appropriately and / or easily increased during a process of manufacturing the display panel 100. For example, since oxygen vacancies are generated in the source region SR and the drain region DR in a process of etching the gate insulating layer GI to expose at least a portion of each of the source region SR and the drain region DR, the carrier concentration of the source region SR and the drain region DR can be increased in a subsequent process (e.g., a process of forming the interlayer insulating layer ILD) without performing a doping process.

[0084] However, embodiments are not limited thereto. For example, in addition to the contact holes for connecting each transistor TR to other circuit elements or lines, the gate insulating layer GI can cover (e.g., completely cover) the active layers ACT of some or all of the transistors TR included in the thin film transistor layer TFT.

[0085] A second conductive layer (e.g., a gate conductive layer) including a gate electrode GE of a pixel transistor can be disposed on the gate insulating layer GI. For example, the gate electrode GE of the transistor TR can be disposed on the gate insulating layer GI covering the channel region CH of the transistor TR. Each of the patterns of the second conductive layer including the gate electrode GE can include at least one conductive material, and can consist of a single layer or multiple layers.

[0086] An interlayer insulating layer ILD can be disposed on the buffer layer BFL, the semiconductor layer including the active layer ACT, the gate insulating layer GI, and the second conductive layer including the gate electrode GE. For example, the interlayer insulating layer ILD can be disposed on the buffer layer BFL to cover the patterns of the semiconductor layer, the gate insulating layer GI, and the second conductive layer. The interlayer insulating layer ILD can include at least one inorganic insulating layer including an inorganic insulating material.

[0087] A third conductive layer (e.g., a source-drain conductive layer) including source and drain electrodes SE and DE of a pixel transistor and / or a conductive pattern electrically connected to at least some of the pixel transistors can be disposed on the interlayer insulating layer ILD. For example, the third conductive layer can include the source and drain electrodes SE and DE of the transistor TR. Each of the patterns of the third conductive layer can include at least one conductive material, and can consist of a single layer or multiple layers.

[0088] The source and drain electrodes SE and DE of each transistor TR can penetrate the interlayer insulating layer ILD, and can be electrically connected to the source and drain regions SR and DR of the transistor TR, respectively. In an embodiment, the source electrode SE of each transistor TR can also penetrate the interlayer insulating layer ILD and the buffer layer BFL, and can be electrically connected to the bottom electrode BE of the transistor TR.

[0089] A planarization layer VIA can be disposed on the pixel transistors. For example, the planarization layer VIA can be disposed on the interlayer insulating layer ILD and the third conductive layer. The planarization layer VIA can include at least one organic insulating layer including an organic insulating material (e.g., an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or other organic insulating material). The planarization layer VIA can include or can not include an inorganic insulating layer. A surface (e.g., an upper surface) of the planarization layer VIA can be substantially planar.

[0090] A light emitting element layer LEL can be disposed on the thin film transistor layer TFT. For example, the light emitting element layer LEL can be disposed on the planarization layer VIA, and can be disposed at least in the display area DA.

[0091] The light emitting element layer LEL can include a light emitting element ED of each pixel PX. For example, the light emitting element layer LEL can include a pixel defining layer PDL (also referred to as a "bank") defining an emission area of each pixel PX and a light emitting element ED disposed in each emission area. In an embodiment, the light emitting element layer LEL can further include a spacer SPC disposed on a portion of the pixel defining layer PDL.

[0092] Each light emitting element ED can include a first electrode ET1 disposed in the emission area and a light emitting layer EML and a second electrode ET2 disposed in sequence on the first electrode ET1. The first electrode ET1 of each light emitting element ED can penetrate the planarization layer VIA and can be electrically connected to at least one pixel transistor (e.g., the transistor TR) included in the corresponding pixel PX.

[0093] The first electrode ET1 of each light emitting element ED can be a single-layer electrode or a multi-layer electrode including at least one conductive material. In an embodiment, the display panel 100 can be a top emission display panel, and the first electrode ET1 can include a reflective electrode layer having a high reflectivity. Since the first electrode ET1 is a main feature of the present disclosure, it will be described in detail later.

[0094] The light emitting layer EML of each light emitting element ED can include a high molecular material or a low molecular material. Light emitted from the light emitting layer EML can contribute to image display.

[0095] Although Figure 3A The display panel 100 in which the light emitting layer EML of the light emitting element ED is formed individually in each pixel area PXA is illustrated, but embodiments are not limited thereto. For example, the display panel 100 can further include a light emitting element having a series structure including a light emitting layer EML formed as a common layer throughout the entire display area DA.

[0096] The second electrode ET2 of each light emitting element ED can include a conductive material. In an embodiment, the second electrode ET2 can be a common layer formed throughout the entire display area DA to cover the light emitting layer EML and the pixel defining layer PDL. In an embodiment, the display panel 100 can be a top emission display panel, and the second electrode ET2 can include a transparent or semi-transparent electrode layer.

[0097] In a top emission structure, the second electrode ET2 can be made of a transparent conductive material (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In the case where the second electrode ET2 is made of a semi-transmissive conductive material, light output efficiency of each light emitting element ED can be improved by a microcavity.

[0098] The positions of the first electrode ET1 and the second electrode ET2 can be reversed.

[0099] The pixel definition layer PDL can have an opening corresponding to (or overlapping) each emission area, and can surround each emission area. For example, the pixel definition layer PDL can be formed to cover an edge portion of the first electrode ET1 of each light emitting element ED, and can include an opening exposing other portions of the first electrode ET1. An area in which the exposed first electrode ET1 and the light emitting layer EML overlap can be an emission area of each pixel PX. In an embodiment, the pixel definition layer PDL can be made of an organic material. The pixel definition layer PDL can include a light blocking material. The pixel definition layer PDL can include a base resin and a colorant. The base resin can include at least one of a cardo resin, an epoxy resin, an acrylate resin, a siloxane resin, and a polyimide. The colorant can be selected from carbon pigments, metal oxide pigments, and organic pigments. For example, the carbon pigments can be selected from carbon black, carbon nanotubes, and vertical aligned nanotube array (VANTA) black, but embodiments are not limited thereto. For example, the metal oxide pigments can be titanium black (TiN x O y ), Cu-Mn-Fe black pigments, but embodiments are not limited thereto. For example, the organic pigments can be selected from lactam black, perylene black, and aniline black, but embodiments are not limited thereto. For another example, the colorant can be a mixture of two or more pigments or dyes having different colors, but embodiments are not limited thereto.

[0100] The pixel definition layer PDL can include a halogen element. The halogen element can be added during a process of manufacturing the pixel definition layer PDL, and can not be removed during purification. In another example, a material including a halogen element can be used as the pixel definition layer PDL.

[0101] The halogen element can include at least one of Cl, Br, and I.

[0102] A spacer SPC can be disposed on a portion of the pixel definition layer PDL. The spacer SPC can include at least one organic insulating layer including an organic insulating material. The spacer SPC can include the same material as the pixel definition layer PDL or a different material from the pixel definition layer PDL. The pixel definition layer PDL and the spacer SPC can be sequentially formed by respective mask processes, or can be simultaneously and / or integrally formed using a half-tone mask.

[0103] An encapsulation layer ENL can be disposed on the light emitting element layer LEL. The encapsulation layer ENL can cover the light emitting element layer LEL in the display area DA and can extend to the non-display area NDA to contact the thin film transistor layer TFT. The encapsulation layer ENL can block oxygen or moisture from permeating into the light emitting element layer LEL and mitigate electrical and / or physical effects on the thin film transistor layer TFT and the light emitting element layer LEL.

[0104] In an embodiment, the encapsulation layer ENL can include a first encapsulation layer ENL1, a second encapsulation layer ENL2, and a third encapsulation layer ENL3 disposed in sequence on the light emitting element layer LEL. Each of the first encapsulation layer ENL1 and the third encapsulation layer ENL3 can be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer ENL2 can be an organic encapsulation layer including an organic material.

[0105] Now, a first electrode ET1, which is a main feature of the display device 10 according to an embodiment, will be described.

[0106] Figure 3B is a magnified schematic cross-sectional view of a region A of a display panel 100 according to an embodiment.

[0107] Referring to Figure 3B The first electrode ET1 can include a second conductive layer ET1_2, a first conductive layer ET1_1 disposed on the second conductive layer ET1_2, and a third conductive layer ET1_3 disposed on the first conductive layer ET1_1.

[0108] The second conductive layer ET1_2 and the third conductive layer ET1_3 can include a conductive oxide.

[0109] The conductive oxide can include at least one of indium tin oxide (ITO), zinc oxide (ZnO), zinc tin oxide (ZTO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), gallium tin oxide (GTO), and fluorine-doped tin oxide (FTO).

[0110] The third conductive layer ET1_3 can be designed to improve a potential barrier between the first conductive layer ET1_1 and the light emitting layer EML. For example, a work function of indium tin oxide (ITO) can be about 5.2 eV, and a work function of the light emitting layer EML can be about 5.1 eV. Since the difference in the work function between the indium tin oxide (ITO) and the light emitting layer EML is small, electron transfer can easily occur.

[0111] The first conductive layer ET1_1 can include silver (Ag), palladium (Pd), and copper (Cu). For example, the first conductive layer ET1_1 can include about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu). For example, the first conductive layer ET1_1 can be an alloy consisting of about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu). The content of silver (Ag), the content of palladium (Pd), and the sum of the content of copper (Cu) in the first conductive layer ET1_1 can be about 100 wt% or less.

[0112] Since the display device 10 according to the embodiment of the disclosure includes the first electrode ET1 including the first conductive layer including about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu), high reflectivity can be achieved while preventing the generation of voids.

[0113] Figure 3C is an enlarged schematic cross-sectional view of a region B of the display panel 100 according to the embodiment.

[0114] Referring to Figure 3C As the amorphous material of the third conductive layer ET1_3 becomes a crystalline material during the high-temperature post-processing process, grain boundaries GB can be generated. The grain boundaries GB_R generated in the third conductive layer ET1_3 in a region in contact with the pixel definition layer PDL can serve as a channel (or function as a channel) through which halogen ions included in the pixel definition layer PDL and silver (Ag) ions of the first conductive layer ET1_1 can move. The halogen ions included in the pixel definition layer PDL and the silver (Ag) ions of the first conductive layer ET1_1 can meet through the grain boundaries GB_R and can combine to generate a salt (AgCl, AgBr, AgI, AgS, etc.). The generated salt can be removed through a cleaning process. However, a void can be formed on a portion of the surface of the first conductive layer ET1_1 and the third conductive layer ET1_3 from which the salt has been removed during the cleaning process. The void can cause a step on the surface of the first electrode ET1. Accordingly, the current flowing from the first electrode ET1 to the second electrode ET2 through the light-emitting layer EML can not be uniform within the first electrode ET1. For example, due to the surface step of the first electrode ET1, the largest amount of current can flow at a thin portion of the light-emitting layer EML, or even a short circuit can occur between the first electrode ET1 and the second electrode ET2, thereby causing a dark spot.

[0115] For example, the third conductive layer ET1_3 can be removed together with the salt during a cleaning process. In the case where the light-emitting layer EML is formed on the first conductive layer ET1_1 from which the third conductive layer ET1_3 has been removed, electron transfer can not easily occur due to a difference in work function between the first conductive layer ET1_1 and the light-emitting layer EML.

[0116] In the case where the first electrode ET1 is made of an APC alloy having a reduced silver (Ag) content, a salt generated due to the combination of silver (Ag) and a halogen element can be reduced compared to when the first electrode ET1 is made of only silver (Ag). Accordingly, defects such as a salt, voids, and dark spots, which are generated in the case where the first electrode ET1 is made of silver (Ag), can be prevented or minimized.

[0117] In the case where the first conductive layer ET1_1 includes less than about 97 wt% of silver (Ag), the light absorption rate of the display device 10 including the first conductive layer ET1_1 can increase, thereby reducing light efficiency. In the case where the first conductive layer ET1_1 includes more than about 99 wt% of silver (Ag), defects can occur in the display panel 100 including the first conductive layer ET1_1.

[0118] The transistor TR including the semiconductor layer made of an oxide semiconductor can be susceptible to light from the outside, and thus the characteristics of the device can change according to the light. In order to maintain the reliability of the device, light from the outside can be blocked. For example, the pixel definition layer PDL can include a light-blocking material. The pixel definition layer PDL including the light-blocking material can be formed on the transistor TR to effectively block light applied to the transistor TR and improve the reliability of the device.

[0119] The pixel definition layer PDL can include at least one halogen element among Cl, Br, and I. The content of the at least one halogen element in the pixel definition layer PDL can be in the range of about 1 wt% to about 30 wt%.

[0120] The light-blocking material included in the pixel definition layer PDL can include a halogen.

[0121] The halogen element can include a halogen element that is not completely purified during a g-synthesis process in the case where a compound for forming the pixel definition layer PDL is synthesized. For example, in the case where a cardo resin is synthesized, a dihydroxy cardo compound and epichlorohydrin can react to obtain a cardo resin. For example, a large amount of chlorine can be generated as a byproduct of synthesis, and chlorine can remain even after purification.

[0122] To improve the reliability of the transistor TR including the semiconductor layer made of the oxide semiconductor, the pixel defining layer PDL can include a light blocking material that blocks light. The light blocking material of the pixel defining layer PDL can include a large amount of halogen elements.

[0123] For example, including an appropriate amount of palladium (Pd) and copper (Cu) in addition to silver (Ag) can increase adhesion between silver (Ag), palladium (Pd), and copper (Cu), thereby suppressing the ionization phenomenon of silver (Ag). As the ionization phenomenon of silver (Ag) is suppressed, salt generated due to a reaction between halogen ions included in the pixel defining layer PDL and silver (Ag) can be prevented or minimized, which in turn suppresses defects such as voids and dark spots.

[0124] Accordingly, the heat resistance and chemical resistance of the first electrode ET1 including the first conductive layer ET1_1 including about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu) are improved while maintaining the reflection efficiency of the display device 10.

[0125] A method of manufacturing a display device relates to a method of manufacturing the above-described display device 10. The method of manufacturing a display device will be described focusing on the differences from the display device 10, and redundant descriptions will be omitted for the convenience of description.

[0126] The method of manufacturing a display device according to an embodiment of the disclosure can include: forming a transistor TR including a semiconductor layer on a substrate SUB; forming a first electrode ET1 on the transistor TR; forming a pixel defining layer PDL including an opening exposing at least a portion of the first electrode ET1; forming an emission layer EML on the first electrode ET1 in the opening; and forming a second electrode ET2 on the emission layer EML and the pixel defining layer PDL. Forming the first electrode ET1 can include forming a first conductive layer at an oxygen (O2) concentration of about 3% or less, and the first conductive layer can include silver (Ag), palladium (Pd), and copper (Cu).

[0127] Forming the first electrode ET1 can include: forming a second conductive layer ET1_2 including a conductive oxide; forming a first conductive layer ET1_1 on the second conductive layer ET1_2; and forming a third conductive layer ET1_3 including a conductive oxide on the first conductive layer ET1_1.

[0128] The first conductive layer ET1_1 including about 97 wt% to about 99 wt% of silver (Ag), about 0.1 wt% to about 2.9 wt% of palladium (Pd), and about 0.1 wt% to about 2.9 wt% of copper (Cu) can be formed at an oxygen (O2) concentration of about 3% or less.

[0129] Since the first conductive layer ET1_1 is formed under an oxygen concentration of about 3% or less, the reflectance efficiency can be maintained similarly to when silver (Ag) is used as the electrode.

[0130] For example, the display device 10 manufactured using the manufacturing method of the present embodiment can maintain a low surface resistance even under high-temperature and high-humidity conditions.

[0131] Hereinafter, the present disclosure will be described in more detail through the following examples. However, the following examples are intended to serve only for the purpose of explanation and are not intended to limit the scope of the present disclosure.

[0132] 1. Manufacturing of display device

[0133] 1) Example 1

[0134] A display panel using indium gallium zinc oxide (IGZO) as a semiconductor layer and a cardo compound of the following reaction formula as a pixel defining layer was prepared. ITO was prepared as a first electrode of the display panel. A conductive layer was formed on the ITO under an oxygen concentration of 0% by using an alloy of 98% silver (Ag), 1% palladium (Pd), and 1% copper (Cu) as a target. ITO was formed on the conductive layer. A display panel using an ITO / 98% Ag, 1% Pd, 1% Cu / ITO structure as a first electrode was manufactured (ITO / APC (O2: 0%) / ITO).

[0135]

[0136] 2) Example 2

[0137] A display panel identical to Example 1 (ITO / APC (O2: 3.0%) / ITO) was manufactured except that the conductive layer was formed under an oxygen concentration of 3%.

[0138] 3) Comparative Example 1

[0139] A display panel identical to Example 1 was manufactured except that ITO / Ag / ITO was used as a first electrode.

[0140] 4) Comparative Example 2

[0141] A display panel identical to Example 1 was manufactured except that ITO / 99.1% Ag, 0.1% Pd, 0.8% Cu / ITO was used as a first electrode.

[0142] 5) Comparative Example 3

[0143] A display panel identical to Example 1 was manufactured except that ITO / 96.9% Ag, 1.5% Pd, 1.6% Cu / ITO was used as a first electrode.

[0144] 6) Comparative Example 4

[0145] A display panel identical to Example 1 (ITO / APC (O2: 5.0%) / ITO) was manufactured, except that the conductive layer was formed at an oxygen concentration of 5%.

[0146] 7) Comparative Example 5

[0147] A display panel identical to Example 1 (ITO / APC (O2: 10.0%) / ITO) was manufactured, except that the conductive layer was formed at an oxygen concentration of 10%.

[0148] 8) Comparative Example 6

[0149] A display panel identical to Example 1 (ITO / APC (O2: 15.0%) / ITO) was manufactured, except that the conductive layer was formed at an oxygen concentration of 15%.

[0150] [Evaluation]

[0151] 1. Heat resistance

[0152] Figure 4A and Figure 4B are scanning electron microscope (SEM) images of the surfaces of Example 1 and Comparative Example 1, respectively, measured after heat treatment at a temperature of 450°C for 1 hour.

[0153] From the results shown in Figure 4B , it can be seen that the entire surface of Comparative Example 1 was not flat due to the formation of a large number of large pinholes after high-temperature treatment. On the other hand, it can be seen that Example 1 according to the embodiment had a uniform surface even after heat treatment, compared to Comparative Example 1. Figure 4A This means that the heat resistance of the electrode according to the embodiment is higher than that of silver (Ag).

[0154] 2. Light efficiency

[0155] The light efficiency characteristics of the display panels manufactured as in Example 1 and Comparative Example 1 with respect to the wavelength region were measured, and the results are shown in Figure 5 , Figure 6 and Figure 7 and Table 1.

[0156] Figure 5 is a graph showing the transmittance of the display panels of Example 1 and Comparative Example 1 with respect to the wavelength region.

[0157] Figure 6 is a graph showing the reflectance of the display panels of Example 1 and Comparative Example 1 with respect to the wavelength region.

[0158] Figure 7is a schematic view showing absorbance of display panels of Example 1 and Comparative Example 1 with respect to wavelength regions.

[0159] Table 1 below shows reflectance, absorbance, surface resistance, and thermoelectric generator (TEG) efficiency of the display panels of Example 1 and Comparative Example 1.

[0160] [Table 1]

[0161] According to Figure 5 , Figure 6 and Figure 7 and the results shown in Table 1, it was measured that Example 1 has higher reflectance and transmittance and lower absorbance and surface resistance than Comparative Example 1. This means that Example 1 has better light efficiency than Comparative Example 1. It can also be seen that the TEG efficiency of Example 1 is higher or similar to that of Comparative Example 1.

[0162] A conventional APC alloy (i.e., an alloy of palladium, copper, and silver) has advantages such as high heat resistance and corrosion resistance compared to silver (Ag), but has a problem of lower light efficiency than silver (Ag). However, by adjusting the composition ratio of silver (Ag), palladium (Pd), and copper (Cu) as in the present disclosure, in addition to advantages such as heat resistance and corrosion resistance, the advantage of improved light efficiency can also be obtained.

[0163] Surface images were obtained to measure the number of defects of the display panels manufactured as in Example 1 and Comparative Examples 1 to 3, and the results are shown in Figure 8 , Figure 9 , Figure 10 and Figure 11 .

[0164] Figure 8 is a surface image of a display panel manufactured according to Example 1.

[0165] Figure 9 is a surface image of a display panel manufactured according to Comparative Example 1.

[0166] Figure 10 is a surface image of a display panel manufactured according to Comparative Example 2.

[0167] Figure 11 is a surface image of a display panel manufactured according to Comparative Example 3.

[0168] Thirty-six points were randomly measured to measure the number of defects in the surface images of Figure 8 , Figure 9 , Figure 10 and Figure 11 . Figure 8 The number of defects of Example 1 shown in Table 1 was 1 out of 36 points, Figure 9The number of defects in Comparative Example 1 shown is 16 out of 36 points. Figure 10 The number of defects in Comparative Example 2 shown is 8 out of 36 points, and Figure 11 The number of defects in Comparative Example 3 shown is 1 out of 36.

[0169] The light efficiency characteristics of display panels manufactured as in Example 1, Comparative Example 2, and Comparative Example 3 relative to the wavelength region were measured, and the results are as follows: Figure 12 , Figure 13 and Figure 14 As shown.

[0170] Figure 12 This is a schematic diagram showing the transmittance of the display panel of Example 1, Comparative Examples 2 and 3 relative to the wavelength region.

[0171] Figure 13 This is a schematic diagram showing the reflectivity of the display panel relative to the wavelength region for Example 1, Comparative Examples 2 and 3.

[0172] Figure 14 This is a schematic diagram showing the absorbance of the display panels of Example 1, Comparative Examples 2 and 3 relative to the wavelength region.

[0173] according to Figure 12 The results shown indicate that transmittance increases with increasing silver content.

[0174] according to Figure 13 The results shown indicate that reflectivity increases with increasing silver content.

[0175] according to Figure 14 The results shown indicate that absorbance increases as silver content decreases.

[0176] As from Figure 12 , Figure 13 and Figure 14 Obviously, Comparative Example 2 has the highest light efficiency. However, according to Figure 10 The results shown in Comparative Example 2 indicate that it suffers from low reliability due to numerous defects.

[0177] according to Figure 11 The results shown are almost flawless compared to Example 3. However, as Figure 12 , Figure 13 and Figure 14 As shown, Comparative Example 3 has the lowest luminous efficiency. Because Comparative Example 3 has low luminous efficiency due to its high absorbance, there are limitations in using it as a display device.

[0178] For example, a display panel in which silver (Ag), palladium (Pd), and copper (Cu) are combined in an appropriate composition ratio and used as an electrode according to the embodiment of the present disclosure exhibits similar or better light efficiency than when silver (Ag) is used as an electrode, while preventing or minimizing defects such as voids. However, a silver (Ag) content higher than 99% can improve the light efficiency of the display panel, but can cause defects such as voids. For example, a silver (Ag) content lower than 97% can improve defects such as voids, but can reduce light efficiency. This indicates that deviating from the appropriate composition ratio of silver (Ag), palladium (Pd), and copper (Cu) can cause defects such as voids or reduce light efficiency.

[0179] The light efficiency characteristics of the display panels manufactured as in Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, and Comparative Example 5 with respect to the wavelength region were measured, and the results are shown in FIGS. Figure 15 、 Figure 16 and Figure 17 .

[0180] Figure 15 is a graph showing the transmittance of the display panels of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, and Comparative Example 5 with respect to the wavelength region.

[0181] According to the results shown in Figure 15 , it can be seen that the transmittance of Example 1 and Example 2 and Comparative Example 1 is always high in the visible light region, while the transmittance of Comparative Example 4 and Comparative Example 5 is relatively low. This means that the transmittance is reduced in the case where the electrode is formed at a high oxygen concentration.

[0182] Figure 16 is a graph showing the reflectance of the display panels of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, and Comparative Example 5 with respect to the wavelength region.

[0183] According to the results shown in Figure 16 , the reflectance of Example 1 and Example 2 and Comparative Example 1 is always high in the visible light region, while the reflectance of Comparative Example 4 and Comparative Example 5 is relatively low. This means that the reflectance is reduced in the case where the electrode is formed at a high oxygen concentration.

[0184] Figure 17 is a graph showing the change in sheet resistance of the display panels of Example 1 and Example 2 and Comparative Example 1, Comparative Example 4, Comparative Example 5, and Comparative Example 6 over time.

[0185] Figure 17 is a graph showing the change in sheet resistance of the display panel in a high-temperature and high-humidity environment of 300°C and 90% over time.

[0186] According to the results shown in Figure 17The results shown indicate that the sheet resistance of Comparative Example 1 increases rapidly over time. This is because silver (Ag) has weak heat resistance and corrosion resistance. On the other hand, in the case of an alloy using 98% silver (Ag), 1% palladium (Pd), and 1% copper (Cu), it can be seen that the surface resistance remains low even in high temperature and high humidity environments. This means that the alloy of 98% silver (Ag), 1% palladium (Pd), and 1% copper (Cu) has excellent heat resistance and corrosion resistance. However, in the case of a display panel formed with electrodes in a 15% oxygen concentration environment, as in Comparative Example 6, it can be seen that the surface resistance increases over time in high temperature and high humidity environments.

[0187] For example, a display panel in which silver (Ag), palladium (Pd) and copper (Cu) are combined in an appropriate composition ratio and formed as electrodes at an oxygen concentration of 3% or lower, according to embodiments of the present disclosure, has excellent heat resistance and corrosion resistance as well as excellent light efficiency.

[0188] Figure 18 This is a schematic perspective view of an electronic device using a display device 10 according to an embodiment.

[0189] refer to Figure 18 The tablet 1, using the display device 10 according to the embodiment, is shown as an example of an electronic device. However, the display device 10 according to the embodiment can also be applied to other electronic devices besides the tablet 1. For example, the display device 10 according to the embodiment can be applied to electronic devices that display moving or still images. For example, the display device 10 according to the embodiment can be applied to portable electronic devices such as mobile phones, smartphones, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, PMPs, navigation devices, and UMPCs. In another example, the display device 10 according to the embodiment can be used as a display screen for various electronic devices such as televisions, laptop computers, monitors, billboards, and IoT devices.

[0190] In the display device 10 according to the embodiment, a conductive layer having an adjusted composition ratio of silver, palladium, and copper is applied to the electrodes to improve the ionization of silver (Ag), thereby suppressing the reaction with halogen elements included in the pixel defining layer PDL. Therefore, the formation of salts due to the reaction with silver (Ag) can be prevented, and defects such as voids and dark spots can be suppressed.

[0191] The display device 10 according to one embodiment of the present disclosure can be applied to various electronic devices. An electronic device according to one embodiment of the present disclosure includes the aforementioned display device 10, and may also include modules or devices with additional functions in addition to the display device 10.

[0192] Figure 19 is a block diagram of an electronic device according to an embodiment of the disclosure.

[0193] Referring to Figure 19 , the electronic device 2 according to an embodiment of the disclosure can include a display module 21, a processor 22, a memory 23, and a power module 24.

[0194] The processor 22 can include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0195] The memory 23 can store data information required for the operation of the processor 22 or the display module 21. When the processor 22 executes an application stored in the memory 23, an image data signal and / or an input control signal are transmitted to the display module 21, and the display module 21 can process the received signal and output image information through a display screen.

[0196] The power module 24 can include a power supply module such as, for example, a power adapter or a battery, and a power conversion module that converts a power source provided by the power supply module to generate a power source required for the operation of the electronic device 2.

[0197] At least one of the components of the electronic device 2 according to an embodiment of the disclosure can be included in the display device 10 according to an embodiment of the disclosure. Also, some of the respective modules functionally included in one module can be included in the display device 10, and the other modules can be provided separately from the display device 10. For example, the display device 10 can include the display module 21, and the processor 22, the memory 23, and the power module 24 can be provided in the form of other devices than the display device 10 within the electronic device 2.

[0198] Figure 20 is a schematic view of an electronic device according to various embodiments of the disclosure.

[0199] Referring to Figure 20 , various electronic devices to which the display device 10 according to an embodiment of the disclosure is applied can not only include image display electronic devices such as a smartphone 2_1a, a tablet PC (personal computer) 2_1b, a laptop computer 2_1c, a TV 2_1d, and a desktop monitor 2_1e, but also include wearable electronic devices including a display module such as, for example, smart glasses 2_2a, a head-mounted display 2_2b, and a smart watch 2_2c, and vehicle electronic devices 2_3 including a display module (for example, a CID (center information display) and an interior mirror display arranged on an instrument panel of a car, a center cluster, and an instrument panel).

[0200] At the conclusion of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing from the principles and spirit of the disclosure and the scope thereof. Therefore, the disclosed embodiments are not to be limited to the particular embodiments described, but are to be accorded the full scope that the principles and spirit of the disclosure encompasses.

Claims

1. A display device comprising: a substrate; a first electrode provided over the substrate; a pixel-defining layer including an opening exposing at least a part of the first electrode; a light-emitting layer provided over the first electrode in the opening; and a second electrode provided over the light-emitting layer and the pixel-defining layer, wherein the first electrode includes a first conductive layer including silver, palladium, and copper, and in the first conductive layer, a content of the silver is in a range from 97 wt% to 99 wt%, a content of the palladium is in a range from 0.1 wt% to 2.9 wt%, and a content of the copper is in a range from 0.1 wt% to 2.9 wt%. the first electrode further includes:

2. The display device according to claim 1, wherein a second conductive layer provided under the first conductive layer and including a conductive oxide; and a third conductive layer provided over the first conductive layer and including the conductive oxide. the conductive oxide includes at least one of indium tin oxide, zinc oxide, zinc tin oxide, indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, gallium tin oxide, and fluorine-doped tin oxide.

3. The display device of claim 2, wherein, the pixel-defining layer includes at least one halogen element among Cl, Br, and I.

4. The display device according to claim 1, wherein a content of the at least one halogen element in the pixel-defining layer is in a range from 1 wt% to 30 wt%.

5. The display device of claim 4, wherein, the pixel-defining layer includes a light-blocking material.

6. The display device according to claim 1, wherein 7. The display device according to claim 1, further comprising: a transistor including a semiconductor layer provided between the substrate and the first electrode and electrically connected to the first electrode, wherein the semiconductor layer includes an oxide semiconductor including at least one of indium, gallium, zinc, tin, and hafnium. the semiconductor layer includes at least one of zinc oxide, zinc tin oxide, indium zinc oxide, indium oxide, titanium oxide, indium gallium oxide, indium gallium zinc oxide, indium gallium tin oxide, indium zinc tin oxide, and indium tin gallium zinc oxide.

8. The display device of claim 7, wherein, 9. A method for manufacturing a display device, the method comprising: forming a transistor including a semiconductor layer over a substrate; forming a first electrode over the transistor; forming a pixel-defining layer including an opening exposing at least a part of the first electrode; forming a light-emitting layer over the first electrode in the opening; and forming a second electrode over the light-emitting layer and the pixel-defining layer, wherein the forming the first electrode includes forming a first conductive layer at an oxygen concentration of 3% or lower, and the first conductive layer includes silver, palladium, and copper. the first conductive layer includes the silver at 97 wt% to 99 wt%, the palladium at 0.1 wt% to 2.9 wt%, and the copper at 0.1 wt% to 2.9 wt%.

11. The method according to claim 9, wherein 10. The method of claim 9, wherein, the forming the first electrode further includes: forming a second conductive layer including a conductive oxide before forming the first conductive layer; and forming a third conductive layer including the conductive oxide over the first conductive layer, and the first conductive layer is provided over the second conductive layer. ​ ​ 12. The method of claim 11, wherein, The conductive oxide includes at least one of indium tin oxide, zinc oxide, zinc tin oxide, indium zinc oxide, indium gallium oxide, indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, aluminum-doped zinc oxide, gallium-doped zinc oxide, gallium tin oxide, and fluorine-doped tin oxide.

13. The method of claim 9, wherein, The pixel-defining layer includes at least one halogen element among Cl, Br, and I.

14. The method of claim 13, wherein, The content of the at least one halogen element in the pixel-defining layer is in a range of 1 wt% to 30 wt%.

15. The method of claim 9, wherein, The pixel-defining layer includes a light-blocking material.

16. The method of claim 9, wherein, The semiconductor layer includes at least one of zinc oxide, zinc tin oxide, indium zinc oxide, indium oxide, titanium oxide, indium gallium oxide, indium gallium zinc oxide, indium gallium tin oxide, indium zinc tin oxide, and indium tin gallium zinc oxide.

17. An electronic device comprising: a display device providing an image; and a processor transmitting an image data signal to the display device, wherein the display device includes: a substrate; a first electrode disposed on the substrate; a pixel-defining layer including an opening exposing at least a portion of the first electrode; a light-emitting layer disposed on the first electrode in the opening; and a second electrode disposed on the light-emitting layer and the pixel-defining layer, the first electrode includes a first conductive layer including silver, palladium, and copper, and in the first conductive layer, the content of the silver is in a range of 97 wt% to 99 wt%, the content of the palladium is in a range of 0.1 wt% to 2.9 wt%, and the content of the copper is in a range of 0.1 wt% to 2.9 wt%.

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