Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a substrate; a thin film transistor on the substrate; a planarization layer on the thin film transistor; a protective layer on the planarization layer and having a plurality of recesses; a first electrode disposed on the protective layer corresponding to each of the plurality of recesses; a pixel defining layer defining a light emitting region and a non-light emitting region on the protective layer; an organic light emitting layer on the first electrode in the light emitting region; and a second electrode on the pixel defining layer and the organic light emitting layer. The first electrode is divided into an inclined portion on an inclined surface of each of the plurality of recesses and a bottom portion at a lower end of the inclined portion, and the inclined portion may have a concave or convex uneven pattern.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0137392, filed on October 10, 2024, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. TECHNICAL FIELD

[0003] One or more embodiments of the present disclosure relate to a display device and an electronic device. BACKGROUND

[0004] As the information society develops, the demand for display devices that display various information in the form of images is rapidly increasing. In response to this, display devices of one or more suitable types (classes) including light-emitting display devices are being developed. SUMMARY

[0005] Aspects and features of embodiments of the present disclosure are directed to a display device capable of improving image quality of the display device by increasing a certain angle luminance ratio (LvA) and minimizing or reducing a luminance ratio deviation (dLvA). Additional aspects and features will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the description and / or the drawings, or can be learned by practice of the embodiments of the present disclosure presented herein.

[0006] However, the present disclosure is not limited to those set forth herein. The above-described and additional embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

[0007] According to one or more embodiments of the present disclosure, a display device includes a substrate; a thin film transistor on the substrate; a planarization layer on (e.g., disposed on) the thin film transistor; a protection layer on (e.g., disposed on) the planarization layer and having a plurality of recesses; a first electrode disposed on the protection layer corresponding to each of the plurality of recesses; a pixel definition layer defining a light emitting area and a non-light emitting area on the protection layer; an organic light emitting layer on (e.g., disposed on) the first electrode in the light emitting area; and a second electrode on (e.g., disposed on) the pixel definition layer and the organic light emitting layer, wherein the first electrode is divided into a sloped portion on (e.g., disposed on) a sloped surface of each of the plurality of recesses and a bottom portion at a lower end of the sloped portion (e.g., disposed at the lower end of the sloped portion), and the sloped portion can have a concave or convex uneven pattern.

[0008] According to one or more embodiments, the bottom portion can have a concave or convex uneven pattern.

[0009] According to one or more embodiments, the protective layer can have an uneven pattern under (e.g., disposed under) the uneven pattern of the inclined portion and the bottom portion of the first electrode.

[0010] According to one or more embodiments, a depth of the uneven pattern of the protective layer can be about 0.5 micrometers (µm) to about 1.0 µm, a width of the uneven pattern of the protective layer can be about 1.0 µm to about 2.0 µm, and a distance between the uneven patterns of the protective layer can be about 1.0 µm to about 2.0 µm.

[0011] According to one or more embodiments, the protective layer can include a first protective layer and a second protective layer disposed on (e.g., disposed on) a top surface of the first protective layer, wherein the uneven pattern of the protective layer is formed on (e.g., in / at) the top surface of the first protective layer and a bottom surface of the second protective layer.

[0012] According to one or more embodiments, the organic light emitting layer can be on (e.g., disposed on) the inclined portion and the bottom portion of the first electrode, wherein the organic light emitting layer includes an uneven pattern corresponding to the uneven pattern of the first electrode.

[0013] According to one or more embodiments, a thickness of each of the plurality of recesses is formed as a depth less than a thickness of the protective layer, and an inclined surface of each of the plurality of recesses is in a range of 20° to 70°. For example, the depth of each of the plurality of recesses can be less than the thickness of the protective layer, and the inclined surface of each of the plurality of recesses can have an inclined angle in a range of 20° to 70°.

[0014] According to one or more embodiments, the inclined portion of the first electrode can have substantially the same inclined angle as the inclined surface of each of the plurality of recesses. For example, the inclined portion of the first electrode can have an inclined angle having (possessing) substantially the same measure (or measurement value) as the inclined angle of the inclined surface of each of the plurality of recesses.

[0015] According to one or more embodiments, the pixel defining layer can not overlap with the inclined portion.

[0016] According to one or more embodiments, the protective layer includes a first protective layer and a second protective layer disposed on a top surface of the first protective layer, wherein the uneven pattern of the protective layer is formed on a top surface of the first protective layer and a bottom surface of the second protective layer.

[0017] According to one or more embodiments, an organic light emitting layer is disposed on the inclined portion and the bottom portion of the first electrode, wherein the organic light emitting layer includes an uneven pattern corresponding to the uneven pattern of the first electrode.

[0018] According to one or more embodiments, a thickness of each of the plurality of recesses is formed as a depth less than a thickness of the protective layer, and wherein an inclined surface of each of the plurality of recesses is in a range of 20° to 70°. For example, the depth of each of the plurality of recesses is less than the thickness of the protective layer, and the inclined surface of each of the plurality of recesses has an inclination angle in a range of 20° to 70°.

[0019] According to one or more embodiments, the inclined portion of the first electrode has the same inclination angle as the inclined surface of each of the plurality of recesses. For example, the inclined portion of the first electrode has an inclination angle having (possessing) the same measure (or measurement value) as the inclination angle of the inclined surface of each of the plurality of recesses.

[0020] According to one or more embodiments, the pixel definition layer does not overlap with the inclined portion.

[0021] According to one or more embodiments, the first electrode further includes a top portion at (e.g., disposed at) an upper end of the inclined portion, and wherein the pixel definition layer covers at least a portion of the top portion.

[0022] According to one or more embodiments of this disclosure, a display device includes: a substrate including a first light-emitting region and a second light-emitting region; a thin-film transistor on the substrate; a planarization layer on the thin-film transistor (e.g., disposed on the thin-film transistor); a protective layer on the planarization layer (e.g., disposed on the planarization layer) and having a first recess and a second recess respectively overlapping the first light-emitting region and the second light-emitting region; a first pixel electrode and a second pixel electrode, the first pixel electrode being disposed on a portion of the protective layer corresponding to the first recess (e.g., disposed on a portion of the protective layer corresponding to the first recess), and the second pixel electrode being disposed on a portion of the protective layer corresponding to the second recess (e.g., disposed on a portion of the protective layer corresponding to the second recess); and an organic light-emitting layer, including the first light-emitting region and the second light-emitting region. A first pixel light-emitting layer on a first pixel electrode in a light-emitting region (e.g., disposed on a first pixel electrode in a first light-emitting region) and a second pixel light-emitting layer on a second pixel electrode in a second light-emitting region (e.g., disposed on a second pixel electrode in a second light-emitting region); a pixel defining layer defining a light-emitting region and a non-light-emitting region on a protective layer; a common electrode on the pixel defining layer and the organic light-emitting layer (e.g., disposed on the pixel defining layer and the organic light-emitting layer), wherein the second pixel electrode is divided into an inclined portion on a second concave inclined surface (e.g., disposed on a second concave inclined surface) and a bottom portion at the lower end of the inclined portion (e.g., disposed at the lower end of the inclined portion), and the inclined portion and the bottom portion each have a concave or convex uneven pattern.

[0023] According to one or more embodiments, the first pixel electrode may be divided into an inclined portion on the inclined surface of the first recess (e.g., disposed on the inclined surface of the first recess) and a bottom portion at the lower end of the inclined portion (e.g., disposed at the lower end of the inclined portion), wherein the first pixel electrode does not include an uneven portion.

[0024] According to one or more embodiments, the first pixel electrode is divided into an inclined portion disposed on an inclined surface of the first recess and a bottom portion disposed at the lower end of the inclined portion, wherein the first pixel electrode does not include an uneven portion.

[0025] According to one or more embodiments, the protective layer has an uneven pattern below the uneven pattern of the inclined portion and bottom portion of the second pixel electrode (e.g., disposed below the uneven pattern of the inclined portion and bottom portion of the second pixel electrode).

[0026] According to one or more embodiments, the depth of the uneven pattern of the protective layer can be from about 0.5 μm to about 1.0 μm, the width of the uneven pattern of the protective layer can be from about 1.0 μm to about 2.0 μm, and the distance between the uneven patterns of the protective layer can be from about 1.0 μm to about 2.0 μm.

[0027] According to one or more embodiments, the protective layer may include a first protective layer and a second protective layer on the top surface of the first protective layer (e.g., disposed on the top surface of the first protective layer), wherein an uneven pattern of the protective layer is formed on the top surface of the first protective layer and the bottom surface of the second protective layer.

[0028] According to one or more embodiments, the thickness of each of the first and second recesses is formed to a depth less than the thickness of the protective layer, and the inclined surface of each of the first and second recesses is in the range of 20° to 70°. For example, the depth of each of the first and second recesses is less than the thickness of the protective layer, and the inclined surface of each of the first and second recesses has an inclined angle in the range of 20° to 70°.

[0029] According to one or more embodiments, the tilted portion of the first pixel electrode has the same tilt angle as the tilted surface of the first recess, and the tilted portion of the second pixel electrode has the same tilt angle as the tilted surface of the second recess. For example, the tilted portion of the first pixel electrode may have a tilt angle that is substantially the same metric (or measured value) as the tilt angle of the tilted surface of the first recess, and the tilted portion of the second pixel electrode may have a tilt angle that is substantially the same metric (or measured value) as the tilt angle of the tilted surface of the second recess.

[0030] According to one or more embodiments, the display device may further include: a thin-film encapsulation layer on a common electrode (e.g., disposed on a common electrode), the thin-film encapsulation layer including a first inorganic film layer, a second inorganic film layer and an organic film layer disposed between the first inorganic film layer and the second inorganic film layer; a color filter layer on the thin-film encapsulation layer; and an outer coating layer between the thin-film encapsulation layer and the color filter layer (e.g., disposed between the thin-film encapsulation layer and the color filter layer).

[0031] According to one or more embodiments, the color filter layer may include a first color filter overlapping a first light-emitting region and a second color filter overlapping a second light-emitting region, wherein the first color filter is one of a blue color filter that transmits blue light and a red color filter that transmits red light, and the second color filter is a green color filter that transmits green light.

[0032] According to one or more embodiments, an irregular pattern can be formed on the inclined portion of the second pixel electrode. This improves the lateral brightness ratio and viewing angle of the pixel and the display device including the pixel. For example, forming these irregular patterns on the inclined portion of the second pixel electrode helps to more effectively scatter light, thereby enhancing the lateral brightness ratio. This scattering effect helps to distribute light more evenly across the viewing angle, reducing the intensity drop that typically occurs at larger angles. Therefore, the viewing angle of the pixel and the display device is improved, providing a more consistent and high-quality image regardless of the observer's position.

[0033] However, the aspects, effects, and benefits of this disclosure are not limited to those described above, and one or more other aspects, effects, and benefits are included in this disclosure. Attached Figure Description

[0034] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to illustrate the principles of the present disclosure. The above and other aspects and features of the present disclosure will become more apparent and readily understood from the following description of exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0035] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure.

[0036] Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0037] Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure.

[0038] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments of the present disclosure.

[0039] Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 4 An example layout diagram of the display area.

[0040] Figure 6 It is an enlarged view of pixels according to one or more embodiments of the present disclosure.

[0041] Figure 7 This illustrates one or more embodiments according to this disclosure. Figure 6 A cross-sectional view of an example display panel cut by line I-I'.

[0042] Figure 8 It may be according to one or more embodiments of this disclosure.Figure 7 Enlarged view of the via layer and light-emitting element in the light-emitting area.

[0043] Figure 9 This illustrates one or more embodiments according to this disclosure. Figure 6 A cross-sectional view of an example display panel cut by line I-I'.

[0044] Figure 10 It may be according to one or more embodiments of this disclosure. Figure 9 Enlarged view of the via layer and light-emitting element in the light-emitting area.

[0045] Figure 11 This may be an enlarged view of the via layer and light-emitting element in the light-emitting region of one or more embodiments of this disclosure.

[0046] Figure 12 This is a graph showing the luminance ratio and luminance ratio deviation of the angle relative to the normal according to one or more embodiments of the present disclosure.

[0047] Figure 13 This is a cross-sectional view illustrating a display device comprising a light-emitting region emitting light of different wavelengths, according to one or more embodiments of the present disclosure.

[0048] Figure 14 This is a perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure.

[0049] Figure 15 This illustrates one or more embodiments according to the present disclosure. Figure 14 An exploded perspective view of the head-mounted display.

[0050] Figure 16 This is a perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure. Detailed Implementation

[0051] The aspects and features of embodiments of this disclosure, as well as methods of implementing them, can be more readily understood through the detailed description of the embodiments and the accompanying drawings. Hereinafter, aspects of one or more embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in one or more suitable and different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, for the sake of brevity, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art are not described.

[0052] Unless otherwise stated, throughout the drawings and written description, the same reference numerals, characters, and / or one or more combinations thereof (e.g., any suitable combination) refer to the same elements, and therefore, redundant descriptions of them will not be repeated. Furthermore, components unrelated to the description of one or more embodiments may be omitted to make the description clear and concise.

[0053] In the accompanying drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specifically stated otherwise, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or properties of the elements.

[0054] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of examples and / or intermediate structures. Thus, variations in the shapes illustrated will be expected, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to this disclosure. Therefore, the embodiments disclosed herein should not be construed as being limited to the specific shapes of the areas shown, but will include deviations in shape due to, for example, manufacturing processes.

[0055] For example, an injection region shown as rectangular may have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection region to a non-injection region. Similarly, a buried region formed by injection may result in some injection in the area between the buried region and the surface through which the injection is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of the device regions, and are therefore not intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in one or more suitable different ways without departing from the spirit and / or scope of this disclosure.

[0056] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of one or more suitable embodiments. However, it will be apparent that one or more other suitable embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known suitable structures and arrangements are shown in block diagram form to avoid unnecessarily obscuring the embodiments shown.

[0057] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and / or “above” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and another element (or feature) or feature (or feature). It will be understood that, in addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device in use or operation. For example, if the device is flipped (e.g., inverted) in the accompanying drawings, an element described as “below,” “below,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below,” “below,” and “below” may cover both above and below orientations (e.g., both above and below). In one or more embodiments, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, if the first component is described as being arranged "on" the second component (e.g., when the first component is described as being arranged "on" the second component), this indicates that the first component is arranged on the upper or lower side of the second component, and is not limited to the upper side of the second component based on the direction of gravity.

[0058] Furthermore, in this disclosure, the phrase "in a plane" or "in a plan view" refers to the target portion viewed from the top, and the phrase "in a cross section" refers to the cross section formed by vertically cutting the target portion viewed from the side.

[0059] It will be understood that if an element, layer, region, or component is referred to as "formed on," "on," "connected to," or "coupled to" another element, layer, region, or component (e.g., when an element, layer, region, or component is referred to as "formed on," "on," "connected to," or "coupled to"), then the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intermediary layers, regions, or components may exist between the element, layer, region, or component and the other element, layer, region, or component. For example, if a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component (e.g., when a layer, region, or component is referred to as "electrically connected" or "electrically coupled" to another layer, region, or component), then the layer, region, or component may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or one or more intermediary layers, regions, or components may exist between the element, layer, region, or component and the other element, layer, region, or component. However, "directly on / directly connected / directly coupled" means that one component is directly on or directly connected to another component without any intermediate components. In one or more embodiments, other expressions describing relationships between components, such as "between" and "immediately between," or "adjacent to" and "directly adjacent to," may be interpreted similarly. Additionally, it will be understood that if an element or layer is referred to as "between" two elements or layers (e.g., when an element or layer is referred to as "between" two elements or layers), then the element or layer may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0060] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, and “selected from…” modify the entire column of elements, but not individual elements within that column, when placed before / after a column of elements. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XYY, XZ, YZ, and ZZ) or any variations thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, when describing embodiments of this disclosure, the use of “may” means “one or more embodiments of this disclosure”.

[0061] It will be understood that although the terms “first,” “second,” and / or “third,” etc., may be used herein to describe one or more suitable elements, components, regions, layers, and / or segments, such elements, components, regions, layers, and / or segments should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or segment from another element, component, region, layer, or segment. Therefore, without departing from the spirit and scope of this disclosure, a first element, first component, first region, first layer, or first segment described herein may be designated as a second element, second component, second region, second layer, or second segment.

[0062] In the example embodiment, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be orthogonal to each other (e.g., perpendicular), or they can represent different directions that are not orthogonal to each other (e.g., perpendicular). The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are also intended to include the plural forms. It will be further understood that if the terms “comprise(s), comprising,” “have(has), having,” and “include(s) and including” are used in this disclosure (e.g., when the terms “comprise(s), comprising,” “have(has), having,” and “include(s) and including” are used in this disclosure), it indicates the presence of the stated feature, integer, number, step, operation, element, and / or component, but does not preclude the presence or addition of one or more other features, integers, numbers, steps, operations, elements, components, and / or groups thereof. Additionally, the terms “comprise(s) / comprising,” “include(s) / including,” “have / has / having,” or other similar terms include or support the terms “composed of” and “substantially composed of” that indicate the presence of the stated features, wholes, numbers, steps, operations, elements, and / or components without the absence or substantial absence of other features, wholes, numbers, steps, operations, elements, components, and / or groups thereof.

[0064] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to describe the inherent bias of a measured or calculated value that will be recognized by one of ordinary skill in the art. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), “approximately” or “approximately” as used herein includes the stated value and refers to a range of acceptable deviations from the stated value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0065] If one or more embodiments can be implemented differently (e.g., when one or more embodiments can be implemented differently), then a particular processing order can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0066] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges of the same numerical precision falling within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and inclusive), such as a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges included within the range expressly described herein.

[0067] The light-emitting elements, display devices / apparatus, electronic or electrical devices / apparatus, their manufacturing equipment, and / or any other related devices or components according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware (e.g., any suitable combination). For example, various components of these devices can be formed in an integrated circuit (IC) chip or in a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, tape-and-carrier package (TCP), printed circuit board (PCB), or formed on a substrate.

[0068] Furthermore, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions can also be stored in other non-transitory computer-readable media such as read-only optical disc storage (CD-ROM) and / or flash memory. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0069] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. For example, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and / or their meaning in this specification, and shall not be interpreted in an idealized or overly formalized sense.

[0070] Figure 1 This is an exploded perspective view showing a display device according to one or more embodiments of the present disclosure. Figure 2 This is a block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0071] refer to Figure 1 and Figure 2 The display device 10 according to one or more embodiments can be a device for displaying moving or still images. The display device 10 according to one or more embodiments can be applied to portable electronic devices, such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, in one or more embodiments, the display device 10 according to one or more embodiments can be applied as a display in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) device. In one or more embodiments, the display device 10 can be applied to a smartwatch, a smartwatch phone, or a head-mounted display (HMD) for implementing virtual reality and / or augmented reality.

[0072] The display device 10 according to one or more embodiments includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0073] In one or more embodiments, the display panel 100 may have a planar shape such as a rectangle. For example, the display panel 100 may have a rectangular planar shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a set or predetermined curvature, or may be formed at right angles. The planar shape of the display panel 100 is not limited to a rectangle, but may be formed as similar to other polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but the embodiments of this disclosure are not limited thereto.

[0074] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple light emission control lines EL, multiple data lines DL, a scan drive section 610, a light emission drive section 620, and a data drive section 700 (also referred to as a data driver). For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0075] Multiple pixels (PX) can be arranged in the display area (DAA). Multiple pixels (PX) can be arranged in a matrix on the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) can extend on the first direction (DR1) and be arranged on the second direction (DR2). Multiple data lines (DL) can extend on the second direction (DR2) and be arranged on the first direction (DR1).

[0076] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. The multiple emission control lines EL include multiple first emission control lines EL1 and multiple second emission control lines EL2.

[0077] Multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. For example, each pixel PX may include a set of sub-pixels SP1, SP2, and SP3. Each sub-pixel selected from the multiple sub-pixels SP1, SP2, and SP3 may include, for example: Figure 3 The plurality of pixel transistors shown herein can be formed by semiconductor processes and can be arranged on a substrate ( Figure 7 The pixel transistors are formed on a substrate (SUB). For example, in one or more embodiments, the plurality of pixel transistors may be formed of complementary metal-oxide-semiconductor (CMOS), but embodiments of this disclosure are not limited thereto.

[0078] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can be supplied with a data voltage from the data line DL according to the write scan signal of the write scan line GWL, and can emit light from the light-emitting element according to the data voltage.

[0079] The scanning drive section 610, the light emission drive section 620, and the data drive section 700 can be arranged in the non-display area NDA.

[0080] The scan driving section 610 includes multiple scan transistors, and the light-emitting driving section 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed using semiconductor processes and can be formed on a substrate (…). Figure 7 On a substrate (SUB). For example, in one or more embodiments, a plurality of scanning transistors and a plurality of light-emitting transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0081] The scan drive section 610 may include a write scan signal output section 611, a control scan signal output section 612, and a bias scan signal output section 613. Each of the write scan signal output section 611, the control scan signal output section 612, and the bias scan signal output section 613 may receive a scan timing control signal SCS from the timing control circuit 400 (also referred to as a timing controller). The write scan signal output section 611 may generate a write scan signal based on the scan timing control signal SCS from the timing control circuit 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output section 612 may generate a control scan signal based on the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output section 613 may generate a bias scan signal based on the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0082] The light-emitting driving section 620 may include a first light-emitting control driving section 621 and a second light-emitting control driving section 622. Each of the first light-emitting control driving section 621 and the second light-emitting control driving section 622 may receive a light-emitting timing control signal ECS from the timing control circuit 400. The first light-emitting control driving section 621 may generate a first light-emitting control signal according to the light-emitting timing control signal ECS and sequentially output the first light-emitting control signal to the first light-emitting control line EL1. The second light-emitting control driving section 622 may generate a second light-emitting control signal according to the light-emitting timing control signal ECS and sequentially output the second light-emitting control signal to the second light-emitting control line EL2.

[0083] The data driving section 700 may include multiple data transistors, and these multiple data transistors can be formed by semiconductor processes and can be formed on a substrate. Figure 7 (Substrate SUB in the image). For example, in one or more embodiments, multiple data transistors may be formed by CMOS, but embodiments of this disclosure are not limited thereto.

[0084] The data driving section 700 can receive digital video data DATA and data timing control signal DCS from the timing control circuit 400. The data driving section 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this regard, sub-pixels SP1, SP2, and / or SP3 are selected by the write scan signal of the scan driving section 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and / or SP3.

[0085] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on a side (e.g., one side) of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated in the display panel 100. The heat dissipation layer 200 may include graphite with high thermal conductivity and / or a metal layer formed of materials such as silver (Ag), copper (Cu), and / or aluminum (Al).

[0086] The circuit board 300 can be electrically connected to the first pad portion of the display panel 100 using a conductive adhesive material such as an anisotropic conductive film. Figure 4 The first pad portion of PDA1) has multiple first pads ( Figure 4 Multiple first pads PD1 in the circuit. In one or more embodiments, the circuit board 300 may be a flexible printed circuit board or a flexible film with a flexible material. Figure 1 In this design, circuit board 300 is shown unfolded, but in one or more embodiments, circuit board 300 may be bent. In these embodiments, one end of circuit board 300 may be disposed on the rear surface of display panel 100 and / or the rear surface of heat dissipation layer 200. The other end of circuit board 300 may be attached to a first pad portion of display panel 100 using a conductive adhesive material. Figure 4 The first pad portion of PDA1) has multiple first pads ( Figure 4 Multiple first pads PD1 in the circuit board 300. One end of the circuit board 300 may be opposite to the other end of the circuit board 300.

[0087] The timing control circuit 400 can receive digital video data and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan drive section 610 and output the light emission timing control signal ECS to the light emission drive section 620. The timing control circuit 400 can also output digital video data DATA and the data timing control signal DCS to the data drive section 700.

[0088] The power supply circuit 500 (also referred to as the power supply unit) can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, in one or more embodiments, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply these voltages to the display panel 100. Reference will be made later. Figure 3 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0089] The timing control circuit 400 and the power supply circuit 500 can each be formed as integrated circuits (ICs) and attached to one side of the circuit board 300. In this regard, the scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 via the circuit board 300. Additionally, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0090] In one or more embodiments, each of the timing control circuit 400 and the power supply circuit 500 may be arranged in the non-display area NDA of the display panel 100 in a manner similar to that of the scan driving section 610, the light-emitting driving section 620, and the data driving section 700. In these embodiments, the timing control circuit 400 may include a plurality of timing transistors, and the power supply circuit 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by semiconductor processes and may be formed on a substrate (…). Figure 7 On the substrate (SUB) in the data drive section. For example, in one or more embodiments, the multiple timing transistors and multiple power transistors may each be formed in CMOS, but embodiments of this disclosure are not limited thereto. In one or more embodiments, each of the timing control circuit 400 and the power supply circuit 500 may be arranged on the data drive section 700 and the first pad section (SUB). Figure 4 The first pad portion of PDA1 is between the two pads.

[0091] Figure 3 This is an equivalent circuit diagram of a first sub-pixel according to one or more embodiments of the present disclosure.

[0092] refer to Figure 3The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to the first driving voltage line VSL applied by the first driving voltage VSS corresponding to a low potential voltage, the second driving voltage line VDL applied by the second driving voltage VDD corresponding to a high potential voltage, and the third driving voltage line VIL applied by the third driving voltage VINT corresponding to the initialization voltage.

[0093] In one or more embodiments, the first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0094] The light-emitting element LE emits light according to the driving current flowing in the channel of the first transistor T1. The amount of light emitted by the light-emitting element LE (e.g., emission intensity) can be proportional to the driving current. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic light-emitting layer disposed between the first electrode and the second electrode; in these embodiments, the light-emitting element LE can be a miniature light-emitting diode.

[0095] The first transistor T1 may be a driving transistor that controls the source-drain current (Ids, also referred to herein as the “drive current”) flowing between the source and drain electrodes according to the voltage applied to its gate electrode.

[0096] The second transistor T2 can be positioned between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by the write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1.

[0097] The third transistor T3 can be arranged between the first node N1 and the second node N2. The third transistor T3 is turned on by the control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Therefore, if the gate electrode and drain electrode of the first transistor T1 are connected (e.g., when the gate electrode and drain electrode of the first transistor T1 are connected), the first transistor T1 can operate like a diode.

[0098] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first light-emitting control signal of the first light-emitting control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. A fifth transistor T5 can be arranged between the third node N3 and the third drive voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third drive voltage line VIL. Therefore, the third drive voltage VINT of the third drive voltage line VIL can be applied to the first electrode of the light-emitting element LE.

[0099] The sixth transistor T6 can be arranged between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second light emission control signal of the second light emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1.

[0100] A first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL.

[0101] Each of the first transistor T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, in one or more embodiments, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET, but embodiments of this disclosure are not limited thereto. In one or more embodiments, each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET. In one or more embodiments, some of the transistors selected from the first transistor T1 to the sixth transistor T6 may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0102] although Figure 3 The diagram shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors C1 and C2, but the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 The equivalent circuit diagram is shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0103] Additionally, the second sub-pixel SP2 (see...) Figure 2 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see Figure 2The equivalent circuit diagram of ) can be combined with ) respectively Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 are not described in this disclosure.

[0104] Figure 4 This is a layout diagram illustrating an example of a display panel according to one or more embodiments of the present disclosure.

[0105] refer to Figure 4 The display area DAA of the display panel 100 according to one or more embodiments includes a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to one or more embodiments includes a scan driving section 610, a light emission driving section 620, a data driving section 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0106] The scanning driving portion 610 may be arranged on a first side of the display area DAA, and the light-emitting driving portion 620 may be arranged on a second side of the display area DAA. For example, in one or more embodiments, the scanning driving portion 610 may be arranged on one side of the display area DAA in the first direction DR1, and the light-emitting driving portion 620 may be arranged on the other side of the display area DAA in the first direction DR1. However, embodiments of this disclosure are not limited to this; for example, the scanning driving portion 610 and the light-emitting driving portion 620 may be arranged on both sides of the first and second sides of the display area DAA (e.g., simultaneously arranged on the first and second sides of the display area DAA).

[0107] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps on the circuit board 300 by a conductive adhesive material. The first pad portion PDA1 may be arranged on a third side of the display area DAA. For example, in one or more embodiments, the first pad portion PDA1 may be arranged on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 may also be arranged on the outer side of the data driving portion 700 in the second direction DR2.

[0108] The second pad portion PDA2 may include multiple second pads PD2 corresponding to test pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to fixtures or probes during the inspection process, or they may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0109] The second pad portion PDA2 can be arranged on the fourth side of the display area DAA. For example, in one or more embodiments, the second pad portion PDA2 can be arranged on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can also be arranged on the outer side of the second distribution circuit 720 in the second direction DR2.

[0110] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, in one or more embodiments, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2.

[0111] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan drive portion 610, the light emission drive portion 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged opposite the first distribution circuit 710 on the other side of the display area DAA in the second direction DR2.

[0112] In the context of this disclosure, unless otherwise specified, "one side of the display area DAA in the second direction DR2" refers to a specific side of the display area DAA along the direction marked "DR2". For example, if "DR2" indicates the vertical direction, this could indicate the bottom side of the display area DAA. Conversely, "the other side of the display area DAA in the second direction DR2" refers to the opposite side of the display area DAA along the same second direction DR2, continuing the previous example, this could indicate the top side of the display area DAA. These phrases are used to describe the positioning of components (such as distribution circuitry) on opposite sides of the display area DAA along a specific second direction DR2.

[0113] The cathode connection portion CCA can be the light-emitting element layer ( Figure 7 The second electrode of the light-emitting element layer (EMTL) in the middle Figure 7The common electrode CM in the display area (NDA) is connected to the area where the first driving voltage line VSL is located. The cathode connection portion CCA can be arranged on at least one side of the display area (DAA). For example, in one or more embodiments, the cathode connection portion CCA can be arranged on at least one of the left, right, top, and bottom sides of the display area (DAA). In one or more embodiments, as... Figure 4 As shown, the cathode connection portion CCA can be arranged around the display area DAA (e.g., around the display area DAA) to minimize or reduce the deviation of the first drive voltage VSS caused by the IR drop or IR rise of the second electrode in the display area DAA.

[0114] Figure 5 This illustrates one or more embodiments according to the present disclosure. Figure 4 An example layout diagram of the display area.

[0115] like Figure 5 As shown, multiple pixels PX (see Figure 2 Each of the light-emitting areas includes a first light-emitting area EA1 as the light-emitting area of ​​the first sub-pixel SP1, a second light-emitting area EA2 as the light-emitting area of ​​the second sub-pixel SP2, and a third light-emitting area EA3 as the light-emitting area of ​​the third sub-pixel SP3. Additionally, each of the light-emitting areas may include a contact hole CT3, which will be discussed later.

[0116] In one or more embodiments, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may each have the following characteristics: Figure 5 The rectangular planar shape shown is not limited to the embodiments disclosed herein. The first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 may have other polygonal, circular, or elliptical planar shapes besides rectangular shapes.

[0117] like Figure 5 As shown, in one or more embodiments, the first light-emitting region EA1 and the second light-emitting region EA2 in each of the plurality of pixels PX can be adjacent in the first direction DR1. Furthermore, the first light-emitting region EA1 and the third light-emitting region EA3 can be adjacent in the first direction DR1. Additionally, the second light-emitting region EA2 and the third light-emitting region EA3 can be adjacent in the second direction DR2. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 can be different.

[0118] The first sub-pixel SP1 can emit a first light, the second sub-pixel SP2 can emit a second light, and the third sub-pixel SP3 can emit a third light. Here, the first light can be light in the blue band, the second light can be light in the green band, and the third light can be light in the red band. For example, the blue band can refer to the band where the main peak wavelength of the light is between approximately 370 nanometers (nm) and 460 nm, the green band can refer to the band where the main peak wavelength of the light is between approximately 480 nm and 560 nm, and the red band can refer to the band where the main peak wavelength of the light is between approximately 600 nm and 750 nm.

[0119] like Figure 5 As shown, each of the plurality of pixels PX may include three light-emitting areas EA1, EA2, and EA3, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the plurality of pixels PX may include four light-emitting areas.

[0120] In one or more embodiments, the light-emitting areas of a plurality of pixels PX can be arranged in a stripe structure in a first direction DR1, wherein light-emitting areas EA1, EA2, EA3 and a fourth light-emitting area are arranged in a rhombus (diamond) shape. The structure or the hexagonal structure in which the light-emitting area is arranged in a hexagonal shape. It is an officially registered trademark of Samsung Display Co., Ltd.

[0121] According to one or more embodiments, the first sub-pixel SP1 may have a larger area than other sub-pixels. For example, the pixel electrode PE of the first sub-pixel SP1 may have a larger area than the pixel electrode PE of the second sub-pixel SP2 or the pixel electrode PE of the third sub-pixel SP3. The pixel electrode PE will be described in more detail later.

[0122] According to one or more embodiments, the first sub-pixel SP1 may have a larger light-emitting area EA than other pixels. For example, the light-emitting area EA of the first sub-pixel SP1 may have a larger area than the light-emitting area EA of the second sub-pixel SP2 or the light-emitting area EA of the third sub-pixel SP3. In this respect, the first sub-pixel SP1 may have a greater number of light-emitting areas EA than other sub-pixels. For example, in one or more embodiments, the first sub-pixel SP1 may include two light-emitting areas EA, and the second sub-pixel SP2 and the third sub-pixel SP3 may each include one light-emitting area EA.

[0123] According to one or more embodiments, in a planar view, the pixel electrode PE and the light-emitting area EA of each sub-pixel SP1, SP2, and SP3 can each have a circular shape. However, the shapes of the pixel electrode PE and the light-emitting area EA are not limited to this, and can have one or more suitable shapes.

[0124] According to one or more embodiments, the light-emitting area EA of each sub-pixel SP1, SP2, and SP3 may include a rough pattern, such as an uneven pattern. The uneven pattern is formed concentrically in the light-emitting area EA, thereby minimizing or reducing the impact on the display device 10 (see [link]). Figure 1 The uneven pattern reduces color difference (or color deviation) of the display device at different viewing angles, thus improving the image quality of the display device 10. The uneven pattern will be specifically described below with reference to the accompanying drawings, and a more detailed description will be provided later.

[0125] Figure 6 It is an enlarged view of pixels according to one or more embodiments of the present disclosure. Figure 7 This illustrates one or more embodiments according to this disclosure. Figure 6 A cross-sectional view of an example display panel cut by line I-I'. For example, Figure 6 The pixels in can be made of Figure 5 The attached figure shows a magnified view of a portion of a subpixel indicated by reference EA3 (SP3). Figure 8 It may be according to one or more embodiments of this disclosure. Figure 7 Enlarged view of the via layer and light-emitting element in the light-emitting area.

[0126] like Figure 7 As shown, one or more embodiments of the display device 10 (see Figure 1 It may include a substrate SUB, a transistor layer TRL, a light-emitting element layer EMTL, and a packaging layer ENC. The light-blocking layer BML, buffer layers BF1 and BF2, transistor layer TRL, light-emitting element layer EMTL, and packaging layer ENC may be arranged on the substrate SUB.

[0127] The substrate SUB can be a rigid substrate SUB or a flexible substrate SUB that can be bent, folded, or rolled up. The substrate SUB can be made of an insulating material such as glass, quartz, or a polymeric material (e.g., a polymeric resin). Non-limiting examples of polymeric materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfonate, polypropylene sulfonate, polyphenylene sulfide, polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and / or one or more combinations thereof (e.g., any suitable combination). In one or more embodiments, the substrate SUB may include a metallic material.

[0128] The first buffer layer BF1 can be disposed on the substrate SUB. The first buffer layer BF1 can be a film used to protect the transistor layer TRL and the light-emitting layer EML of the light-emitting element layer EMTL from moisture penetrating the moisture-sensitive substrate SUB. The first buffer layer BF1 can be formed from a plurality of inorganic films stacked alternately. For example, in one or more embodiments, the first buffer layer BF1 can be formed as a multilayer of alternatingly stacked inorganic films selected from silicon nitride films, silicon oxynitride films, silicon oxide films, titanium oxide films, and aluminum oxide films.

[0129] A photoblocking layer BML can be disposed on the first buffer layer BF1. The photoblocking layer BML can be disposed on the substrate SUB to overlap with the active layer ACT, which will be described in more detail later. For example, the photoblocking layer BML can be formed from a metallic material such as chromium (Cr) and / or molybdenum (Mo), or from black ink or black dye. In one or more embodiments, if the photoblocking layer BML is made of a metallic material (e.g., when the photoblocking layer BML is made of a metallic material), the photoblocking layer BML can be supplied with electrostatic charge (e.g., a constant voltage). In this way, the photoblocking layer BML is not electrically floating, and the transistor TR on the photoblocking layer BML can stabilize its electrical characteristics. For example, performance degradation of oxide-based transistors can be minimized or reduced. For example, oxide semiconductors are sensitive to light, and current magnitudes, etc., may fluctuate due to external light. In contrast, the photoblocking layer BML can be used as the relative gate electrode of the transistor TR. The photoblocking layer BML can be connected to the gate electrode GE of the transistor TR, which will be described in more detail later. Therefore, the relative gate electrode and the gate electrode GE of the transistor TR can be connected to each other.

[0130] The second buffer layer BF2 can be disposed on the light-blocking layer BML. The second buffer layer BF2 can be made of the same material as the first buffer layer BF1.

[0131] The active layer ACT can be disposed on the second buffer layer BF2. For example, the active layer ACT can be disposed on the second buffer layer BF2 to overlap with the light-blocking layer BML. The active layer ACT can be, for example, an oxide semiconductor. For example, in one or more embodiments, the active layer ACT can be a semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO). In one or more embodiments, the active layer ACT can be, for example, monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

[0132] The gate insulating layer GI can be disposed on the active layer ACT. For example, the gate insulating layer GI can be disposed to overlap with the channel region CH of the active layer ACT. The gate insulating layer GI may include tetraethoxysilane (tetraethyl orthosilicate, TEOS), silicon nitride (SiN), etc. xAt least one of silicon nitride (SiO2) and silicon oxide (SiO2). For example, in one or more embodiments, the gate insulating layer GI may have a bilayer structure in which a silicon nitride film having a thickness of 40 nanometers (nm) and a tetraethoxysilane film having a thickness of 80 nm are sequentially stacked.

[0133] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be disposed on the gate insulating layer GI to overlap with the channel region CH of the active layer ACT. The gate electrode GE may be made of aluminum (Al) and / or titanium (Ti). In one or more embodiments, the gate electrode GE may have a two-layer or three-layer structure in which aluminum (Al) layers and titanium (Ti) layers are stacked.

[0134] The first interlayer insulating layer ITL1 may be disposed on the gate electrode GE. The first interlayer insulating layer ITL1 may be disposed on the entire surface of the substrate SUB, including the gate electrode GE. The first interlayer insulating layer ITL1 may include an inorganic film, such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film. In one or more embodiments, the first interlayer insulating layer ITL1 may include multiple inorganic films.

[0135] The capacitor electrode CPE can be disposed on the first interlayer insulating layer ITL1. For example, the capacitor electrode CPE can be disposed on the first interlayer insulating layer ITL1 to overlap with the gate electrode GE. A capacitor can be formed in the region where the capacitor electrode CPE and the gate electrode GE overlap.

[0136] The second interlayer insulating layer ITL2 can be disposed on the capacitor electrode CPE. The second interlayer insulating layer ITL2 can be disposed on the entire surface of the capacitor electrode CPE, including the substrate SUB. The second interlayer insulating layer ITL2 can be made of the same material as the first interlayer insulating layer ITL1 described above.

[0137] The source connection electrode SCE and the drain connection electrode DCE can be disposed on the second interlayer insulating layer ITL2. The source connection electrode SCE can be connected to the source electrode SE of the active layer ACT through a first contact hole CT1 that penetrates the second interlayer insulating layer ITL2, the first interlayer insulating layer, and the gate insulating layer GI. The drain connection electrode DCE can be connected to the drain electrode DE of the active layer ACT through a second contact hole CT2 that penetrates the second interlayer insulating layer ITL2, the first interlayer insulating layer ITL1, and the gate insulating layer GI.

[0138] The first protective layer VA1 can be disposed on the source connection electrode SCE and the drain connection electrode DCE. For example, the first protective layer VA1 can be disposed on the entire surface of the substrate including the source connection electrode SCE and the drain connection electrode DCE. The first protective layer VA1 can be made of the same material as the first interlayer insulating layer ITL1.

[0139] The first protective layer VA1 may include an uneven pattern PVP formed in the area overlapping the light-emitting region EA in the thickness direction (third direction DR3). Reference Figure 6 The uneven pattern PVP can have the shape of closed curves with the same center on a plane. For example, in one or more embodiments, the uneven pattern PVP can have a concentric circle shape on a plane. In this disclosure, "on a plane" is defined based on a plane parallel to the plane defined by the first direction DR1 and the second direction DR2. In this disclosure, "in section" is defined as the state viewed from the first direction DR1 or the second direction DR2. In the context of this disclosure, unless otherwise specified, "on a plane" or "in a plan view" can refer to the orthographic projection of a three-dimensional object from a position on a horizontal plane intersecting the object. That is, it is a top view showing the layout and spatial relationships of various elements within the object or structure. "On a plane" or "in a plan view" based on a third direction DR3 (e.g., the thickness direction) refers to a top view of the object, as if viewing the surface directly from above. In this context, the third direction DR3 is perpendicular to or orthogonal to the plane defined by the first direction DR1 and the second direction DR2.

[0140] The uneven pattern PVP can be an engraved pattern and can have side surfaces that are vertical or inclined toward the front or rear surface of the first protective layer VA1.

[0141] refer to Figure 6 and Figure 7 In one or more embodiments, the depth h1 of the non-flat pattern PVP (see...) Figure 8 The width w1 of the uneven pattern can be from about 0.5 μm to about 1.0 μm. The width w1 of the uneven pattern can be from about 1.0 μm to about 2.0 μm, and the spacing w2 of the uneven pattern can be formed to be from about 1.0 μm to about 2.0 μm. The width w1 and the spacing w2 of the uneven pattern PVP can be the same, but the embodiments of this disclosure are not limited thereto.

[0142] The second protective layer VA2 can be disposed on the first protective layer VA1, which includes the uneven pattern PVP. For example, the second protective layer VA2 can be disposed on the front surface of the substrate SUB. For example, the second protective layer VA2 can be disposed on the front surface of the first protective layer VA1. The second protective layer VA2 can be made of the same material as the first interlayer insulation layer ITL1. The second protective layer VA2 can define a recess VA-R (see...). Figure 8 The recess VA-R can overlap with the light-emitting area EA. The upper opening OP of the recess VA-R (see...) Figure 8 It can be smaller than the light-emitting area EA defined by the pixel-limiting layer PDL.

[0143] The depth of the recess VA-R can be less than the thickness of the second protective layer VA2.

[0144] The bottom surface of the second protective layer VA2 is formed with an uneven pattern based on the uneven pattern PVP of the first protective layer VA1. The uneven pattern of the second protective layer VA2 may have a shape (e.g., pattern) similar to the uneven pattern PVP of the first protective layer VA1.

[0145] On the second protective layer VA2, an EMTL layer comprising an ED light-emitting element and a PDL pixel-defining layer can be arranged.

[0146] A light-emitting element (ED) may include a pixel electrode (PE), a light-emitting layer (EML), and a common electrode (CM). The light-emitting region (EA) represents the region where the pixel electrode (PE), the light-emitting layer (EML), and the common electrode (CM) are sequentially stacked, and holes from the pixel electrode (PE) and electrons from the common electrode (CM) recombine with each other in the light-emitting layer (EML) to emit light. In this case, the pixel electrode (PE) may be the anode electrode of the ED, and the common electrode (CM) may be the cathode electrode of the ED. In one or more embodiments, the pixel electrode (PE) may also be referred to as the first electrode of the ED, and the common electrode (CM) may also be referred to as the second electrode of the ED.

[0147] The pixel electrode PE can be connected to the source electrode SCE through the third contact hole CT3, which penetrates the first protective layer VA1 and the second protective layer VA2. The pixel electrode PE can be connected to the source electrode SE of the active layer ACT through the source electrode SCE.

[0148] refer to Figure 8The pixel electrode PE can be arranged to overlap with the recess VA-R defined by the second protective layer VA2. The pixel electrode PE is arranged along the inclined surface SSL1 of the recess VA-R. Therefore, the pixel electrode PE can have an inclined structure. The pixel electrode PE may include an inclined portion PE-S disposed on the inclined surface SSL1 of the recess VA-R, a bottom portion PE-B connected to the bottom portion of the inclined portion PE-S, and a top portion PE-T connected to the top portion of the inclined portion PE-S and disposed on the top portion of the second protective layer VA2. The tilt angle of the inclined portion PE-S of the pixel electrode PE can be the same as the tilt angle θ of the inclined surface SSL1 of the recess VA-R. For example, the tilt angle θ of the recess VA-R can be from 20 degrees to 70 degrees. As the tilt angle θ increases, the viewing angle can become narrower, and as the tilt angle θ decreases, the brightness can be improved. The pixel electrode PE can have a concave shape. The inclined portion PE-S surrounds the bottom portion PE-B, and the inclined portion PE-S and the bottom portion PE-B do not overlap vertically. The bottom portion PE-B and the top portion PE-T can be considered substantially flat (e.g., relatively flat), but may be formed to have curvature during the process. Even if the bottom portion PE-B and the top portion PE-T have curvature during the process (e.g., when the bottom portion PE-B and the top portion PE-T have curvature during the process), the bottom portion PE-B and the top portion PE-T can still be formed to be relatively flat compared to the sloping portion PE-S.

[0149] The pixel electrode PE has an uneven pattern PVP-P formed in the light-emitting region EA according to the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2. For example, the uneven pattern PVP-P derived from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 is formed in the inclined portion PE-S and the bottom portion PE-B of the pixel electrode PE. Therefore, the uneven pattern PVP-P derived from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 in the inclined portion PE-S and the bottom portion PE-B can have a shape substantially similar to the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2, or at least a portion of the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2. In the case of the uneven pattern PVP-P of the inclined portion PE-S, although it originates from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2, the inclined portion PE-S may have a shape that is partially different from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 due to the inclination.

[0150] Due to the uneven pattern PVP-P of the inclined portion PE-S and the bottom portion PE-B of the pixel electrode PE, light emitted from the emissive layer EML (e.g., organic emissive layer EML) can be effectively reflected. In particular, because light emitted laterally from the organic emissive layer EML is effectively reflected, the luminance ratio LvA (see [reference]) based on the angle relative to the normal (e.g., the normal direction) is [higher / low ... Figure 12 It can be increased, and based on the brightness ratio deviation dLvA relative to the normal (see...). Figure 12 It can be reduced.

[0151] In a top-emitting structure that emits light in the direction of the common electrode CM based on an organic light-emitting layer (EML), in one or more embodiments, the pixel electrode PE is formed as a monolayer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), aluminum and titanium (Ti / Al / Ti), aluminum and ITO (ITO / Al / ITO), an APC alloy, or an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0152] A pixel defining layer (PDL) is used to define the light-emitting region EA of pixel PX. For this purpose, the pixel defining layer (PDL) may be disposed on the top flat surface of the second protective layer VA2 to expose a portion of the pixel electrode PE. The pixel defining layer (PDL) may cover at least a portion of the top portion PE-T of the pixel electrode PE. The pixel defining layer (PDL) does not cover the inclined portion PE-S of the pixel electrode PE. For example, the pixel defining layer (PDL) may not overlap with the inclined portion PE-S of the pixel electrode PE. The pixel defining layer (PDL) may be formed of an organic film comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin. In one or more embodiments, spacers may be disposed on the pixel defining layer (PDL). The spacers may be used to support the mask during the process of fabricating the organic light-emitting layer (EML). The spacers may be formed of an organic film comprising, for example, acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin. In one or more embodiments, the pixel defining layer (PDL) may include a light-absorbing material to prevent or reduce light reflection. For example, the pixel defining layer (PDL) may include a polyimide (PI) binder and pigments as a mixture of red, green, and blue pigments. In one or more embodiments, the pixel defining layer (PDL) may include a Cardo-type binder resin and a mixture of lactam black and blue pigments (e.g., any suitable mixture). In one or more embodiments, the pixel defining layer (PDL) may include carbon black.

[0153] An organic light-emitting layer (EML) can be formed on a pixel electrode (PE). The EML can include organic materials and can emit light with a set or predetermined color. For example, in one or more embodiments, the EML can include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer can include a host and dopants. The organic material layer can include materials that emit set or predetermined light and can be formed using phosphorescent or fluorescent materials.

[0154] For example, the organic material layer of the emissive layer EML that emits light of a first color (e.g., blue) may include a phosphorescent material comprising a host material containing CBP or mCP and a substrate containing (4,6-F2ppy)2Irpic (bis[2-(4,6-difluorophenyl)pyridino-C... 2 The doped materials are [N](pyridyl)iridium(III) or L2BD111, but the embodiments of this disclosure are not limited thereto.

[0155] The organic material layer of the emissive layer EML emitting a second color (e.g., green) may include a host material comprising CBP or mCP and a phosphorescent material comprising a dopant material (including Ir(ppy)3 (planar tris(2-phenylpyridine)iridium)). In one or more embodiments, the organic material layer of the emissive layer EML emitting a second color may include a fluorescent material comprising Alq3 (tris(8-hydroxyquinoline)aluminum), but embodiments of this disclosure are not limited thereto.

[0156] The organic material layer of the emissive layer EML emitting a third color (e.g., red) includes a host material and a phosphorescent material. The host material includes carbazole biphenyl (CBP) or mCP (1,3-bis(carbazole-9-yl)), and the phosphorescent material includes at least one selected from PIQIr(acac) (bis(1-phenylisoquinoline)acetylacetone iridium), PQIr(acac) (bis(1-phenylquinoline)acetylacetone iridium), PQIr (tris(1-phenylquinoline)iridium), and PtOEP (octaethylporphyrin platinum). In one or more embodiments, the organic material layer of the emissive layer EML emitting a third color may include a fluorescent material, such as PBD:Eu(DBM)3(Phen) or perylene, but the embodiments of this disclosure are not limited thereto.

[0157] In one or more embodiments, the organic light-emitting layer (EML) of the light-emitting element (ED) can be formed as a single common layer integrally disposed on different pixel electrodes (PE) and pixel defining layers (PDL), and the light-emitting layers (EML) disposed on different pixel electrodes (PE) can emit light of the same color. In these embodiments, the display device 10 may further include a color adjustment layer disposed on the light-emitting element (ED) (e.g., a color conversion layer including a wavelength conversion pattern and / or a color adjustment layer including a color filter).

[0158] A common electrode CM can be disposed on the organic light-emitting layer (EML) of each of the light-emitting elements (EDs). In one or more embodiments, the common electrode CM can be formed as a single common layer disposed across the entire surface of the display area (DAA), and the light-emitting elements (EDs) of the pixels can share a common electrode CM. The common electrode CM can receive a common voltage (e.g., a second pixel voltage or a cathode voltage).

[0159] The encapsulation layer ENC can be disposed on the common electrode CM and cover the light-emitting element ED. In one or more embodiments, the encapsulation layer ENC may include at least one inorganic film to prevent or reduce the penetration of oxygen and / or moisture into the light-emitting element layer EMTL and at least one organic film to protect the light-emitting element layer EMTL from debris such as dust.

[0160] In one or more embodiments, the encapsulation layer ENC may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 sequentially disposed on the light-emitting element ED. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may each be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0161] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may each comprise an inorganic insulating material. For example, each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may comprise aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, and / or other inorganic insulating materials.

[0162] The second encapsulation layer TFE2 may include an organic insulating material. For example, the second encapsulation layer TFE2 may include a polymeric organic insulating material, such as acrylic resin, epoxy resin, polyimide, polyethylene, and / or any other organic insulating material. The second encapsulation layer TFE2 may be formed by curing monomers or by applying polymers.

[0163] In one or more embodiments, the touch sensor layer and / or color filter layer may be included on the encapsulation layer ENC.

[0164] The touch sensing layer may include a conductive pattern containing touch electrodes. The conductive pattern can sense patterns used to detect touch input. For example, the conductive pattern of the touch sensing layer can be used to detect changes in electrical characteristics (e.g., changes in electrostatic capacitance) in response to touch input and thus detect the touch input.

[0165] The color filter layer can be disposed on the light-emitting element layer EMTL. In one or more embodiments, the color filter layer can be disposed on the touch sensing layer and can cover the light-emitting element layer EMTL, the encapsulation layer ENC, and the touch sensing layer.

[0166] The color filter layer may include a light-blocking layer, a color filter, and at least one outer coating.

[0167] Color filters can include colorants such as dyes or pigments that absorb light in wavelengths other than a specific wavelength.

[0168] The outer coating can be light-transmitting. The outer coating can be applied throughout the entire display area DAA arrangement to flatten the steps caused by the color filter and light-blocking layer and protect the display panel 100.

[0169] Figure 9 This illustrates one or more embodiments according to this disclosure. Figure 6 A cross-sectional view of an example display panel cut by I-I'. Figure 10 It may be according to one or more embodiments of this disclosure. Figure 9 Enlarged view of the via layer and light-emitting element in the light-emitting area.

[0170] Figure 9 and Figure 10 Implementation examples and Figure 7 and Figure 8 The difference in the embodiment is that the uneven pattern PVP of the first protective layer VA1, the uneven pattern of the second protective layer VA2, and the uneven pattern PVP-P of the pixel electrode PE are formed in a concave-convex form. Figure 9 and Figure 10 In one or more embodiments, for the sake of simplicity, no [details related to...] will be provided. Figure 11 and Figure 11 Any description repeated in the embodiments.

[0171] refer to Figure 8 and Figure 11 The uneven pattern PVP of the first protective layer VA1 is formed in the light-emitting area EA in a concave-convex form, and also forms a concave-convex uneven pattern in the second protective layer VA2 arranged on the first protective layer VA1 along the uneven pattern PVP of the first protective layer VA1.

[0172] The uneven pattern PVP-P derived from the uneven pattern of the second protective layer VA2 can also be formed in the pixel electrode PE arranged on the second protective layer VA2.

[0173] Figure 8 This is an enlarged view of the via layer and light-emitting element in the light-emitting region of one or more embodiments of this disclosure.

[0174] Figure 11 Implementation examples and Figure 12 The difference between one or more embodiments is that the uneven pattern PVP of the first protective layer VA1, the uneven pattern of the second protective layer VA2, and the uneven pattern PVP-P of the pixel electrode PE are formed only in a portion of the light-emitting region EA. Figure 12 In one or more embodiments, for the sake of simplicity, no [details related to...] will be provided. Figure 5 to Figure 8 The embodiments are described repeatedly.

[0175] refer to Figure 12 The uneven pattern PVP is formed only in the region that overlaps with the inclined surface SSL1 of the second protective layer VA2 in the thickness direction. Therefore, the uneven pattern of the second protective layer VA2 is formed on the inclined portion PE-S of the pixel electrode PE disposed on the inclined surface SSL1 of the second protective layer VA2. In contrast, the uneven pattern PVP is not formed on the bottom surface of the recess VA-R of the second protective layer VA2. Therefore, the uneven pattern PVP-P may not be formed on the bottom portion PE-B of the pixel electrode PE disposed on the bottom surface of the recess VA-R.

[0176] Therefore, since the light emitted laterally from the organic light-emitting layer EML is effectively reflected, the brightness (lightness) ratio LvA relative to the normal can be increased, and the brightness (lightness) ratio deviation dLvA can be decreased.

[0177] Figure 13 This is a graph illustrating the luminance ratio and luminance ratio deviation relative to the normal according to one or more embodiments of the present disclosure.

[0178] Figure 13 It shows the reference Figure 5 to Figure 8 The luminance ratio LvA and luminance ratio deviation dLvA of the display device according to one or more embodiments described.

[0179] The display device in which the pixel electrode PE does not have a raised pattern is referenced in REF, and case 1, in which the width of the raised portion of the uneven pattern of the pixel electrode PE and the distance between the raised portions of the uneven pattern of the pixel electrode PE are 1.2 μm and 1.2 μm respectively, is compared with case 2, in which the width of the raised portion of the uneven pattern of the pixel electrode PE and the distance between the raised portions of the uneven pattern of the pixel electrode PE are 1.4 μm and 1.4 μm respectively.

[0180] refer to Figure 13 With reference to REF, the luminance ratio LvA (i.e., LvA@45°) based on the angle relative to the normal (45 degrees) is 37.82%, and the luminance ratio deviation dLvA based on the angle relative to the normal (45 degrees) is 2.49%. For the sake of brevity, the luminance ratio deviation dLvA based on the angle relative to the normal (45 degrees) is also referred to as the luminance ratio deviation dLvA in this document.

[0181] In case 1, the luminance ratio LvA based on the angle (45 degrees) relative to the normal is 47.56%, and the luminance ratio deviation dLvA is 1.93%.

[0182] In case 2, the luminance ratio LvA based on the angle (45 degrees) relative to the normal is 71.44%, and the luminance ratio deviation dLvA is 1.55%.

[0183] In this way, compared with a reference REF in which the pixel electrode PE does not have an uneven pattern, according to embodiments 1 and 2 in which the pixel electrode PE has an uneven pattern, the brightness is higher than LvA based on the angle, and the brightness is lower than the deviation dLvA.

[0184] Figure 13 This is a cross-sectional view illustrating a display device comprising a light-emitting region emitting light of different wavelengths, according to one or more embodiments of the present disclosure. Figure 5 to Figure 8 Cross sections of the second light-emitting region EA2 and the third light-emitting region EA3 according to one or more embodiments are shown.

[0185] Apart from Figure 5 to Figure 8 In addition, we will also refer to Figure 8 To describe the cross-sectional structure of the display device 10.

[0186] refer to Figure 13 The second light-emitting region EA2 and the third light-emitting region EA3 can emit light of different wavelengths. For example, the second light-emitting region EA2 and the third light-emitting region EA3 can emit red light and green light, or green light and red light, or blue light and green light, or green light and blue light, respectively. However, the embodiments disclosed herein are not limited thereto.

[0187] The second light-emitting area EA2 may include the second light-emitting element ED2, and the third light-emitting area EA3 may include the third light-emitting element ED3.

[0188] Light-emitting elements included in different light-emitting regions can have different structures. For example, as shown in the reference... Figure 12 As described, in one or more embodiments, the third light-emitting region EA3 may include a third pixel electrode PE3 having a non-flat pattern PVP-P.

[0189] The second light-emitting element ED2 may include a second pixel electrode PE2, a second pixel light-emitting layer (or a second organic light-emitting layer) EML2, and a common electrode CM2.

[0190] The second pixel electrode PE2 can be arranged to overlap with one of the recesses VA-R defined by the second protective layer VA2. The second pixel electrode PE2 is arranged along the inclined surface SSL1 of the second protective layer VA2. Therefore, the second pixel electrode PE2 can have an inclined structure. The second pixel electrode PE2 may include an inclined portion disposed on the inclined surface SSL1 of the recess VA-R of the second protective layer VA2, a bottom portion connected to the bottom portion of the inclined portion, and a top portion connected to the top portion of the inclined portion and disposed on the top portion of the second protective layer VA2. The tilt angle of the inclined portion of the second pixel electrode PE2 can be equal to the tilt angle of the inclined surface SSL1 of the second protective layer VA2. For example, in one or more embodiments, the tilt angle of the inclined portion can be from 20 degrees to 70 degrees. The larger the tilt angle, the narrower the viewing angle, and the smaller the tilt angle, the better the brightness. The second pixel electrode PE2 can have a concave shape.

[0191] The second pixel emitting layer EML2 can be disposed on the second pixel electrode PE2. Because the second pixel emitting layer EML2 is formed along the second pixel electrode PE2, the second pixel emitting layer EML2 can have an inclined structure.

[0192] The second pixel light-emitting layer EML2 can be an organic light-emitting layer made of organic materials. When the second pixel light-emitting layer EML2 corresponds to the organic light-emitting layer, if the thin-film transistor applies a set or predetermined voltage to the second pixel electrode PE2 of the second light-emitting element ED2 and the common electrode CE2 of the second light-emitting element ED2 receives the common voltage or the cathode voltage (for example, when the thin-film transistor applies a set or predetermined voltage to the second pixel electrode PE2 of the second light-emitting element ED2 and the common electrode CE2 of the second light-emitting element ED2 receives the common voltage or the cathode voltage), light can be emitted from the second pixel light-emitting layer EML2.

[0193] The common electrode CE2 can be arranged in the second light-emitting area EA2 on the second pixel light-emitting layer EML2, and can also be arranged on the pixel limiting layer PDL.

[0194] The third light-emitting element ED3 may include a third pixel electrode PE3, a third light-emitting layer (or a third organic light-emitting layer) EML3, and a common electrode CE3.

[0195] The third light-emitting area EA3 may include the third light-emitting element ED3.

[0196] Light-emitting elements included in different light-emitting regions can have different structures. For example, as shown in the reference... Figure 12 As described, the third pixel electrode PE3 of the third light-emitting region EA3 may include an uneven pattern PVP-P.

[0197] In the third luminescent region EA3, the first protective layer VA1 may include an uneven pattern PVP formed in the region overlapping with the luminescent region EA3 in the thickness direction (third direction DR3). The depth h1 of the uneven pattern PVP may be from approximately 0.5 μm to approximately 1.0 μm. The width w1 of the uneven pattern may be from approximately 1.0 μm to approximately 2.0 μm, and the spacing w2 of the uneven pattern may be formed from approximately 1.0 μm to approximately 2.0 μm. In one or more embodiments, the width w1 and the spacing w2 of the uneven pattern PVP may be the same, but the embodiments disclosed herein are not limited thereto.

[0198] A second protective layer VA2 can be disposed on a first protective layer VA1, which includes an uneven pattern PVP. For example, the second protective layer VA2 can be disposed on the front surface of a substrate SUB. The second protective layer VA2 can be made of the same material as the first interlayer insulating layer ITL1. The second protective layer VA2 can define a recess VA-R. The recess VA-R can overlap with the light-emitting area. The upper opening OP of the recess VA-R can be smaller than the light-emitting area defined by the pixel defining layer PDL.

[0199] The depth of the recess VA-R can be less than the thickness of the second protective layer VA2.

[0200] The bottom surface of the second protective layer VA2 has an uneven pattern formed based on the uneven pattern PVP of the first protective layer VA1. The uneven pattern of the second protective layer VA2 can have a shape similar to the uneven pattern PVP of the first protective layer VA1.

[0201] On the second protective layer VA2, an EMTL layer comprising an ED light-emitting element and a PDL pixel-defining layer can be arranged.

[0202] In one or more embodiments, the third light-emitting element ED3 may include a third pixel electrode PE3, a third organic light-emitting layer EML3, and a common electrode CM3. The light-emitting region EA3 represents the region where the third pixel electrode PE3, the third organic light-emitting layer EML3, and the common electrode CM3 are sequentially stacked, and holes from the third pixel electrode PE3 and electrons from the common electrode CM3 recombine with each other in the third organic light-emitting layer EML3 to emit light. In these embodiments, the third pixel electrode PE3 may be the anode electrode of the third light-emitting element ED3, and the common electrode CM3 may be the cathode electrode of the light-emitting element ED3.

[0203] The third pixel electrode PE3 can be arranged to overlap with the recess VA-R defined by the second protective layer VA-R. The third pixel electrode PE3 is arranged along the inclined surface SSL1 of the recess VA-R. Therefore, the third pixel electrode PE3 can have an inclined structure. (Reference) Figure 14 and Figure 15 The third pixel electrode PE3 may include an inclined portion PE-S disposed on the inclined surface SSL1 of the recess VA-R, a bottom portion PE-B connected to the bottom portion of the inclined portion PE-S, and a top portion PE-T connected to the top portion of the inclined portion PE-S and disposed on the top portion of the second protective layer VA2. The tilt angle of the inclined portion PE-S of the third pixel electrode PE3 may be the same as the tilt angle θ of the inclined surface SSL1 of the recess VA-R. For example, the tilt angle θ of the recess VA-R may be 20 degrees to 70 degrees. As the tilt angle θ increases, the viewing angle may become narrower, and as the tilt angle θ decreases, the brightness may be improved. The third pixel electrode PE3 may have a concave shape. The inclined portion PE-S surrounds the bottom portion PE-B, and the inclined portion PE-S and the bottom portion PE-B do not overlap vertically. The bottom portion PE-B and the top portion PE-T may be substantially flat (e.g., relatively flat), but may be formed to have curvature in the process. Even if the bottom portion PE-B and the top portion PE-T have curvature in the process (e.g., when the bottom portion PE-B and the top portion PE-T have curvature in the process), the bottom portion PE-B and the top portion PE-T can be formed to be relatively flat compared to the inclined portion PE-S.

[0204] The third pixel electrode PE3 has an uneven pattern PVP-P formed in the light-emitting region EA3 based on the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2. For example, the uneven pattern PVP-P derived from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 is formed in the inclined portion PE-S and the bottom portion PE-B of the third pixel electrode PE3. Therefore, the uneven pattern PVP-P derived from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 in the inclined portion PE-S and the bottom portion PE-B can have a shape substantially similar to the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2, or at least a portion of the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2. In the case of the uneven pattern PVP-P of the inclined portion PE-S, although it originates from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2, the inclined portion PE-S may have a shape that is partially different from the uneven pattern PVP of the first protective layer VA1 and the uneven pattern of the second protective layer VA2 due to the inclination.

[0205] Due to the uneven pattern PVP-P of the inclined portion PE-S and the bottom portion PE-B of the third pixel electrode PE3, light emitted from the third organic light-emitting layer EML3 can be effectively reflected. In particular, because light emitted laterally from the third organic light-emitting layer EML3 is effectively reflected, the brightness (luminance) ratio LvA relative to the angle with respect to the normal is increased (see [reference]). Figure 14 It can be increased, and based on the luminance (lightness) ratio deviation dLvA relative to the normal (see...). Figure 14 It can be reduced.

[0206] The first outer coating OC1 can be placed on the encapsulation layer ENC.

[0207] The color filter layer CFL and the light-blocking pattern BM can be arranged on the first outer coating OC1.

[0208] Color filters CF2 and CF3, included in the color filter layer CFL, can be arranged in the light-emitting regions EA2 and EA3, respectively. Color filters CF2 and CF3 may include a second color filter CF2 and a third color filter CF3. Color filters CF2 and CF3 may each independently include a colorant (such as a dye and / or pigment) that absorbs light of wavelengths other than a specific wavelength and can be arranged in response to the color of the light emitted from the light-emitting regions EA2 and EA3.

[0209] For example, in one or more embodiments, the second color filter CF2 may be arranged to overlap with the second light-emitting region EA2, and may be a red color filter that transmits only red light. The third color filter CF3 may be arranged to overlap with the third light-emitting region EA3, and may be a green color filter that transmits only green light.

[0210] The light-blocking pattern BM may include a light-absorbing material. For example, the light-blocking pattern BM may include inorganic black pigments and / or organic black pigments. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, but the embodiments disclosed herein are not limited thereto. The light-blocking pattern BM can improve the color reproduction of the display device 10 by preventing or reducing visible light interference between the light-emitting areas EA2 and EA3 and by mixing colors between the light-emitting areas EA2 and EA3.

[0211] The second outer coating OC2 can be applied to the color filter layer CFL and the light-blocking pattern BM.

[0212] The second outer coating OC2 can be disposed on the color filter layer CFL. The second outer coating OC2 can be a colorless, light-transmitting layer that does not have color in the visible light band. For example, in one or more embodiments, the second outer coating OC2 can include a colorless, light-transmitting organic material, such as acrylic resin.

[0213] Figure 15 This is a perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure. Figure 1 to Figure 8 This illustrates one or more embodiments. Figure 9 An exploded perspective view of the head-mounted display.

[0214] refer to Figure 10 and Figure 16 A head-mounted display 1000 according to one or more embodiments includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0215] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. This is because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 16 The display devices 10 described are substantially the same, so for the sake of brevity, a description of the first display device 10_1 and the second display device 10_2 will not be provided.

[0216] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0217] The intermediate frame 1400 can be arranged between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0218] The control circuit board 1600 can be arranged between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert an externally input image source into digital video data DATA, and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 via connectors.

[0219] In one or more embodiments, the control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image that is improved or optimized for the user's left eye to a first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image that is improved or optimized for the user's right eye to a second display device 10_2. In one or more embodiments, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0220] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is arranged to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for viewing with the user's left eye and a second eyepiece 1220 for viewing with the user's right eye. Figure 16 and Figure 16 The first eyepiece 1210 and the second eyepiece 1220 are shown arranged separately, but embodiments of this disclosure are not limited thereto. In one or more embodiments, the first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0221] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0222] The headband 1300 is used to secure the display device housing 1100 to the user's head, such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 remain aligned with the user's left and right eyes, respectively. In one or more embodiments, the head-mounted display 1000 can be provided as follows when the display device housing 1100 is implemented to be lightweight and compact: ​ The eyeglass frame shown is not the headband 1300.

[0223] ​ This is a perspective view illustrating an example of a head-mounted display according to one or more embodiments of the present disclosure.

[0224] refer to ​ The head-mounted display 1000_1 according to one or more embodiments may be an eyeglass-type (or similar) display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0225] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the optical path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its optical path is changed by the optical path changing component 1070, can be provided to the user's right eye through the right eye lens 1020. Therefore, the user can view augmented reality images through their right eye, where the virtual image displayed on the display device 10_3 and the real image seen through the right eye lens 1020 are combined.

[0226] ​The illustration shows a display device housing 1200_1 positioned at the right end of the support frame 1030, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in these embodiments, the image displayed on the display device 10_3 may be provided to the user's left eye. In one or more embodiments, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030 (e.g., simultaneously positioned at both the left and right ends of the support frame 1030), and in these embodiments, the user may view the image displayed on the display device 10_3 using both the left and right eyes (e.g., simultaneously viewing the image displayed on the display device 10_3 using both the left and right eyes).

[0227] In view of the entire contents of this disclosure, those skilled in the art will appreciate that, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of one another or in combination with one another in any suitable way.

[0228] However, it should be understood that the aspects and features of the embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains by referring to the claims, to which their equivalents will be included. It should be further understood that the scope of this disclosure is defined by the appended claims and their equivalents, rather than by the specific embodiments described above, and that all modifications and alterations derived from the claims and their equivalents fall within the scope of this disclosure.

Claims

1. A display device, wherein, The display device includes: Base; Thin-film transistor, on the substrate; A planarization layer is applied to the thin-film transistor. A protective layer is provided on the planarization layer and has multiple recesses. A first electrode is arranged on the protective layer corresponding to each of the plurality of recesses; A pixel defining layer, defining a light-emitting area and a non-light-emitting area, is located on the protective layer; An organic light-emitting layer, located on the first electrode in the light-emitting region; and The second electrode is located on the pixel defining layer and the organic light-emitting layer. The first electrode includes an inclined portion on the inclined surface of each of the plurality of recesses and a bottom portion at the lower end of the inclined portion. The inclined portion has a concave or convex uneven pattern.

2. The display device according to claim 1, wherein, The bottom portion has an uneven pattern, either concave or convex.

3. The display device according to claim 2, wherein, The protective layer has an uneven pattern below the uneven pattern of the inclined portion and the bottom portion of the first electrode.

4. The display device according to claim 3, in, The depth of the uneven pattern in the protective layer is 0.5 μm to 1.0 μm. The width of the uneven pattern in the protective layer is 1.0 μm to 2.0 μm, and The distance between the uneven patterns in the protective layer is 1.0 μm to 2.0 μm.

5. The display device according to claim 3, in, The protective layer includes a first protective layer and a second protective layer on the top surface of the first protective layer, and The uneven pattern of the protective layer is on the top surface of the first protective layer and the bottom surface of the second protective layer.

6. The display device according to claim 1, in, The organic light-emitting layer is located on the inclined portion and the bottom portion of the first electrode, and The organic light-emitting layer includes an uneven pattern corresponding to the uneven pattern of the first electrode.

7. The display device according to claim 1, in, The depth of each of the plurality of recesses is less than the thickness of the protective layer, and The inclined surface of each of the plurality of recesses has an inclination angle in the range of 20° to 70°.

8. The display device according to claim 7, wherein, The inclined portion of the first electrode has the same inclination angle as the inclined surface of each of the plurality of recesses.

9. The display device according to claim 1, in, The pixel-defining layer does not overlap with the tilted portion.

10. The display device according to claim 9, in, The first electrode also includes a top portion at the upper end of the inclined portion, and The pixel-defining layer covers at least a portion of the top portion.

11. A display device, wherein, The display device includes: The substrate includes a first light-emitting region and a second light-emitting region; Thin-film transistor, on the substrate; A planarization layer is applied to the thin-film transistor. A protective layer, on the planarization layer, having a first recess and a second recess that overlap with the first light-emitting area and the second light-emitting area, respectively; A first pixel electrode and a second pixel electrode, wherein the first pixel electrode is on the portion of the protective layer corresponding to the first recess, and the second pixel electrode is on the portion of the protective layer corresponding to the second recess; An organic light-emitting layer includes a first pixel light-emitting layer on the first pixel electrode in the first light-emitting region and a second pixel light-emitting layer on the second pixel electrode in the second light-emitting region; A pixel defining layer, defining a light-emitting area and a non-light-emitting area, is located on the protective layer; and A common electrode is located on the pixel defining layer and the organic light-emitting layer. The second pixel electrode includes an inclined portion on the inclined surface of the second recess and a bottom portion at the lower end of the inclined portion. The inclined portion and the bottom portion have concave or convex uneven patterns.

12. The display device according to claim 11, in, The first pixel electrode includes an inclined portion on the inclined surface of the first recess and a bottom portion at the lower end of the inclined portion of the first pixel electrode. The first pixel electrode does not include uneven portions.

13. The display device according to claim 12, in, The protective layer has an uneven pattern beneath the uneven pattern of the inclined portion and the bottom portion of the second pixel electrode.

14. The display device according to claim 13, in, The depth of the uneven pattern in the protective layer is 0.5 μm to 1.0 μm. The width of the uneven pattern in the protective layer is 1.0 μm to 2.0 μm, and The distance between the uneven patterns in the protective layer is 1.0 μm to 2.0 μm.

15. The display device according to claim 13, in, The protective layer includes a first protective layer and a second protective layer on the top surface of the first protective layer, and The uneven pattern of the protective layer is on the top surface of the first protective layer and the bottom surface of the second protective layer.

16. The display device according to claim 11, in, The first pixel electrode includes an inclined portion on the inclined surface of the first recess and a bottom portion at the lower end of the inclined portion of the first pixel electrode. Wherein, the organic light-emitting layer is located on the inclined portion and the bottom portion of each of the first pixel electrode and the second pixel electrode, and The organic light-emitting layer includes an uneven pattern corresponding to the uneven pattern of the second pixel electrode.

17. The display device according to claim 11, in, The depth of each of the first and second recesses is less than the thickness of the protective layer. The inclined surface of the first recess has an inclination angle in the range of 20° to 70°, and The inclined surface of the second recess has an inclination angle in the range of 20° to 70°.

18. The display device according to claim 17, in, The tilted portion of the first pixel electrode has the same tilt angle as the tilted surface of the first recess, and The inclined portion of the second pixel electrode has the same inclination angle as the inclined surface of the second recess.

19. The display device according to claim 11, wherein, The display device further includes: A thin-film encapsulation layer is provided on the common electrode and includes a first inorganic film layer, a second inorganic film layer, and an organic film layer between the first inorganic film layer and the second inorganic film layer. Color filter layer, on the thin film encapsulation layer; and An outer coating layer is placed between the thin film encapsulation layer and the color filter layer. The color filter layer includes a first color filter that overlaps with the first light-emitting area and a second color filter that overlaps with the second light-emitting area. The first color filter is one of a blue color filter that transmits blue light and a red color filter that transmits red light. The second color filter is a green color filter that transmits green light.

20. An electronic device, wherein, The electronic device includes a display panel; The display panel includes, Base; Thin-film transistor, on the substrate; A planarization layer is applied to the thin-film transistor. A protective layer is provided on the planarization layer and has multiple recesses. A first electrode is arranged on the protective layer corresponding to each of the plurality of recesses; A pixel defining layer, defining a light-emitting area and a non-light-emitting area, is located on the protective layer; An organic light-emitting layer is located on the first electrode in the light-emitting region; as well as The second electrode is located on the pixel defining layer and the organic light-emitting layer. The first electrode includes an inclined portion on the inclined surface of each of the plurality of recesses and a bottom portion at the lower end of the inclined portion. The inclined portion has a concave or convex uneven pattern.

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