Manufacturing method of semiconductor structure

Abstract

The manufacturing method of the semiconductor structure comprises the steps that a dielectric layer is formed on a substrate, the dielectric layer comprises a discrete through hole area and a dense through hole area, and each of the discrete through hole area and the dense through hole area comprises a plurality of through holes; forming a plasticizer in a bottom region of each of the through holes; forming a photoresist layer on the dielectric layer and in the through hole, wherein the photoresist layer is in contact with the plasticizer; and heating the photoresist layer and the plasticizer so that the photoresist layer interacts with the plasticizer and an expansion part is formed in the photoresist layer. According to the manufacturing method, the height difference between the discrete through hole region and the dense through hole region can be effectively reduced, so that the process uniformity is enhanced, the yield is improved, and a photoetching process window for manufacturing an advanced semiconductor element is expanded.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor structure and a coating apparatus for manufacturing a semiconductor structure. Background Technology

[0002] In traditional dual damascene (DD) lithography, vias and trench patterns are formed within the same dielectric layer. When a photoresist layer is applied to define the trench pattern, the photoresist tends to flow into the multiple vias. As a result, because the photoresist needs to fill a large number of vias, the photoresist thickness above the dense via seas is typically lower than the photoresist thickness above the discrete via seas. This uneven photoresist thickness narrows the lithography window and makes it difficult to obtain accurate trench profiles in the dense via seas.

[0003] Variations in photoresist thickness can lead to various defects, including photoresist line breakage causing short circuits in the metal lines, or tapered photoresist sidewalls resulting in open circuits or narrower linewidths and increased resistance. Traditional methods for mitigating this problem often involve complex multi-step lithography or etch-back processes, which not only increase manufacturing costs and timelines but also offer limited improvement in lithography process margins. Summary of the Invention

[0004] According to one or more embodiments of the present invention, a method for manufacturing a semiconductor structure includes: forming a dielectric layer on a substrate, wherein the dielectric layer includes a discrete via region and a dense via region, and each of the discrete via region and the dense via region includes a plurality of vias; forming a plasticizer in the bottom region of each of the plurality of vias; forming a photoresist layer on the dielectric layer and within the vias, wherein the photoresist layer contacts the plasticizer; and heating the photoresist layer and the plasticizer to cause the photoresist layer and the plasticizer to interact and form an expanded portion in the photoresist layer.

[0005] In some embodiments of the present invention, a photoresist layer is formed on the dielectric layer and inside the vias such that the photoresist layer covers the top surface of the dielectric layer, and after the expansion portion is formed, the height difference between the photoresist layer in the discrete via region and the dense via region is less than 5 nanometers.

[0006] In one or more embodiments of the present invention, a plasticizer is formed in the bottom region of each of the through holes such that the plasticizer occupies 1% to 20% of the height of each of the through holes.

[0007] In one or more embodiments of the present invention, the expanded portion occupies 20% to 40% of the height of each of the through holes.

[0008] In one or more embodiments of the present invention, the expanded portion contacts the substrate.

[0009] In one or more embodiments of the present invention, the expanded portion is formed between a portion of the photoresist layer that does not interact with the plasticizer and the plasticizer that does not interact with the photoresist layer.

[0010] In one or more embodiments of the present invention, the expanded portion together with the plasticizer that does not interact with the photoresist layer occupies 20% to 40% of the height of each of the vias.

[0011] In one or more embodiments of the present invention, the plasticizer is selected from the group consisting of phthalate plasticizers, adipate plasticizers, sebacic acid ester plasticizers, azelaic acid ester plasticizers, citrate plasticizers, trimethylbenzene diester plasticizers, sulfonamide plasticizers, polyether plasticizers and benzoate plasticizers.

[0012] In one or more embodiments of the present invention, the material of the photoresist layer is selected from the group consisting of phenolic resin, epoxy resin, acrylic resin and polyvinylphenol resin.

[0013] In one or more embodiments of the present invention, the expanded portion pushes the photoresist layer upward.

[0014] In one or more embodiments of the present invention, the method of manufacturing a semiconductor structure further includes: after forming an expanded portion, patterning a photoresist layer to form a trench pattern having a plurality of trenches.

[0015] In one or more embodiments of the present invention, the trenches are connected to the through holes, such that a portion of the substrate is exposed by the through holes and the trenches.

[0016] In one or more embodiments of the present invention, a plasticizer is formed in the bottom region of each of the through holes by applying the plasticizer onto the dielectric layer at a controlled rotation speed greater than 0 rpm and less than or equal to 3000 rpm.

[0017] In one or more embodiments of the present invention, the plasticizer is formed in the bottom region of each of the through holes by at least two coating stages, and the two coating stages have different controlled rotation speeds.

[0018] According to one or more embodiments of the present invention, a method for manufacturing a semiconductor structure includes: coating a plasticizer onto a dielectric layer of a substrate using a coating apparatus, allowing the plasticizer to flow into a plurality of vias in the dielectric layer; and forming a photoresist layer in contact with the plasticizer, such that the photoresist layer interacts with the plasticizer and forms an expanded portion within the photoresist layer. The coating apparatus includes a substrate support stage, a dispensing unit, a control unit, and a monitoring unit. The substrate support stage is configured to support the substrate. The dispensing unit is disposed above the substrate support stage and configured to supply the plasticizer. The control unit is electrically connected to the dispensing unit and configured to dynamically adjust the position and angle of the dispensing unit relative to the substrate. The monitoring unit is disposed above the substrate support stage and configured to monitor the position of the plasticizer in real time.

[0019] In one or more embodiments of the present invention, the photoresist layer is formed using a coating device.

[0020] In one or more embodiments of the present invention, the expanded portion occupies 20% to 40% of the height of each of the through holes.

[0021] In one or more embodiments of the present invention, the expanded portion contacts the substrate.

[0022] In one or more embodiments of the present invention, the expanded portion is formed between a portion of the photoresist layer that does not interact with the plasticizer and the plasticizer that does not interact with the photoresist layer.

[0023] In one or more embodiments of the present invention, the expanded portion together with the plasticizer that does not interact with the photoresist layer occupies 20% to 40% of the height of each of the vias.

[0024] According to the above embodiments of the present invention, the manufacturing method employs plasticizer-assisted photoresist planarization technology to effectively reduce the height difference between discrete via regions and dense via regions. By filling the bottom portion of the via in a controlled manner with plasticizer and utilizing thermal induction to induce expansion interaction between the plasticizer and the overlying photoresist layer, an expanded portion is formed to push the photoresist surface upward, thereby achieving a planarization effect before the formation of the trench pattern. This method can ensure focal length stability during photolithography exposure and reduce defects such as sidewall taper or line breakage of photoresist lines, thereby improving trench contour accuracy and critical dimension control. Furthermore, the present invention also provides an apparatus for implementing the above process (method) to enhance process uniformity, improve yield, and expand the photolithography process window for advanced semiconductor device manufacturing. Attached Figure Description

[0025] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figure 1 This is a schematic diagram of a coating apparatus for manufacturing semiconductor structures according to some embodiments of the present invention; Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figures 6A-6B This is a cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure according to some embodiments of the present invention. Figure 7 A cross-sectional schematic diagram of a semiconductor structure manufactured using conventional techniques; and Figure 8 This is a flowchart illustrating the steps of a semiconductor structure manufacturing method according to some embodiments of the present invention. Detailed Implementation

[0026] The following description, with reference to the accompanying drawings, discloses several embodiments of the present invention. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details are not intended to limit the invention. That is, in some embodiments of the invention, these practical details are not essential and therefore are not intended to limit the invention. Furthermore, for the sake of simplicity in the drawings, some conventionally used structures and elements will be shown in a simplified schematic manner. In addition, for the reader's convenience, the dimensions of the elements in the drawings are not drawn to scale.

[0027] It should be understood that although the terms “first,” “second,” and “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, “first element,” “component,” “region,” “layer,” or “part” as used below may also be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0028] It should be understood that relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship of one element to another, as illustrated in the accompanying drawings. It should be understood that relative terms are intended to include different orientations of the device beyond those shown in the figures. For example, if a device in one of the figures is flipped, an element described as being “down” to other elements will be oriented “up” to other elements. Thus, the exemplary term “down” can include both “down” and “up” orientations, depending on the specific orientation of the figure. Similarly, if a device in one of the figures is flipped, an element described as being “down” or “below” to other elements will be oriented “above” to other elements. Thus, the exemplary term “down” or “below” can include both “up” and “down” orientations.

[0029] Furthermore, as used herein, “about,” “approximately,” or “roughly” generally refers to ±20% of a given value or range, preferably ±10%, and more preferably ±5%. The numerical values ​​listed herein are approximate, meaning that unless explicitly stated otherwise, the use of “about,” “approximately,” or “roughly” is to be understood.

[0030] This invention provides a method for manufacturing a semiconductor structure and a coating apparatus for manufacturing the semiconductor structure. The manufacturing method disclosed herein improves the photolithography process window of a double-layer trench structure by introducing a plasticizer into the vias of a dielectric layer and allowing it to interact with a photoresist layer to form an expanded portion in the photoresist layer. The expansion reduces the variation in photoresist layer thickness between discrete and densely packed via regions, thereby improving the formation effect of the trench pattern and the overall photolithography performance. In addition to the manufacturing method, this invention further provides a coating apparatus designed for high-precision dispensing of the plasticizer into the vias of the dielectric layer. The coating apparatus is equipped with functional units to ensure precise positioning and monitoring of the plasticizer. In the following embodiments, the coating apparatus will be described first, followed by a detailed description of the manufacturing method.

[0031] refer to Figure 1 , Figure 1 This is a schematic diagram of a coating apparatus 10 for manufacturing semiconductor structures according to some embodiments of the present invention. The coating apparatus 10 includes a substrate support stage 11, a dispensing unit 12, a control unit 13, and a monitoring unit 14. These units are operatively connected to achieve precise dispensing of plasticizer 130 into a plurality of vias V in a dielectric layer 120. The substrate support stage 11 is disposed at the bottom of the coating apparatus 10 to stably support a substrate 110 on which the dielectric layer 120 having a plurality of vias V is disposed. The dispensing unit 12 is disposed above the substrate support stage 11 and configured to dispense plasticizer 130 onto the dielectric layer 120. The control unit 13 is electrically connected to the dispensing unit 12 and configured to dynamically adjust the position of the dispensing unit 12 relative to the top surface 111 of the substrate 110 and the dispensing angle θ. The monitoring unit 14 is located above the substrate support stage 11 and is configured to monitor the position and distribution of the plasticizer 130 applied in real time and feed the information back to the control unit 13 to achieve precise deposition of the plasticizer 130 in the through hole V.

[0032] A substrate support stage 11 is configured to securely hold a substrate 110 having a dielectric layer 120 with multiple through-holes V. The substrate support stage 11 may include a clamping system 11A, such as a vacuum chuck mechanism, an electrostatic chuck mechanism, or a mechanical clamping mechanism, to ensure that the substrate 110 remains flat and stable during dispensing, facilitating precise deposition of the plasticizer 130 into the through-holes V. In some embodiments, the substrate support stage 11 may also include a rotation mechanism 11B to achieve uniform distribution of the plasticizer 130 and promote its flow into the bottom region of the through-holes V. In some embodiments, the coating apparatus 10 may also include a control unit 15 electrically connected to the substrate support stage 11 and configured to control the rotation mechanism 11B, adjusting the rotation speed and direction to optimize coating uniformity and effectively fill the bottom region of the through-holes V.

[0033] A dispensing unit 12 is disposed above a substrate support stage 11 and configured to dispense a controlled amount of plasticizer 130 onto the dielectric layer 120. The dispensing unit 12 may include at least one nozzle 12A, which may be vertically positioned (dispensing angle θ of 90°) or set at a dispensing angle θ of 60° to less than 90° relative to the top surface 111 of the substrate 110 (e.g., 65°, 70°, 75°, 80°, or 85°). Adjusting the dispensing angle θ within this range allows the coating apparatus 10 to adapt to vias V of different shapes or aspect ratios, thereby increasing the likelihood of precise deposition of the plasticizer 130 into the bottom region of the via V. For example, for narrow or deep vias V, the dispensing angle θ may be reduced to help the plasticizer 130 reach the bottom; while for wide or shallow vias V, the dispensing angle θ may be increased to ensure uniform coverage.

[0034] Control unit 13 is electrically connected to dispensing unit 12 and configured to dynamically adjust the position of dispensing unit 12 relative to the top surface 111 of substrate 110 and the dispensing angle θ. Control unit 13 can store predetermined process parameters corresponding to different substrate layouts and can operate in real time based on information fed back by monitoring unit 14. In some embodiments, control unit 13 can also adjust dispensing speed, flow rate, or time to improve the uniformity of plasticizer 130 deposition. Monitoring unit 14 is disposed above substrate stage 11 and electrically connected to control unit 13. Monitoring unit 14 is configured to monitor the position and distribution of plasticizer 130 in real time and may include optical sensors, cameras, or other detection elements that can provide real-time images or coating thickness measurements. Data collected by monitoring unit 14 is transmitted to control unit 13 to dynamically adjust dispensing parameters to ensure that plasticizer 130 is accurately deposited in the bottom region of via V of dielectric layer 120.

[0035] The following provides a detailed description of the manufacturing method of the semiconductor structure 100. Figure 2 , Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figures 6A-6B This is a cross-sectional schematic diagram of each step in a method for manufacturing a semiconductor structure 100 according to some embodiments of the present invention. Figure 8 This is a schematic flowchart illustrating the steps of a method for manufacturing a semiconductor structure 100 according to some embodiments of the present invention. In some embodiments, the step of forming a plasticizer 130 in the semiconductor structure 100 can be performed using the coating equipment 10 described above. The following description will explain each process step sequentially.

[0036] refer to Figure 2 In step S10, a dielectric layer 120 is formed on the substrate 110. The dielectric layer 120 includes two distinct regions: a discrete via region R1 and a dense via region R2. Each of these regions includes a plurality of vias V passing through the dielectric layer 120, exposing a portion of the top surface 111 of the substrate 110 through the vias V. The discrete via region R1 includes vias V spaced relatively far apart, while the dense via region R2 includes vias V arranged in a high density. More specifically, the "discrete via region R1" refers to the portion of the dielectric layer 120 with a large spacing between vias V and a low via density; the "dense via region R2" refers to the portion of the dielectric layer 120 with a dense arrangement of vias V and a high via density. This dielectric layer 120 serves as the foundation structure for subsequent process steps of the semiconductor structure 100.

[0037] In some embodiments, the via V has a tapered profile, with its top critical dimension CDt being greater than its bottom critical dimension CDb (i.e., wider at the top and narrower at the bottom). This tapering facilitates subsequent deposition or electroplating of conductive materials, improves coverage, and reduces void formation within the via V. In other embodiments, the via V may be substantially vertical (CDt≈CDb). The dielectric layer 120 may be formed of a low dielectric constant (k) material (k<3.0), silicon oxide, or other interlayer dielectric materials. In some embodiments, the boundary between the discrete via region R1 and the dense via region R2 may be defined by a via spacing threshold, wherein the via V spacing in the discrete via region R1 is greater than the threshold, and the via V spacing in the dense via region R2 is less than or equal to the threshold.

[0038] refer to Figure 3Next, in step S20, a plasticizer 130 is formed in the bottom region B of each via V in the dielectric layer 120. In some embodiments, the plasticizer 130 completely covers the top surface 111 of the substrate 110 exposed by the via V and is in direct contact with the top surface 111 of the substrate 110. In some embodiments, the formation of the plasticizer 130 is controlled so that it occupies about 1% to about 20% of the total height H of the via V (e.g., 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15%, 16%, 17%, 18%, 19%). This partial filling ensures that the bottom region B of the via V is adequately filled to facilitate subsequent interaction with the photoresist layer 140, while avoiding overfilling that could affect the flatness or pattern accuracy of subsequent processes.

[0039] If the plasticizer 130 exceeds the required height range, the photoresist layer 140 located on it (see...) Figure 4 The plasticizer 130 may overreact with the photoresist layer 140, causing it to expand excessively and be pushed upwards excessively, resulting in an uneven surface profile. This can affect subsequent photolithography accuracy, causing issues such as defocusing, uneven exposure, or trench pattern deformation. Conversely, if the plasticizer 130 is too thin, its contact and interaction with the photoresist layer 140 may be insufficient, resulting in limited expansion and a significant height difference between the discrete via region R1 and the dense via region R2. This insufficient filling reduces the planarization effect, causing persistent surface topographic differences, which in turn affects critical dimension control and reduces photolithography process margin. Therefore, precise control of the height of the plasticizer 130 helps achieve ideal planarization and maintain pattern resolution consistency in subsequent processes.

[0040] In some embodiments, plasticizer 130 may be selected from the group consisting of phthalate-based, adipate-based, sebacic acid ester-based, azelaic acid ester-based, citrate-based, trimethylbenzene diester-based, sulfonamide-based, polyether-based, and benzoate-based plasticizers. Such plasticizers are chosen because they can effectively interact with photoresist layer 140 (see...). Figure 4 The interaction promotes controlled expansion, thereby assisting the top surface 141 of the photoresist layer 140 (see...) Figure 4 as well as Figure 5A Smoothing. The choice of plasticizer 130 can be adjusted according to the chemical compatibility, thermal stability and mechanical properties required by the process to meet specific semiconductor manufacturing needs.

[0041] Examples of specific compounds for each plasticizer 130 are as follows. For phthalate-based plasticizers, examples include diethyl phthalate (DEP), dibutyl phthalate (DBP), di(2-ethylhexyl) phthalate (DEHP), and butyl benzyl phthalate (BBP). For adipate-based plasticizers, examples include di(2-ethylhexyl) adipate (DOA), diisononyl adipate (DINA), and diisodecyl adipate (DIDA). For sebacic acid ester-based plasticizers, examples include dioctyl sebacate (DOS) and dibutyl sebacate (DBS). Examples of azelate-based plasticizers include dioctyl azelate (DOZ) and diisononyl azelate (DINA-Z). Examples of citrate-based plasticizers include tributyl citrate (TBC), acetyl tributyl citrate (ATBC), and triethyl citrate (TEC). Examples of trimellitate-based plasticizers include tris(2-ethylhexyl) trimellitate (TOTM) and trioctyl trimellitate (TOTM-O). Examples of sulfonamide-based plasticizers include N-ethyl o / p-toluenesulfonamide (o / p-ETSA) and N-butylbenzenesulfonamide (NBSA). Examples of polyether-based plasticizers include polyethylene glycol (PEG), polypropylene glycol (PPG), and polyethylene glycol dibenzoate (PEGDB).Examples of benzoate plasticizers include dipropylene glycol dibenzoate (DPGDB), diethylene glycol dibenzoate (DEGDB), and triethylene glycol dibenzoate (TEGDB).

[0042] refer to Figure 1 and Figure 3 In some embodiments, the coating equipment 10 described above can be used to form plasticizer 130 in the bottom region B of the via V. In some embodiments, the dispensing unit 12 precisely dispenses a controlled amount of plasticizer 130 through at least one nozzle 12A, which can move horizontally and vertically and is positioned at a specific dispensing angle θ. Adjusting the dispensing angle θ allows the plasticizer 130 to flow more effectively into vias V of different shapes or aspect ratios, ensuring that the bottom region B of the via V is fully covered. Furthermore, the rotation mechanism 11B of the substrate carrier stage 11 generates a centrifugal diffusion effect when activated, promoting uniform distribution of the plasticizer 130 and assisting its flow into the bottom of the via V. In some preferred embodiments, the dispensing angle θ adjustment, nozzle position, and optimal rotation speed of the substrate carrier stage 11 can be combined to ensure that the plasticizer 130 is selectively deposited only in the via V, minimizing the amount of residue on the top surface 121 of the dielectric layer 120. The control unit 13 works in conjunction with the monitoring unit 14 to dynamically adjust the nozzle position, dispensing angle θ and dispensing flow rate based on real-time feedback, thereby precisely controlling the height and coverage of the plasticizer 130 in each through hole V.

[0043] For example, when coating a dielectric layer 120 with a deep via V having a high aspect ratio (e.g., aspect ratio ≥ 3:1), the dispensing unit 12 can be positioned at a dispensing angle θ of approximately 60° to 75° relative to the top surface 111 of the substrate 110 to improve the ability of the plasticizer 130 to reach and cover the bottom region B of the via V. Conversely, for shallow or wide vias with low aspect ratios, the dispensing angle θ can be adjusted to close to 90° (e.g., 75° to 90°) to ensure uniform vertical deposition without excessive lateral diffusion. The rotation mechanism 11B of the substrate carrier stage 11 can control the rotation speed range from 0 rpm to 3000 rpm (e.g., 100 rpm, 200 rpm or 300 rpm, 400 rpm, 500 rpm, 600 rpm, 700 rpm or 800 rpm, 900 rpm, 1000 rpm, 1100 rpm, 1200 rpm or 1300 rpm, 1400 rpm, 1500 rpm, 1600 rpm or 1700 rpm, 1800 rpm, 1900 rpm, 2000 rpm, 2100 rpm or 2200 rpm, 2300 rpm, 2400 rpm, 2500 rpm or 2600 rpm, 2700 rpm, 2800 rpm, 2900 rpm), depending on the viscosity of the plasticizer 130, the geometry of the through-hole V, and the desired coating characteristics. For example, rotating at 100 rpm to 800 rpm for 5 to 20 seconds can promote the uniform deposition of plasticizer 130 in the through-holes, especially ensuring that the bottom region B of the dense through-hole region R2 is fully filled, while avoiding overflow or excessive diffusion in the discrete through-hole region R1.

[0044] In some embodiments, the dispensing of plasticizer 130 can be performed in multiple stages, each stage having a different dispensing angle θ, a controlled rotation speed of the substrate support stage 11, and a nozzle position. For example, the initial stage may use a smaller dispensing angle θ and a slower rotation speed to deposit plasticizer primarily into narrow or deep vias V; subsequent stages adjust the dispensing angle θ to be larger and increase the rotation speed to better fill wide or shallow vias V. Furthermore, the position of the nozzle 12A can be moved laterally or vertically between stages to align with specific areas of the substrate 110, thereby enhancing uniform coverage and precisely controlling the height and distribution of plasticizer 130 within different via areas. This staged dispensing allows for fine-tuning of coating parameters to adapt to different via geometries and ensures optimal filling of the bottom portion of the vias.

[0045] Please see Figure 4Next, in step S30, a photoresist layer 140 is formed on the dielectric layer 120 and within the via V, such that the photoresist layer 140 directly contacts the plasticizer 130 in the bottom region B of the via V. In some embodiments, the photoresist layer 140 is coated in such a way that it fills the entire via V and covers the top surface 121 of the dielectric layer 120, thereby forming a continuous coating layer on the discrete via region R1 and the dense via region R2. In some embodiments, the photoresist layer 140 is formed using a spin-coating or spray-coating process. Coating parameters (e.g., rotation speed, rotation time, and solution viscosity) can be adjusted to ensure that the photoresist material properly fills the via V without creating voids, bubbles, or uneven thickness. For example, for the dense via region R2, a lower rotation speed or a multi-step coating process can be used to promote deep penetration; while a higher rotation speed helps control surface planarization on the discrete via region R1.

[0046] Considering the difference in via density between the dense via region R2 and the discrete via region R1, the top surface 141 of the photoresist layer 140 formed in these regions often exhibits a significant height variation. Specifically, in the dense via region R2, due to the influx and filling of numerous closely packed vias V by a large amount of photoresist material, the top surface 141 of the photoresist layer 140 may appear concave or lower relative to the adjacent region (i.e., the discrete via region R1). Conversely, in the discrete via region R1, where the spacing between vias V is larger and the number of vias is smaller, less photoresist material is used for filling, resulting in the photoresist layer 140 maintaining a relatively high position on the top surface 121 of the dielectric layer 120. The uneven height distribution between the discrete via region R1 and the dense via region R2 can cause the top surface 141 of the photoresist layer 140 to exhibit a stepped or wavy topography, which may adversely affect subsequent photolithography focusing and pattern accuracy. Therefore, the present invention introduces plasticizer 130 as a planarization mechanism to compensate for this height difference, making the top surface 141 of photoresist layer 140 flatter.

[0047] In some embodiments, the photoresist layer 140 may be selected from materials such as phenolic resin, epoxy resin, acrylic resin, and polyvinylphenol resin. These materials are chosen based on their ability to allow the plasticizer 130 to effectively penetrate or insert (diffused) between the polymer chains of the photoresist layer 140, thereby inducing controlled expansion of the photoresist layer 140 upon contact. This expansion promotes upward expansion of the photoresist layer 140, thereby compensating for the initial topographic difference between the discrete via region R1 and the dense via region R2. Furthermore, by selecting a photoresist material with appropriate polymer chain fluidity, crosslinking density, and chemical affinity to the plasticizer 130, the degree of penetration and expansion can be finely controlled, thereby achieving the desired planarization effect while maintaining the lithographic integrity of the photoresist layer 140.

[0048] Examples of phenolic resins include cresol novolac resin (CNR), phenolnovolac resin (PNR), and bisphenol A novolac resin (BPA-NR). Examples of epoxy resins include bisphenol A diglycidyl ether (BADGE) and bisphenol F diglycidyl ether (BFDGE). Examples of acrylic resins include poly(methyl methacrylate) (PMMA), poly(ethyl methacrylate) (PEMA), and copolymers of methyl methacrylate with methacrylic acid (MMA-MAA). Examples of polyvinylphenol resins include poly(4-hydroxystyrene) (PHS), partially hydrogenated polyvinylphenol, and modified polyvinylphenol copolymers such as poly(4-hydroxystyrene-co-allyl alcohol).

[0049] refer to Figure 5A Next, in step S40, the photoresist layer 140 and the plasticizer 130 beneath it are heated, causing the photoresist layer 140 and the plasticizer 130 to interact and form an expanded portion 140E in the photoresist layer 140. The applied heat energy increases the molecular fluidity of the photoresist layer 140 and reduces the viscosity of the plasticizer 130, promoting the diffusion of plasticizer 130 molecules into the polymer chains of the photoresist layer 140. When the plasticizer 130 diffuses, it can partially penetrate into the polymer chains of the photoresist layer 140, weakening the intermolecular forces and causing the photoresist layer 140 to expand locally. This expansion effect mainly occurs in the bottom region B near the via V, where the concentration of plasticizer 130 is highest, thereby forming the expanded portion 140E that directly contacts the substrate 110.

[0050] In some embodiments, the expanded portion 140E pushes the photoresist layer 140 upward, effectively compensating for the topographic differences between the discrete via region R1 and the dense via region R2. Through this controlled expansion, the height difference ΔH of the photoresist layer 140 (i.e., the vertical distance between the top surface 141 of the photoresist layer 140 in the discrete via region R1 and the top surface 141 of the photoresist layer 140 in the dense via region R2) is less than 5 nm (e.g., 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm), significantly improving the planarization effect and providing a more uniform surface profile for subsequent photolithography patterns. In some embodiments, the expanded portion 140E accounts for approximately 20% to 40% of the total height H of each via V (e.g., 21%, 22%, 23%, 24%, 25%, 26%, 27% or 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35% or 36% or 37%, 38%, 39%). This expansion range achieves an optimal balance between planarization and the structural integrity of the photoresist layer 140, preventing excessive expansion from causing trench pattern deformation or reduced feature accuracy. Furthermore, the presence of the expanded portion 140E ensures that the photoresist layer 140 maintains direct contact with the substrate 110, enhancing adhesion and reducing void formation.

[0051] In some embodiments, the heat treatment conditions can be finely controlled to modulate the interaction between the plasticizer 130 and the photoresist layer 140, thereby precisely controlling the formation of the expanded portion 140E. For example, baking or soft baking treatments can be performed at temperatures ranging from 70°C to 300°C (e.g., 80°C, 100°C, 120°C, 140°C, 160°C, 180°C, 200°C, 220°C, 240°C, 260°C, or 280°C) for durations ranging from 30 seconds to 120 seconds (e.g., 40 seconds, 50 seconds, 60 seconds, 70 seconds, 80 seconds, 90 seconds, 100 seconds, or 110 seconds), depending on the composition and viscosity of the photoresist layer 140 and the type of plasticizer 130 used. Lower temperatures or shorter baking times may result in insufficient diffusion of the plasticizer 130, leading to insufficient expansion and reduced planarization. Conversely, excessively high temperatures or prolonged heating may cause over-expansion of the photoresist layer 140, resulting in an excessively high top surface 141 or pattern deformation. In a preferred embodiment, a multi-stage heating method can be employed, such as gradually increasing the temperature and then maintaining it at a constant temperature, to ensure that the expanded portion 140E is uniformly formed in the discrete via region R1 and the dense via region R2. This multi-stage approach helps maintain the height of the expanded portion 140E within the target range (20% to 40% of the total via height H), thereby achieving optimal planarization while avoiding irregular surface undulations or internal stress accumulation in the photoresist layer 140.

[0052] refer to Figure 5BIn other embodiments, the interaction between the plasticizer 130 and the photoresist layer 140 after heat treatment may be incomplete, resulting in the formation of an expanded portion 140E between the portion 140U of the photoresist layer 140 that does not interact with the plasticizer 130 and the portion of the plasticizer 130 that does not interact with the photoresist layer 140. This partial interaction creates a layered structure within each via V, including the portion 140U of the photoresist layer 140 that does not interact with the plasticizer 130, the remaining plasticizer 130, and the expanded portion 140E located above the remaining plasticizer 130 and between the portion 140U of the photoresist layer 140 that does not interact with the plasticizer 130. In other words, the expanded portion 140E is separated from the substrate 110 by the remaining plasticizer 130, meaning the expanded portion 140E does not directly contact the substrate 110.

[0053] exist Figure 5B In the illustrated embodiment, the expanded portion 140E, together with the plasticizer 130 that does not interact with the photoresist layer 140, accounts for 20% to 40% of the total height H of each via V (e.g., 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28% or 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36% or 37%, 38%, 39%). This configuration effectively planarizes the top surface 141 of the photoresist layer 140, reduces surface topographic variations, and promotes a smoother top surface 141. In some embodiments, the thickness T1 of the expanded portion 140E is greater than the thickness T2 of the remaining plasticizer 130, indicating that most of the plasticizer 130 has diffused into the photoresist layer 140 and further expanded the photoresist layer 140.

[0054] In some embodiments, the plasticizer 130 and the expanded portion 140E maintain complete and tight surface contact with the sidewall VS of the through-hole V, ensuring continuous and gapless filling of the sidewall VS. In other words, in some embodiments, the plasticizer 130 and the expanded portion 140E each have a shape that is wider at the top and narrower at the bottom, and when viewed as a whole, they conform to this tapered profile, closely fitting the profile of the through-hole V. This contour-compliant contact and tapered filling geometry helps improve the structural accuracy during subsequent photoresist patterning and trench formation processes, thereby reducing defects caused by uneven sidewalls or incomplete coverage.

[0055] refer to Figure 5B and Figure 6ANext, after the expansion portion 140E is formed, the photoresist layer 140 is patterned to form a trench pattern containing multiple trenches T. In some embodiments, photolithography techniques (such as immersion lithography or extreme ultraviolet lithography) can be used to define the trench openings with high precision. The expansion portion 140E is located below the photoresist layer 140, which ensures that the top surface 141 of the photoresist layer 140 is sufficiently planarized before exposure and development, improving the focus margin and pattern accuracy of this trench formation step. In some embodiments, after the trenches T are formed, they communicate with the vias V of the underlying layer, allowing a portion of the substrate 110 to be exposed through the vias V and the trenches T. This configuration can reduce topographic variations in subsequent deposition or filling processes (such as conductive material deposition), thereby improving critical dimension (CD) control and enhancing the uniformity of the discrete via region R1 and the dense via region R2.

[0056] refer to Figure 6A and Figure 6B Since the top surface 141 of the photoresist layer 140, located above the discrete via region R1 and the dense via region R2, exhibits only a slight or no significant height difference ΔH (see [reference]...), the photoresist layer 140 is situated above the discrete via region R1 and the dense via region R2. Figure 5A as well as Figure 5B The trench etching process achieves higher precision, resulting in the top surface 143 of the patterned photoresist layer 140 having a minimum ( Figure 6A () or can be ignored Figure 6B The height difference ΔD( Figure 6B The height difference ΔD is 0, meaning the top surface 143 above the discrete via region R1 and the top surface 143 above the dense via region R2 are substantially flat with no significant height difference. Simultaneously, the sidewalls 145 of the photoresist layer 140 remain substantially perpendicular during the trench etching step, avoiding tilting or focal length deviation issues. This planarization condition prevents photolithographic defects caused by uneven height reducing the process window. For example, photoresist line breakage may lead to a short circuit in the final metal line, or photoresist line taper may cause an open circuit or narrowing of the final metal line, increasing resistance. By mitigating these risks, this method improves the yield and electrical performance of the resulting semiconductor structure.

[0057] Compared to traditional methods, the top surface of the photoresist layer above the discrete via region R1 is higher, while the top surface of the photoresist layer above the dense via region R2 is lower, resulting in significant topographic differences. This invention addresses this by forming an expanded portion 140E (see...). Figure 4This effectively reduces height variations before photoresist layer patterning. This improved surface planarization ensures that the top surface 141 of the photoresist layer maintains a substantially uniform and flat profile before trench patterning, thereby maintaining a narrower focusing window during photolithography. As a result, risks such as focus deviation, exposure unevenness, and line edge roughness are significantly reduced. Therefore, the improved planarization enhances the accuracy of trench patterning, making the width and depth of trenches T in areas with different via densities more consistent. Furthermore, by expanding the photolithography process window, the method of this invention improves process robustness and yield, enables more precise critical dimension control, and reduces defects associated with photoresist surface inhomogeneity. Overall, this invention offers significant advantages over existing technologies in terms of pattern accuracy and process stability, and is particularly suitable for complex semiconductor structures.

[0058] See Figure 7 , Figure 7 This is a cross-sectional view of a semiconductor structure 100 manufactured using conventional techniques. Due to the lack of an expanded portion 140E, there is a significant height difference between the top surface 141 above the discrete via region R1 and the dense via region R2 of the photoresist layer 140 before trench patterning. This uneven surface topography can lead to uneven exposure and focusing during photolithography, potentially resulting in tilted or deformed trench sidewalls 145. Such tilted sidewalls not only reduce the accuracy of trench dimensions but also increase the risk of rough edges, incomplete trench openings, or photoresist footing, ultimately affecting the patterning accuracy of the metal lines and potentially causing electrical problems such as increased resistance or short circuits.

[0059] According to the above embodiments of the present invention, the manufacturing method employs plasticizer-assisted photoresist planarization technology to effectively reduce the height difference between discrete via regions and dense via regions. By filling the bottom portion of the via in a controlled manner with plasticizer and utilizing thermal induction to induce expansion interaction between the plasticizer and the overlying photoresist layer, an expanded portion is formed to push the photoresist surface upward, thereby achieving a planarization effect before the formation of the trench pattern. This method can ensure focal length stability during photolithography exposure and reduce defects such as sidewall taper or line breakage of photoresist lines, thereby improving trench contour accuracy and critical dimension control. Furthermore, the present invention also provides an apparatus for implementing the above process (method) to enhance process uniformity, improve yield, and expand the photolithography process window for advanced semiconductor device manufacturing.

[0060] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0061] [Symbol Explanation] 10: Coating equipment 11: Substrate support platform 11A: Clamping System 11B: Rotating mechanism 12: Dispensing Unit 12A: Nozzle 13: Control Unit 14: Monitoring Unit 15: Control Unit 100: Semiconductor Structure 110:Substrate 111: Top surface 120: Dielectric layer 121: Top surface 130: Plasticizer 140: Photoresist layer 140E: Expansion section 140U: Partial 141: Top surface 143: Top surface 145: Sidewall R1: Discrete via region R2: Densely perforated area T: Trench T1: Thickness T2: Thickness V: Through hole VS: Sidewall H: Total height ΔH: Height difference ΔD: Height difference θ: Dispensing angle B: Bottom area CDt: Top Key Dimension CDb: Key Bottom Dimensions S10~S40: Steps.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A dielectric layer is formed on a substrate, wherein the dielectric layer includes a discrete via region and a dense via region, and each of the discrete via region and the dense via region includes a plurality of vias; A plasticizer is formed in the bottom region of each of the plurality of through holes; A photoresist layer is formed on the dielectric layer and within the plurality of vias, wherein the photoresist layer contacts the plasticizer; as well as The photoresist layer and the plasticizer are heated, causing the photoresist layer and the plasticizer to interact and form an expanded portion in the photoresist layer.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein the photoresist layer is formed on the dielectric layer and within the plurality of vias such that the photoresist layer covers the top surface of the dielectric layer, and after the expansion portion is formed, the height difference of the photoresist layer between the discrete via region and the dense via region is less than 5 nanometers.

3. The method of manufacturing a semiconductor structure according to claim 1, wherein the plasticizer is formed in the bottom region of each of the plurality of vias such that the plasticizer occupies 1% to 20% of the height of each of the plurality of vias.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein the expanded portion occupies 20% to 40% of the height of each of the plurality of vias.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein the expanded portion contacts the substrate.

6. The method of manufacturing a semiconductor structure according to claim 1, wherein the expanded portion is formed between a portion of the photoresist layer that does not interact with the plasticizer and the plasticizer that does not interact with the photoresist layer.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein the expanded portion and the plasticizer that does not interact with the photoresist layer together occupy 20% to 40% of the height of each of the plurality of vias.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein the plasticizer is selected from the group consisting of phthalate plasticizers, adipate plasticizers, sebacic acid ester plasticizers, azelaic acid ester plasticizers, citrate plasticizers, trimethylbenzene diester plasticizers, sulfonamide plasticizers, polyether plasticizers and benzoate plasticizers.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein the material of the photoresist layer is selected from the group consisting of phenolic resin, epoxy resin, acrylic resin and polyvinylphenol resin.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein the expansion portion pushes the photoresist layer upward.

11. The method for manufacturing a semiconductor structure according to claim 1, wherein, Also includes: After the expansion portion is formed, the photoresist layer is patterned to form a groove pattern with multiple trenches.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein the plurality of trenches are respectively connected to the plurality of vias, such that a portion of the substrate is exposed by the plurality of vias and the plurality of trenches.

13. The method of manufacturing a semiconductor structure according to claim 1, wherein the plasticizer is formed in the bottom region of each of the plurality of vias by applying the plasticizer onto the dielectric layer at a controlled rotational speed greater than 0 rpm and less than or equal to 3000 rpm.

14. The method of manufacturing a semiconductor structure according to claim 13, wherein the plasticizer is formed in the bottom region of each of the plurality of vias by at least two coating stages, and the two coating stages have different controlled rotation speeds.

15. A method for manufacturing a semiconductor structure, characterized in that, include: A plasticizer is applied to the dielectric layer of a substrate using a coating device, allowing the plasticizer to flow into multiple vias of the dielectric layer. The coating device includes: A substrate support stage, configured to support the substrate; A dispensing unit is disposed above the substrate support stage and configured to supply the plasticizer; A control unit, electrically connected to the dispensing unit and configured to dynamically adjust the position and angle of the dispensing unit relative to the substrate; and A monitoring unit is disposed above the substrate support platform and configured to monitor the position of the plasticizer in real time; and A photoresist layer is formed in contact with the plasticizer, so that the photoresist layer interacts with the plasticizer and forms an expanded portion in the photoresist layer.

16. The method of manufacturing a semiconductor structure according to claim 15, wherein the photoresist layer is formed using the coating apparatus.

17. The method of manufacturing a semiconductor structure according to claim 15, wherein the expanded portion occupies 20% to 40% of the height of each of the plurality of vias.

18. The method of manufacturing a semiconductor structure according to claim 17, wherein the expanded portion contacts the substrate.

19. The method of manufacturing a semiconductor structure according to claim 15, wherein the expanded portion is formed between a portion of the photoresist layer that does not interact with the plasticizer and the plasticizer that does not interact with the photoresist layer.

20. The method of manufacturing a semiconductor structure according to claim 19, wherein the expanded portion and the plasticizer that does not interact with the photoresist layer together occupy 20% to 40% of the height of each of the plurality of vias.

Images