Semiconductor structure and forming method thereof

Abstract

In some embodiments, during a bonding process for forming a semiconductor package, an ultra-thin bonding layer (e.g., between 5 angstroms and 2500 angstroms in thickness) is used at the bonding interface instead of one or both bonding layers used at the bonding interface in a semiconductor package without structures of the present disclosure. In some examples, a plasma process may be performed to activate one of the bonding surfaces, and an intermediate compound layer is formed at the bonding interface by a chemical reaction between materials of the bonding surfaces. The intermediate compound layer provides enhanced adhesion to the ultrathin bonding layer. The enhanced adhesion, ultra-thin thickness, and excellent flatness of the ultra-thin bonding layer greatly improve heat dissipation efficiency in the formed semiconductor package. Additional advantages include reduced height of the semiconductor package, and cheaper materials can be used for certain components of the semiconductor package. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density has largely come from repeated reductions in the minimum feature size of components, allowing more components to be integrated into a given area.

[0003] As the demand for smaller electronic devices increases, there is a need for smaller and more creative packaging technologies for semiconductor dies. An example is the integrated system on chip (SoIC) technology, which is a three-dimensional (3D) inter-chip stacking technology that integrates active and / or passive chips into a single system on chip (SoC) system. The SoIC platform uses front-end technology and precision methods from silicon foundries to stack chips in a 3D manner. The SoIC platform allows for the integration of known good dies (KGDs) with different chip sizes, functions, and wafer node technologies. The resulting structure enables ultra-high density vertical stacking to achieve high performance, low power consumption, and low resistance inductance capacitance (RLC). These packaging technologies enable the production of semiconductor devices with enhanced functionality and small footprint. SUMMARY

[0004] Embodiments of the present application provide, in one aspect, a method of forming a semiconductor structure, the method comprising: attaching a first semiconductor die to a carrier substrate, wherein the first semiconductor die comprises a first substrate, a first contact pad, and a first dielectric layer surrounding the first contact pad, wherein the first contact pad and the first dielectric layer are at a first side of the first substrate facing away from the carrier substrate; bonding a second semiconductor die to the first semiconductor die, wherein the second semiconductor die comprises a second substrate, a second contact pad, a second dielectric layer surrounding the second contact pad, and a support substrate attached to the second substrate, wherein the second contact pad and the second dielectric layer are at a first side of the second substrate facing the first semiconductor die, wherein the support substrate is at an opposite second side of the second substrate, wherein bonding the second semiconductor die comprises bonding the second contact pad to the first contact pad without solder, and bonding the second dielectric layer to the first dielectric layer by direct dielectric-to-dielectric bonding; forming a gap fill layer around the second semiconductor die over the carrier substrate; forming a first bonding film over the gap fill layer and the second semiconductor die, wherein the first bonding film is a dielectric material; activating a surface of a heat sink using a plasma process; and bonding the activated surface of the heat sink to the first bonding film.

[0005] Another aspect of this application provides a method for forming a semiconductor structure, the method comprising: attaching a bottom die to a carrier substrate, wherein the bottom die includes a first semiconductor substrate, an interconnect structure located on a first side of the first semiconductor substrate, and a substrate via (TSV) extending from a conductive component of the interconnect structure into the first semiconductor substrate, wherein, after attaching the bottom die, the interconnect structure is situated between the carrier substrate and the first semiconductor substrate of the bottom die; forming a first gap fill layer on the carrier substrate around the bottom die; and, after forming a first molding material, thinning the first semiconductor substrate from a second side of the first semiconductor substrate away from the carrier substrate, wherein, after the thinning, the substrate via protrudes into the first semiconductor substrate. Above the second side; after the thinning, a first dielectric layer is formed above the first gap fill layer and the bottom die; a first contact pad is formed in the first dielectric layer, and the first contact pad is electrically coupled to the substrate via, wherein the substrate via provides an electrical connection from the conductive component to the first contact pad through the first semiconductor substrate; a second contact pad of the top die is bonded to the first contact pad; after bonding the second contact pad, a second gap fill layer is formed around the top die above the first dielectric layer; a bonding layer is formed above the second gap fill layer and the top die, wherein the bonding layer comprises a dielectric material; the surface of the heat sink is treated by performing a plasma process; and after the treatment, the surface of the heat sink is bonded to the bonding layer.

[0006] This application provides another aspect of a semiconductor structure, comprising: a bottom die; a first gap-filling layer surrounding the bottom die; a top die bonded to the bottom die, wherein a first contact pad of the bottom die is bonded to a second contact pad of the top die via direct metal-to-metal bonding, and a first dielectric layer of the bottom die is bonded to a second dielectric layer of the top die via direct dielectric-to-dielectric bonding; a second gap-filling layer above the first gap-filling layer and surrounding the top die; a bonding layer above the second gap-filling layer and the top die; a heat sink bonded to the bonding layer; and an intermediate compound layer between the bonding layer and the heat sink, wherein the intermediate compound layer comprises a compound material, wherein the compound material comprises chemical bonds between a first material of the heat sink and a second material of the bonding layer. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0008] Figures 1 to 3 Cross-sectional views of a semiconductor device at various manufacturing stages according to an embodiment are shown.

[0009] Figure 4 A cross-sectional view of a semiconductor device according to an embodiment is shown.

[0010] Figures 5 to 11 Cross-sectional views of the semiconductor structure at various manufacturing stages according to an embodiment are shown.

[0011] Figures 12 to 14 Cross-sectional views of a semiconductor structure at various manufacturing stages are shown according to another embodiment.

[0012] Figure 15 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0013] Figure 16 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0014] Figure 17 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0015] Figure 18 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0016] Figure 19 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0017] Figure 20 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0018] Figure 21 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0019] Figure 22 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0020] Figure 23 A cross-sectional view of a semiconductor structure according to another embodiment is shown.

[0021] Figure 24 A cross-sectional view of a semiconductor structure according to yet another embodiment is shown.

[0022] Figure 25A flowchart of a method for forming a semiconductor structure according to an embodiment is shown. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Throughout the description, unless otherwise stated, the same or similar reference numerals in different figures refer to the same or similar components formed using the same or similar materials and by the same or similar methods.

[0024] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] Embodiments of this disclosure are discussed in the context of forming SoIC packages, wherein it should be understood that the disclosed bonding schemes, structures and methods can be applied to other types of semiconductor structures, such as integrated fan-out (InFO) packages, integrated fan-out stacked packages (InFO_PoP) structures, etc.

[0026] In some embodiments, during the bonding process for forming a semiconductor package, an ultrathin bonding layer (e.g., with a thickness between 5 angstroms and 2500 angstroms) is used at the bonding interface instead of one or two bonding layers used at the bonding interface in semiconductor packages without the structure disclosed herein. In some embodiments, a plasma process may be performed to activate one of the bonding surfaces, and an intermediate compound layer is formed at the bonding interface through a chemical reaction between the materials of the bonding surfaces. The intermediate compound layer provides enhanced adhesion to the ultrathin bonding layer. The enhanced adhesion, ultrathin thickness, and excellent flatness of the ultrathin bonding layer significantly improve the heat dissipation efficiency in the formed semiconductor package. Additional advantages include a reduced height of the formed semiconductor package and the ability to use cheaper materials (e.g., silicon) for certain components of the semiconductor package (e.g., heatsinks).

[0027] Figures 1 to 3 Cross-sectional views of a semiconductor device 50 at various manufacturing stages according to an embodiment are shown. In some embodiments, the semiconductor device 50 is a semiconductor die (also referred to as a die). In the illustrated embodiment, the semiconductor device 50 serves as a top die in the formation of an integrated system-on-a-chip (SoIC) package. Details are discussed below.

[0028] exist Figure 1 In this embodiment, device region 13 is formed in semiconductor substrate 11 (also referred to as substrate 11). Device region 13 includes active electronic components (e.g., transistors, diodes) or passive electronic components (e.g., resistors, capacitors, inductors) formed in or on substrate 11. The electronic components in device region 13 are interconnected by subsequently formed interconnect structures 16 to form the functional circuitry of semiconductor die 50.

[0029] Substrate 11 may be a doped or undoped semiconductor substrate (e.g., a silicon substrate), or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0030] The electronic components in device region 13 include a wide variety of active components (e.g., transistors, diodes) and / or passive devices (e.g., capacitors, resistors, inductors), etc. The electronic components can be formed within or on substrate 11 using any suitable method.

[0031] Interconnect structure 16 is formed over substrate 11 and device region 13. Interconnect structure 16 may include an interlayer dielectric (ILD, not separately labeled) filling the space between gate stacks of transistors (not shown) in device region 13. According to some embodiments, the ILD is formed of silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), etc. The ILD can be formed using spin coating, flowable chemical vapor deposition (FCVD), etc. According to some embodiments of this disclosure, the ILD can also be formed using deposition methods such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0032] Contact plugs are formed in the ILD and serve to electrically connect device region 13 to metal lines and vias thereon. According to some embodiments of this disclosure, the contact plugs are formed of or comprise conductive materials selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Forming the contact plugs may include forming contact openings in the ILD, filling the contact openings with conductive material, and performing planarization processes (such as chemical mechanical polishing (CMP) or mechanical polishing) to make the top surface of the contact plug flush with the top surface of the ILD. In this discussion, unless otherwise stated, the terms "conductive" and "conductive material" are used to refer to "conductive" and "conductive material," respectively.

[0033] According to some embodiments, the interconnect structure 16 also includes a plurality of dielectric layers 15 and a plurality of conductive components 17, such as metal wires and vias, located within the dielectric layers 15. According to some embodiments, the dielectric layers 15 (also referred to as intermetallic dielectrics (IMDs)) may include low-k dielectric layers. For example, the dielectric constant (k value) of the low-k dielectric layer may be lower than about 3.5 or 3.0. The low-k dielectric layer may include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc.

[0034] Forming metal lines and vias in dielectric layer 15 can include single-damascene and / or dual-damascene processes. In a single-damascene process for forming metal lines or vias, a trench or via opening is first formed in one of the dielectric layers 15, and then the trench or via opening is filled with a conductive material. A planarization process (such as CMP) is then performed to remove excess conductive material above the top surface of the dielectric layer, leaving metal lines or vias in the respective trench or via openings. In a dual-damascene process, both trenches and via openings are formed in the dielectric layer, with the via opening located below and connected to the trench. Conductive material is then filled into the trench and via opening to form metal lines and vias, respectively. The conductive material can include a diffusion barrier layer and a copper-containing metal material located above the diffusion barrier layer. The diffusion barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0035] The metal lines of interconnect structure 16 include top conductive components, such as metal lines or metal pads, located in the top dielectric layer of interconnect structure 16 (e.g., away from substrate 11). According to some embodiments, the top dielectric layer is formed of a low-k dielectric material similar to that of the underlying dielectric layer 15. In other embodiments, the top dielectric layer is formed of a non-low-k dielectric material, such as silicon oxide, silicon nitride, undoped silicate glass, etc. The top conductive components in the top dielectric layer may also be formed of copper or a copper alloy and may have a dual-damascene structure or a single-damascene structure.

[0036] In some embodiments, a plurality of semiconductor dies 50 are formed on a substrate 11 (e.g., a wafer). A probing process can be performed to test the semiconductor dies 50 and identify defective semiconductor dies 50. The probing process can be performed via the top conductive components of the interconnect structure 16.

[0037] Next, in Figure 2 In this process, a bonding layer 23 is formed on the interconnect structure 16, and a bonding layer 21 (also referred to as an ultrathin bonding layer 21) is formed on the support substrate 19. The support substrate 19 is a pre-formed substrate (e.g., formed before bonding and forming the bonding layer 21), such as a silicon substrate. Next, the bonding layer 21 is bonded to the bonding layer 23, such that the support substrate 19 is attached to the substrate 11. In some embodiments, the bonding between the bonding layers 23 and 21 is achieved by dielectric-to-dielectric bonding (e.g., without the use of an adhesive layer). Further details of dielectric-to-dielectric bonding are discussed below.

[0038] In some embodiments, a bonding layer 23, such as alumina, silicon oxide, silicon carbonitride, titanium oxide, aluminum nitride, boron nitride, silicon oxynitride, or silicon oxycarbide, is formed from a suitable dielectric material using a suitable formation method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The thickness of the bonding layer 23 can be between about 5 angstroms and about 2500 angstroms. The thermal conductivity of the bonding layer 23 can be between about 0.5 W / m / Kelvin (W / (m·K)) and about 20 W / (m·K). In some embodiments, a bonding layer 21, such as alumina, silicon oxide, silicon carbonitride, titanium oxide, aluminum nitride, boron nitride, silicon oxynitride, or silicon oxycarbide, is formed from a suitable dielectric material using a suitable formation method, such as CVD, ALD, etc. The thickness of the bonding layer 21 can be between about 5 angstroms and about 2500 angstroms. In some embodiments, the thickness of the bonding layer 23 is between about 10 times and 100 times the thickness of the bonding layer 21. The thermal conductivity of bonding layer 21 can be between about 0.5 W / (m·K) and about 20 W / (m·K). In some embodiments, bonding layers 21 and 23 are formed of the same dielectric material. In other embodiments, bonding layers 21 and 23 are formed of different dielectric materials.

[0039] Next, in Figure 3In this process, a thinning process is performed from the back side of substrate 11 to reduce the thickness of substrate 11. The thinning process can be a mechanical polishing process, a chemical mechanical planarization (CMP) process, an etch-back process, a combination thereof, etc. After the thinning process, a back-side interconnect structure 26 is formed on the back side of substrate 11. In some embodiments, the back-side interconnect structure 26 includes one or more dielectric layers 25 and conductive components 27 (e.g., metal lines, vias, bonding pads) formed in one or more dielectric layers 25. The conductive components 27 of the back-side interconnect structure 26 are electrically coupled to electronic components in device region 13. The materials and formation methods of the back-side interconnect structure 26 can be the same as or similar to those of interconnect structure 16, and therefore will not be repeated. Note that, for simplicity, Figure 3 The diagram shows a dielectric layer 25 and a conductive layer 27 of a back-side interconnect structure 26. It should be understood that the number of dielectric layers 25 and the number of conductive layers 27 in the back-side interconnect structure 26 (or interconnect structure 16) can be any suitable number.

[0040] Next, along Figure 3 The dicing region shown by the dashed line 18 in the figure undergoes a dicing process (also called a cutting process) to separate the multiple semiconductor dies 50 formed on the substrate 11 into individual (e.g., isolated) semiconductor dies 50. Known Good Die (KGD) pieces of the semiconductor dies 50 are used in subsequent processing steps to form SoIC packages. Note that in Figure 3 In the example, each semiconductor die 50 includes a portion of a support substrate 19 (e.g., bulk silicon material) bonded to a substrate 11 via bonding layers 21 and 23. In some embodiments, the support substrate 19 in the semiconductor die 50 serves as a built-in heat sink (also referred to as a built-in heat sink) for the semiconductor die 50, which facilitates heat dissipation away from the semiconductor die 50 in the subsequently formed SoIC package. Furthermore, the thermal conductivity of the bonding layers 21 and 23 of the semiconductor die 50, as well as their small thickness, also contribute to heat dissipation away from the semiconductor die 50.

[0041] Figure 4 A cross-sectional view of a semiconductor device 50A according to an embodiment is shown. In the illustrated embodiment, semiconductor device 50A is a semiconductor die similar to semiconductor die 50, but has a substrate through-hole (TSV) 14 and lacks a support substrate 19 and bonding layers 21 and 23. As will be readily understood by those skilled in the art, semiconductor device 50A can be formed using the same or similar formation methods as semiconductor device 50, and therefore details are not repeated. A probing process is performed to test semiconductor die 50A, and the tested semiconductor die 50A (e.g., KGD) is used to form a SoIC package in subsequent processing.

[0042] exist Figure 4In the example, TSV 14 is electrically coupled to a conductive component 17 of the interconnect structure 16 of the semiconductor device 50A. In the illustrated embodiment, TSV 14 extends from the front side of substrate 11 (or from a location within the interconnect structure 16) to an intermediate level of substrate 11. The intermediate level of substrate 11 is located between the front and back sides of substrate 11. In some embodiments, each TSV 14 is surrounded by a dielectric isolation layer (e.g., a diffusion barrier layer, not shown) for electrically insulating the sidewalls of the respective TSV 14 from substrate 11.

[0043] Figures 5 to 11 Cross-sectional views of a semiconductor structure 100 at various manufacturing stages according to an embodiment are shown. In the illustrated embodiment, the semiconductor structure 100 is a SoIC package and therefore may also be referred to as semiconductor package 100 or SoIC package 100. In the illustrated embodiment, semiconductor dies 50A and 50 serve as the bottom die and top die of the SoIC package, respectively.

[0044] refer to Figure 5 The front side of the semiconductor die 50A is attached to the carrier 101 (also referred to as the carrier substrate). It should be understood that although one semiconductor die 50A is shown, multiple semiconductor dies 50A are attached to the carrier 101, and the multiple semiconductor dies 50A can be arranged in an array. In some embodiments, Figures 5 to 11 The processing steps involve forming multiple semiconductor packages 100 in a wafer structure and performing a subsequent dicing process to separate the multiple semiconductor packages 100 into individual (e.g., separate) semiconductor packages 100. For simplicity, Figures 5 to 11 A cross-sectional view corresponding to one of the semiconductor packages 100 formed in the wafer structure is shown.

[0045] According to some embodiments, the carrier 101 is a semiconductor carrier such as a silicon carrier, and the semiconductor die 50A is attached to the carrier 101 using an adhesive layer such as a die attachment film (DAF). In some embodiments, a first dielectric layer (not shown), such as silicon oxide, silicon carbide, silicon nitride, etc., is formed on the upper surface of the carrier 101, and a second dielectric layer (not shown) that is the same as or similar to the first dielectric layer is formed on the outer surface of the interconnect structure 16 of each semiconductor die 50A (e.g., away from the substrate 11). The semiconductor die 50A is then attached to the carrier 101 by a dielectric-to-dielectric bonding between the first and second dielectric layers. In some embodiments, the carrier 101 is a transparent substrate (such as a glass substrate), and an adhesive layer (such as a photothermal conversion (LTHC) material) is formed on the upper surface of the carrier 101 for attaching the semiconductor die 50A.

[0046] Next, as Figure 5As shown, a gap-filling process is performed to fill the gap between adjacent semiconductor dies 50A, and the semiconductor dies 50A are encapsulated in a gap-filling layer 103 (also referred to as a sealant). According to some embodiments, the gap-filling layer 103 includes a dielectric pad and a dielectric gap-filling material located above the dielectric pad. The dielectric pad and dielectric gap-filling material are not shown separately. The dielectric pad may be formed of a material that has good adhesion to the semiconductor die 50A. According to some embodiments, the dielectric pad is formed of or includes silicon nitride. The dielectric pad is formed in a conformal deposition process and is therefore a conformal layer. The dielectric gap-filling material may be formed of an oxide-based dielectric material, such as silicon oxide, silicon oxynitride, silicate glass, etc. The dielectric pad and dielectric gap-filling material may be formed by deposition processes such as CVD, ALD, combinations thereof, etc.

[0047] According to an optional embodiment, the gap filling layer 103 is formed of or includes a molding material, such as a molding compound, a molding underfill, etc. The corresponding process may include dispensing a dielectric material in a flowable form and curing the dielectric material. Next, after depositing the gap filling layer 103, a planarization process such as CMP is performed to make the top surface of the semiconductor die 50A flush with the top surface of the gap filling layer 102.

[0048] Next, in Figure 6 In this process, the substrate 11 and gap fill layer 103 of the semiconductor die 50A are recessed to expose the upper portion of the TSV 14. In some embodiments, one or more etching processes are performed using an etchant that is selective to the materials of the substrate 11 and the gap fill layer 103 (e.g., has a higher etch rate) to cause the substrate 11 and the gap fill layer 103 to be recessed. The TSV 14 is essentially not etched by the one or more etching processes and thus protrudes above the (recessed) substrate 11. Hereinafter, the remaining portion of the gap fill layer 103 after the one or more etching processes will be referred to as the gap fill region 103.

[0049] Next, a dielectric isolation layer 105 is formed over the semiconductor die 50A, over the gap filling region 103, and around the TSV 14. The dielectric isolation layer 105 can be formed from a suitable dielectric material (such as silicon oxide, silicon nitride, low-k dielectric, etc.) using a suitable formation method (such as CVD, ALD, etc.). Next, a planarization process such as CMP is performed to achieve a flush upper surface between the TSV 14 and the dielectric isolation layer 105. In other words, after the planarization process, the dielectric isolation layer 105 covers (e.g., contacts and extends along the sidewalls of the TSV 14) the sidewalls of the TSV 14 and exposes the upper surface of the TSV 14. In some embodiments, the dielectric isolation layer 105 after the planarization process is considered part of the semiconductor die 50A.

[0050] Next reference Figure 7 A bonding layer 107 is deposited above the dielectric isolation layer 105, and bonding pads 109 (also referred to as contact pads) are formed in the bonding layer 107. The bonding layer 107 can be formed from a silicon-containing dielectric material, such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbonoxynitride, silicon carbonitride, silicon carbonitride, etc., or combinations thereof, using a suitable formation method (such as CVD, ALD, combinations thereof). A planarization process can then be performed to achieve a flush upper surface of the bonding layer 107.

[0051] Bond pads 109 are formed in the bonding layer 107. According to some embodiments, the bonding pads 109 are formed by etching the bonding layer 107 to form openings in the bonding layer 107 that expose the upper surface of the TSV 14, filling the openings with a conductive material, and performing a planarization process such as CMP. Therefore, the top surfaces of the bonding pads 109 and the bonding layer 107 are coplanar. The bonding pads 109 may include conductive materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc. For example, each bonding pad 109 may include a titanium nitride barrier layer and a copper region located on the titanium nitride barrier layer. In some embodiments, the bonding layer 107 and the bonding pads 109 are considered as part of the semiconductor die 50A.

[0052] Next reference Figure 8 The semiconductor die 50 is bonded to the semiconductor die 50A. Although one semiconductor die 50 is shown, the semiconductor die 50 shown represents multiple semiconductor dies 50, each semiconductor die 50 being located above and bonded to a corresponding underlying semiconductor die 50A. Bonding can be performed via a face-to-back bonding process, wherein the front side of the semiconductor die 50 is bonded to the back side of the semiconductor die 50A.

[0053] In the illustrated embodiment, the bonding pads 109 of the semiconductor die 50A are bonded to the corresponding bonding pads of the conductive components 27 of the semiconductor die 50 via metal-to-metal bonding. Furthermore, the bonding layer 107 of the semiconductor die 50A is bonded to the topmost dielectric layer 25 of the back-side interconnect structure 26 of the semiconductor die 50 via dielectric-to-dielectric bonding. Figure 8 The structure shown is a wafer structure including multiple semiconductor packages 100, and can be referred to as a reconstructed wafer 100 prior to the subsequent dicing process, and more components will be formed to further expand the reconstructed wafer 100 in subsequent processing steps.

[0054] Dielectric-to-dielectric bonding (also known as direct dielectric-to-dielectric bonding) and metal-to-metal bonding (also known as direct metal-to-metal bonding) are bonding techniques that can be used in direct bonding processes to bond two semiconductor devices together without the use of intermediate layers (e.g., solder or adhesive layers). Direct bonding processes use dielectric-to-dielectric bonding and / or metal-to-metal bonding to achieve robust and reliable connections at the interface of two devices. Metal-to-metal bonding involves aligning on metal surfaces (such as copper or aluminum surfaces) and applying sufficient pressure, often accompanied by heat treatment, to promote atomic diffusion and interface adhesion without intermediate layers (e.g., solder). Dielectric-to-dielectric bonding uses surfaces such as silicon dioxide or other insulating materials, which, when aligned under appropriate conditions (e.g., elevated temperatures and / or pressure applied at the surface), form a bond through forces such as van der Waals forces. Direct bonding processes help create high-density, low-resistance connections while reducing or minimizing the thermal budget.

[0055] Still referencing Figure 8 Multiple dummy dies 111 are also attached to the bonding layer 107. According to some embodiments, each dummy die 111 is attached via layer 108. Layer 108 may be a bonding layer of a silicon-containing dielectric material, such as silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, combinations thereof, etc. The dummy dies 111 can be attached via a dielectric-to-dielectric bonding between bonding layers 107 and 108. According to some embodiments, the same annealing process may be performed to facilitate direct bonding of the dummy dies 111 and the semiconductor die 50 to the underlying structure.

[0056] According to an alternative embodiment, the dummy die 111 is attached to the bonding layer 107 via an adhesive layer (e.g., DAF). In other words, layer 108 may be DAF.

[0057] The dummy die 111 provides structural support for the formed SoIC package 100, thus improving the structural integrity of the SoIC package 100. Furthermore, the dummy die 111 also serves as the semiconductor die 50A and the subsequently formed heat sink (e.g., see...). Figure 11 The heat dissipation path between 121).

[0058] According to some embodiments, the entire dummy die 111 is formed of a homogeneous material, in which no other materials or structures are present. For example, the dummy die 111 may be formed of a semiconductor material, such as silicon (e.g., bulk silicon), which has a thermal conductivity of about 150 W / (m·K). The dummy die 111 may optionally be formed of a material with a thermal conductivity higher than that of silicon. For example, the dummy die 111 may be formed of a suitable dielectric material or a suitable conductive material (such as a metal). For example, the dummy die 111 may be formed of SiC (thermal conductivity of about 160 W / (m·K)), AlN (thermal conductivity of about 180 W / (m·K)), Ag (thermal conductivity of about 429 W / (m·K)), etc., but other materials such as Al, BeO, Cu, Au, SiCN, etc. may also be used. As will be discussed in more detail below, the disclosed SoIC package 100 includes a semiconductor die 50 / 50A and a heat sink (e.g., see Figure 11 A low thermal resistance (or equivalent, high heat dissipation efficiency) is achieved between 121 and silicon, a level of thermal resistance unattainable in previous designs. As a result, the dummy die 111 in the disclosed SoIC package can be formed from silicon instead of other materials with higher thermal conductivity, while still achieving satisfactory heat dissipation for the formed SoIC package. Note that the manufacturing cost and time of the dummy die 111 formed from silicon can be significantly lower than that of dummy dies 111 formed from other materials (such as those listed above).

[0059] Next, refer to Figure 9 A gap-filling region 113 (also referred to as a sealant) is formed. The formation process, structure, and materials of the gap-filling region 113 can be the same as or similar to those of the gap-filling regions 103. For example, the gap-filling region 113 may include a dielectric pad and a dielectric gap-filling layer located above the dielectric pad. Optionally, the gap-filling region 113 may include a molding compound, a molded underfill, etc. A planarization process is performed to make the top surfaces of the support substrate 19 of the semiconductor die 50, the dummy die 111, and the gap-filling region 113 flush.

[0060] Next, a bonding layer 115 (also referred to as a bonding film) is deposited on the support substrate 19, the dummy die 111, and the gap filling region 113 of the semiconductor die 50. A planarization process can then be performed to make the top surface of the bonding layer 115 flush. In some embodiments, the planarization process is omitted because the deposited bonding layer 115 already has good planarity (e.g., formed by an ALD process). In some embodiments, the bonding layer 115 is formed from a suitable dielectric material, such as alumina (e.g., AlO), using a suitable formation method (e.g., CVD, ALD, etc.). x ), silicon dioxide (e.g., SiO2) xThe bonding layer 115 may be made of silicon carbonitride (e.g., SiCN), titanium oxide (e.g., TiO2), aluminum nitride (e.g., AlN), boron nitride (e.g., BN), silicon oxynitride (e.g., SiON), or silicon oxycarbide (e.g., SiOC). The thickness of the bonding layer 115 may be between about 5 angstroms and about 2500 angstroms. The thermal conductivity of the bonding layer 115 may be between about 0.5 W / (m·K) and about 20 W / (m·K). In some embodiments, the bonding layer 115 is formed of the same material as the bonding layer 21 of the semiconductor die 50.

[0061] Next, as Figure 10 As shown, a plasma process 123 is performed to treat (e.g., activate) the surface of the heat sink 121 in preparation for bonding the heat sink 121 to the bonding layer 115. In the illustrated embodiment, the heat sink 121 is pre-formed prior to the plasma process 123.

[0062] According to some embodiments, the entire heat sink 121 is formed of a homogeneous material, without any other materials or structures. For example, the heat sink 121 may be formed of a semiconductor material, such as silicon (e.g., bulk silicon material, such as a silicon wafer). The heat sink 121 may optionally be formed of a suitable dielectric or conductive material, such as the materials listed above for the pseudo die 111. In an example embodiment, the heat sink 121 and the pseudo die 111 are formed of silicon. Because the disclosed SoIC package achieves excellent heat dissipation, the pseudo die 111 and the heat sink 121 in the disclosed SoIC package can be formed of silicon instead of other materials with higher thermal conductivity, while still achieving satisfactory heat dissipation for the formed SoIC package. Note that the manufacturing cost and time of the heat sink 121 formed of silicon can be much lower than that of heat sinks formed of other materials (such as those listed above for the pseudo die 111).

[0063] In some embodiments, a plasma process is performed by exciting a gas source into plasma and then treating the surface of a heat sink 121 (e.g., silicon) with plasma. The gas source may be an inert gas (e.g., Ar, He, Ne), a reactive gas (e.g., N2, O2, H2, NH3), or a mixture of inert and reactive gases (e.g., a mixture of Ar and O2, a mixture of N2 and H2, or a mixture of Ar and N2). The surface of the heat sink 121 (e.g., silicon) is activated by a plasma process 123. In some embodiments, plasma bombardment breaks surface bonds and creates dangling bonds on the surface of the heat sink 121 (e.g., the silicon surface). In some embodiments, the plasma process 123 creates reactive sites (e.g., free radicals) on the surface of the heat sink 121 (e.g., the silicon surface). As a result of the plasma process 123, the treated surface of the heat sink 121 becomes chemically reactive and / or has a higher surface energy.

[0064] Next, in Figure 11 In some embodiments, the heat sink 121 is bonded to the bonding layer 115 by pressing the processed surface of the heat sink 121 against the upper surface of the bonding layer 115 (e.g., direct contact). In some embodiments, the processed surface of the chemically reactive heat sink 121 forms a chemical bond with the bonding layer 115. As a result, an intermediate compound layer 125 (also referred to as an intermediate layer or interface layer) is formed between the bonding layer 115 and the heat sink 121. In other words, the intermediate compound layer 125 comprises a compound material formed through a chemical reaction between the material of the heat sink 121 (e.g., silicon) and the material of the bonding layer 115. As an example, when the bonding layer 115 is made of AlO... x When the heat sink 121 is formed of silicon (e.g., Si), the compound material of the intermediate compound layer 125 is silicon alumina (e.g., AlSiO2). y As another example, when the bonding layer 115 is formed of TiO2, AlN, or BN, and the heat sink 121 is formed of Si, the compound material of the intermediate compound layer 125 is TiSiO2, AlN, or BN. x AlSiN or BSiN. As yet another example, when the bonding layer 115 is made of a silicon-containing material (such as SiO2), x When the intermediate compound layer 125 is formed of Si, and the heat sink 121 is formed of Si, the compound material of the intermediate compound layer 125 is a compound material with different atomic ratios between silicon atoms and other atoms in the compound material, such as SiO₂, SiCN, SiON, or SiCO. y SiCN x SiON x or SiCO x In some embodiments, the thickness of the intermediate compound layer 125 is between about 1 angstrom and about 100 angstroms. In some embodiments, the thickness of the intermediate compound layer 125 is between about 1 / 10 and about 1 / 100 of the thickness of the bonding layer 115. The thermal conductivity of the intermediate compound layer 125 can be between about 0.5 W / (m·K) and about 20 W / (m·K).

[0065] Although Figure 10 The example illustrates the application of plasma process 123 to heat sink 121, but those skilled in the art will readily understand that plasma process 123 may also be optionally applied to Figure 9 The upper surface of the bonding layer 115 is then bonded to the active surface of the bonding layer 115 by a heat sink 121. The resulting SOIC package has the same characteristics as... Figure 11 The same or similar intermediate compound layer 125 is shown. These and other modifications are intended to be included within the scope of this disclosure.

[0066] For vertically stacked packages, such as SoIC packages, more dies are stacked together to increase transistor integration density. However, the higher the transistor density, the more heat is generated per unit area. Due to heat accumulation within the package, heat dissipation becomes a major challenge, which, if not handled properly, can lead to performance degradation and / or device failure.

[0067] In reference packages without the structure disclosed herein, the bonding between the heat sink 121 and the reconstructed wafer 100 is typically achieved using two bonding layers. For example, in the case of... Figure 11 A first bonding layer (e.g., a dielectric layer) is formed at the same location as bonding layer 115 in the heat sink 121, and a second bonding layer (e.g., a dielectric layer) is formed at the lower surface of the heat sink 121. The first and second bonding layers are then bonded together, for example, by dielectric-to-dielectric bonding. In this disclosure, the first and second bonding layers are typically much thicker than bonding layer 115, such as about 10 times and about 100 times thicker, respectively. For example, the first and second bonding layers of the reference package may have thicknesses between about 5,000 angstroms and about 20,000 angstroms. The significantly larger thickness of the first and second bonding layers in the reference package greatly reduces the heat dissipation efficiency between the heat sink 121 and the semiconductor die 50. Furthermore, the adhesion between the first and second bonding layers may be much weaker than the adhesion achieved in this disclosure. Weak adhesion can result in void regions (e.g., empty spaces or microbubbles) between the first and second bonding layers. Void regions further reduce the heat dissipation efficiency in the reference package.

[0068] The embodiments disclosed herein use an ultrathin bonding layer 115, the thickness of which is between approximately 1 / 10 and approximately 1 / 100 of the thickness of the first bonding layer (or second bonding layer) used in the reference package. This ultrathin bonding layer 115 achieves better heat dissipation efficiency and reduces the height of the formed semiconductor structure. Furthermore, the bonding layer 115 achieves enhanced / improved adhesion compared to the reference package, for example, because the intermediate compound layer 125 includes chemical bonds between the two layers bonded together. In contrast, the bonding between the first and second bonding layers used in the reference package can include weaker physical bonds achieved, for example, by van der Waals forces. Enhanced adhesion can prevent or reduce the formation of void regions (e.g., microbubbles) between the bonded layers, further improving heat dissipation efficiency. Moreover, due to the smaller thickness of the bonding layer 115, a formation method with excellent flatness (such as ALD) can be used to form the bonding layer 115. The improved flatness of the bonding layer 115 further facilitates bonding with another layer and can eliminate the need for planarization processes used to planarize the bonding layer 115. Note that due to the enormous thickness of the first bonding layer (or the second bonding layer) and the time required to achieve that thickness, forming methods such as ALD may be impractical or uneconomical for forming the first and second bonding layers used in the reference package.

[0069] Still referencing Figure 11 After bonding the heat sink 121, the carrier 101 is debonded, a redistribution structure (RDS) 132 is formed on the front side of each semiconductor die 50A, and an electrical connector 137 is formed on the RDS 132.

[0070] In some embodiments, the carrier 101 is debonded using a suitable removal process, such as etching, CMP, mechanical polishing, or combinations thereof. In embodiments where the carrier 101 is a glass carrier and an LTHC coating material is used to bond the semiconductor die 50A, the carrier 101 can be debonded by irradiating the LTHC coating material with light (e.g., UV light or a laser beam) through the carrier 101, causing the LTHC coating material to decompose and thereby releasing the reconstructed wafer 100 from the carrier 101. In embodiments where an adhesive layer (e.g., DAF) is used to bond the semiconductor die 50A, the adhesive can also be removed (at least partially) by a carrier debonding process. After the carrier debonding process, the remaining portion of the adhesive layer can be removed by an etching process, exposing the conductive components 17 (e.g., contact pads) of the interconnect structure 16 of the semiconductor die 50A.

[0071] Next, RDS132 is formed on the interconnect structure 16 of the semiconductor die 50A and electrically coupled to exposed conductive components 17 of the interconnect structure 16. The redistribution structure 132 includes conductive components, such as one or more layers of wires 133 and vias 135 formed in one or more dielectric layers 131. In some embodiments, the one or more dielectric layers 131 are formed of polymers such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 131 is formed of materials such as nitrides, such as silicon nitride; oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG), etc. The one or more dielectric layers 131 can be formed by any acceptable deposition process, such as spin coating, CVD, lamination, etc., or combinations thereof.

[0072] In some embodiments, the conductive components of the redistribution structure 132 include wires 133 and vias 135 formed of a suitable conductive material (such as copper, titanium, tungsten, aluminum, etc.). The conductive components can be formed, for example, by forming an opening in the dielectric layer 131 to expose the underlying conductive components, forming a seed layer over the dielectric layer 131 and in the opening, forming a patterned photoresist with a design pattern over the seed layer, plating (e.g., electroplating or electroless plating) a conductive material over the design pattern and the seed layer, and removing portions of the photoresist and the seed layer on which no conductive material is formed.

[0073] Next, as Figure 11 As shown, connector 137 (also referred to as a conductive bump, external connector) is formed on RDS 132 and electrically coupled to conductive parts of RDS 132 to provide electrical connection to external circuitry. Connector 137 may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel-palladium immersion gold (ENEPIG) technology, combinations thereof (e.g., metal pillars with solder balls attached), etc. Connector 137 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, connector 137 includes metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, etc., with or without solder material 139. The metal pillars may be solderless and have substantially vertical or tapered sidewalls.

[0074] In some embodiments, a plurality of SoIC packages are formed in the reconstructed wafer 100. Along Figure 11 The cutting area shown by the dashed line 140 undergoes a slitting process (also known as a cutting process). After the slitting process, multiple individual (e.g., separate) SoIC packages 100 are formed. Figure 11 One of the SoIC packages 100 is shown.

[0075] Figures 12 to 14 Cross-sectional views of a semiconductor structure 100A at various manufacturing stages according to another embodiment are shown. Figure 12 The structure can be executed and used to form Figure 9 The same or similar processing steps are used to form the structure, but the bonding layer 115 is not formed. Figure 12 The structure can also be referred to as the reconstructed wafer 100A prior to the subsequent dicing process.

[0076] Next, in Figure 13 In this process, a bonding layer 115 is formed on a heat sink 121 (e.g., bulk silicon material, silicon wafer). The materials and formation methods used for the bonding layer 115 are the same or similar to those discussed above, and therefore will not be repeated. Next, a plasma process 123 is performed to treat (e.g., activate) the surface of the bonding layer 115, the details of which are the same or similar to those discussed above, and therefore will not be repeated.

[0077] Next, in Figure 14 In this process, the treated (e.g., activated) surface of the bonding layer 115 is bonded to the reconstructed wafer 100A. For example, the bonding layer 115 is bonded to the semiconductor die 50, the dummy die 111, and the gap-filling region 113 of the reconstructed wafer 100A. Figure 14 As shown, an intermediate compound layer 125 is formed between the bonding layer 115 and the reconstructed wafer 100A through a chemical reaction between the material of the bonding layer 115 and the material of the reconstructed wafer 100A. In an alternative embodiment, a plasma process 123 is performed to treat (e.g., activate) the upper surfaces of the semiconductor die 50, the dummy die 111, and the gap-filling region 113 (instead of treating the bonding layer 115), and then the bonding layer 115 is bonded to the treated upper surfaces of the semiconductor die 50, the dummy die 111, and the gap-filling region 13 to form Figure 14 The structure.

[0078] Note that in Figure 14 In the example, the intermediate compound layer 125 comprises different portions, such as Figure 14 The intermediate compound layers 125 are designated as intermediate compound layers 125A and 125B, and these different portions comprise different compound materials. The different portions of the intermediate compound layers 125 (e.g., 125A and 125B) are formed at different locations between the bonding layer 115 and different regions of the reconstructed wafer 100A formed of different materials. The bonding layer 115 is composed of AlO₂... x The substrate 19 and the dummy die 111 are formed of Si, and the gap filling region 113 is formed of SiO. y In the formed example, the intermediate compound layers 125A and 125B respectively comprise AlSiO z and AlSiOw Where Z≠W. In other words, the atomic percentages of different atoms in the intermediate compound layers 125A and 125B are different. The bonding layer 115 is composed of AlO₂. x The substrate 19 and the dummy die 111 are formed of Si, and the gap filling region 113 is formed of SiN. y In another example of the formation, the intermediate compound layers 125A and 125B respectively comprise AlSiO z and AlSiN w .

[0079] In some embodiments, the gap-filling region 113 is formed of a molding material, which may be an organic polymer. In some embodiments, the surface chemistry and reactivity of the molding material differ from silicon or non-organic dielectric materials (e.g., SiO2). x or SiN x Therefore, the bonding mechanism between the bonding layer 115 and the molding material may be physical rather than chemical in nature. For example, the bonding layer 115 and the molding material of the gap-filling region 113 may be bonded by physical adhesion, van der Waals forces, etc., without a chemical reaction occurring between the bonding layer 115 and the molding material. As a result, no intermediate compound layer 125B is formed. In other words, in some embodiments where the gap-filling region 113 is formed of molding material, the intermediate compound layer 125 only includes Figure 14 The intermediate compound layer 125A is shown. In other words, in some embodiments, when the gap-filling region 113 is formed by molding material, the intermediate compound layer 125 only includes Figure 14 The discrete (e.g., individual) part marked as 125A.

[0080] Next, the carrier 101 is debonded to form the RDS 132, and the connector 137 is formed. A dicing process can then be performed to separate the reconstructed wafer 100A into individual semiconductor packages 100A. Details will not be repeated here.

[0081] Figure 15 A cross-sectional view of a semiconductor structure 100B according to another embodiment is shown. The semiconductor structure 100B can be formed following the same or similar processing steps as that used for the semiconductor structure 100, but without performing the plasma process 123 to activate the surface of the heat sink 121 (or bonding layer 115). As a result, the bonding between the bonding layer 115 and the heat sink 121 can be achieved through physical bonding (e.g., van der Waals forces) rather than chemical bonding (e.g., chemical bonds formed through a chemical reaction). Therefore, no intermediate compound layer 125 is formed in the semiconductor structure 100B. Other details are the same or similar to those discussed above and will not be repeated.

[0082] Figure 16 A cross-sectional view of a semiconductor structure 100C according to another embodiment is shown. The semiconductor structure 100C may be formed following the same or similar processing steps as that used for the semiconductor structure 100, but with another bonding layer 127 (also referred to as bonding film 127) formed on the reconstructed wafer prior to the formation of the bonding layer 115. Note that the bonding layer 115 in the semiconductor package 100 can be considered to replace the first bonding layer (e.g., attached to heat sink 121) and the second bonding layer (e.g., attached to the reconstructed wafer) in the aforementioned reference package; in contrast, the bonding layer 115 in the semiconductor package 100C can be considered to replace only the first bonding layer of the reference package.

[0083] like Figure 16 As shown, after activating the surface of the heat sink 121 (or bonding layer 115) using plasma process 123, the heat sink 121 is bonded to the bonding layer 115, and an intermediate compound layer 125 is formed between the heat sink 121 and the bonding layer 115.

[0084] In some embodiments, the bonding layer 127 is formed from a suitable dielectric material, such as aluminum oxide (e.g., AlO), using a suitable formation method (e.g., CVD, ALD, etc.). x ), silicon dioxide (e.g., SiO2) x The bonding layer 127 can be made of silicon carbonitride (e.g., SiCN), titanium oxide (e.g., TiO2), aluminum nitride (e.g., AlN), boron nitride (e.g., BN), silicon oxynitride (e.g., SiON), or silicon oxycarbide (e.g., SiOC). The thickness of the bonding layer 127 can be between about 5 angstroms and about 2500 angstroms. The thermal conductivity of the bonding layer 115 can be between about 0.5 W / (m·K) and about 20 W / (m·K). In some embodiments, bonding layers 127 and 115 are formed of the same material.

[0085] In some embodiments, bonding layer 127 is formed to be thicker than bonding layer 115. For example, the thickness of bonding layer 127 may be 1.5 times, two times, three times, or more the thickness of bonding layer 115. As discussed below, bonding layer 127 may be used to enhance the flatness of subsequently formed bonding layer 115. In some embodiments, after the gap-fill region 113 is formed, the flatness of the “coplanar surface” of the dummy die 111, the support substrate 19, and the gap-fill region 113 may be poor. Poor flatness may be caused by factors such as the gap-fill region 113 being formed of a molding material, and the molding material and the material of the dummy die 111 and the support substrate 19 (e.g., silicon) may respond differently to the planarization process used to form the “coplanar surface”. If an ultrathin bonding layer 115 (e.g., with a thickness between approximately 5 angstroms and 2500 angstroms) is formed directly on the gap-filling region 13, the dummy die 11, and the support substrate 9, the bonding layer 115 may also have poor flatness, which could lead to poor bonding. By forming a bonding layer 127 prior to the bonding layer 115, the bonding layer 127 can be planarized to achieve a high level of flatness, preparing for the deposition of the bonding layer 115. As a result, the subsequently formed bonding layer 115 has a high level of flatness and achieves good adhesion.

[0086] Figure 17 A cross-sectional view of a semiconductor structure 100D according to another embodiment is shown. The semiconductor structure 100D can be formed according to the same or similar processing steps as that used for semiconductor structure 100C, but with an intermediate compound layer 125 formed between bonding layer 115 and bonding layer 127. The semiconductor structure 100D can be formed by the following steps: forming bonding layer 127 on the upper surface of the support substrate 19, the dummy die 111, and the gap filling region 113; forming bonding layer 115 on the heat sink 121; activating the surface of the heat sink 121 (or bonding layer 127) by performing a plasma process 123; and bonding layers 115 and 127 together. Figure 17 As shown, an intermediate compound layer 125 is formed between the bonding layer 115 and the bonding layer 127.

[0087] Figure 18 A cross-sectional view of a semiconductor structure 100E according to another embodiment is shown. The semiconductor structure 100E may be formed following the same or similar processing steps as those used for semiconductor structure 100C (or 100D), but without the intermediate compound layer 125. In some embodiments, the semiconductor structure 100E is formed by omitting the plasma process 123 performed on the semiconductor structure 100C (or 100D). As a result, no intermediate compound layer 125 is formed in the semiconductor structure 100E.

[0088] Figure 19A cross-sectional view of a semiconductor structure 100F according to another embodiment is shown. The semiconductor structure 100F may be formed according to the same or similar processing steps as that used for semiconductor structure 100, but has a bonding layer 129 formed on a heat sink 121 and an intermediate compound layer 125 formed between bonding layers 129 and 115. In some embodiments, to form the semiconductor structure 100F, bonding layer 129 is formed on the surface of heat sink 121, and bonding layer 115 is formed on the upper surfaces of the dummy die 111, the support substrate 19, and the gap-filling region 113. In some embodiments, bonding layer 129 is formed of the same material having the same thickness as bonding layer 115. Next, a plasma process 123 is performed to treat (e.g., activate) the outer surface of bonding layer 129 (or bonding layer 115). Next, bonding layer 129 is bonded to bonding layer 115, and an intermediate compound layer 125 is formed between bonding layers 115 and 129.

[0089] Figure 20 A cross-sectional view of a semiconductor structure 100G according to another embodiment is shown. The semiconductor structure 100G may be formed following the same or similar processing steps as for the semiconductor structure 100F, but a bonding layer 129 is formed on the bonding layer 115 before bonding the heat sink 121. Next, a plasma process 123 is performed to treat (e.g., activate) the surface of the heat sink 121 or the surface of the bonding layer 129. Next, the heat sink 121 is bonded to the bonding layer 129, and an intermediate compound layer 125 is formed between the heat sink 121 and the bonding layer 129. Although not shown, another alternative embodiment involves sequentially forming the bonding layers 129 and 115 on the heat sink 121, performing the plasma process 123 to activate the outer surface of the bonding layer 115, or to activate the upper surface of the dummy die 111, the support substrate 9, and the gap-filling region 113, and then bonding the bonding layer 115 to the upper surface of the dummy die 111, the support substrate 9, and the gap-filling region 113. In this alternative embodiment, an intermediate compound layer 125 is formed between the bonding layer 115 and the upper surfaces of the dummy die 111, the support substrate 19, and the gap-filling region 113, and... Figure 14 The intermediate compound layer 125 shown is the same as or similar to that shown.

[0090] Figure 21 A cross-sectional view of a semiconductor structure 100H according to another embodiment is shown. The semiconductor structure 100H can be formed according to the same or similar processing steps as those used for semiconductor structures 100F (or 100G), but without the intermediate compound layer 125. In some embodiments, the semiconductor structure 100H is formed by omitting the plasma process 123 performed on the semiconductor structure 100F (or 100G). As a result, no intermediate compound layer 125 is formed in the semiconductor structure 100H.

[0091] Figure 22 A cross-sectional view of a semiconductor structure 100I according to another embodiment is shown. The semiconductor structure 100I can be formed following the same or similar processing steps as that used for the semiconductor structure 100F, but a bonding layer 127 is formed on the upper surfaces of the dummy die 111, the support substrate 19, and the gap-filling region 113 before the bonding layer 115 is formed. As discussed above, the bonding layer 127 can be used to improve the flatness of the bonding layer 115 and can have a greater thickness than the bonding layers 115 or 129 (e.g., 1.5 times, two times, three times, or more). An intermediate compound layer 125 is formed between the bonding layers 129 and 115.

[0092] Figure 23 A cross-sectional view of a semiconductor structure 100J according to another embodiment is shown. The semiconductor structure 100J can be formed following the same or similar processing steps as that used for the semiconductor structure 100G, but a bonding layer 127 is formed on the upper surfaces of the dummy die 111, the support substrate 19, and the gap-filling region 113 before the bonding layer 115 is formed. As discussed above, the bonding layer 127 can be used to improve the flatness of the bonding layer 115 and can have a greater thickness than the bonding layers 115 or 129 (e.g., 1.5 times, two times, three times, or more). An intermediate compound layer 125 is formed between the heat sink 121 and the bonding layer 129.

[0093] Figure 24 A cross-sectional view of a semiconductor structure 100K according to yet another embodiment is shown. The semiconductor structure 100K can be formed following the same or similar processing steps as that used for semiconductor structure 100H, but a bonding layer 127 is formed on the upper surfaces of the dummy die 111, the support substrate 19, and the gap-filling region 113 before the bonding layer 115 is formed. As discussed above, the bonding layer 127 can be used to improve the flatness of the bonding layer 115 and can have a greater thickness than the bonding layers 115 or 129 (e.g., 1.5 times, two times, three times, or more). The plasma process 123 is omitted, and therefore, no intermediate compound layer 125 is formed in the semiconductor structure 100K.

[0094] Variations and modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of this disclosure. For example, in Figure 2In this document, as a non-limiting example, the bonding between bonding layers 21 and 23 of semiconductor die 50 is shown as a direct dielectric-to-dielectric bonding to illustrate the attachment of support substrate 19 to interconnect structure 16. The attachment of support substrate 19 to interconnect structure 16 can be achieved by any bonding scheme disclosed herein, using bonding layer 21 formed of the same material having the same thickness as bonding layer 115 and treating bonding layer 21 as an ultrathin bonding layer 115 (e.g., consider). For example, a plasma process 123 can be performed to activate at least one bonding surface, resulting in the formation of an intermediate compound layer 125 at the bonding interface, for example, at some location between support substrate 19 and interconnect structure 16 of semiconductor die 50, depending on which surface is treated by plasma process 123. As another example, only bonding layer 21 is used for bonding, and bonding layer 23 can be omitted. As yet another example, two ultrathin bonding layers 21 can be used at the bonding interface, with or without bonding layer 127.

[0095] The disclosed embodiments achieve various advantages. For example, the disclosed semiconductor structure uses an ultrathin bonding layer (e.g., 115) at the bonding interface instead of one or two bonding layers used in a reference package without the disclosed bonding scheme / structure. The thickness of the disclosed bonding layer is between about 1 / 10 and about 1 / 100 of the thickness of the bonding layer used in the reference package, thus significantly improving heat dissipation efficiency and reducing thermal resistance. Prior to bonding, a plasma process is performed to activate at least one of the two surfaces to be bonded. As a result, an intermediate compound layer is formed at the bonding interface through chemical bonds formed by chemical reactions between the materials of the bonding surfaces. The intermediate compound layer provides enhanced adhesion. The ultrathin bonding layer also has improved flatness due to the deposition method used (e.g., ALD) and / or the underlying bonding layer (e.g., 127). The enhanced adhesion, together with the improved flatness, achieves a strong bond at the bonding interface with virtually no void regions (e.g., bubbles), which further improves heat dissipation efficiency. The improved heat dissipation efficiency allows for the use of inexpensive materials such as silicon as materials for heat sinks and / or dummy dies used in semiconductor packages, which reduces production costs. The ultrathin bonding layer also reduces the height of the formed semiconductor structure.

[0096] Figure 25 A flowchart illustrating a method for forming a semiconductor device in some embodiments is shown. It should be understood that... Figure 25 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 25 The various steps shown.

[0097] refer to Figure 25At block 1010, a first semiconductor die is attached to a carrier substrate, wherein the first semiconductor die includes a first substrate, a first contact pad, and a first dielectric layer surrounding the first contact pad, wherein the first contact pad and the first dielectric layer are located on a first side of the first substrate away from the carrier substrate. At block 1020, a second semiconductor die is bonded to the first semiconductor die, wherein the second semiconductor die includes a second substrate, a second contact pad, a second dielectric layer surrounding the second contact pad, and a support substrate attached to the second substrate, wherein the second contact pad and the second dielectric layer are located on a first side of the second substrate facing the first semiconductor die, wherein the support substrate is located on a second opposite side of the second substrate, wherein bonding the second semiconductor die includes bonding the second contact pad to the first contact pad without solder, and bonding the second dielectric layer to the first dielectric layer by direct dielectric-to-dielectric bonding. At block 1030, a gap-filling layer is formed around the second semiconductor die over the carrier substrate. At frame 1040, a first bonding film is formed over the gap filling layer and the second semiconductor die, wherein the first bonding film is a dielectric material. At frame 1050, the surface of the heat sink is activated using a plasma process. At frame 1060, the activated surface of the heat sink is bonded to the first bonding film.

[0098] According to an embodiment, a method for forming a semiconductor structure includes: attaching a first semiconductor die to a carrier substrate, wherein the first semiconductor die includes a first substrate, a first contact pad, and a first dielectric layer surrounding the first contact pad, wherein the first contact pad and the first dielectric layer are located on a first side of the first substrate away from the carrier substrate; and bonding a second semiconductor die to the first semiconductor die, wherein the second semiconductor die includes a second substrate, a second contact pad, a second dielectric layer surrounding the second contact pad, and a support substrate attached to the second substrate, wherein the second contact pad and the second dielectric layer are located on a first side of the second substrate away from the carrier substrate; Facing a first side of a first semiconductor die, with a support substrate located on a second side opposite to a second substrate, bonding the second semiconductor die includes bonding a second contact pad to a first contact pad without solder, and bonding a second dielectric layer to a first dielectric layer via direct dielectric-to-dielectric bonding; forming a gap-filling layer around the second semiconductor die over a carrier substrate; forming a first bonding film over the gap-filling layer and the second semiconductor die, wherein the first bonding film is a dielectric material; activating a surface of a heat sink using a plasma process; and bonding the activated surface of the heat sink to the first bonding film. In an embodiment, bonding the activated surface of the heat sink includes placing the activated surface of the heat sink in direct contact with the first bonding film, wherein after bonding the activated surface of the heat sink, an intermediate compound layer is formed between the heat sink and the first bonding film. In an embodiment, the intermediate compound layer includes a compound material formed by a chemical reaction between a first material at the activated surface of the heat sink and a second material of the first bonding film. In an embodiment, the heat sink is a bulk silicon material. In an embodiment, the first bonding film is alumina, and the compound material is aluminosilicate. In an embodiment, the heat sink is a bulk silicon material, and the first bonding film is aluminum oxide, silicon oxide, silicon carbonitride, titanium oxide, aluminum nitride, boron nitride, silicon oxynitride, or silicon oxycarbide. In an embodiment, the first thickness of the first bonding film is between about 10 and about 100 times the second thickness of the intermediate compound layer. In an embodiment, the thermal conductivity of the first bonding film is between about 0.5 W / m / Kelvin (W / (m·K)) and about 20 W / (m·K). In an embodiment, the method further includes forming a second bonding film over a gap-filling layer and a second semiconductor die before forming the first bonding film, wherein the second bonding film is disposed between the first bonding film and the gap-filling layer after forming the first bonding film. In an embodiment, the third thickness of the second bonding film is greater than the first thickness of the first bonding film. In an embodiment, the first and second bonding films are formed of the same material.

[0099] According to an embodiment, a method for forming a semiconductor structure includes: attaching a bottom die to a carrier substrate, wherein the bottom die includes a first semiconductor substrate, an interconnect structure located on a first side of the first semiconductor substrate, and a substrate through-hole (TSV) extending from a conductive component of the interconnect structure into the first semiconductor substrate, wherein after attaching the bottom die, the interconnect structure is situated between the carrier substrate and the first semiconductor substrate of the bottom die; forming a first gap-filling layer around the bottom die on the carrier substrate; and after forming a first molding material, thinning the first semiconductor substrate from a second side of the first semiconductor substrate away from the carrier substrate, wherein after thinning, the TSV protrudes to the second side of the first semiconductor substrate. Above; after thinning, a first dielectric layer is formed above the first gap fill layer and the bottom die; a first contact pad is formed in the first dielectric layer and electrically coupled to the TSV, wherein the TSV provides electrical connection from the conductive component to the first contact pad through the first semiconductor substrate; a second contact pad of the top die is bonded to the first contact pad; after bonding the second contact pad, a second gap fill layer is formed around the top die above the first dielectric layer; a bonding layer is formed above the second gap fill layer and the top die, wherein the bonding layer includes a dielectric material; the surface of the heat sink is treated by performing a plasma process; and after treatment, the surface of the heat sink is bonded to the bonding layer. In one embodiment, after thinning, the upper portion of the TSV protrudes over a second side of the first semiconductor substrate. The method further includes forming a second dielectric layer on the first gap-fill layer and the bottom die after thinning and before forming the first dielectric layer. The second dielectric layer contacts and extends along the sidewalls of the upper portion of the TSV. The second dielectric layer and the TSV have flush upper surfaces away from the carrier substrate. The first dielectric layer is formed on the second dielectric layer. In one embodiment, after bonding the heat sink surface, an intermediate compound layer is formed between the heat sink and the bonding layer. The intermediate compound layer comprises a compound material formed by a chemical reaction between a first material of the heat sink and a second material of the bonding layer. In one embodiment, the second contact pad of the top die is bonded to the first contact pad without solder. The second dielectric layer of the top die is bonded to the first dielectric layer by direct dielectric-to-dielectric bonding. In one embodiment, the method further includes attaching a dummy die to the first dielectric layer using an adhesive layer between the dummy die and the first dielectric layer before forming the second gap-fill layer. In one embodiment, the top die includes a second semiconductor substrate, a second contact pad located on a first side of the second semiconductor substrate facing the bottom die, a support substrate located on a opposite second side of the second semiconductor substrate, and another bonding layer located between the support substrate and the second semiconductor substrate, wherein the bonding layer and the other bonding layer are formed of the same material, and wherein the dummy die, the support substrate, and the second gap filler layer have flush upper surfaces away from the bottom die.

[0100] According to an embodiment, the semiconductor structure includes: a bottom die; a first gap-filling layer surrounding the bottom die; a top die bonded to the bottom die, wherein a first contact pad of the bottom die is bonded to a second contact pad of the top die via direct metal-to-metal bonding, and a first dielectric layer of the bottom die is bonded to a second dielectric layer of the top die via direct dielectric-to-dielectric bonding; a second gap-filling layer above the first gap-filling layer and surrounding the top die; a bonding layer above the second gap-filling layer and the top die; a heat sink bonded to the bonding layer; and an intermediate compound layer between the bonding layer and the heat sink, wherein the intermediate compound layer comprises a compound material, wherein the compound material comprises chemical bonds between a first material of the heat sink and a second material of the bonding layer. In an embodiment, the heat sink is a bulk silicon material, wherein the bonding layer comprises alumina, silicon oxide, silicon carbonitride, titanium oxide, aluminum nitride, boron nitride, silicon oxynitride, or silicon carbonitride. In the embodiments, the thickness of the bonding layer is between about 5 angstroms and about 2500 angstroms, and the thermal conductivity of the bonding layer is between about 0.5 W / m / Kelvin (W / (m·K)) and about 20 W / (m·K).

[0101] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, the method comprising: A first semiconductor die is attached to a carrier substrate, wherein the first semiconductor die includes a first substrate, a first contact pad, and a first dielectric layer located around the first contact pad, wherein the first contact pad and the first dielectric layer are located on a first side of the first substrate away from the carrier substrate; A second semiconductor die is bonded to a first semiconductor die, wherein the second semiconductor die includes a second substrate, a second contact pad, a second dielectric layer surrounding the second contact pad, and a support substrate attached to the second substrate, wherein the second contact pad and the second dielectric layer are located on a first side of the second substrate facing the first semiconductor die, wherein the support substrate is located on a second opposite side of the second substrate, wherein bonding the second semiconductor die includes bonding the second contact pad to the first contact pad without solder, and bonding the second dielectric layer to the first dielectric layer by direct dielectric-to-dielectric bonding; A gap-filling layer is formed around the second semiconductor die above the carrier substrate; A first bonding film is formed over the gap filling layer and the second semiconductor die, wherein the first bonding film is a dielectric material; Activating the surface of a heat sink using plasma technology; and The activated surface of the heat sink is bonded to the first bonding film.

2. The method according to claim 1, wherein, The activation surface of the heat sink is bonded to the heat sink by placing the activation surface of the heat sink in direct contact with the first bonding film, wherein, after the activation surface of the heat sink is bonded, an intermediate compound layer is formed between the heat sink and the first bonding film.

3. The method according to claim 2, wherein, The intermediate compound layer comprises a compound material formed by a chemical reaction between a first material at the activated surface of the heat sink and a second material of the first bonding film.

4. The method according to claim 3, wherein, The heat sink is made of bulk silicon material.

5. The method according to claim 4, wherein, The first bonding film is aluminum oxide, and the compound material is alumina silicon.

6. The method according to claim 3, wherein, The heat sink is a bulk silicon material, and the first bonding film is aluminum oxide, silicon oxide, silicon carbonitride, titanium oxide, aluminum nitride, boron nitride, silicon oxynitride, or silicon carbonitride.

7. The method according to claim 3, wherein, The first thickness of the first bonding film is between 10 and 100 times the second thickness of the intermediate compound layer.

8. The method according to claim 7, wherein, The thermal conductivity of the first bonding film is between 0.5 W / m / Kelvin (W / (m·K)) and 20 W / (m·K).

9. A method for forming a semiconductor structure, the method comprising: A bottom die is attached to a carrier substrate, wherein the bottom die includes a first semiconductor substrate, an interconnect structure located on a first side of the first semiconductor substrate, and a substrate through-hole (TSV) extending from a conductive component of the interconnect structure into the first semiconductor substrate, wherein, after the bottom die is attached, the interconnect structure is located between the carrier substrate and the first semiconductor substrate of the bottom die; A first gap-filling layer is formed on the carrier substrate around the bottom die; After the first molding material is formed, the first semiconductor substrate is thinned from a second side away from the carrier substrate, wherein, after the thinning, the substrate vias protrude over the second side of the first semiconductor substrate; After the thinning, a first dielectric layer is formed over the first gap filler layer and the bottom die; A first contact pad is formed in the first dielectric layer, and the first contact pad is electrically coupled to the substrate via, wherein the substrate via provides an electrical connection from the conductive component to the first contact pad through the first semiconductor substrate; The second contact pad of the top die is bonded to the first contact pad; After the second contact pad is bonded, a second gap filler layer is formed around the top die above the first dielectric layer; A bonding layer is formed over the second gap-filling layer and the top die, wherein the bonding layer comprises a dielectric material; The surface of the heat sink is treated by performing a plasma process; and After the treatment, the surface of the heat sink is bonded to the bonding layer.

10. A semiconductor structure, comprising: Bottom core; A first gap-filling layer is located around the bottom core; A top die is bonded to the bottom die, wherein a first contact pad of the bottom die is bonded to a second contact pad of the top die via direct metal-to-metal bonding, and a first dielectric layer of the bottom die is bonded to a second dielectric layer of the top die via direct dielectric-to-dielectric bonding. The second gap filler layer is located above the first gap filler layer and around the top die; A bonding layer is located above the second gap-filling layer and the top die; Heat sink, bonded to the bonding layer; and An intermediate compound layer is provided between the bonding layer and the heat sink, wherein the intermediate compound layer comprises a compound material, wherein the compound material comprises chemical bonds between a first material of the heat sink and a second material of the bonding layer.

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